STA518 40V 3.5A quad power half bridge Feature ■ Multipower BCD technology ■ Minimum input output pulse width distortion ■ 200mΩ RdsON complementary dmos output stage ■ CMOS compatible logic inputs ■ Thermal protection ■ Thermal warning output ■ Under voltage protection ■ Short circuit protection PSSO36 (slug up) Description STA518 is a monolithic quad half bridge stage in Multipower BCD Technology. The device can be used also as dual bridge or reconfigured, by connecting CONFIG pin to Vdd pin, as single bridge with double current capability. The device is particularly designed to make the output stage of a stereo All-Digital High Efficiency (DDX™) amplifier capable to deliver an output power of 24W x 4 channels @ THD = 10% at Vcc 30V on 4W load in single ended configuration. It can also deliver 50 + 50W @ THD = 10% at Vcc 29V as output power on 8W load in BTL configuration and 70W @ THD = 10% at Vcc 34V on 8W in single paralleled BTL configuration. The input pins have threshold proportional to VL pin voltage. Order codes Part number Temp range, °C Package Packing STA518 -40 to 90 PowerSSO36 (slug up) Tube STA51813TR -40 to 90 PowerSSO36 (slug up) Tape & reel May 2006 Rev 3 1/19 www.st.com 1 Contents STA518 Contents 1 Audio application circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 2 Pins description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 3 Electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 4 3.1 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 3.2 Recommended operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 3.3 Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 3.4 Thermal information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 3.5 Electrical characteristcs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Technical information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 4.1 Logic interface and decode: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 4.2 Power outputs: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 4.3 Parallel output / high current operation: . . . . . . . . . . . . . . . . . . . . . . . . . . 13 4.4 Additional informations: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 5 Characterization curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 6 Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 7 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 2/19 STA518 List of tables List of tables Table 1. Table 2. Table 3. Table 4. Table 5. Table 6. Table 7. Table 8. Table 9. Pin Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Functional Pin Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Recommended operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Electrical Characteristcs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 VLOW, VHIGH variation with Ibias . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Logic Truth Table (see Figure 4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 3/19 List of figures STA518 List of figures Figure 1. Figure 2. Figure 3. Figure 4. Figure 5. Figure 6. Figure 7. Figure 8. Figure 9. Figure 10. Figure 11. Figure 12. Figure 13. Figure 14. Figure 15. Figure 16. Figure 17. Figure 18. Figure 19. 4/19 Audio application circuit ( Quad single ended) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Pin Connection (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Low current dead time for Single End application: test circuit. . . . . . . . . . . . . . . . . . . . . . . 11 High current dead time for Bridge application: block diagram . . . . . . . . . . . . . . . . . . . . . . 11 High current dead time for Bridge application: test circuit. . . . . . . . . . . . . . . . . . . . . . . . . . 11 STA518 Block Diagram Full-Bridge DDX® or Binary Modes . . . . . . . . . . . . . . . . . . . . . . . 12 STA518 Block Diagram Binary Half-Bridge Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Typical Stereo Full Bridge Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Typical Single BTL Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Power Dissipation vs Output Power . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Power Derating Curve . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 THD+N vs Output Power . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Output Power vs Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 THD vs Frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Output Power vs Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 THD+N vs Output Power . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Power Dissipation vs Output Power . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 THD+N vs Output Power . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 PSSO36 (Slug Up) Mechanical Data & Package Dimensions . . . . . . . . . . . . . . . . . . . . . . 17 R57 10K C58 100nF TH_WAR +3.3V C60 100nF 33 34 VSS VSS GND-Reg GNDSUB IN2B 1 32 19 20 M14 M16 5 2 3 4 6 9 8 7 13 10 11 D03AU1474 PGND2N OUTNR OUTNR C52 1µF VCC2N PGND2P OUTPR OUTPR VCC2P PGND1N OUTNL OUTNL C51 1µF VCC1N PGND1P OUTPL OUTPL C44 330pF R44 20 C62 100nF C43 330pF R43 20 C42 330pF R42 20 C61 100nF C41 330pF R41 20 R54 6 C74 100nF L14 22µH R53 6 C73 100nF L13 22µH R52 6 C72 100nF L12 22µH R51 6 C71 100nF L11 22µH C84 100nF C83 100nF C82 100nF C81 100nF R68 5K R67 5K R66 5K R65 5K R64 5K R63 5K R62 5K R61 5K C94 1µF C34 820µF C93 1µF C33 820µF C92 1µF C32 820µF C91 1µF C31 820µF 4Ω 4Ω 4Ω 4Ω C21 2200µF Audio application circuit ( Quad single ended) GND-Clean M15 M17 M4 M5 12 14 16 17 Figure 1. 31 36 REGULATORS PROTECTIONS & LOGIC M2 M3 +VCC Audio application circuit IN2A VCCSIGN 35 22 VDD VCCSIGN 21 30 IN1B VDD 28 TH_WAR 26 27 FAULT TRI-STATE 25 24 PWRDN 23 VL 29 CONFIG IN1A VCC1P 1 IN2B IN2A C53 100nF IN1B C58 100nF R59 10K PWRDN IN1A 15 STA518 Audio application circuit 5/19 Pins description 2 STA518 Pins description Figure 2. Pin Connection (top view) VCCSign 36 1 GND-SUB VCCSign 35 2 OUT2B VSS 34 3 OUT2B VSS 33 4 VCC2B IN2B 32 5 GND2B IN2A 31 6 GND2A IN1B 30 7 VCC2A IN1A 29 8 OUT2A TH_WAR 28 9 OUT2A FAULT 27 10 OUT1B TRI-STATE 26 11 OUT1B PWRDN 25 12 VCC1B CONFIG 24 13 GND1B VL 23 14 GND1A VDD 22 15 VCC1A VDD 21 16 OUT1A GND-Reg 20 17 OUT1A GND-Clean 19 18 N.C. D01AU1273 Table 1. 6/19 Pin Function N° Pin Description 1 GND-SUB 2;3 OUT2B Output half bridge 2B 4 Vcc2B Positive supply 5 GND2B Negative Supply 6 GND2A Negative Supply 7 Vcc2A Positive supply 8;9 OUT2A Output half bridge 2A 10 ; 11 OUT1B Output half bridge 1B 12 Vcc1B Positive supply 13 GND1B Negative Supply 14 GND1A Negative Supply 15 Vcc1A Positive supply 16 ; 17 OUT1A Output half bridge 1A 35 ; 36 Vcc Sign Signal Positive supply Substrate ground STA518 Pins description Table 1. Pin Function (continued) N° Pin 18 NC Not connected 19 GND-clean Logical ground 20 GND-Reg Ground for regulator Vdd 21 ; 22 Vdd 5V Regulator referred to ground 23 VL Logic Reference Voltage 24 CONFIG Configuration pin 25 PWRDN Stand-by pin 26 TRI-STATE 27 FAULT 28 TH-WAR 29 IN1A Input of half bridge 1A 30 IN1B Input of half bridge 1B 31 IN2A Input of half bridge 2A 32 IN2B Input of half bridge 2B 33 ; 34 Vss 5V Regulator referred to +Vcc 35 ; 36 Vcc Sign Table 2. Description Hi-Z pin Fault pin advisor Thermal warning advisor Signal Positive supply Functional Pin Status Pin Name Pin N. Logical value FAULT 27 0 Fault detected (Short circuit, or Thermal.) FAULT * 27 1 Normal Operation TRI-STATE 26 0 All powers in Hi-Z state TRI-STATE 26 1 Normal operation PWRDN 25 0 Low consumption PWRDN 25 1 Normal operation THWAR 28 0 Temperature of the IC =130C 28 1 Normal operation CONFIG 24 0 Normal Operation CONFIG(2) 24 1 OUT1A=OUT1B ; OUT2A=OUT2B (IF IN1A = IN1B; IN2A = IN2B) (1) THWAR IC - STATUS 1. The pin is open collector. To have the high logic value, it needs to be pulled up by a resistor. 2. To put CONFIG = 1 means connect Pin 24 (CONFIG) to Pins 21, 22 (Vdd) to implemented single BTL (MONO MODE) operation for high current. 7/19 Electrical specifications STA518 3 Electrical specifications 3.1 Absolute maximum ratings Table 3. Absolute maximum ratings Symbol 3.2 Parameter Value Unit VCC DC Supply Voltage (Pin 4,7,12,15) 40 V Vmax Maximum Voltage on pins 23 to 32 5.5 V -40 to 90 °C Top Operating Temperature Range Ptot Power Dissipation (Tcase = 70°C) 21 W Tstg, Tj Storage and Junction Temperature -40 to 150 °C Recommended operating conditions Table 4. Recommended operating conditions (*) Symbol VCC Parameter Min. DC Supply Voltage 10 VL Input Logic Reference 2.7 Tamb Ambient Temperature 0 Typ. 3.3 Max. Unit 36.0 V 5.0 V 70 °C Max. Unit 1.5 °C/W (*) performances not guaranteed beyond recommended operating conditions 3.3 Thermal data Table 5. Thermal data (*) Symbol Tj-case Parameter Min. Typ. Thermal Resistance Junction to Case (thermal pad) TjSD Thermal shut-down junction temperature 150 °C Twarn Thermal warning temperature 130 °C thSD Thermal shut-down hysteresis 25 °C (*) see Thermal information 3.4 Thermal information The power dissipated within the device depends primarly on the supply voltage, load impedance and output modulation level. The PSSO36 Package of the STA518 includes an exposed thermal slug on the top of the device to provide a direct thermal path from the IC to the heatsink. For the Quad single ended application the Dissipated Power vs Ouptut Power is shown in Figure 10. 8/19 STA518 Electrical specifications Considering that for the STA518 the Thermal resistance Junction to slug is 1.5°C/W and the extimated Thermal resistance due to the grease placed between slug and heat sink is 2.3°C/W ( the use of thermal pads for this package is not recommended), the suitable Heat Sink Rth to be used can be drawn from the following graph Figure 11, where is shown the Derating Power vs.Tambient for different heatsinkers. 3.5 Electrical characteristcs Table 6. Electrical Characteristcs Refer to circuit in Figure 3 (VL = 3.3V; VCC = 30V; RL = 8Ω; fsw = 384KHz; Tamb = 25°C unless otherwise specified) Symbol Parameter Test conditions Min. Typ. Max. Unit 200 270 mΩ 50 µA RdsON Power Pchannel/Nchannel MOSFET RdsON Id = 1A Idss Power Pchannel/Nchannel leakage Idss VCC = 35V gN Power Pchannel RdsON Matching Id = 1A 95 % gP Power Nchannel RdsON Matching Id = 1A 95 % Dt_s Low current Dead Time (static) see test circuit Figure 3 Dt_d High current Dead Time (dinamic) td ON td OFF 20 ns L = 22µH; C = 470nF; RL = 8 Ω Id = 3A; seeFigure 5 50 ns Turn-on delay time Resistive load; VCC = 30V 100 ns Turn-off delay time Resistive load; VCC = 30V 100 ns 25 ns 25 ns 36 V VL/2 +300mV V tr Rise time tf Fall time 10 Resistive load; as Figure 3 VCC Supply voltage operating voltage VIN-H High level input voltage VIN-L Low level input voltage IIN-H Hi level Input current Pin voltage = VL 1 µA IIN-L Low level input current Pin voltage = 0.3V 1 µA 35 µA IPWRDNH 10 VL/2 300mV Hi level PWRDN pin input current VL = 3.3V VLOW Low logical state voltage VLow (pin PWRDN, TRISTATE) (1) VL = 3.3V VHIGH High logical state voltage VHigh (pin PWRDN, TRISTATE) (1) VL = 3.3V IVCCPWRDN Supply current from Vcc in Power PWRDN = 0 Down V 0.8 V 1.7 V 3 mA 9/19 Electrical specifications Table 6. Electrical Characteristcs (continued) Refer to circuit in Figure 3 (VL = 3.3V; VCC = 30V; RL = 8Ω; fsw = 384KHz; Tamb = 25°C unless otherwise specified) Symbol IFAULT IVCC-hiz IVCC IVCC-q VUV tpw_min STA518 Parameter Test conditions Min. Typ. Max. Unit Output Current pins FAULT -TH-WARN when FAULT CONDITIONS Vpin = 3.3V 1 mA Supply current from Vcc in Tristate VCC = 30V; Tri-state = 0 22 mA Supply current from VCC in operation (both channel switching) VCC = 30V; Input pulse width = 50% Duty; Switching Frequency = 384kHz; No LC filters; 50 mA Isc (short circuit current limit) (2) VCC = 30V 6 A 7 V 3.5 Undervoltage protection threshold Output minimum pulse width No Load 70 150 ns 1. The Table 7 explains the VLOW, VHIGH variation with Ibias. 2. See relevant Application Note AN1994 Table 7. VLOW, VHIGH variation with Ibias VL VLow min VHigh max Unit 2.7 0.7 1.5 V 3.3 0.8 1.7 V 5 0.85 1.85 V Table 8. Logic Truth Table (see Figure 4) TRI-STATE INxA INxB Q1 Q2 Q3 Q4 OUTPUT MODE 0 x x OFF OFF OFF OFF Hi-Z 1 0 0 OFF OFF ON ON DUMP 1 0 1 OFF ON ON OFF NEGATIVE 1 1 0 ON OFF OFF ON POSITIVE 1 1 1 ON ON OFF OFF Not used 10/19 STA518 Electrical specifications Figure 3. Low current dead time for Single End application: test circuit. OUTxY Vcc (3/4)Vcc Low current dead time = MAX(DTr,DTf) (1/2)Vcc (1/4)Vcc +Vcc t DTr Duty cycle = 50% DTf M58 OUTxY INxY R 8Ω M57 + - gnd Figure 4. V67 = vdc = Vcc/2 D03AU1458 High current dead time for Bridge application: block diagram +VCC Q1 Q2 OUTxA INxA OUTxB Q3 INxB Q4 GND Figure 5. D00AU1134 High current dead time for Bridge application: test circuit High Current Dead time for Bridge application = ABS(DTout(A)-DTin(A))+ABS(DTOUT(B)-DTin(B)) +VCC Duty cycle=A Duty cycle=B DTout(A) M58 DTin(A) Q1 Q2 Rload=8Ω OUTA INA Iout=4A M57 Q3 DTout(B) L67 22µ C69 470nF L68 22µ C71 470nF C70 470nF M64 DTin(B) OUTB INB Iout=4A Q4 Duty cycle A and B: Fixed to have DC output current of 4A in the direction shown in figure M63 D03AU1517 11/19 Technical information 4 STA518 Technical information The STA518 is a dual channel H-Bridge that is able to deliver 50W per channel (@ THD=10% RL = 8Ω, VCC = 29V) of audio output power in high efficiency. The STA518 converts both DDX and binary-controlled PWM signals into audio power at the load. It includes a logic interface , integrated bridge drivers, high efficiency MOSFET outputs and thermal and short circuit protection circuitry. In DDX mode, two logic level signals per channel are used to control high-speed MOSFET switches to connect the speaker load to the input supply or to ground in a Bridge configuration, according to the damped ternary Modulation operation. In Binary Mode operation , both Full Bridge and Half Bridge Modes are supported. The STA518 includes over-current and thermal protection as well as an under-voltage Lockout with automatic recovery. A thermal warning status is also provided. Figure 6. STA518 Block Diagram Full-Bridge DDX® or Binary Modes INL[1:2] INR[1:2] VL PWRDN OUTPL Logic I/F and Decode Left H-Bridge OUTNL TRI-STATE Protection Circuitry FAULT TWARN OUTPR Right H-Bridge Regulators Figure 7. STA518 Block Diagram Binary Half-Bridge Mode LeftA ‰-Bridge OUTPL LeftB ‰-Bridge OUTNL Protection Circuitry RightA ‰-Bridge OUTPR Regulators RightB ‰-Bridge OUTNR INL[1:2] INR[1:2] VL Logic I/F and Decode PWRDN TRI-STATE FAULT TWARN 4.1 OUTNR Logic interface and decode: The STA518 power outputs are controlled using one or two logic level timing signals. In order to provide a proper logic interface, the Vbias input must operate at the dame voltage as the DDX control logic supply. Protection circuitry: 12/19 STA518 Technical information The STA518 includes protection circuitry for over-current and thermal overload conditions. A thermal warning pin (pin.28) is activated low (open drain MOSFET) when the IC temperature exceeds 130°C, in advance of the thermal shutdown protection. When a fault condition is detected , an internal fault signal acts to immediately disable the output power MOSFETs, placing both H-Bridges in high impedance state. At the same time an open-drain MOSFET connected to the fault pin (pin.27) is switched on. There are two possible modes subsequent to activating a fault: 4.2 1. SHUTDOWN mode: with FAULT (pull-up resistor) and TRI-STATE pins independent, an activated fault will disable the device, signaling low at the FAULT output. The device may subsequently be reset to normal operation by toggling the TRI-STATE pin from High to Low to High using an external logic signal. 2. AUTOMATIC recovery mode: This is shown in the Audio Application Circuit of Quad single Ended). The FAULT and TRI-STATE pins are shorted together and connected to a time constant circuit comprising R59 and C58. An activated FAULT will force a reset on the TRI-STATE pin causing normal operation to resume following a delay determined by the time constant of the circuit. If the fault condition is still present , the circuit operation will continue repeating until the fault condition is removed . An increase in the time constant of the circuit will produce a longer recovery interval. Care must be taken in the overall system design as not to exceed the protection thesholds under normal operation. Power outputs: The STA518 power and output pins are duplicated to provide a low impedance path for the device's bridged outputs. All duplicate power, ground and output pins must be connected for proper operation. The PWRDN or TRI-STATE pins should be used to set all MOSFETS to the Hi-Z state during power-up until the logic power supply, VL , is settled. 4.3 Parallel output / high current operation: When using DDX Mode output , the STA518 outputs can be connected in parallel in order to increase the output current capability to a load. In this configuration the STA518 can provide 70W into 8 ohm. This mode of operation is enabled with the CONFIG pin (pin.24) connected to VREG1 and the inputs combined INLA=INLB, INRA=INRB and the outputs combined OUTLA=OTLB, OUTRA=OUTRB. 4.4 Additional informations: Output Filter: A passive 2nd-order passive filter is used on the STA518 power outputs to reconstruct an analog Audio Signal . System performance can be significantly affected by the output filter design and choice of passive components. A filter design for 6ohm/8ohm loads is shown in the Typical Application circuit of Figure 9. Quad Single ended circuit (Figure 1) shows a filter for ½ bridge mode, 4 ohm loads. 13/19 Technical information STA518 Figure 8. Typical Stereo Full Bridge Configuration to Obtain 50+50W @ THD = 10%, RL = 8Ω, VCC =29V +VCC VCC1A IN1A 29 VL 23 CONFIG 24 M3 IN1A +3.3V PWRDN R57 10K PWRDN 25 FAULT 27 R59 10K 26 16 M2 PROTECTIONS & LOGIC TH_WAR M5 TH_WAR 28 IN1B 30 VDD 21 VDD 22 VSS 33 VSS 34 OUT1A 14 GND1A 12 VCC1B C31 1µF 11 REGULATORS VCCSIGN 13 GND1B 7 VCC2A C60 100nF VCCSIGN IN2A IN2A GND-Reg GND-Clean IN2B IN2B GNDSUB 9 36 M15 31 20 19 M16 4 VCC2B C33 1µF 3 2 32 OUT2B OUT2B M14 1 5 8Ω C21 100nF C110 100nF C109 330pF R103 6 OUT2A GND2A R100 6 L113 22µH OUT2A 6 C99 100nF C23 470nF C101 100nF R98 6 L19 22µH C32 1µF 8 35 R63 20 OUT1B M17 C53 100nF C20 100nF C52 330pF OUT1B M4 C55 1000µF L18 22µH OUT1A 10 IN1B C58 100nF C30 1µF 17 TRI-STATE C58 100nF 15 R104 20 C107 100nF C108 470nF C106 100nF R102 6 8Ω C111 100nF L112 22µH GND2B D00AU1148B Figure 9. Typical Single BTL Configuration to Obtain 70W @ THD 10%, RL = 8Ω, VCC = 34V (note 1)) VL +3.3V GND-Clean GND-Reg 10K 23 18 N.C. 22µH 100nF 100nF X7R VDD VDD CONFIG TH_WAR TH_WAR PWRDN nPWRDN 10K FAULT IN1A IN1B IN1A IN2A IN2B IN1B VSS VSS 100nF X7R 20 21 22 24 28 25 27 TRI-STATE 100nF 19 VCCSIGN 100nF X7R VCCSIGN Add. GNDSUB 26 29 17 16 11 10 OUT1B OUT1B OUT2A 8 34 22Ω 1/2W 6.2 1/2W 330pF 6.2 1/2W OUT2B 3 2 15 12 7 4 100nF X7R 470nF FILM 100nF X7R 100nF FILM OUT2B 22µH VCC1A VCC1B 32V 1µF X7R VCC2A 32 33 100nF FILM OUT1A OUT2A 9 30 31 OUT1A VCC2B 2200µF 63V 32V 1µF X7R GND1A 14 GND1B 35 13 36 6 1 5 GND2A GND2B D04AU1549 Note: 14/19 1 "A PWM modulator as driver is needed . In particular, this result is performed using the STA308+STA518+STA50X demo board". Peak Power for t ≤1sec 8Ω STA518 5 Characterization curves Characterization curves The following characterization are obtained using the quad single ended configuration (Figure 1) with STA308A controller Figure 10. Power Dissipation vs Output Power Figure 11. Power Derating Curve Pd(W) Pd (W)16 25 1 14 Vcc=30V Rl=4ohm F =1Kz 12 10 20 1)Infinite 2) 1.5 C/W 3 2 3) 3 C/W 4 15 4) 4.5 C/W 8 5) 6 C/W 6 5 10 4 5 2 0 0 4 8 12 16 20 24 20 0 40 60 80 100 120 140 160 Tambient(C) 4 x Pout (W) Figure 12. THD+N vs Output Power Figure 13. Output Power vs Supply Voltage Pout(W) THD(%) 10 30 27.5 Vcc = 26V 5 25 Rl = 4 ohm 22.5 F = 1KHz 2 Rl=4 ohm F=1KHz Single Ended 20 Single Ended 17.5 1 15 THD=10% 12.5 0.5 10 THD=1% 7.5 0.2 5 0.1 100m 200m 500m 1 2 Pout(W) 5 10 20 30 2.5 +10 +12 +14 +16 +18 +20 +22 +24 +26 +28 +30 Vdc Figure 14. THD vs Frequency THD(%) 1 0.5 0.2 Rl=4 ohm 0.1 Pout=1W Single Ended 0.05 0.02 0.01 20 50 100 200 500 1k Freq(Hz) 2k 5k 10k 20k 15/19 Characterization curves STA518 The following characterizations are obtained using the stereo full bridge configuration (Figure 8) with STA308A controller. Figure 15. Output Power vs Supply Voltage o(W) Figure 16. THD+N vs Output Power THD(%) 10 90 5 80 Rl=8ohm 70 2 F=1KHz 1 60 THD=10% 0.5 50 Stereo Full BTL Vcc=29V Rl=8ohm F=1KHz Double BTL 0.2 40 0.1 30 Single Parallel BTL THD=1% 0.05 20 0.02 10 0 +10 +12 +14 +16 +18 +20 +22 +24 +26 +28 +30 +32 0.01 100m +34 +36 200m 500m Vsupply(V) 1 2 Pout(W) 5 10 20 60 Figure 17. Power Dissipation vs Output Power Pd (W) 12 Vcc=29V 10 Rl=8ohm 8 F=1KHz 6 4 2 0 0 10 20 30 2 X Pout (W) 40 50 The following characterizations are obtained using the single BTL configuration (Figure 9) with STA308A controller. Figure 18. THD+N vs Output Power THD(%) 10 5 2 1 0.5 Vcc=34V Rl=8ohm F=1KHz Single BTL 0.2 0.1 0.05 0.02 0.01 100m 16/19 200m 500m 1 2 5 Pout(W) 10 20 50 80 STA518 6 Package information Package information In order to meet environmental requirements, ST offers these devices in ECOPACK® packages. These packages have a Lead-free second level interconnect. The category of second Level Interconnect is marked on the package and on the inner box label, in compliance with JEDEC Standard JESD97. The maximum ratings related to soldering conditions are also marked on the inner box label. ECOPACK is an ST trademark. ECOPACK specifications are available at: www.st.com. Figure 19. PSSO36 (Slug Up) Mechanical Data & Package Dimensions DIM. A A2 a1 b c D (1) E (1) e e3 F G G1 H h L M N O Q S T U X Y MIN. 2.15 2.15 0 0.18 0.23 10.10 mm TYP. 7.4 MAX. 2.47 2.40 0.075 0.36 0.32 10.50 MIN. 0.084 0.084 0 0.007 0.009 0.398 7.6 0.291 0.50 8.50 2.3 0.55 MAX. 0.097 0.094 0.003 0.014 0.012 0.413 OUTLINE AND MECHANICAL DATA 0.299 0.020 0.035 0.090 0.10 0.06 10.50 0.40 0.85 10.10 inch TYP. 0.004 0.002 0.413 0.016 0.033 0.398 0.022 4.3 0.169 10˚ (max) 1.2 0.8 2.9 3.65 1.0 4.10 6.50 0.047 0.031 0.114 0.144 0.039 4.70 7.10 0.161 0.256 0.185 0.279 (1) “D and E” do not include mold flash or protusions. Mold flash or protusions shall not exceed 0.15mm (0.006”) (2) No intrusion allowed inwards the leads. (3) Flash or bleeds on exposed die pad shall not exceed 0.4 mm per side PowerSSO-36 (slug-up) 7618147 A 17/19 Revision history 7 STA518 Revision history Table 9. 18/19 Document revision history Date Revision Changes 19-Aug-2004 1 Initial release. 11-Nov-2004 2 Changed symbol in “Electrical Characteristics”. 18-May-2006 3 Changed operating temperature range value to -40 to 90°C (seeTable 3). STA518 Please Read Carefully: Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at any time, without notice. All ST products are sold pursuant to ST’s terms and conditions of sale. Purchasers are solely responsible for the choice, selection and use of the ST products and services described herein, and ST assumes no liability whatsoever relating to the choice, selection or use of the ST products and services described herein. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted under this document. If any part of this document refers to any third party products or services it shall not be deemed a license grant by ST for the use of such third party products or services, or any intellectual property contained therein or considered as a warranty covering the use in any manner whatsoever of such third party products or services or any intellectual property contained therein. UNLESS OTHERWISE SET FORTH IN ST’S TERMS AND CONDITIONS OF SALE ST DISCLAIMS ANY EXPRESS OR IMPLIED WARRANTY WITH RESPECT TO THE USE AND/OR SALE OF ST PRODUCTS INCLUDING WITHOUT LIMITATION IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE (AND THEIR EQUIVALENTS UNDER THE LAWS OF ANY JURISDICTION), OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT. UNLESS EXPRESSLY APPROVED IN WRITING BY AN AUTHORIZE REPRESENTATIVE OF ST, ST PRODUCTS ARE NOT DESIGNED, AUTHORIZED OR WARRANTED FOR USE IN MILITARY, AIR CRAFT, SPACE, LIFE SAVING, OR LIFE SUSTAINING APPLICATIONS, NOR IN PRODUCTS OR SYSTEMS, WHERE FAILURE OR MALFUNCTION MAY RESULT IN PERSONAL INJURY, DEATH, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE. Resale of ST products with provisions different from the statements and/or technical features set forth in this document shall immediately void any warranty granted by ST for the ST product or service described herein and shall not create or extend in any manner whatsoever, any liability of ST. ST and the ST logo are trademarks or registered trademarks of ST in various countries. Information in this document supersedes and replaces all information previously supplied. The ST logo is a registered trademark of STMicroelectronics. All other names are the property of their respective owners. © 2006 STMicroelectronics - All rights reserved STMicroelectronics group of companies Australia - Belgium - Brazil - Canada - China - Czech Republic - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan Malaysia - Malta - Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States of America www.st.com 19/19