STM6502, STM6503 STM6504, STM6505 Dual push-button Smart ResetTM with user-adjustable setup delays Features ■ Dual Smart Reset push-button inputs with extended reset setup delay ■ Adjustable Smart Reset setup delay (tSRC): by external capacitor or three-state logic (product options): tSRC = 2, 6, 10 s (min.) ■ Power-on reset ■ Single RST output, active-low, open-drain ■ Factory-programmable thresholds to monitor VCC in the range of 1.575 to 4.625 V typ. ■ Operating voltage 1.0 V (active-low output valid) to 5.5 V TDFN8 (DG) 2 mm x 2 mm Applications ■ Mobile phones, smartphones ■ Low supply current ■ e-books ■ Operating temperature: industrial grade –40 °C to +85 °C ■ MP3 players ■ Games ■ Portable navigation devices ■ Any application that requires delayed reset push-button(s) response for improved system stability ■ TDFN8 package: 2 mm x 2 mm x 0.75 mm ■ RoHS compliant Table 1. Device summary Voltage inputs Smart Reset inputs Part number VCC VBAT SR0 SR1 STM6502(1) ✓ ✓ ✓ STM6503 ✓ ✓ ✓ STM6504(1) ✓ ✓ STM6505 ✓ ✓ ✓ tSRC programming SRE Ext. immediate, SRC pin independent Threestate input ✓ ✓ Package RST BLD TSR ✓ ✓ Reset or Power Good outputs ✓ TDFN-8L ✓ ✓ TDFN-8L ✓ ✓ TDFN-8L ✓ ✓ TDFN-8L 1. Contact local ST sales office for availability. June 2010 Doc ID 16101 Rev 5 1/29 www.st.com 1 Contents STM6502, STM6503, STM6504, STM6505 Contents 1 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 1.1 Smart Reset devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 1.2 Pin descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 1.2.1 Power supply (VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 1.2.2 Ground (VSS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 1.2.3 Primary Smart Reset input (SR0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 1.2.4 Secondary Smart Reset input (SR1) . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 1.2.5 Edge-triggered Smart Reset input (SRE pin) – STM6504 only . . . . . . . 11 1.2.6 Adjustable delay of Smart Reset input (SRC pin) – STM6502 and STM6505 only . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 1.2.7 Programmable Smart Reset input delay (TSR pin) – STM6503 and STM6504 only . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 1.2.8 Reset output (RST) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 1.2.9 Battery monitoring input (VBAT) – STM6505 only . . . . . . . . . . . . . . . . . 12 1.2.10 Battery low detect output (BLD) – STM6505 only . . . . . . . . . . . . . . . . . 12 2 Typical operating characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 3 Maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 4 DC and AC parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 5 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 6 Part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 7 Package marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 8 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 2/29 Doc ID 16101 Rev 5 STM6502, STM6503, STM6504, STM6505 List of tables List of tables Table 1. Table 2. Table 3. Table 4. Table 5. Table 6. Table 7. Table 8. Table 9. Table 10. Table 11. Table 12. Table 13. Table 14. Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Signal names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 tSRC programmed by an ideal external capacitor – STM6502 and STM6505 . . . . . . . . . . 11 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Operating and measurement conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 DC and AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 VCC voltage thresholds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 TDFN – 8-lead 2 x 2 x 0.75 mm, 0.5 mm pitch package mechanical data . . . . . . . . . . . . . 21 Parameter for landing pattern - TDFN – 8-lead 2 x 2 mm package . . . . . . . . . . . . . . . . . . 22 Carrier tape dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Reel dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Package marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Doc ID 16101 Rev 5 3/29 STM6502, STM6503, STM6504, STM6505 List of figures List of figures Figure 1. Figure 2. Figure 3. Figure 4. Figure 5. Figure 6. Figure 7. Figure 8. Figure 9. Figure 10. Figure 11. Figure 12. Figure 13. Figure 14. Figure 15. Figure 16. Figure 17. Figure 18. Figure 19. Figure 20. Figure 21. Logic diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Pin connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Block diagram - STM6502, STM6503, STM6504 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Block diagram - STM6505 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Single-button Smart Reset typical hookup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Dual-button Smart Reset typical hookup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 STM6502, STM6503 timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 STM6504 timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 STM6505 timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Supply current (ICC) vs. temperature (STM6505) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Smart Reset delay (tSRC) vs. temperature, CSRC = 0.62 µF (STM6505) . . . . . . . . . . . . . . 13 Reset threshold (VRST) vs. temperature, “S” threshold option, VCC falling (STM6505) . . . 14 VBAT monitoring threshold (VBATTH) vs. temperature, falling (STM6505) . . . . . . . . . . . . . . 14 AC testing input/output waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 TDFN – 8-lead 2 x 2 x 0.75 mm, 0.5 mm pitch package outline . . . . . . . . . . . . . . . . . . . . . 21 Landing pattern - TDFN – 8-lead 2 x 2 mm without thermal pad . . . . . . . . . . . . . . . . . . . . 22 Carrier tape . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Reel dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Tape trailer/leader. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Pin 1 orientation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Package marking, top view . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Doc ID 16101 Rev 5 4/29 STM6502, STM6503, STM6504, STM6505 1 Description Description STM6502 has two combined Smart Reset inputs (SR0 and SR1) with delayed Smart Reset setup time (tSRC) programmed by an external capacitor on the SRC pin. STM6503 is similar to STM6502, has two combined delayed Smart Reset inputs (SR0, SR1) and three user-selectable delayed Smart Reset setup time (tSRC) options of 2 s, 6 s and 10 s through a three-state TSR input pin: when connected to ground, tSRC = 2 s; when left open, tSRC = 6 s; when connected to VCC, tSRC = 10 s (all the times are minimum). STM6504 has two independent Smart Reset inputs. SR0 provides the delayed Smart Reset setup time (tSRC) function with three user-selectable tSRC options through a three-state TSR input pin: when connected to ground, tSRC = 2 s; when left open, tSRC = 6 s; when connected to VCC, tSRC = 10 s (all the times are minimum). SRE provides instant reset. SRE is edge-triggered with a special debounce time (tDEBOUNCE = 240 ms min.) at the falling edge after a valid reset period. STM6505 has two combined delayed Smart Reset inputs (SR0, SR1) and provides an adjustable reset delay setup time via an external capacitor connected to the SRC pin. The RST output depends also on the VCC monitoring threshold. STM6505 also provides independent low battery detect (BLD) output controlled by the secondary external input voltage VBAT. VBAT is monitored for low voltage and provides an indication on the battery low detect output pin (BLD). VBAT threshold is 1.25 V, fixed, and an external resistor divider is to be used to set the actual battery voltage threshold. VBAT threshold hysteresis is 8 mV typ. (16 mV max.). VBAT is voltage monitoring input only, the device is powered only from the VCC pin; VCC must be ≥ 1.575 V for proper operation of the VBAT comparator. 1.1 Smart Reset devices The Smart Reset device family STM65xx provides a useful feature that ensures inadvertent short reset push-button closures do not cause system resets. This is done by implementing extended Smart Reset input delay (tSRC). Once the valid Smart Reset input levels and setup delay are met, the device generates an output reset pulse with user-programmable timeout period (tREC). The Smart Reset inputs can be also connected to the applications interrupt to allow the control of both the interrupt pin and the hard reset functions. If the push-buttons are closed for a short time, the processor is only interrupted. If the system still does not respond properly, holding the push-buttons for the extended setup time (tSRC) causes hard reset of the processor through the reset outputs. The Smart Reset feature helps significantly increase system stability. The STM65xx family of Smart Reset devices consists of low current microprocessor reset circuits targeted at applications such as MP3 players, navigation, smartphones or mobile phones; generally any application that requires delayed reset push-button(s) response for improved system stability. The STM65xx devices feature single or dual Smart Reset inputs (SR). The delayed Smart Reset setup time (tSRC) options of 2 s, 6 s and 10 s (all min.) are adjustable by an external capacitor on the SRC pin or selectable by three-state logic. The delayed setup period ignores switch closures shorter than tSRC, thus preventing unwanted resets. Doc ID 16101 Rev 5 5/29 Description STM6502, STM6503, STM6504, STM6505 The STM65xx devices have active-low (optionally active-high) open-drain reset (RST) output(s) with or without internal pull-up resistor or push-pull as output options, with factoryprogrammed or capacitor-adjustable or push-buttons defined output reset pulse duration, with or without power-on reset function. Some devices also have an undervoltage monitoring feature: the reset output is also asserted when the monitored supply voltage VCC drops below the specified threshold. The reset output remains asserted for the reset timeout period (tREC) after the monitored supply voltage goes above the specified threshold. Figure 1. Logic diagrams VCC VCC SR0 SR0 STM6502 SR1 RST STM6503 SR1 RST TSR SRC VSS VSS VCC VCC SR0 SR0 STM6504 SRE RST RST SR1 STM6505 SRC TSR BLD VBAT VSS VSS AM00378 Figure 2. 6/29 Pin connections RST 1 8 VCC RST 1 8 VCC VSS 2 7 SR0 VSS 2 7 SR0 SR1 3 6 SRC SR1 3 6 TSR NC 4 5 NC NC 4 5 NC STM 6502 STM 6503 RST 1 8 VCC RST 1 8 VCC VSS 2 7 SR0 VSS 2 7 SR0 SRE 3 6 TSR SR1 3 6 SRC NC 4 5 NC BLD 4 5 VBAT STM 6504 Doc ID 16101 Rev 5 STM 6505 AM00379 STM6502, STM6503, STM6504, STM6505 Table 2. Description Signal names Symbol Input/ output RST Output Open-drain reset output, active-low. BLD Output Battery low detect output, active-low, open-drain. STM6505 only. SR0 Input Primary push-button Smart Reset input. Active-low, with or without internal 65 kΩ pull-up to VCC (product options). SR1 Input Secondary push-button Smart Reset input - combines with the primary pushbutton reset to provide setup delay time before reset. Active-low, with or without internal 65 kΩ pull-up to VCC (product options). SRE Input Secondary push-button Smart Reset input - provides instant Smart Reset. SRE is edge-triggered with a special debounce time (tDEBOUNCE = 240 ms min.) at the falling edge after a valid reset period. Active-high, no internal pull-up to VCC. STM6504 only. SRC Input Smart Reset input delay setup control: connect to an external capacitor to adjust the delay setup time (tSRC). STM6502 and STM6505 only. TSR Input A three-state Smart Reset input delay setup control. When connected to ground, tSRC = 2 s; when left open, tSRC = 6 s; when connected to VCC, tSRC = 10 s (all times are minimum). TSR is a DC-type input, intended to be either permanently grounded, permanently connected to VCC or permanently left open. If left open, for improved system glitch immunity it is strongly recommended to connect a 0.1 µF decoupling ceramic capacitor between the TSR and VSS pins. STM6503 and STM6504 only. VCC Supply VBAT Input VSS Supply NC Description Supply voltage input. Power supply for the device and an input for the monitored supply voltage. A 0.1 µF decoupling ceramic capacitor is recommended to be connected between the VCC and VSS pins. Battery voltage monitoring input. STM6505 only. Ground No connect (not bonded); should be connected to VSS. Doc ID 16101 Rev 5 7/29 Description STM6502, STM6503, STM6504, STM6505 Figure 3. Block diagram - STM6502, STM6503, STM6504 VCC SR1 (SRE STM6504 only)(1) SR0 SRC (STM6502) TSR (STM6503, STM6504) VRST COMPARE Logic tREC generator RST Logic AM00352a 1. STM6504 only: SR0 and SRE are working independently. SRE is edge-triggered and has a special debounce time (tDEBOUNCE = 240 ms min.) at the falling edge after a valid reset period. Figure 4. Block diagram - STM6505 6"!4 6## 6"!44( #/-0!2% 6234 #/-0!2% ",$ T2%# GENERATOR 6## 234 32 32 ,OGIC 32# !-B 8/29 Doc ID 16101 Rev 5 STM6502, STM6503, STM6504, STM6505 Figure 5. Description Single-button Smart Reset typical hookup 6## 6## 2%3%4 234 6## 432 34- -#5 32 ).4 .-) 32 633 633 053("544/. 37)4#( !-B Figure 6. Dual-button Smart Reset typical hookup 6## 6## 234 2%3%4 6## 432 34- -#5 32 ).4 .-) 32 633 053("544/. 37)4#( 633 053("544/. 37)4#( !-6 Doc ID 16101 Rev 5 9/29 Description STM6502, STM6503, STM6504, STM6505 1.2 Pin descriptions 1.2.1 Power supply (VCC) This pin is used to provide the power to the device and to monitor the power supply. A 0.1 µF decoupling ceramic capacitor is recommended to be connected between the VCC and VSS pins. 1.2.2 Ground (VSS) This is the supply ground for the device. 1.2.3 Primary Smart Reset input (SR0) The primary push-button Smart Reset input, active-low pin is connected to the first pushbutton switch. 1.2.4 Secondary Smart Reset input (SR1) The secondary push-button Smart Reset input, active-low pin is connected to the second push-button switch. Keeping both Smart Reset inputs SR0 and SR1 active for longer than tSRC activates the reset output pulse. Figure 7. STM6502, STM6503 timing tSRC tREC SR0 SR1 RST AM00327 Reset is asserted “low” right after the Smart Reset setup delay (tSRC) has been met and returns to high after the tREC period. 10/29 Doc ID 16101 Rev 5 STM6502, STM6503, STM6504, STM6505 1.2.5 Description Edge-triggered Smart Reset input (SRE pin) – STM6504 only The SRE pin is active-high, immediate and independent reset input that includes an edge trigger with debounce delay tDEBOUNCE on the falling edge. Note: The triggering edge must be a high-to-low or low-to-high transition with a slew-rate faster than 1 V/µs typ. Figure 8. STM6504 timing t < tDEBOUNCE => tREC timer reset t < tSRC => no output response tSRC SR0 Independent SRE RST No debounce tREC tDEBOUNCE tREC (rising edges within tDEBOUNCE are ignored) 1.2.6 tREC AM00328V2 Adjustable delay of Smart Reset input (SRC pin) – STM6502 and STM6505 only This pin controls the setup time before the push-button action is validated by the reset output. It is connected to an external capacitor (CSRC), which is tied to ground to provide the desired value of the setup time (tSRC). Calculated tSRC and CSRC examples are given in Table 3. Refer also to Table 6. Table 3. tSRC programmed by an ideal external capacitor – STM6502 and STM6505 Calculated CSRC value [µF] Setup delay tSRC [s](1)(2) Min. Typ. Max. Closest common CSRC value [µF] 0.2 2 2.5 3.0 0.22 0.3 3 3.75 4.5 0.33 0.6 6 7.5 9 0.56 1 10 12.5 15 1 1. At 25 °C. Example calculations based on an ideal capacitor. During application design and component selection it should be considered that the current flowing into the external tSRC programming capacitor (CSRC) is on the order of 100 nA, therefore a low-leakage capacitor (ceramic or film capacitor) should be used and placed as close as possible to the SRC pin. Also an adequate low-leakage PCB environment should be ensured to prevent tSRC accuracy from being affected. A recommended minimum value of CSRC is 0.01 µF. 2. In case of repeated activations of the tSRC timer, an interval of 10 ms min. is needed between the activations to fully discharge C SRC, so that the next tSRC is as specified. Doc ID 16101 Rev 5 11/29 Description 1.2.7 STM6502, STM6503, STM6504, STM6505 Programmable Smart Reset input delay (TSR pin) – STM6503 and STM6504 only The TSR pin allows the user to program the setup time before the push-button action is validated by the reset output. It is controlled by different voltage levels on the three-state TSR input pin: when connected to ground, tSRC = 2 s; when left open, tSRC = 6 s; when connected to VCC, tSRC = 10 s (all times are minimum). TSR is a DC-type input, intended to be either permanently grounded, permanently connected to VCC or permanently left open. If it is left open, for improved system glitch immunity it is strongly recommended to connect a 0.1 µF decoupling ceramic capacitor between the TSR and VSS pins. 1.2.8 Reset output (RST) RST is the active-low, open-drain reset output in the Smart Reset family. 1.2.9 Battery monitoring input (VBAT) – STM6505 only VBAT is an input for monitoring the battery voltage. VBAT threshold is 1.25 V, fixed, and an external resistor divider is to be used to set the actual battery voltage threshold. 1.2.10 Battery low detect output (BLD) – STM6505 only The battery low detect output is controlled by the VBAT voltage monitoring input and is active-low, open-drain, with no pull-up. Figure 9. STM6505 timing tSRC tREC SR0 SR1 RST VBAT VBATTH BLD AM00329 12/29 Doc ID 16101 Rev 5 STM6502, STM6503, STM6504, STM6505 2 Typical operating characteristics Typical operating characteristics Figure 10. Supply current (ICC) vs. temperature (STM6505) 3 2.5 ICC [μA] 2 1.5 1 0.5 0 -60 -40 -20 0 20 40 60 80 100 120 140 Temperature [°C] 5.5 V 2V 5V 3V AM04886v1 Figure 11. Smart Reset delay (tSRC) vs. temperature, CSRC = 0.62 µF (STM6505) 9.2 8.7 tSRC [s] 8.2 7.7 7.2 6.7 6.2 -60 -40 -20 0 20 40 60 80 100 120 140 Temperature [°C] 5.75 V 5.5 V 3.3 V Doc ID 16101 Rev 5 AM04887v1 13/29 Typical operating characteristics STM6502, STM6503, STM6504, STM6505 Figure 12. Reset threshold (VRST) vs. temperature, “S” threshold option, VCC falling (STM6505) 2.99 2.97 VRST [V] 2.95 2.93 2.91 2.89 2.87 2.85 -60 -40 -20 0 20 40 60 80 100 120 140 Temperature [°C] AM04888v1 Figure 13. VBAT monitoring threshold (VBATTH) vs. temperature, falling (STM6505) 1.275 1.27 1.265 1.26 VBATTH [V] 1.255 1.25 1.245 1.24 1.235 1.23 1.225 -60 -40 -20 0 20 40 60 80 100 120 140 Temperature [°C] 5.75 V 14/29 5.5 V 3.3 V Doc ID 16101 Rev 5 2V 1.58 V AM04889v1 STM6502, STM6503, STM6504, STM6505 3 Maximum ratings Maximum ratings Stressing the device above the rating listed in Table 4: Absolute maximum ratings may cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions above those indicated in the operating sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Refer also to the STMicroelectronics SURE Program and other relevant quality documents. Table 4. Absolute maximum ratings Symbol TSTG Parameter Storage temperature (VCC off) TSLD(1) Lead solder temperature for 10 seconds θ JA Thermal resistance (junction to ambient) VIO Input or output voltage VCC Supply voltage TDFN8 Value Unit –55 to +150 °C 260 °C 149.0 °C/W –0.3 to 5.5(2) V –0.3 to 7 V 1. Reflow at peak temperature of 260 °C. The time above 255 °C must not exceed 30 seconds. 2. For inputs or outputs with internal pull-up resistors and push-pull type outputs –0.3 to VCC +0.3 V only. Doc ID 16101 Rev 5 15/29 DC and AC parameters 4 STM6502, STM6503, STM6504, STM6505 DC and AC parameters This section summarizes the operating measurement conditions, and the DC and AC characteristics of the device. The parameters in the DC and AC characteristics tables that follow, are derived from tests performed under the measurement conditions summarized in Table 5: Operating and measurement conditions. Designers should check that the operating conditions in their circuit match the operating conditions when relying on the quoted parameters. Table 5. Operating and measurement conditions Parameter Value Unit VCC supply voltage 1.0 to 5.5 V Ambient operating temperature (TA) –40 to +85 °C ≤ 5 ns Input pulse voltages 0.2 to 0.8 V CC V Input and output timing ref. voltages 0.3 to 0.7 V CC V Input rise and fall times Figure 14. AC testing input/output waveforms 16/29 0.8 VCC 0.7 VCC 0.2 VCC 0.3 VCC Doc ID 16101 Rev 5 AM00478 STM6502, STM6503, STM6504, STM6505 Table 6. DC and AC characteristics Symbol VCC DC and AC parameters Test conditions(1) Parameter Supply voltage range Reset output valid - active-low STM6502 STM6503 (3) VCC = 5.0 V, TSR left open VCC = 3.0 V, TSR left open Supply current (inputs in their inactive state) STM6504 STM6505 Unit 5.5 V µA 1.1 µA 5.8 3 4 (3) 2.3 V(3) µA µA 5.8 3 VCC = 5.0 V VCC = 3.0 Max. 1.2 4 (3) VCC = 5.0 V, TSR left open VCC = 3.0 V, TSR left open Typ.(2) 1.0 VCC = 5.0 V VCC = 3.0 V ICC Min. µA µA 3.3 2.2 µA µA Output characteristics VOL tREC Reset output voltage low (reset asserted: RST, BLD) Reset timeout delay, factory-programmed VCC ≥ 4.5 V, sinking 3.2 mA 0.3 V VCC ≥ 3.3 V, sinking 2.5 mA 0.3 V VCC ≥ 1.0 V, sinking 0.1 mA 0.3 V Option A 140 210 280 ms Option B 240 360 480 ms –40 to +85 °C VRST –2.5% VRST VRST +2.5% V 25 °C VRST –2.0% VRST VRST +2.0% V VCC monitoring reset thresholds VRST Fixed voltage trip point for VCC monitoring (refer to Table 7) L, M VHYST Hysteresis of VRST VCC to reset delay 0.5% T, S, R, Z, Y, W, V 1% VCC falling from (VRST + 100 mV) to (VRST - 100 mV) at 10 mV/µs(4) 20 µs VBAT monitoring VBATTH Fixed VBAT monitoring threshold STM6505 only VBATHYST VBATTH hysteresis STM6505 only ILI(VBAT) VBAT input leakage current STM6505 only Doc ID 16101 Rev 5 1.225 –100 1.25 1.275 V 8 16 mV 10 100 nA 17/29 DC and AC parameters Table 6. STM6502, STM6503, STM6504, STM6505 DC and AC characteristics (continued) Symbol Test conditions(1) Parameter Min. Typ.(2) Max. Unit Smart Reset inputs VIL SR0, SR1, SRE input voltage low VSS –0.3 0.3 VCC V VIH SR0, SR1, SRE input voltage high 0.7 VCC 5.5 V ILI(SR) Input leakage current, SR and SRE inputs Option without internal pull-up resistor –1 +1 µA ILI(TSR) Input leakage current, TSR input STM6503 and STM6504 only –5 +7 µA RPUI Internal pull-up resistor, input (optional - refer to Table 12) tDEBOUNCE SRE input falling edge debounce time 65 STM6504 only kΩ 240 360 480 ms TA = 25 °C 10 x CSRC (µF) 12.5 x CSRC (µF) 15 x CSRC (µF) s TSR = VSS 2 2.5 3 s 6 7.5 9 s 10 12.5 15 s Smart Reset delay tSRC (5) Capacitor-programmable Smart Reset setup time, STM6502 and STM6505. Refer to Table 3. tSRC (5) TSR pin-programmable Smart Reset setup time, STM6503 and STM6504. TSR = floating(6) TSR = VCC 1. Valid for ambient operating temperature: TA = –40 to +85 °C; VCC = 1.0 to 5.5 V (except where noted). 2. Typical value is at 25 °C and VCC = 3.3 V unless otherwise noted. 3. For devices with VRST < 3.0 V. 4. Guaranteed by design. 5. Input glitch immunity is equal to tSRC (when both SR inputs are low, otherwise infinite). STM6502, STM6503, STM6505 only. 6. If left open, for improved system glitch immunity it is strongly recommended to connect a 0.1 µF decoupling ceramic capacitor between the TSR and VSS pins. 18/29 Doc ID 16101 Rev 5 STM6502, STM6503, STM6504, STM6505 . Table 7. DC and AC parameters VCC voltage thresholds VCC monitoring threshold VRST ±2.5% (–40 °C to +85 °C) ±2.0% (25 °C) Typ. Unit Min. Max. Min. Max. L (falling) 4.625 4.509 4.741 4.533 4.718 V M (falling) 4.375 4.266 4.484 4.288 4.463 V T (falling) 3.075 2.998 3.152 3.014 3.137 V S (falling) 2.925 2.852 2.998 2.867 2.984 V R (falling) 2.625 2.559 2.691 2.573 2.678 V Z (falling) 2.313 2.255 2.371 2.267 2.359 V Y (falling) 2.188 2.133 2.243 2.144 2.232 V W (falling) 1.665 1.623 1.707 1.632 1.698 V V (falling) 1.575 1.536 1.614 1.544 1.607 V Doc ID 16101 Rev 5 19/29 Package mechanical data 5 STM6502, STM6503, STM6504, STM6505 Package mechanical data In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK® packages, depending on their level of environmental compliance. ECOPACK® specifications, grade definitions and product status are available at: www.st.com. ECOPACK® is an ST trademark. 20/29 Doc ID 16101 Rev 5 STM6502, STM6503, STM6504, STM6505 Package mechanical data Figure 15. TDFN – 8-lead 2 x 2 x 0.75 mm, 0.5 mm pitch package outline D A B PIN 1 INDEX AREA E 0.10 C 2x 0.10 C 2x TOP VIEW 0.10 C C A1 A SEAT ING PLANE SIDE VIEW 0.08 C e b PIN 1 INDEX AREA 1 4 0.10 C A B Pin#1 ID L 5 8 BOTTOM VIEW 8070540_A Table 8. TDFN – 8-lead 2 x 2 x 0.75 mm, 0.5 mm pitch package mechanical data Dimension (mm) Dimension (inches) Symbol Min. Nom. Max. Min. Nom. Max. A 0.70 0.75 0.80 0.028 0.030 0.031 A1 0.00 0.02 0.05 0.000 0.001 0.002 b 0.15 0.20 0.25 0.006 0.008 0.010 D BSC 1.9 2.00 2.1 0.075 0.079 0.083 E BSC 1.9 2.00 2.1 0.075 0.079 0.083 e L 0.50 0.45 0.55 0.020 0.65 Doc ID 16101 Rev 5 0.018 0.022 0.026 21/29 Package mechanical data STM6502, STM6503, STM6504, STM6505 Figure 16. Landing pattern - TDFN – 8-lead 2 x 2 mm without thermal pad D P E E1 L b Table 9. AM00441 Parameter for landing pattern - TDFN – 8-lead 2 x 2 mm package Dimension (mm) Parameter 22/29 Description Min. Nom. Max. L Contact length 1.05 — 1.15 b Contact width 0.25 — 0.30 E Max. land pattern Y-direction — 2.85 — E1 Contact gap spacing — 0.65 — D Max. land pattern X-direction — 1.75 — P Contact pitch — 0.5 — Doc ID 16101 Rev 5 STM6502, STM6503, STM6504, STM6505 Package mechanical data Figure 17. Carrier tape P0 D P2 T E A0 F Top cover tape W B0 Center lines of cavity K0 P1 User direction of feed AM03073v2 Table 10. Carrier tape dimensions Package W D TDFN8 8.00 +0.30 –0.10 1.50 +0.10/ –0.00 E P0 P2 F 1.75 4.00 2.00 3.50 ±0.10 ±0.10 ±0.10 ±0.05 A0 B0 K0 P1 T 2.30 ±0.05 2.30 ±0.05 1.00 ±0.05 4.00 ±0.10 0.250 ±0.05 Doc ID 16101 Rev 5 Unit Bulk qty. mm 3000 23/29 Package mechanical data STM6502, STM6503, STM6504, STM6505 Figure 18. Reel dimensions T 40 mm min. acces hole at slot location B D C N A Full radius Tape slot in core for tape start 25 mm min width G measured at hub AM00443 Table 11. 24/29 Reel dimensions Tape sizes A max. B min. C D min. N min. G T max. 8 mm 180 (7 inches) 1.50 13.0 +/– 0.20 20.20 60 8.4 +2/–0 14.40 Doc ID 16101 Rev 5 STM6502, STM6503, STM6504, STM6505 Package mechanical data Figure 19. Tape trailer/leader End Top cover tape Start No components Components 100 mm min. T RA IL ER No components L EA D ER 160 mm min. 400 mm min. Sealed with cover tape User direction of feed AM00444 Figure 20. Pin 1 orientation User direction of feed Note: 1 Drawings are not to scale. 2 All dimensions are in mm, unless otherwise noted. Doc ID 16101 Rev 5 AM00442 25/29 Part numbering STM6502, STM6503, STM6504, STM6505 6 Part numbering Table 12. Ordering information scheme Example: STM6505 W C A B DG 6 F Device type STM6502(1) STM6503 STM6504(1) STM6505 Reset (VCC monitoring) threshold voltage (VRST), typ., falling L = 4.625 V S = 2.925 V R = 2.625 V Z = 2.313 V W = 1.665 V V = 1.575 V Smart Reset setup delay (tSRC); presence of internal input pull-up on all Smart Reset inputs (SRx, SRE) A = user-programmable (external capacitor); no input pull-up C = user-programmable (external capacitor); 65 kΩ input pull-up E = 2 or 6 or 10 s min., user-programmable (three-state); no input pull-up F = 2 or 6 or 10 s min., user-programmable (three-state); 65 kΩ input pull-up Output type A = open-drain, no pull-up, active-low Reset timeout period (tREC) A = 140 ms min. B = 240 ms min. Package DG = TDFN8 2 x 2 x 0.75 mm, 0.5 mm pitch Temperature range 6 = –40 °C to +85 °C Shipping method F = ECOPACK® package, tape and reel 1. Contact local ST sales office for availability. For device options currently available refer to Table 13. For other options, voltage threshold values etc. or for more information on any aspect of this device, please contact the ST sales office nearest you. 26/29 Doc ID 16101 Rev 5 STM6502, STM6503, STM6504, STM6505 7 Package marking Package marking Table 13. Package marking tSRC delay control Smart Reset inputs(1) VRST RST output(1) TSR AL V AL, OD A — 3VG TSR AL S AL, OD B — 4SG STM6505SCABDG6F CSRC AL, PU S AL, OD B AL, OD 5SK STM6505RCABDG6F CSRC AL, PU R AL, OD B AL, OD 5RK STM6505WCABDG6F CSRC AL, PU W AL, OD B AL, OD 5WK Part number STM6503VEAADG6F STM6504SEABDG6F (2) tREC BLD option output(1) Topmark 1. AL = active-low, AH = active-high, PU = with internal pull-up resistor, OD = open-drain. 2. Contact local ST sales office for availability. Figure 21. Package marking, top view A B C D E Topmark A = dot (pin 1 reference) B = assembly plant (P) C = assembly year (Y, 0-9): 9 = 2009 etc. D = assembly work week (WW, 01 to 52): 20 = WW20 etc. E = marking area (topmark) AM00479 Doc ID 16101 Rev 5 27/29 Revision history 8 STM6502, STM6503, STM6504, STM6505 Revision history Table 14. Document revision history Date Revision 31-Aug-2009 1 Initial release. 06-Nov-2009 2 Updated Applications, Section 1, Section , Figure 3 to Figure 6 updated and moved to Section , updated Table 1, Table 2, Table 3, Table 4, Table 6, Table 12, Section 1.2.3, Section 1.2.7, Section 1.2.9, Section 5, added package footprint, tape and reel information, and Section 7. 15-Jan-2010 3 Updated Features, Section 1, Section 1.2.6, Table 1, Table 2, Figure 5, Figure 6, Table 3, Table 6, Table 12, Table 13, removed Table 4. 01-Mar-2010 4 Updated title of datasheet, Features, Applications, Table 1, 2, 6, 12, footnote 5 of Table 6; updated Figure 3, 4; added Section 2: Typical operating characteristics; minor textual and formatting changes. 5 Updated Features, Section 1, Figure 8, footnote 1 and 2 of Table 3, updated Table 4, added footnote 2 to Table 4, Table 6, added footnote 6 to Table 6, updated Table 6 to Table 9, and added footnote 2 of Table 13. 21-Jun-2010 28/29 Changes Doc ID 16101 Rev 5 STM6502, STM6503, STM6504, STM6505 Please Read Carefully: Information in this document is provided solely in connection with ST products. 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