STPMS2 Smart sensor II dual-channel 1-bit, 4 MHz, second-order sigma-delta modulator with embedded PGLNA Features ■ VCC supply range 3.2 V - 5.5 V ■ Two second-order sigma-delta (ΣΔ) modulators ■ Programmable chopper-stabilized low noise and low offset amplifier ■ Supports 50-60 Hz, EN 50470-1, EN 50470-3, IEC 62053-21, IEC 62053-22 and IEC 6205323 standards specs for class 1, class 0.5 and class 0.2 AC watt meters ■ STPM02H: less than 0.5% error over 1:10000 range ■ STPM02L: less than 0.5% error over 1:5000 range ■ Precision voltage reference: 1.23 V with programmable TC (STPMS2L only) ■ Internal low drop regulator @ 3 V (typ.) Applications ■ Power metering ■ Motor control ■ Industrial process control ■ Weight scales ■ Pressure transducers QFN16 (4 x 4) or multi-phase energy meters along with the STPMC1 device, a digital signal processor designed for energy measurement. This device can be used in medium and high resolution measurement applications where single or double inputs must be monitored at the same time. The STPMS2 are mixed signal ICs consisting of an analog and digital section. The analog section consists of a programmable gain, low noise choppered amplifier, two second-order ΔΣ modulator blocks, a band-gap voltage reference, a low-drop voltage regulator and DC buffers, while the digital section consists of a clock generator and output multiplexer. Description The STPMS2, also called “smart sensor” devices, are ASSPs designed for effective measurement in power line systems utilizing Rogowski coil, current transformer, Hall or shunt sensors. These devices are designed as building blocks for single-phase Table 1. Device summary Order codes Package Packaging STPMS2H-PUR QFN16 (4 x 4 mm) 4500 parts per reel STPMS2L-PUR QFN16 (4 x 4 mm) 4500 parts per reel October 2011 Doc ID 16525 Rev 3 1/33 www.st.com 33 Contents STPMS2 Contents 1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 2 Internal block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 3 Pin configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 4 Maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 4.1 General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 5 Application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 6 Terminology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 6.1 Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 6.2 Notation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 7 Typical performance characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 8 Theory of operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 8.1 General operation description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 8.2 Functional description of the analog part . . . . . . . . . . . . . . . . . . . . . . . . . 17 8.3 Functional description of the digital part . . . . . . . . . . . . . . . . . . . . . . . . . . 20 8.3.1 Decoder for different modes of operation . . . . . . . . . . . . . . . . . . . . . . . 21 8.3.2 Generator for clock frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 8.4 Hard mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 8.5 Soft mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 8.5.1 Writing to the configuration register in Soft mode . . . . . . . . . . . . . . . . . 27 9 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 10 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 2/33 Doc ID 16525 Rev 3 STPMS2 1 Introduction Introduction The STPMS2 is a device designed to measure electrical line parameters (voltage and current) via analog signals from voltage sensors (current divider) and current sensors (inductive Rogowski coil, current transformer or shunt resistors). The device is used together with a digital signal processing circuit to implement an effective measuring system for multi-phase power meters. The device consists of two analog measuring channels, consisting of second-order sigmadelta modulators with appropriate non-overlapping control signal generator. The STPMS2 also includes a temperature compensated band-gap reference voltage generator, a lowdrop supply voltage stabilizer and minimal digital circuitry that includes BIST (built-in selftest) structures. In a current signal processing channel, a low-noise preamplifier is included in front of the sigma-delta converter. All reference voltages (band-gap, AGND) are internally buffered to eliminate channel crosstalk. The STPMS2 can operate in fast or low-power mode. In fast mode, a nominal clock frequency of 4.1 or 4.9 MHz is applied to the clock input. In this mode, signal bandwidth is specified between 0 and 4 kHz. In low-power mode, the nominal clock is four times slower in order to reduce the power consumption of the circuit. In low-power mode, the quiescent bias currents of the preamplifier and sigma-delta integrators are lowered and the signal bandwidth is narrowed to the frequency bandwidth of 0 to 1 kHz. Doc ID 16525 Rev 3 3/33 Internal block diagram STPMS2 2 Internal block diagram Figure 1. STPMS2 internal block diagram VDDav EINCHPV VIP DAT VIN 2nd ord ΣΔ modulator MUX MV, NV ECHPLFV, ECHPHFV EPRSV MS3 PDV EINCHPC, EINCHPV BIST DAC DATN GAIN EPRSV ECHPLFC, ECHPHFC MC, NC DIGITAL FRONT END MS2 GAIN MS1 MUX CIP 2nd ord ΣΔ modulator PLNA MS0 CIN CLK EINCHPC VDDac VCC TC VRefV VOLTAGE REFERENCE LDR VRefC GND VDDa VBG AM09892v1 4/33 Doc ID 16525 Rev 3 Figure 2. Pin connections VCC 1 VDDac 2 MS3 Pin configuration CLK 3 DAT Pin configuration DATn STPMS2 16 15 14 13 12 MS2 11 MS1 GND Table 2. VBG 4 9 VDDav 5 6 7 8 VIP MS0 VIN 10 CIP 3 CIN VDDa AM09382v1 Pin description Pin n° Symbol Description 1 VCC 2 VDDac Current channel modulator supply input 3 VDDa Output of internal + 3.0 V low drop regulated power supply 4 VBG Output of internal + 1.23 V bias generator (STPMS2L); Input of external precision reference voltage (STPMS2H) 5 CIN Current channel - 6 CIP Current channel + 7 VIN Voltage channel - 8 VIP Voltage channel + 9 VDDav 10 MS0 Input for configurator 0 11 MS1 Input for configurator 1 12 MS2 Input for configurator 2 13 MS3 Input for configurator 3 14 CLK Input for external measurement clock 15 DAT Output of multiplexed ΣΔ signal Output of current ΣΔ signal 16 DATn Output of inverted multiplexed ΣΔ signal Output of voltage ΣΔ signal Exp PAD GND Ground level for signals and pin protection Unregulated supply voltage for pad-ring, bandgap, low-drop and level shifters Voltage channel modulator supply input Doc ID 16525 Rev 3 5/33 Maximum ratings STPMS2 4 Maximum ratings Table 3. Absolute maximum ratings Symbol Parameter VCC DC Input voltage IPIN Current on any pin (sink/source) VID Input voltage at any pin VIA Input voltage at analog pins (VIP, VIN, IIP, IIN) Value Unit -0.3 to 6 V ±150 mA -0.3 to VCC +0.3 V -0.7 to 0.7 V ±2 kV ESD Human body model (all pins) TOP Operating ambient temperature -40 to 85 °C Junction temperature -40 to 150 °C Storage temperature range -55 to 150 °C TJ TSTG Note: Absolute maximum ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is not implied. Table 4. Thermal data Symbol Parameter Value Unit RthJA (1) Thermal resistance junction-ambient 38.66 °C/W 1. This value is referred to single-layer PCB, JEDEC standard test board. 6/33 Doc ID 16525 Rev 3 STPMS2 4.1 Maximum ratings General operating conditions VCC = 5 V, TAMB = 25 °C, 1 µF between VCC, VDDa, VDDac, VDDav and GND, 100 nF between VBG and GND, fCLK = 4.19 MHZ unless otherwise specified. Table 5. General operating conditions Symbol Parameter Test conditions Min. Typ. Max. Unit 5.25 V General section VCC Operating supply voltage 3.135 LP, 1.229MHz; VCC=3.3V; CL=100nF; no loads ICC Power on reset on VCC VDD Regulated supply voltage fBW 1.5 mA HP, 4.915MHz; VCC=3.2V; CL=100nF; no loads VPOR ILATCH 1.2 Quiescent current 4 2.5 1.049MHz; VCC=3.2V; CL=100nF; no loads 2.95 3.00 Limited by chopper V 3.05 V 300 mA 0 4091 Hz 11 16 bit Current injection latchup immunity Effective bandwidth 5 DC measurement accuracy Resolution INL DNL Integral non linearity Differential linearity Offset error Gain error Result referred to a 16-bit word of CIPCIN channel, HP mode, fCLK= 2.047MHz 3.3 Result referred to a 12-bit word of VIPVIN channel, HP mode, fCLK=2.047MHz 3.9 Result referred to a 16-bit word of CIPCIN channel, HP mode, fCLK=2.047MHz 0.3 Result referred to a 12-bit word of VIPVIN channel, HP mode, fCLK=2.047MHz 0.5 Result referred to a 16-bit word of CIPCIN channel, HP mode, fCLK=2.047MHz 0.02 Result referred to a 12 bit-word of VIPVIN channel, HP mode, fCLK=2.047MHz 0.005 Result referred to a 16-bit word of CIPCIN channel, HP mode, fCLK=2.047MHz Result referred to a 12-bit word of VIPVIN channel, HP mode, fCLK=2.047MHz NF Noise floor LSB LSB LSB 0.04 0.4 LSB/uV 0.003 CIP-CIN channel gain 2x 120 CIP-CIN channel gain 16x 118 VIP-VIN channel 95 Doc ID 16525 Rev 3 dB 7/33 Maximum ratings Table 5. Symbol PSRRDC STPMS2 General operating conditions (continued) Parameter Power supply DC rejection Test conditions Voltage signal: 200 mVrms/50Hz Current signal: 10 mVrms/50Hz fCLK=2.048 MHz VCC=3.3V ±10%, 5V ±10% Min. Typ. Max. 90 Unit dB AC measurement accuracy CIP-CIN channel – Vin=±230mV @ 55Hz gain 2x over 4 kHz bandwidth SNR SINAD THD SFDR PSRRAC 82 Signal to noise ratio Signal to noise ratio + distortion dB VIP-VIN channel – Vin=±230mV @ 55Hz over 4 kHz bandwidth 52 CIP-CIN channel – Vin=±230mV @ 55Hz gain 2x over 4 kHz bandwidth 82 dB VIP-VIN channel – Vin=±230mV @ 55Hz over 4 kHz bandwidth 52 CIP-CIN channel – Vin=±230mV @ 55Hz gain 2x over 4 kHz bandwidth -105 Total harmonic distortion Spurious free dynamic range Power supply AC rejection dB VIP-VIN channel – Vin=±230mV @ 55Hz over 4 kHz bandwidth -78 CIP-CIN channel – Vin=±230mV @ 55Hz gain 2x over 4 kHz bandwidth 90 dB VIP-VIN channel – Vin=±230mV @ 55Hz over 4 kHz bandwidth 68 Voltage signal: 200 mVrms/50Hz Current signal: 10 mVrms/50Hz fCLK=2.048 MHz VCC=3.3V+0.2Vrms1@100Hz VCC=5.0V+0.2Vrms1@100Hz 120 VIP-VIN channel -0.3 +0.3 -0.3 -0.15 -0.075 -0.0375 -VREF/ GAIN +0.3 +0.15 +0.075 +0.0375 +VREF/ GAIN dB Analog inputs (CIP, CIN, VIP, VIN) VMAX Maximum input signal levels STPMS2L Gain 2x Gain 4x Gain 8x Gain 16x CIP-CIN channel STPMS2H CIP-CIN channel fSPL A/D sampling frequency Voff Amplifier offset ZIP VIP, VIN impedance Over total operating voltage range ZIN CIP, CIN impedance Over total operating voltage range GERR Gain error of current channels 8/33 fCLK V Hz ±20 mV 100 400 kΩ 35 50 kΩ ±10 Doc ID 16525 Rev 3 V % STPMS2 Maximum ratings Table 5. General operating conditions (continued) Symbol Parameter Test conditions IILV Voltage channel leakage VCC=5.25V, fCLK=4.19MHz current IILI VCC=5.25V, fCLK=4.19MHz Current channel leakage VCC=5.25V, fCLK=4.19MHz input current enabled Min. Max. Unit -1 1 µA -1 1 -10 10 Crosstalk between channels Typ. 130 dB Digital I/O (CLK, DAT, DATN, MS0, MS1, MS2, MS3) 0.75VC VIH Input High voltage VIL Input Low Voltage VOH Output high voltage IO=-1mA, CL=50pF, VCC=3.2V VOL Output low voltage IO=+1mA, CL=50pF, VCC=3.2V IUP Pull up current tTR Transition time CLOAD=50pF Latency From 50% of CLK to 50% to DAT tL 5.3 V 0.25VC V C -0.3 C VCC-0.4 V 0.4 V 15 µA 10 ns 40 ns Clock input fCLK Nominal frequencies Low precision mode 1.0 1.228 High precision mode 2.0 2.458 Very high precision mode 4.0 4.915 STPMS2L only (1) 1.21 MHz On chip reference voltage VREF Reference voltage Zout Output impedance IL Maximum load current TC Temperature coefficient 1.23 30 1.25 V 200 kΩ 0 After calibration 30 µA 50 ppm/°C 1. This level may be delivered from external source in STPMS2H. Doc ID 16525 Rev 3 9/33 Maximum ratings Figure 3. STPMS2 Timing diagram AM09383v1 CLK - clock signal on CLK pin CLKsample - sigma-delta sampling frequency bsV - sigma-delta bit stream of voltage signal bsC - sigma-delta bit stream of current signal DATA - multiplexed data of voltage and current signal on DAT pin 10/33 Doc ID 16525 Rev 3 STPMS2 Application The choice of external components in the transduction section of the application is a crucial point in the application design, affecting the precision and the resolution of the entire system. Among the several considerations, a compromise should be found between the following requirements: 1. Maximize the signal-to-noise ratio in the voltage and current channel 2. Choose the current-to-voltage conversion ratio Ks and the voltage divider ratio in a way that calibration can be achieved 3. Choose Ks to take advantage of the whole current dynamic range in accordance with desired maximum current and resolution. To maximize the signal-to-noise ratio of the current channel, the voltage divider resistors ratio should be as close as possible to those shown in Table 6. Figure 4 below provides a reference application schematic diagram: ● P = 64000 imp/kWh ● INOM = 5 A ● IMAX = 60 A Typical sensitivity values for the current sensors are indicated inTable 6. Figure 4. Detailed application schematic L N VCC C14 C5 C6 1µ 1µ 1µ R7 1K 1% R8 1K 1% C8 4.7n cin 2 1 17 U1 STPMS2H/L 18 VDD e1 e2 5 3 VDDac 4 C7 4.7n R6 3.3 1% VDDa E4622_X503 VBG L3 e3 e4 19 20 16 6 DATn cip DAT 7 vin CLK 15 14 DAT CLK VN VL R3 150k R2 150k 10n 9 MS3 10 11 13 MS2 vip C3 MS1 R5 470 1% MS0 8 VDDav 5 Application 12 R4 150k C9 CLK L1 1µ LOAD 1µ MS0 = MS1 = MS2 = MS3 = CLK HP Ampl x4 0 TC = 50 ppm/rC 0 Voltage channel ON, DAT =(CLK)? bsV : bsC 0 HardMode, BIST Mode OFF AM09379v1 Doc ID 16525 Rev 3 11/33 Application Table 6. STPMS2 Recommended external components in metering applications Function Line voltage interface Component Description Value Calculator STPMC1 --- Resistor divider R to R ratio VRMS=230V 1:1650 R to R ratio VRMS=110V 1:830 Rogowski coil Line current interface CT Current-to-voltage ratio KS Shunt Tolerance Unit --- --- --- ±1% 50ppm/°C V/V 50ppm/°C mV/A 0.15 ±5% 1.7 ±5% 0.43 ±5% Note: Above listed components refer to typical metering application. Anyhow, STPMS2 operation is not limited to the choice of these external components. Figure 5. Simplified application schematics for STPMC1 based energy metering S e ns or Cur r e nt R S TN Ant i Al i a s i ng Ne t wor k MS 0 CIP MS 1 MS 2 MS 3 CL K CIN DAT VIP S e ns or Cur r e nt VIN VCC MS 0 Ant i Al i a s i ng Ne t wor k DAT n VBG GND MS 1 MS 2 CIP VDD MS 3 CL K CL K DAT DAS DAT CIN DAR VIP S e ns or Cur r e nt VIN VCC MS 0 Ant i Al i a s i ng Ne t wor k Ca lc ula t or S T PM C1 A DAT n VBG GND MS 1 MS 2 CIP VDD MS 3 CL K CIN DAT VIP VIN VCC DAT n VBG GND VDD LOAD 12/33 AM09893v1 Doc ID 16525 Rev 3 STPMS2 Figure 6. Application Connection schematics for DSP-based applications Sensor 1 MS0 MS1 MS2 CIP Anti Aliasing Network MS3 CLK DSP CIN DAT Sensor 2 CLKOUT DATIN VIP Anti Aliasing Network DATn VIN VCC VBG GND VDD AM09380v1 Doc ID 16525 Rev 3 13/33 Terminology 6 Terminology 6.1 Conventions STPMS2 The lowest analog and digital power supply voltage is called GND which represents the system ground. All voltage specifications for digital input/output pins are referred to GND. The highest power supply voltage is called VCC. The highest core power supply is internally generated and is called VDD. Positive currents flow into a pin. Sinking current means that the current is flowing into the pin and thus it is positive. Sourcing current means that the current is flowing out of the pin and thus it is negative. A positive logic convention is used in all equations. 6.2 Notation Output bit streams of the modulator are indicated as bsV and bsC for voltage and current channels, respectively. 14/33 Doc ID 16525 Rev 3 STPMS2 Typical performance characteristics 7 Typical performance characteristics Figure 7. VREF/VREF at 25 deg vs. temp Figure 8. SNHR of I channel, gain 16x AM09901v1 90 80 70 60 SNHR [dB] 50 40 30 20 Current 16x, Fsig = 55Hz, HP mode 2.047MHz, 3.3V, -30deg Current 16x, Fsig = 55Hz, HP mode 2.047MHz, 3.3V, 0deg 10 Current 16x, Fsig = 55Hz, HP mode 2.047MHz, 3.3V, 25deg 0 Current 16x, Fsig = 55Hz, HP mode 2.047MHz, 3.3V, 60deg Current 16x, Fsig = 55Hz, HP mode 2.047MHz, 3.3V, 85deg -10 10 100 1000 10000 100000 1000000 I peak-peak [µV] Figure 9. SNHR of I channel, gain 2x Figure 10. SNHR of V channel, gain 2x AM09902v1 90 AM09903v1 60 80 50 70 40 60 30 50 SNHR [dB] SNHR [dB] 20 40 30 10 0 20 -10 Current 2x, Fsig = 55Hz, HP mode 2.047MHz, 3.3V, -30deg 10 Current 2x, Fsig = 55Hz, HP mode 2.047MHz, 3.3V, 0deg 0 Voltage 2x, Fsig = 55Hz, HP mode 2.047MHz, 3.3V, -30deg Voltage 2x, Fsig = 55Hz, HP mode 2.047MHz, 3.3V, 0deg -20 Voltage 2x, Fsig = 55Hz, HP mode 2.047MHz, 3.3V, 25deg Current 2x, Fsig = 55Hz, HP mode 2.047MHz, 3.3V, 25deg -30 Current 2x, Fsig = 55Hz, HP mode 2.047MHz, 3.3V, 60deg -10 -40 -20 10 100 1000 10000 100000 1000000 Voltage 2x, Fsig = 55Hz, HP mode 2.047MHz, 3.3V, 60deg Voltage 2x, Fsig = 55Hz, HP mode 2.047MHz, 3.3V, 85deg Current 2x, Fsig = 55Hz, LP mode 2.047MHz, 3.3V, 85deg 100 10000000 1000 10000 100000 1000000 10000000 U peak-peak [µV] I peak-peak [µV] Figure 11. SINAD of I channel, gain 16x (temp. Figure 12. SINAD of I channel, gain 16x (temp. variation) variation) AM09904v1 50 70 40 60 30 50 20 40 30 AM09905v1 60 80 SINAD [dB] SINAD [dB] 90 10 0 20 Current 16x, Fsig = 55Hz, HP mode 2.047MHz, 3.3V, -30deg -10 Voltage 2x, Fsig = 55Hz, HP mode 2.047MHz, 3.3V, -30deg Current 16x, Fsig = 55Hz, HP mode 2.047MHz, 3.3V, 0deg 10 Voltage 2x, Fsig = 55Hz, HP mode 2.047MHz, 3.3V, 0deg -20 Current 16x, Fsig = 55Hz, HP mode 2.047MHz, 3.3V, 25deg 0 Current 16x, Fsig = 55Hz, HP mode 2.047MHz, 3.3V, 60deg Voltage 2x, Fsig = 55Hz, HP mode 2.047MHz, 3.3V, 25deg -30 Voltage 2x, Fsig = 55Hz, HP mode 2.047MHz, 3.3V, 60deg Current 16x, Fsig = 55Hz, HP mode 2.047MHz, 3.3V, 85deg -10 Voltage 2x, Fsig = 55Hz, HP mode 2.047MHz, 3.3V, 85deg -40 10 100 1000 10000 100000 1000000 100 I peak-peak [µV] 1000 10000 100000 1000000 10000000 U peak-peak [µV] Doc ID 16525 Rev 3 15/33 Typical performance characteristics STPMS2 Figure 13. Relative gain error of I channel, gain 16x AM09899v1 1.1 AM09900v1 1.1 1.08 1.08 1.06 1.06 1.04 1.04 Relative Gain Error [ - ] Relative Gain Error [ - ] Figure 14. Relative gain error of I channel, gain 2x 1.02 1 0.98 0.96 Current 32x, Current 32x, Current 32x, Current 32x, Current 32x, Current 32x, Current 32x, Current 32x, 0.94 0.92 0.9 10 100 1000 10000 Fsig Fsig Fsig Fsig Fsig Fsig Fsig Fsig = 55Hz, = 55Hz, = 55Hz, = 55Hz, = 55Hz, = 55Hz, = 55Hz, = 55Hz, HP mode 2.455MHz, HP mode 2.455MHz, HP mode 2.047MHz, HP mode 2.047MHz, LP mode 1.229MHz, LP mode 1.229MHz, LP mode 1.048MHz, LP mode 1.048MHz, 100000 1.02 1 0.98 0.96 3.3V 5.0V 3.3V 5.0V 3.3V 5.0V 3.3V 5.0V Current 4x, Current 4x, Current 4x, Current 4x, Current 4x, Current 4x, Current 4x, Current 4x, 0.94 0.92 0.9 10 1000000 100 1000 10000 100000 Fsig Fsig Fsig Fsig Fsig Fsig Fsig Fsig = 55Hz, HP mode 2.455MHz, 3.3V = 55Hz, HP mode 2.455MHz, 5.0V = 55Hz, HP mode 2.047MHz, 3.3V = 55Hz, HP mode 2.047MHz, 5.0V = 55Hz, LP mode 1.229MHz, 3.3V = 55Hz, LP mode 1.229MHz, 5.0V = 55Hz, LP mode 1.048MHz, 3.3V = 55Hz, LP mode 1.048MHz, 5.0V 1000000 10000000 I peak-peak [µV] I peak-peak [µV] Figure 15. Accuracy over dynamic range AM09906v1 0.5% 0.4% 0.3% 0.2% 0.1% AW Error [%] 0.035% 0.035% 0.0% -0.096% -0.1% -0.096% 0.040% 0.027% -0.008% -0.065% -0.096% 0.076% 0.097% -0.087% -0.087% -0.2% Class 0.2 limits -0.3% -0.352% -0.4% -0.487% -0.435% -0.5% -0.6% 0.01% 0.10% 1.00% 10.00% % of FS 16/33 Doc ID 16525 Rev 3 100.00% 1000.00% STPMS2 Theory of operation 8 Theory of operation 8.1 General operation description The STPMS2 performs second-order analog modulation of two channels in parallel, with appropriate non-overlapping control signal generator, of signals with frequencies varying from DC to 4 kHz on two independent channels in parallel. The outputs of the converters provide two streams of digital ones and zeros which can be then be multiplexed in time to reduce the number of external connections. The STPMS2 converts analog signals on two independent channels in parallel via deltasigma (ΣΔ) analog-to-digital converters into a binary stream of sigma-delta signals. The device is particularly suitable to measure electrical line parameters (voltage and current) via analog signals from voltage sensors (current divider) and current sensors (inductive Rogowski coil, current transformer or shunt resistors). There is a current channel for measuring line current and a voltage channel for measuring line voltage. The current channel input is connected through an external anti-aliasing RC filter to a Rogowski coil, current transformer (CT) or shunt current sensor which converts line current into an appropriate voltage signal. The current channel includes a low-noise voltage preamplifier with programmable gain. The voltage channel is connected directly through a resistor voltage divider and anti-aliasing filter to a line voltage modulator (ADC). Both channels have quiescent zero signal point at GND, so the STPMS2 is able to sample differential signals on both channels with their zero point around GND. The converted ΣΔ signals are multiplexed in time in order to reduce the number of external connections. The conversion and the multiplex are driven by external clock signal CLK. The device is used in conjunction with a digital signal processing circuit to implement an effective measuring system of a multi-phase power meter. The STPMS2 also includes a temperature compensated band-gap reference voltage generator, low-drop supply voltage regulator and minimal digital circuitry that includes BIST (built-in self-test) structures. In a current signal processing channel, a low-noise preamplifier is included upstream of the sigma-delta converter. All reference voltages are designed to eliminate channel crosstalk. The STPMS2 can operate in fast (HP) or low-power (LP) mode (see also Table 7). In fast mode, a nominal clock frequency of up to 4.1 / 4.9 MHz is applied to the clock input. In this mode, signal bandwidth is specified between 0 and 4 kHz. In low-power mode, the nominal clock is four times slower (1 MHz) to lower the power consumption of the circuit. In lowpower mode, the quiescent bias currents of the preamplifier and sigma-delta integrators are reduced and the signal bandwidth is narrowed to the frequency bandwidth of 0 to 1 kHz. The mode of operation and configuration of the device can be selected by wiring configuration pins (MS0, MS1, MS2 and MS3) to VCC, GND, CLK or NCLK signal. This approach can be used to change the settings of a current channel, sigma-delta stream output mode and temperature compensation curve of an internal band-gap reference. These pins can act as a serial port to change the configuration of the device. 8.2 Functional description of the analog part The supply pins for the analog part are VCC, VDDa, VDDac, VDDav, VBG and GND. The GND pin also represents a reference point. The VDDa is an analog I/O pin of the internal +3.0 V low drop voltage regulator and the VDDac and VDDav are the modulator Doc ID 16525 Rev 3 17/33 Theory of operation STPMS2 supply inputs. A 1 µF capacitor should be connected between VDDxx and GND. The input of the regulator is VCC, which also powers the band-gap and bias generators. The band-gap output is VBG, which should be connected to GND via a 100 nF capacitor. MS3 CLK DATn Analog Supply 3.3 - 5.0 V DAT Figure 16. Power supply external connection scheme MS2 VCC 1 µF VDDac MS1 1 µF GND VDDa MS0 VBG VDDav 1 µF VIP VIN CIP CIN 100 nF AM09381v1 The analog part of the STPMS2 consists of: ● pre-amplifier in the current channel ● 1.23 V reference voltage generator (STPMS2L only) ● +3 V low-drop supply voltage regulator ● two sigma-delta 2nd order modulators ● BIST DAC ● AGND and VREF reference buffers ● bias current generators The voltage channel has a pre-amplification gain of 2, which defines the maximum differential voltage on voltage channel inputs to ± 300 mV. The relative gain of the current channel is selectable among 2, 4, 8 or 16, which defines the maximum differential voltage on the current channel to ± 300 mV, ± 150 mV, ± 75 mV or ± 37.5 mV, respectively. The full range of gains is available only in soft mode (see Section 8.5), while in hard mode only 2 and 16 are selectable. The temperature-compensated reference voltage generator produces VREF = 1.23 V. This generator is implemented as a band gap generator, whose temperature compensation curve can be selected through configuration. The low drop regulator fixes and stabilizes the core supply voltage to VDDa = 3 V. All digital pads tolerate 5 V logic levels. The STPMS2 is clocked by an external clock signal connected to pin CLK. The STPMS2L sigma-delta modulators work in several operating modes, shown in Table 7 below. 18/33 Doc ID 16525 Rev 3 STPMS2 Table 7. Theory of operation Operating modes Device fCLK Current consumption LPR (low precision) STPMS2L 1 MHZ 1,2 mA typ HPR (high precision) STPMS2L 2 MHz – 4MHz HHPR (very high precision) STPMS2H 4 MHz Operating mode LP (low power) HP (fast) 4 mA typ LPR (low precision): fCLK = 1 MHz and settings defined by MS0 through MS3 HPR (high precision): the normal mode of operation with fCLK = 2 MHz to 4 MHz The STPMS2H sigma-delta modulators work in the following mode: HHPR (very high precision) external reference must be connected to VBG, fCLK = 4 MHz. The STPMS2 performs operations in 2 basic modes: Hard mode and Soft mode. In Hard mode the configuration is set through external pins MS0, MS1, MS2 and MS3. In Soft mode, 40 configuration bits can be accessed through CFG[39:0], via serial communication. The pins used for serial communication are: MS0, MS1 and MS2. Switching between Hard and Soft modes is achieved through pin MS3. ● Hard mode: In this case the device configuration is bootstrapped at startup and signals come from VIN and VIP for voltage channels, and CIP and CIN for current channels or from internal BIST DAC. ● Soft mode: In this mode all possible settings from Hard mode are accessible, as well as the additional settings described in Section 8.5. Figure 17. Block diagram of the modulator dithering input - ∫ - 1 st integrator a1 stream out ∫ 2 nd integrator comparator a2 D/A AM09894v1 The STPMS2 sends to the DAT and DATn pins selected signals based on the configuration used. Both outputs have cross-current and slew rate limiters to prevent excessive current spikes on supply lines. Doc ID 16525 Rev 3 19/33 Theory of operation STPMS2 Figure 18. Example of sigma-delta modulator output in case of sinusoidal waveform AM09895v1 8.3 Functional description of the digital part The digital section (DFE) includes: ● a decoder for different modes of operation ● a generator for clock frequency ● level shifters, pull-up stages and power buffers outside the DFE block Figure 19. Block diagram and definition of DFE digital signals Outputs f or analog part Clock Generator MS0 MS1 MS2 MS3 Clock signals Chopper DECODER CLK Pseudo Random DOMUL DTMC DAT Sigma-Delta streams Synchro CLK Mux DATn CLK AM09896v1 20/33 Doc ID 16525 Rev 3 STPMS2 8.3.1 Theory of operation Decoder for different modes of operation The decoder defines the operating mode according to the state of the bootstrap MS0, MS1, MS2 and MS3 pins. Two different operational modes can be defined: 8.3.2 ● Hard mode: In this case the device configuration is bootstrapped at startup and signals come from VIN and VIP for voltage channels, and CIP and CIN for current channels or from internal BIST DAC. ● Soft mode: In this mode all possible settings from Hard mode are accessible, as well as additional settings such as dither and chopper signal frequencies and operation (see Section 8.5). Generator for clock frequency Chopper and BIST frequency generator The Chopper block generates the chopper frequencies and BIST signals for the voltage and current channels. The BIST DAC output levels are appropriately adjusted for the current channel according to the gain selection, while for the voltage channel the max DC voltage is used. The levels are 300 mV for the voltage channel and 300 mV / 150 mV / 75 mV / 37.5 mV for the current channel, in accordance with gain settings 2/4/8/16, respectively, when operating in Soft mode, while 300 mV / 37.5 mV based on gain settings 2/16 when operating in Hard mode. Pseudo random The Pseudo random block generates pseudo random signals for the voltage and current channels. These random signals are used to implement a dithering technique to decorrelate the output of the modulators and avoid accumulation points on the frequency spectrum. Synchro In Synchro block the synchronization of sigma-delta input streams with strobe signals from analog part and clock signal is performed. Mux In the Mux block, which signals are connected to output pins DAT and DATn are selected. In HardMode, the output signals are selected by input pin MS2. In SoftMode, the output signals are selected by 8 configuration bits. 8.4 Hard mode The STPMS2 operates in Hard mode when input pin MS3 is connected to GND or VCC, as described in Table 11. In Hard mode, the STPMS2 has four digital input pins (MS0, MS1, MS2 and MS3) to configure the basic operating parameters: ● BIST DAC enable ● temperature curve of reference voltage ● current and voltage channels settings ● output mode settings Doc ID 16525 Rev 3 21/33 Theory of operation STPMS2 In this way it is possible to access 128 different combinations, which are controlled through pins MS0, MS1, MS2 and MS3. MS0 sets the operating mode and amplifier gain selection as described in Table 8. For the STPMS2L: ● MS0=GND or CLK to select LPR (low precision); fCLK = 1 MHz is the typical input clock frequency and low power mode is selected. ● MS0=NCLK or VCC to select HPR (high precision): fCLK = 2 MHz is the typical input clock frequency and accuracy is enhanced. For the STPMS2H, LPR mode is not used and the settings should be chosen between MS0=NCLK or VCC. In this case, fCLK = 4 MHz is typical. The relative gain of the current channel is selectable between 2 or 16, which defines the maximum differential voltage on the current channel to ± 300 mV or ± 37.5 mV, respectively. The voltage channel gain setting is fixed at 2, which defines the maximum differential voltage on the voltage channel inputs to ± 300 mV. Table 8. Precision mode and input amplifier gain selection MS0 Mode Description GND 0 LPR, amplifier GAIN selection g3 = 16 CLK 1 LPR, amplifier GAIN selection g0 = 2 NCLK 2 HPR, amplifier GAIN selection g0 = 2 VCC 3 HPR, amplifier GAIN selection g3 = 16 MS1 defines the temperature compensation (TC) curve of the internal voltage reference of the STPMS2L, as described in Table 9. This bootstrap function is not used with the STPMS2H. The temperature-compensated reference voltage generator produces VREF = 1.23 V. This generator is implemented as a band gap generator, whose temperature compensation curve can be selected through the MS1 configuration pin. Table 9. TC of the band-gap reference MS1 Mode Description GND 0 TC = 60 ppm/°C CLK 1 Flattest TC = +30 ppm/°C NCLK 2 TC = +160 ppm/°C VCC 3 TC = -160 ppm/°C MS2 defines the outputs of the device: The STPMS2 sends to the DAT and DATn pins the sigma-delta streams synchronous to the CLK signal. The output mode can be configured according to Table 10 as follows: 22/33 ● The output current channel's sigma-delta stream on DAT and the voltage channel's sigma-delta stream on DATn ● Output multiplexed signals, so when CLK = 0, the current channel output sigma-delta value is set on the DAT pin, and when CLK = 1, the voltage channel output sigma-delta value is set on the DAT pin. The DATn pin tracks DAT, so DATn = ~DAT. ● Output current channel's sigma-delta stream on DAT and the current channel's sigmadelta stream negated on DATn Doc ID 16525 Rev 3 STPMS2 Table 10. Theory of operation Control of voltage channel and output signals MS2 Mode Description GND 0 Voltage channel ON, DATn = ~ [DAT =(CLK) ? bsV : bsC)] CLK 1 Voltage channel OFF, DATn = bsCn, DAT = bsC NCLK 2 Voltage channel OFF, DATn = bsCn, DAT = bsC VCC 3 Voltage channel ON, DATn = bsC, DAT = bsV MS3 enables or disables the BIST DAC output levels. If enabled (MS3=VCC), the input of the modulators are disconnected from pin VIP, VIN and CIP, and CIN, and connected to the output of BIST DAC which generates 2 different levels appropriately adjusted for the current channel 300 mV / 37.5 mV depending on gain settings 2/16, while for the voltage channel, 300 mV is used. This mode is used as auto diagnostic methodology of good behavior of the two modulators. When disabled (MS3=GND), the input of the modulators comes from pins VIP, VIN and CIP, and CIN. This is the normal operating condition. Table 11. Selection of Hard, Soft or Test mode and enable of BIST MS3 Mode GND 0 HardMode, BIST mode OFF CLK 1 Soft mode NCLK 2 Reserved VCC 3 HardMode, BIST mode ON 8.5 Description Soft mode The STPMS2 switches to Soft mode when MS3 is connected to CLK. In Soft mode, input pins MS0, MS1 and MS2 control the serial communication port, as described in Table 12. This way, all settings of the 40 internal configuration bits can be changed. The old values remain in the registers until they are overwritten. Table 12. Pins for SPI communication Pin Function Description MS0 SCL Clock input MS1 TDI Data input MS2 TDS Enable MS3 CLK SPI operation Doc ID 16525 Rev 3 23/33 Theory of operation Table 13. Hard mode STPMS2 Description of output signals and configuration bits CFG[39:0] Soft mode MS0 CFG[0] MS0 CFG[1] MS0 CFG[2] MS1 CFG[3] MS1 CFG[4] MS2 CFG[5] Internal signal LP/HP Operating mode: LP/HP=0: LPR LP/HP=1: HPR GAIN Gain selector of current channel pre-amplifier: GAIN=0: x2 GAIN=1: x4 GAIN=2: x8 GAIN=3: x16 TC MS2 MS3 CFG[6] CFG[7] Description Temperature compensation of voltage reference: TC=0: TC = 60 ppm/°C TC=1: Flattest TC = +30 ppm/°C TC=2: TC = +160 ppm/°C TC=3: TC = -160 ppm/°C DOMUL Output multiplexer enable: DOMUL=0: outputs not multiplexed DOMUL=1: outputs multiplexed PDV Power-down of voltage modulator: PDV=0: Voltage modulator on PDV=1: Voltage modulator off EBISTC Current modulator BIST DAC enable: EBISTC=0: BISTC disabled EBISTC=1: BISTC enabled – EBISTC Frequency output 0 0 1 CLK/215 x LFC Voltage modulator BIST DAC enable: EBISTC=0: BISTV disabled EBISTC=1: BISTV enabled – EBISTV Frequency output 0 0 1 CLK/215 x LFV MS3 CFG[8] EBISTV MS3 CFG[9] EINCHPC CIP, CIN input pin enable: EINCHPC=0: CIN CIP disabled EINCHPC=1: CIN CIP enabled MS3 CFG[10] EINCHPV VIP, VIN input pin enable: EINCHPC=0: VIN VIP disabled EINCHPC=1: VIN VIP enabled 1 CFG[11] ECHPLFC Low frequency chopper of current modulator enable: ECHPLFC=0: LFC disabled ECHPLFC=1: LFC enabled (1) 24/33 Doc ID 16525 Rev 3 STPMS2 Table 13. Theory of operation Description of output signals and configuration bits CFG[39:0] (continued) Hard mode Soft mode 1 CFG[12] 0 CFG[13] Internal signal MC 0 CFG[14] 1 CFG[15] 1 CFG[16] 1 CFG[17] ECHPHFC NC 0 CFG[18] 1 CFG[19] 1 CFG[20] 0 CFG[21] ECHPLFV MV 0 1 CFG[22] CFG[23] ECHPHFV Description LFC of current channel frequency selector: – MC[2:0] Frequency 000 CLK/1024 CLK/512 001 (1) 010 CLK/256 011 CLK/128 100 CLK/64 CLK/64 101 (2) CLK/64 110 (2) (2) CLK/64 111 High Frequency Chopper of current modulator enable: ECHPHFC=0: HFC disabled ECHPHFC=1: HFC enabled (1) HFC of current channel frequency selector – NC[2:0] Frequency CLK/256 000 (2) CLK/128 001 (2) 010 CLK/256 CLK/128 011 (1) 100 CLK/64 101 CLK/32 110 CLK/16 111 CLK/8 Low Frequency Chopper of voltage modulator enable: ECHPLFV=0: LFV disabled ECHPLFV=1: LFV enabled (1) LFC of voltage channel frequency selector: – MV[2:0] Frequency 000 CLK/1024 (1) CLK/512 001 010 CLK/256 011 CLK/128 100 CLK/64 CLK/64 101 (2) CLK/64 110 (2) CLK/64 111 (2) High Frequency Chopper of voltage modulator enable: ECHPHFC=0: HFV disabled ECHPHFC=1: HFV enabled (1) Doc ID 16525 Rev 3 25/33 Theory of operation Table 13. STPMS2 Description of output signals and configuration bits CFG[39:0] (continued) Hard Mode Soft mode 1 CFG[24] 1 CFG[25] Internal signal NV Description HFC of voltage channel frequency selector: – NV[2:0] Frequency CLK/256 000 (2) CLK/128 001 (2) 010 CLK/256 CLK/128 011 (1) 100 CLK/64 101 CLK/32 110 CLK/16 111 CLK/8 0 CFG[26] 1 CFG[27] EPRSC Current modulator pseudo random signals enable: EPRSC=0: PRSC disabled EPRSC=1: PRSC enabled (1) 1 CFG[28] EPRSV Voltage modulator pseudo random signals enable: EPRSV=0: PRSV disabled EPRSV=1: PRSV enabled (1) 0 CFG[29] - Reserved 0 CFG[30] - Reserved 0 CFG[31] - Reserved 0 CFG[32] 0 CFG[33] 0 CFG[34] 0 CFG[35] 0 CFG[36] DTMC DAT and DAT output signal selector: – DTMC[5:0] pdV domul DAT 00XXXX 0 0 bsV 00XXXX 0 1 (bsV,bsC) 00XXXX 1 0 bsC 00XXXX 1 1 bsC 01XX00 0 0 bsV 01XX01 0 1 (bsV,bsC) 01XX10 1 0 bsC 01XX11 1 1 bsC 1000XX 0 0 LFV 1001XX 0 1 HFV 1010XX 1 0 BISTV 1011XX 1 1 PRSV 110000 X X LFV 110101 X X HFV 111010 X X BISTV 111111 X X PRSV 0 CFG[37] 0 CFG[38] - Reserved 0 CFG[39] - Reserved 1. Default value for Hard mode 2. Combinations not used 26/33 Doc ID 16525 Rev 3 DATn bsC (bsVn,bsCn) bsCn bsCn LFC HFC BISTC PRSC bsC (bsVn,bsCn) bsCn bsCn LFC HFC BISTC PRSC STPMS2 8.5.1 Theory of operation Writing to the configuration register in Soft mode All 40 configuration bits must be overwritten. Figure 20. Timings to switch to Soft mode after POR CLK MS0/SCL CFG[0] MS1/TDI CFG[1] CFG[2] CFG[38] CFG[39] MS2/TDS MS3/CLK delay1 NEW values CFG AM09897v1 1. After power-on reset, Soft mode is selected (MS3=CLK), the bits MS0 .. MS2 must be stable at least 5*CLK Figure 21. Timings to switch to Soft mode CLK MS0/SCL MS1/TDI CFG[0] CFG[1] CFG[2] CFG[3] CFG[38] CFG[39] MS2/TDS MS3/CLK delay2 OLD values CFG NEW values Hard Mode AM09898v1 2. After switching into Soft mode (MS3=CLK), the bits MS0 .. MS2 must be stable at least 2*CLK. The same rule applies when switching from Soft mode to Hard mode: MS0 .. MS2 must be stable at least 2*CLK Doc ID 16525 Rev 3 27/33 Package mechanical data 9 STPMS2 Package mechanical data In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK® packages, depending on their level of environmental compliance. ECOPACK® specifications, grade definitions and product status are available at: www.st.com. ECOPACK® is an ST trademark. Table 14. QFN16 (4 x 4 mm.) mechanical data mm. Dim. Min. Typ. Max. A 0.80 0.90 1.00 A1 0.00 0.02 0.05 A3 0.20 b 0.25 0.30 0.35 D 3.90 4.00 4.10 D2 2.50 E 3.90 E2 2.50 e L 28/33 2.80 4.00 4.10 2.80 0.65 0.30 Doc ID 16525 Rev 3 0.40 0.50 STPMS2 Package mechanical data Figure 22. QFN16 (4 x 4 mm.) drawing 7571203_A Doc ID 16525 Rev 3 29/33 Package mechanical data STPMS2 Tape & reel QFNxx/DFNxx (4x4) mechanical data mm. inch. Dim. Min. Typ. A Min. Typ. 330 C 12.8 D 20.2 N 99 13.2 Max. 12.992 0.504 0.519 0.795 101 T 30/33 Max. 3.898 3.976 14.4 0.567 Ao 4.35 0.171 Bo 4.35 0.171 Ko 1.1 0.043 Po 4 0.157 P 8 0.315 Doc ID 16525 Rev 3 STPMS2 Package mechanical data Figure 23. QFN16 (4 x 4) footprint recommended data (dimension in mm.) Doc ID 16525 Rev 3 31/33 Revision history STPMS2 10 Revision history Table 15. Document revision history Date Revision 23-Oct-2009 1 Initial release. 06-Jul-2011 2 Document status promoted from preliminary data to datasheet. 11-Oct-2011 3 Modified: 100 µF ==> 100 nF Section 8.2 on page 17. 32/33 Changes Doc ID 16525 Rev 3 STPMS2 Please Read Carefully: Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at any time, without notice. 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