8-BIT SHIFT REGISTER DESCRIPTION FEATURES ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ SY10E141 SY100E141 700MHz min. shift frequency Extended 100E VEE range of –4.2V to –5.5V 8 bits wide Bi-directional Four selectable modes for full functionality Asynchronous Master Reset Fully compatible with industry standard 10KH, 100K ECL levels Internal 75KΩ input pulldown resistors Fully compatible with Motorola MC10E/100E141 Pin-compatible with E241 Available in 28-pin PLCC package The SY10/100E141 are 8-bit, full-function shift registers designed for use in new, high-performance ECL systems. The E141 performs serial/parallel in and serial/parallel out, shifting in either direction. The eight inputs D0–D7 accept parallel input data, while DL/DR accept serial input data for left/right shifting. The two select pins, SEL0 and SEL1 permit four modes of operation: Load, Hold, Shift Left and Shift Right, as shown in the Truth Table. Input data is clocked into the register on the rising clock edge after meeting the minimum set-up time. A logic HIGH on the Master Reset (MR) pin asynchronously resets all the registers to zero. BLOCK DIAGRAM DL BITS 1-6 D DR D0 Q D R D Q R Q0 R Q7 Q D Q D7 SEL1 SEL0 CLK MR Rev.: C 1 Amendment: /1 Issue Date: February, 1998 SY10E141 SY100E141 Micrel PIN NAMES D5 VCCO Q7 SEL0 DL D7 D6 PIN CONFIGURATION Pin Function D0-D7 Parallel Data Inputs DL, DR Serial Data Inputs SEL1 26 18 Q6 SEL0, SEL1 Mode Select Inputs CLK MR VEE DR 27 17 CLK Clock 28 16 Q5 VCC NC Q0-Q7 Data Outputs VCCO Q4 Q3 MR Master Reset VCCO VCC to Output 25 24 23 22 21 20 19 PLCC TOP VIEW J28-1 1 2 D0 3 D1 4 15 14 13 12 7 8 9 10 11 DL DR SEL0 SEL1 MR CLK Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 Load X X L L L Z D0 D1 D2 D3 D4 D5 D6 D7 Shift Right X X L H L L H H L L Z Z L H Q0 L Q1 Q0 Q2 Q1 Q3 Q2 Q4 Q3 Q5 Q4 Q6 Q5 Shift Left L H X X H H L L L L Z Z L Q0 Q0 Q1 Q1 Q2 Q2 Q3 Q3 Q4 Q4 Q5 Q5 L L H Hold X X X X H H H H L L Z Z Q0 Q0 Q1 Q1 Q2 Q2 Q3 Q3 Q4 Q4 Q5 Q5 L L H H Reset X X X X H X L L L L L L L L D2 D3 Q0 Q1 Q2 6 D4 VCCO 5 TRUTH TABLE Function DC ELECTRICAL CHARACTERISTICS VEE = VEE (Min.) to VEE (Max.); VCC = VCCO = GND TA = 0°C Symbol Parameter TA = +25°C Min. Typ. Max. Min. Typ. IIH Input HIGH Current IEE Power Supply Current 10E 100E TA = +85°C Max. Min. Typ. Max. Unit Condition µA — mA — — — 150 — — 150 — — 150 — — 131 131 157 157 — — 131 131 157 157 — — 131 151 157 181 2 SY10E141 SY100E141 Micrel AC ELECTRICAL CHARACTERISTICS VEE = VEE (Min.) to VEE (Max.); VCC = VCCO = GND TA = 0°C Symbol Parameter TA = +25°C Min. Typ. Max. Min. Typ. TA = +85°C Max. Min. Typ. Max. Unit Condition MHz — ps — ps — ps — fSHIFT Max. Shift Frequency 700 900 — 700 900 — 700 900 — tPLH tPHL Propagation Delay to Output CLK MR 625 600 750 725 975 975 625 600 750 725 975 975 625 600 750 725 975 975 tS Set-up Time D SEL0 SEL1 175 350 300 25 200 150 — — — 175 350 300 25 200 150 — — — 175 350 300 25 200 150 — — — Hold Time D SEL0 SEL1 200 100 100 –25 –200 –150 — — — 200 100 100 –25 –200 –150 — — — 200 100 100 –25 –200 –150 — — — tRR Reset Recovery Time 900 700 — 900 700 — 900 700 — ps — tPW Minimum Pulse Width CLK, MR 400 — — 400 — — 400 — — ps — tskew Within-Device Skew — 60 — — 60 — — 60 — ps 1 tr tf Rise/Fall Time 20% to 80% 300 525 800 300 525 800 300 525 800 ps — tH NOTE: 1. Within-device skew is defined as identical transitions on similar paths through a device. PRODUCT ORDERING CODE Ordering Code Package Type Operating Range SY10E141JC J28-1 Commercial SY10E141JCTR J28-1 Commercial SY100E141JC J28-1 Commercial SY100E141JCTR J28-1 Commercial 3 SY10E141 SY100E141 Micrel 28 LEAD PLCC (J28-1) Rev. 03 MICREL-SYNERGY TEL 3250 SCOTT BOULEVARD SANTA CLARA CA 95054 USA + 1 (408) 980-9191 FAX + 1 (408) 914-7878 WEB http://www.micrel.com This information is believed to be accurate and reliable, however no responsibility is assumed by Micrel for its use nor for any infringement of patents or other rights of third parties resulting from its use. No license is granted by implication or otherwise under any patent or patent right of Micrel Inc. © 2000 Micrel Incorporated 4