6-BIT D REGISTER FEATURES DESCRIPTION ■ 1100MHz toggle frequency ■ Extended 100E VEE range of –4.2V to –5.46V The SY10/100E151 offer 6 edge-triggered, high-speed, master-slave D-type flip-flops with differential outputs, designed for use in new, high-performance ECL systems. The two external clock signals (CLK1, CLK2) are gated through a logical OR operation before use as clocking control for the flip-flops. Data is clocked into the flip-flops on the rising edge of either CLK1 or CLK2 (or both). When both CLK1 and CLK2 are at a logic LOW, data enters the master and is transferred to the slave when either CLK1 or CLK2 (or both) go HIGH. The MR (Master Reset) signal operates asynchronously to make all Q outputs go to a logic LOW. ■ ■ ■ ■ Differential outputs Asynchronous Master Reset Dual clocks Fully compatible with industry standard 10KH, 100K ECL levels ■ Internal 75KΩ input pulldown resistors ■ Fully compatible with Motorola MC10E/100E151 ■ Available in 28-pin PLCC package BLOCK DIAGRAM R VCCO Q5 Q5 Q0 D CLK1 NC PIN CONFIGURATION MR CLK2 D0 SY10E151 SY100E151 Q0 25 24 23 22 21 20 19 Q1 27 17 Q4 VCC Q3 D2 2 D1 3 D0 4 Q2 28 15 14 13 12 5 Q3 16 PLCC TOP VIEW J28-1 1 Q4 D R D5 Q4 D4 D3 VEE Q3 D R D4 18 Q2 D R D3 26 6 7 8 9 Q3 Q2 Q2 10 11 VCCO D2 D5 Q0 R Q1 Q0 Q1 Q1 D NC VCCO D1 Q4 Q5 D R PIN NAMES Q5 CLK1 CLK2 Pin M R Function D0–D5 Data Inputs CLK1, CLK2 Clock Inputs MR Master Reset Q0–Q5 True Outputs Q0–Q5 Inverting Outputs VCCO VCC to Output Rev.: D 1 Amendment: /0 Issue Date: November, 1998 SY10E151 SY100E151 Micrel TRUTH TABLES(1) Synchronous Operation Asynchronous Operation Inputs Inputs Output Output Dn CLK1 CLK2 MR Qn(t + 1) Dn CLK1 CLK2 MR Qn(t + 1) X X X H L L u L L L H u L L H L L u L L H L u L H X H u L Qn(t) X u H L Qn(t) X L L L Qn(t) NOTE: 1. H = HIGH Voltage Level L = LOW Voltage Level X = Don’t Care t = Time before positive CLK transition t+1 = Time after positive CLK transition u = LOW-to-HIGH transition DC ELECTRICAL CHARACTERISTICS VEE = VEE (Min.) to VEE (Max.); VCC = VCCO = GND TA = 0°C Symbol Parameter TA = +25°C Min. Typ. Max. Min. Typ. IIH Input HIGH Current IEE Power Supply Current 10E 100E TA = +85°C Max. Min. Typ. Max. Unit Condition µA — mA — — — 150 — — 150 — — 150 — — 65 65 78 78 — — 65 65 78 78 — — 65 75 78 90 2 SY10E151 SY100E151 Micrel AC ELECTRICAL CHARACTERISTICS VEE = VEE (Min.) to VEE (Max.); VCC = VCCO = GND TA = 0°C Symbol Parameter TA = +25°C Min. Typ. Max. Min. Typ. — 1100 1400 TA = +85°C Max. Min. Typ. — Unit Condition — MHz — ps — fMAX Max. Toggle Frequency 1100 1400 tPLH tPHL Propagation Delay to Output CLK MR 475 475 650 650 800 850 475 475 650 650 800 850 475 475 650 650 800 850 tS Set-up Time, D 0 –175 — 0 –175 — 0 –175 — ps — tH Hold Time, D 350 175 — 350 175 — 350 175 — ps — tRR Reset Recovery Time 750 550 — 750 550 — 750 550 — ps — tPW Minimum Pulse Width CLK, MR 400 — — 400 — — 400 — — ps — tskew Within-Device Skew — 65 — — 65 — — 65 — ps 1 tr tf Rise/Fall Time 20% to 80% 300 450 700 300 450 700 300 450 700 ps — NOTE: 1. Within-device skew is defined as identical transitions on similar paths through a device. PRODUCT ORDERING CODE Ordering Code Package Type Operating Range SY10E151JC J28-1 Commercial SY10E151JCTR J28-1 Commercial SY100E151JC J28-1 Commercial SY100E151JCTR J28-1 Commercial 3 1100 1400 Max. SY10E151 SY100E151 Micrel 28 LEAD PLCC (J28-1) Rev. 03 MICREL-SYNERGY TEL 3250 SCOTT BOULEVARD SANTA CLARA CA 95054 USA + 1 (408) 980-9191 FAX + 1 (408) 914-7878 WEB http://www.micrel.com This information is believed to be accurate and reliable, however no responsibility is assumed by Micrel for its use nor for any infringement of patents or other rights of third parties resulting from its use. No license is granted by implication or otherwise under any patent or patent right of Micrel Inc. © 2000 Micrel Incorporated 4