5-BIT 2:1 MUX-LATCH FEATURES DESCRIPTION ■ ■ ■ ■ ■ ■ ■ 750ps max. LEN to output Extended 100E VEE range of –4.2V to –5.5V 700ps max. D to output Differential outputs Asynchronous Master Reset Dual latch-enables Fully compatible with industry standard 10KH, 100K ECL levels ■ Internal 75KΩ input pulldown resistors ■ Fully compatible with Motorola MC10E/100E154 ■ Available in 28-pin PLCC package The SY10/100E154 offer five 2:1 multiplexers followed by latches with differential outputs, designed for use in new, high-performance ECL systems. The two external Latch-Enable signals (LEN1, LEN2) are gated through a logical OR operation before use as control for the five latches. When both LEN1 and LEN 2 are at a logic LOW, the latches are transparent, thus presenting the data from the multiplexers at the output pins. If either LEN1 or LEN2 (or both) are at a logic HIGH, the outputs are latched. The multiplexer operation is controlled by the SEL(Select) signal which selects one of the two bits of input data at each mux to be passed through. The MR (Master Reset) signal operates asynchronously to make all Q outputs go to a logic LOW. D3a MUX SEL D4a MUX SEL VCCO Q4 Q4 26 18 Q3 27 17 28 16 15 Q3 VCC Q2 Q Q1 E Q NR Q1 VEE 1 MR 2 14 Q2 D0a 3 13 D0b 4 12 Q1 Q1 Q Q2 E Q NR Q2 D Q Q3 E Q NR Q3 D Q Q4 E Q N R Q4 PLCC TOP VIEW J28-1 5 6 D1a D1b SEL 25 24 23 22 21 20 19 SEL LEN1 LEN2 D MUX D4b Q0 7 8 9 10 11 Q0 SEL D2a D3b E Q NR D MUX D2b Q0 VCCO Q0 SEL D1a D1b Q D MUX D2a D2b D0a D3b D3a PIN CONFIGURATION D4b D4a BLOCK DIAGRAM D0b SY10E154 SY100E154 PIN NAMES Pin SEL LEN1 LEN2 MR Function D0a–D4a Input Data a D0b–D4b Input Data b SEL Data Select Input LEN1, LEN2 Latch Enables MR Master Reset Q0–Q4 True Outputs Q0–Q4 Inverted Outputs VCCO VCC to Output Rev.: C 1 Amendment: /1 Issue Date: February, 1998 SY10E154 SY100E154 Micrel TRUTH TABLES SEL Data LEN1 LEN2 Latch H a L L Transparent L b H X Latched X H Latched DC ELECTRICAL CHARACTERISTICS VEE = VEE (Min.) to VEE (Max.); VCC = VCCO = GND TA = 0°C Symbol Parameter TA = +25°C Min. Typ. Max. Min. Typ. IIH Input HIGH Current IEE Power Supply Current 10E 100E TA = +85°C Max. Min. Typ. Max. Unit Condition µA — mA — Unit Condition ps — ps — ps — — — 150 — — 150 — — 150 — — 76 76 91 91 — — 76 76 91 91 — — 76 87 91 105 AC ELECTRICAL CHARACTERISTICS VEE = VEE (Min.) to VEE (Max.); VCC = VCCO = GND TA = 0°C Symbol Parameter TA = +25°C TA = +85°C Min. Typ. Max. Min. Typ. Max. Min. Typ. Max. tPLH tPHL Propagation Delay to Output D SEL LEN MR 325 475 350 450 500 650 500 600 700 925 750 800 325 475 350 450 500 650 500 600 700 925 750 800 325 475 350 450 500 650 500 600 700 925 750 800 tS Set-up Time D SEL 300 500 100 250 — — 300 500 100 250 — — 300 500 100 250 — — Hold Time D SEL 300 200 –100 –250 — — 300 200 –100 –250 — — 300 200 –100 –250 — — tRR Reset Recovery Time 800 600 — 800 600 — 800 600 — ps — tPW Minimum Pulse Width, MR 400 — — 400 — — 400 — — ps — tskew Within-Device Skew — 50 — — 50 — — 50 — ps 1 tr tf Rise/Fall Time 20% to 80% 300 475 800 300 475 800 300 475 800 ps — tH NOTE: 1. Within-device skew is defined as identical transitions on similar paths through a device. PRODUCT ORDERING CODE Ordering Code Package Type Operating Range SY10E154JC J28-1 Commercial SY10E154JCTR J28-1 Commercial SY100E154JC J28-1 Commercial SY100E154JCTR J28-1 Commercial 2 SY10E154 SY100E154 Micrel 28 LEAD PLCC (J28-1) Rev. 03 3 SY10E154 SY100E154 Micrel MICREL-SYNERGY TEL 3250 SCOTT BOULEVARD SANTA CLARA CA 95054 USA + 1 (408) 980-9191 FAX + 1 (408) 914-7878 WEB http://www.micrel.com This information is believed to be accurate and reliable, however no responsibility is assumed by Micrel for its use nor for any infringement of patents or other rights of third parties resulting from its use. No license is granted by implication or otherwise under any patent or patent right of Micrel Inc. © 2000 Micrel Incorporated 4