ClockWorks™ PRELIMINARY SY89801A HP PA-8000 CLOCK SOURCE FEATURES DESCRIPTION ■ ■ ■ ■ ■ 3.3V, –1.9V power suppies Differential LVPECL clock input Differential HSTL/LVPECL outputs Compatible with HP PA-8000 microprocessors Low-jitter source for all PA-8000 required timing signals ■ Available in 44-pin MQUAD package Micrel-Synergy's SY89801A PLL based clock generator provides, in a single chip, all the necessary clocks for HewlettPackard's PA-8000 Microprocessor. Utilizing Micrel-Synergy's advanced PLL technology, the SY89801A accepts a Positive-ECL (PECL) reference clock input at 100MHz-132MHz, and provides precisely aligned, ultra-low-jitter ratios of frequencies necessary for the operation of the processor. In addition, the SY89801A provides the "USYNC" synchronizing signals as required by the PA-8000. The frequency ratios are 1:1, 4:3, 3:2, 5:3 and 2:1. To facilitate direct interfacing to the PA-8000, the SY89801A operates across +3.3 volt and -1.9 volt supplies. The processor clock (PCLK), runway clock (RCLK) , and USYNC outputs are HSTL-compatible. Additionally, there is a PECL-compatible runway clock output (RCLKLV). The SY89801A requires only a simple external series-RC loop filter. Coupling Micrel-Synergy's advanced PLL technology with our proprietary ASSET bipolar process has produced a Timing Generator IC which meets the stringent requirements of the PA-8000 µP, while setting a new standard for performance and flexibility. 4 3 RCLKLV RCLKLV VEE 2 5 RCLK RCLK REF_CLK VCC 6 1 44 43 42 41 40 7 39 8 38 9 37 10 36 11 12 13 14 35 TOP VIEW MQUAD M44-1 34 33 32 15 31 16 30 17 29 VEE PCLK1 PCLK1 PCLK2 PCLK2 VCC USYNC USYNC NC NC VCC PIN NAMES FSEL1 FSEL2 VCC NC FSEL0 RST VEE 18 19 20 21 22 23 24 25 26 27 28 VCC NC NC NC VEEA NC NC FILP FILN VCCA NC NC NC NC NC VEE NC NC REF_CLK PIN CONFIGURATION Pin Function REF_CLK, REF_CLK Differential Input Ref. Clock FILP, FILN Filter Pins (Positive & Negative) VCCA, VEEA Analog VCC, VEE RST Master Reset FSEL2-0 LVPECL Frequency Select Pins USYNC, USYNC Diff. HSTL Sync Signal for PA-8000 PCLK1-2, PCLK1-2 Diff. HSTL Processor Clock Signal RCLK, RCLK RCLKLV, RCLKLV Diff. HSTL Runway Clock Signal Diff. LVPECL Clock Signal Rev.: E 1 Amendment: /0 Issue Date: November 1998 ClockWorks™ PRELIMINARY SY89801A Micrel BLOCK DIAGRAM LOOP FILTER VCC 2 REFCLK (100-132MHz) LF VCO (600-800) (PECL) f/2 MF VCO (800-1060) ÷3 f/2 AVCC VCCO 3 2 HF VCO (1000-1320) ÷4 f/2 ÷5 PCLK1 ÷ (HSTL) 2/ 3/ 4/ 5 f/2 PCLK2 (HSTL) SYNC LOGIC USYNC (HSTL) VCO ENAB RCLK f/2 FSEL (HSTL) 3 RCLKLV DECODE (PECL) RESET TEST (PECL) (PECL) (PECL) 2 2 2 3 GND DVEE AVEE ClockWorks™ PRELIMINARY SY89801A Micrel 3.3V DC ELECTRICAL CHARACTERISTICS VCC = VCCA = 3.3V ±10%; VEEA = VEE = –1.9V Symbol Parameter Min. Typ. Max. Unit VCC Power Supply Voltage 3.0 — 3.6 V ICC Power Supply Current (VCC) — 250 321 mA Condition VEE = –1.9V PECL DC ELECTRICAL CHARACTERISTICS VCC = 3.3V ±10%; VEE = –1.9V Symbol Parameter Min. Typ. Max. Unit VOH Output HIGH Voltage VCC – 1.075 — VCC – 0.830 V VOL Output LOW Voltage VCC – 1.860 — VCC – 1.570 V VIH Input HIGH Voltage VCC – 1.165 — VCC – 0.880 V VIL Input LOW Voltage VCC – 1.810 — VCC – 1.475 V VBB PECL Threshold — VCC – 1.35 — V Min. Typ. Max. Unit Condition HSTL DC ELECTRICAL CHARACTERISTICS VCC = 3.3V ±10%; VEE = –1.9V Symbol Parameter VOH Output HIGH Voltage VCC – 2.3 — VCC – 2.1 V VOL Output LOW Voltage VCC – 3.1 — VCC – 2.9 V Condition AC ELECTRICAL CHARACTERISTICS(1) VCC = 3.3V ±10%; VEE = –1.9V TA = 0°C Symbol Parameter TA = +25°C TA = +70°C Min. Typ. Max. Min. Typ. Max. Min. Typ. Max. Unit fVCO Maximum VCO Frequency 1320 — — 1320 — — 1320 — — MHz fMAX Maximum PCLK Output Frequency 264 Maximum RCLK Output Frequency 132 — — — — 264 132 — — — — 264 132 — — — — MHz MHz tskew(2) PCLK to PCLK RCLK to RCLKLV PCLK to RCLK PCLK (neg.) to USYNC — — — — — — — — ±50 ±100 ±100 ±500 — — — — — — — — ±50 ±100 ±100 ±500 — — — — — — — — ±50 ±100 ±100 ±500 ps ps ps ps tpe Phase Error RCLK to REF_CLK — — ±250 — — ±250 — — ±250 ps tj(2) Output Jitter –50 — +50 –50 — +50 –50 — +50 ps tdc(2) Output Duty Cycle 49 — 51 49 — 51 49 — 51 % tr (2) tf Rise/Fall Times (20% to 80%) 100 — 800 100 — 800 100 — 800 ps NOTES: 1. All HSTL outputs terminated into 50 ohms in parallel with 3pf to GND. 2. tskew, tj, tdc, tr and tf are specified by HP for the PA-8000. This is our best information as of the date of this document. 3 Condition Measured at differential crossover Peak to Peak, Cycle to Cycle ClockWorks™ PRELIMINARY SY89801A Micrel APPLICATIONS INFORMATION ■ 2.5:1 VCO frequency range ■ Maximum system frequency of 120MHz plus 10% margin ■ Maximum output frequency of 264MHz The following table lists the various PCLK and RCLK ratios supported by the SY89801A and the corresponding PCLK, RCLK, FB and VCO frequencies. The table is arranged in order of increasing PCLK:RCLK ratio. The table was designed to balance several constraints: FSEL <2:0> PCLK:RCLK fPCLK (MHz) fRCLK (MHz) VCO ÷ ratios VCO/P:VCO/R fVCO (MHz) 000 1:1 100-132 100-132 8:8 800-1056 001 4:3 133.3-176 100-132 6:8 800-1056 010 3:2 150-198 100-132 4:6 600-792 011 5:3 166.7-220 100-132 6:10 1000-1320 100 2:1 200-264 100-132 4:8 800-1056 101 1:1 100-132 100-132 6:6 600-792 110 1:1 100-132 100-132 10:10 1000-1320 111 n/a n/a n/a n/a n/a LOOP FILTER COMPONENT SELECTION R C1 filp filn R = 500Ω ±10% C1 = 1000pF ±10% PRODUCT ORDERING CODE Ordering Code SY89801AMC SY89801AMCA (1) Package Type Operating Range M44-1 Commercial M44-1 Commercial NOTES: 1. "A" denotes enhanced 200MHz testing. 4 ClockWorks™ PRELIMINARY SY89801A Micrel 44 LEAD MLCC (M44-1) Rev. 02 MICREL-SYNERGY TEL 3250 SCOTT BOULEVARD SANTA CLARA CA 95054 USA + 1 (408) 980-9191 FAX + 1 (408) 914-7878 WEB http://www.micrel.com This information is believed to be accurate and reliable, however no responsibility is assumed by Micrel for its use nor for any infringement of patents or other rights of third parties resulting from its use. No license is granted by implication or otherwise under any patent or patent right of Micrel Inc. © 2000 Micrel Incorporated 5