® Precision Edge 3.3V 1GHz DUAL 1:10 PRECISION SY89828L ® Precision Edge LVDS FANOUT BUFFER/ SY89828L TRANSLATOR WITH 2:1 INPUT MUX MicreL, Inc. FEATURES ■ High-performance dual 1:10, 1GHz LVDS fanout buffer/translator ■ Two banks of 10 differential LVDS outputs ■ Guaranteed AC parameters over temperature and voltage: • > 1GHz fMAX • < 50ps within device skew • < 400ps tr, tf time ■ Each bank includes a 2:1 input mux ■ 2:1 mux input accepts LVDS and LVPECL ■ Low jitter performance • < 1psRMS cycle-to-cycle jitter • < 1psPP total jitter ■ 3.3V supply voltage ■ Output enable function ■ LVDS input includes internal 100Ω termination ■ Available in a 64-Pin EPAD-TQFP Precision Edge® DESCRIPTION The SY89828L is a precision fanout buffer with 20 differential LVDS (Low Voltage Differential Swing) output pairs. The part is designed for use in low voltage 3.3V applications that require a large number of outputs to drive precisely aligned, ultra low-skew signals to their destination. The input is multiplexed from either LVDS or LVPECL (Low Voltage Positive Emitter Coupled Logic) by the CLK_SEL1 and CLK_SEL2 pins. The Output Enables (OE1 and OE2) are synchronous so that the outputs will only be enabled/ disabled when they are already in the LOW state. This avoids any chance of generating a runt clock pulse when the device is enabled/disabled as can happen with an asynchronous control. The SY89828L features a low pin-to-pin skew of less than 50ps—performance previously unachievable in a standard product having such a high number of outputs. The SY89828L is available in a single space saving package, enabling a lower overall cost solution. APPLICATIONS ■ Enterprise networking ■ High-end servers ■ Communications TYPICAL APPLICATION CIRCUIT 5 Primary Clock Source LVDS_CLKA 100Ω Primary Card 5 /LVDS_CLKA Backup Clock Source LVDS_CLKB 5 /LVDS_CLKB 5 100Ω Redundant Card SEL1 Primary/Backup Clock Select (Switchover with 2.0ns) System using SY89828L as a switchover circuit from a Primary Clock to a Redundant backup Clock in a fail-safe application. LVPECL inputs not shown in this application. Precision Edge is a registered trademark of Micrel, Inc. M9999-012208 [email protected] or (408) 955-1690 Rev.: D 1 Amendment: /0 Issue Date: January 2008 Precision Edge® SY89828L Micrel, Inc. PACKAGE/ORDERING INFORMATION VCCO Q0 /Q0 Q1 /Q1 Q2 /Q2 Q3 /Q3 Q4 /Q4 Q5 /Q5 Q6 /Q6 VCCO Ordering Information(1) Package Type Operating Range Package Marking Lead Finish SY89828LHI(2) H64-1 Industrial SY89828LHI Sn-Pb SY89828LHITR(2) H64-1 Industrial SY89828LHI Sn-Pb SY89828LHY(2) H64-1 Industrial SY89828LHY with Pb-Free Pb-Free bar-line indicator Matte-Sn SY89828LHYTR(2) H64-1 Industrial SY89828LHY with Pb-Free Pb-Free bar-line indicator Matte-Sn 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 SEL2 LVDS_CLKB /LVDS_CLKB VCCI LVDS_CLKA /LVDS_CLKA CLK_SEL1 LVPECL_CLKA /LVPECL_CLKA GNDI OE1 LVPECL_CLKB /LVPECL_CLKB CLK_SEL2 OE2 SEL1 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 GNDO Q7 /Q7 Q8 /Q8 Q9 /Q9 VCCO VCCO Q10 /Q10 Q11 /Q11 Q12 /Q12 GNDO VCCO /Q19 Q19 /Q18 Q18 /Q17 Q17 /Q16 Q16 /Q15 Q15 /Q14 Q14 /Q13 Q13 VCCO 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 Part Number Notes: 1. Contact factory for die availability. Dice are guaranteed at TA = 25°C, DC electricals only. 2. Pb-Free package recommended for new designs. 64-Pin TQFP (H64-1) FUNCTIONAL BLOCK DIAGRAM 100Ω termination internal CLK_SEL1 SEL1 OE1 LVDS_CLKA /LVDS_CLKA 0 0 LVPECL_CLKA 10 1 10 /LVPECL_CLKA 1 LEN 100Ω termination internal Q0 – Q9 /Q0 – /Q9 Q D LVDS_CLKB /LVDS_CLKB 0 0 10 10 1 LVPECL_CLKB LEN 1 /LVPECL_CLKB D CLK_SEL2 M9999-012208 [email protected] or (408) 955-1690 SEL2 2 OE2 Q Q10 – Q19 /Q10 – /Q19 Precision Edge® SY89828L MicreL, Inc. PIN DESCRIPTIONS Internal P/U Pin Number Pin Name I/O Type 5, 6 LVDS_CLKA /LVDS_CLKA Input LVDS 3.5kΩ Pull-up See Fig. 2 Differential clock input selected by CLK_SEL1, SEL1 and SEL2. Can be left floating if not selected. Floating input, if selected produces an indeterminate output. Has internal 100Ω termination. 2, 3 LVDS_CLKB /LVDS_CLKB Input LVDS 3.5kΩ Pull-up See Fig. 2 Differential clock input selected by CLK_SEL1, SEL1 and SEL2. Can be left floating if not selected. Floating input, if selected produces an indeterminate output. Has internal 100Ω termination. 8, 9 LVPECL_CLKA /LVPECL_CLKA Input LVPECL 75kΩ pull-down See Fig. 1 Differential clock input selected by CLK_SEL1, SEL1 and SEL2. Can be left floating. Floating input, if selected produces a LOW at output. Requires external termination. 12, 13 LVPECL_CLKB /LVPECL_CLKB Input LVPECL 75kΩ pull-down See Fig. 1 Differential clock input selected by CLK_SEL2, SEL1 and SEL2. Requires external termination. 7 CLK_SEL1 Input LVTTL/ CMOS 11kΩ Pull-up Selects LVDS_CLKA input when LOW and LVPECL_CLKA input when HIGH. 14 CLK_SEL2 Input LVTTL/ CMOS 11kΩ Pull-up Selects LVDS_CLKB input when LOW and LVPECL_CLKB input when HIGH. 16 SEL1 Input LVTTL/ CMOS 11kΩ Pull-up Selects input source CLKA when LOW and CLKB when HIGH for outputs Q0 – Q9 and /Q0 – /Q9. 1 SEL2 Input LVTTL/ CMOS 11kΩ Pull-up Selects input source CLKA when LOW and CLKB when HIGH for outputs Q10 – Q19 and /Q10 – /Q19. 11 OE1 Input LVTTL/ CMOS 11kΩ Pull-up Enable input synchronized internally to prevent output glitches or runt pulses. 15 OE2 Input LVTTL/ CMOS 11kΩ Pull-up Enable input synchronized internally to prevent output glitches or runt pulses. 4 VCCI Power Core VCC connected to 3.3V supply. Not connected to VCCO internally. Connected to VCCO on PCB. Bypass with 0.1µF in parallel with 0.01µF low ESR capacitors as close to VCC pins as possible. 17, 32, 40, 41, 49, 64 VCCO Power Output buffer VCC connected to 3.3V suppy. Not connected to VCCI internally. Connected to VCCI on PCB. Bypass with 0.1µF in parallel with 0.01µF low ESR capacitors as close to VCC pins as possible. 10 GNDI Power Core ground not connected to GNDO internally. To be connected to GNDO on PCB. 33, 48 GNDO Power Output buffer ground not connected to GNDI internally. To be connected to GNDI on PCB. 63, 61, 59, 57, 55 53, 51, 47, 45, 43 Q0 – Q9 Output LVDS Differential clock outputs from CLKA when SEL1 = LOW and from CLKB when SEL1 = HIGH. Q outputs are static when OE1 = LOW. Unused output pair must be terminated with 100Ω to maintain low jitter and skew. 62, 60, 58, 56, 54 52, 50, 46, 44, 42 /Q0 – /Q9 Output LVDS Differential clock outputs (complement) from CLKA when SEL1 = LOW and from CLKB when SEL1 = HIGH. /Q outputs are static HIGH when OE1 = LOW. Unused output pairs must be externally terminated with 100Ω to maintain low jitter and skew. 39, 37, 35, 31, 29 27, 25, 23, 21, 19 Q10 – Q19 Output LVDS Differential outputs from CLKA when SEL2 = LOW and from CLKB when SEL2 = HIGH. Q outputs are static LOW when OE2 = LOW. Unused output pairs must be externally terminated with 100Ω to maintain low jitter and skew. M9999-012208 [email protected] or (408) 955-1690 3 Pin Function Precision Edge® SY89828L Micrel, Inc. Pin Number Pin Name I/O Type 38, 36, 34, 30, 28 26, 24, 22, 20, 18 /Q10 – /Q19 Output LVDS M9999-012208 [email protected] or (408) 955-1690 Internal P/U Pin Function Differential outputs (complement) from CLKA when SEL2 = LOW and from CLKB when SEL2 = HIGH. /Q outputs are static HIGH when OE2 = LOW. Unused output pairs must be externally terminated with 100Ω to maintain low jitter and skew. 4 Precision Edge® SY89828L MicreL, Inc. TRUTH TABLE OE1(1) OE2(1) SEL1(1) SEL2(1) CLK_SEL1(1) CLK_SEL2(1) Q0 – Q9 /Q0 – /Q9 Q10 – Q19 /Q10 – /Q19 1 1 1 1 0 0 0 0 0 1 X X LVDS_CLKA /LVDS_CLKA LVDS_CLKA /LVDS_CLKA LVPECL_CLKA /LVPECL_CLKA LVPECL_CLKA /LVPECL_CLKA 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 1 0 1 LVDS_CLKA /LVDS_CLKA LVDS_CLKB /LVDS_CLKB LVDS_CLKA /LVDS_CLKA LVPECL_CLKB /LVPECL_CLKB LVPECL_CLKA /LVPECL_CLKA LVDS_CLKB /LVDS_CLKB LVPECL_CLKA /LVPECL_CLKA LVPECL_CLKB /LVPECL_CLKB 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 1 1 0 1 0 1 LVDS_CLKB /LVDS_CLKB LVDS_CLKA /LVDS_CLKA LVPECL_CLKB /LVPECL_CLKB LVDS_CLKA /LVDS_CLKA LVDS_CLKB /LVDS_CLKB LVPECL_CLKA /LVPECL_CLKA LVPECL_CLKB /LVPECL_CLKB LVPECL_CLKA /LVPECL_CLKA 1 1 1 1 1 1 1 1 X X 0 1 LVDS_CLKB /LVDS_CLKB LVDS_CLKB /LVDS_CLKB LVPECL_CLKB /LVPECL_CLKB LVPECL_CLKB /LVPECL_CLKB 0 0 0 0 1 1 1 1 X X X X 0 0 1 1 0 1 X X X X 0 1 1 1 1 1 0 0 0 0 0 0 1 1 X X X X 0 1 X X X X 0 1 0 0 X X X X LOW LOW LOW LOW LVDS_CLKA /LVDS_CLKA LVPECL_CLKA /LVPECL_CLKA LVDS_CLKB /LVDS_CLKB LVPECL_CLKB /LVPECL_CLKB LOW NOTE: 1. Input has internal pull-up so floating input = 1. M9999-012208 [email protected] or (408) 955-1690 HIGH HIGH HIGH HIGH 5 HIGH LVDS_CLKA /LVDS_CLKA LVPECL_CLKA /LVPECL_CLKA LVDS_CLKB /LVDS_CLKB LVPECL_CLKB /LVPECL_CLKB LOW LOW LOW LOW HIGH HIGH HIGH HIGH LOW HIGH Precision Edge® SY89828L Micrel, Inc. Absolute Maximum Ratings(Note 1) Operating Ratings(Note 2) Power Supply Voltage (VCCI, VCCO) .............. –0.5 to +4.0V Input Voltage (VIN) ........................................... –0.5 to VCCI Output Current (IOUT) ............................................... ±10mA Storage Temperature (TS) ........................... –65 to +150°C ESD Rating, Note 3 ...................................................... 1kV Supply Voltage ............................................... +3V to +3.6V Ambient Temperature (TA) ......................... –40°C to +85°C Package Thermal Resistance TQFP (θJA) Exposed pad soldered to GND Still-Air (multi-layer PCB) ................................. 23°C/W –200lfpm (multi-layer PCB) ............................. 18°C/W –500lfpm (multi-layer PCB) ............................. 15°C/W Exposed pad NOT soldered to GND (not recommened) Still-Air (multi-layer PCB) ................................. 44°C/W –200lfpm (multi-layer PCB) ............................. 36°C/W –500lfpm (multi-layer PCB) ............................. 30°C/W TQFP (θJC) ......................................................... 4.4°C/W DC ELECTRICAL CHARACTERISTICS Power Supply: TA = –40°C to +85°C Symbol Parameter Condition Min Typ Max Units VCCI, VCCO VCC Core, VCC Output Note 4 3.0 3.3 3.6 V ICCI ICC Core Max. VCC 45 70 mA ICCO ICC Output No Load, Max. VCC 160 260 mA Typ Max Units 2.4 V LVDS Input: VCC = 3.3V ±10%, TA = –40°C to +85°C Symbol Parameter VIN Input Voltage Range VID Differential Input Swing IIL Input LOW Current RIN LVDS Differential Input Resistance (LVDS_CLK to /LVDS_CLK) Condition Min 0 100 mV –1.25 mA 80 100 120 Ω Note 1. Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. This is a stress rating only and functional operation is not implied at conditions other than those detailed in the operational sections of this data sheet. Exposure to ABSOLUTE MAXIMUM RATlNG conditions for extended periods may affect device reliability. Note 2. The data sheet limits are not guaranteed if the device is operated beyond the operating ratings. Note 3. Devices are ESD sensitive. Handling precautions recommended. Note 4. VCCI and VCCO must be connected together on the PCB such that they remain at the same potential. VCCI and VCCO are not internally connected on the die. M9999-012208 [email protected] or (408) 955-1690 6 Precision Edge® SY89828L MicreL, Inc. DC ELECTRICAL CHARACTERISTICS LVPECL Input: VCC = 3.3V ±10%, TA = –40°C to +85°C Symbol Parameter Condition VIH Input HIGH Voltage (Single-Ended) VIL Input LOW Voltage VPP Minimum Input Swing (LVPECL_CLK) VCMR Common Mode Range (LVPECL_CLK) Note 6 IIH Input HIGH Current IIL Input LOW Current Min Note 5 Typ Max Units VCC –1.165 VCC –0.880 V VCC –1.945 VCC –1.625 V 300 mV GNDI +1.8 VCCI –0.4 V 150 µA 0.5 µA Note 5. The VPP (min.) is defined as the minimum input differential voltage which will cause no increase in the propagation delay. Note 6. VCMR is defined as the range within which the VIH level may vary, with the device still meeting the propagation delay specification. The numbers in the table are referenced to VCCI. The VIL level must be such that the peak-to-peak voltage is less than 1.0V and greater than or equal to VPP (min.). CMR range varies 1:1 with VCCI. VCMR (min) is fixed at GNDI + 1.8V. CMOS/LVTTL: VCC = 3.3V ±10%, TA = –40°C to +85°C Symbol Parameter Condition VIH Input HIGH Voltage VIL Input LOW Voltage IIH Input HIGH Current VIN = VCC IIL Input LOW Current VIN = 0.5V Min Typ Max 2.0 Units V 0.8 V 150 µA –600 µA LVDS Output: VCC = 3.3V ±10%, TA = –40°C to +85°C Symbol Parameter Condition Min Typ Max Units VOD Differential Output Voltage Note 7, 8 250 350 400 mV VOH Output HIGH Voltage Note 7 1.474 V VOL Output LOW Voltage Note 7 0.925 VOCM Output Common Mode Voltage Note 8 1.125 1.375 V ∆VOCM Change in Commom Mode Voltage –50 50 mV Note 7. Measured as per Figure 3, 100Ω across Q and /Q outputs. Note 8. Measured as per Figure 4. M9999-012208 [email protected] or (408) 955-1690 7 V Precision Edge® SY89828L Micrel, Inc. AC ELECTRICAL CHARACTERISTICS(NOTE 1) VCC = 3.3V ±10%, TA = –40°C to +85°C, unless noted. Symbol Parameter Condition Min Typ Max Units fMAX Maximum Toggle Frequency Note 2 1.0 tPHL tPLH Differential Propagation Delay Note 3 LVPECL Input: 150mV LVPECL Input: 800mV 0.950 0.80 1.15 1.0 1.45 1.3 ns ns LVDS Input: 100mV LVDS Input: 400mV 1.10 0.950 1.35 1.20 1.60 1.450 ns ns 1.55 1.85 ns GHz tSWITCHOVER Clock Input Switchover CLK_SEL to Valid Output tS(OE) Output Enable Set-Up Time Note 4 1.0 ns tH(OE) Output Enable Hold Time Note 4 0.5 ns tSKEW Within Device Skew Note 5 Part-to-Part Skew Note 6 Cycle-to-Cycle Total Jitter Note 7 Note 8 tJITTER tr, tf 0°C to +85°C –40°C Output Rise/Fall Times (20% to 80%) 25 35 200 50 75 ps ps 400 ps <1 <1 2 psRMS psPP 290 400 ps Note 1. 100Ω termination between Q and /Q outputs. Airflow ≥300lfpm, or exposed pad soldered to ground plane. Note 2. Note 3. fMAX is defined as the maximum toggle frequency, measured with a 750mV LVPECL input or 350mV LVDS input. Outut swing is > 200mV. Differential propagation delay is defined as the delay from the crossing point of the differential input signals to the crossing point of the differential output signals. Set-up and hold time applies to synchronous applications that intend to enable/disable before the next clock cycle. For asynchronous applications, set-up and hold time does not apply. OE set-up time is defined with respect to the rising edge of the clock. OE HIGH to LOW transition ensures outputs remain disabled during the next clock cycle. OE LOW to HIGH transition enables normal operation of the next input clock. The within-device skew is defined as the worst case difference between any two similar delay paths within a single device identical input transition, operating at the same voltage and temperature. The part-to-part skew is defined as the absolute worst case difference between any two delay paths on any two devices operating at the same voltage and temperature. Part-to-part skew is the total skew difference; pin-to-pin skew + part-to-part skew. Cycle-to-cycle jitter definition: The variation period between adjacent cycles over a random sample of adjacent cycle pairs. TJITTER_CC = Tn –Tn+1 where T is the time between rising edges of the output signal. Total jitter definition: with an ideal clock input, no more than one output edge in 1012 output edges will deviate by more than the specified peakto-peak jitter value. Note 4. Note 5. Note 6. Note 7. Note 8. M9999-012208 [email protected] or (408) 955-1690 8 Precision Edge® SY89828L MicreL, Inc. TYPICAL OPERATING CHARACTERISTICS Output Amplitude vs. Frequency PROPAGATION DELAY (ps) 500 450 400 350 300 250 200 150 100 50 0 2000 1800 1600 1400 1200 1000 800 600 400 200 0 0 200 400 600 800 1000 1200 FREQUENCY (MHz) Propagation Delay vs. Input Amplitude LVDS INPUT LVPECL INPUT 0 1200 1000 800 600 400 200 0 -50 9 LVPECL INPUT -25 0 25 50 75 TEMPERATURE (°C) 100 CLK_SEL Switchover Time vs. Temperature 1600 1400 1200 1000 800 600 400 200 0 -50 200 400 600 800 1000 INPUT AMPLITUDE (mV) M9999-012208 [email protected] or (408) 955-1690 Nominal Propagation Delay vs. Temperature 2000 LVPECL IN = 750mV 1800 LVDS IN = 250mV 1600 LVDS INPUT 1400 1800 SWITCHOVER TIME (ns) PROPAGATION DELAY (ns) OUTPUT VOLTAGE (mV) (Conditions: VCC = 3.3V, TA = 25°C, unless otherwise stated) -25 0 25 50 75 TEMPERATURE (°C) 100 Precision Edge® SY89828L Micrel, Inc. FUNCTIONAL CHARACTERISTICS 155MHz Output 622MHz Output TA = 25°C VCC = 3.3V Output Swing (50mV/div.) Output Swing (50mV/div.) TA = 25°C VCC = 3.3V TIME (500ps/div.) TIME (200ps/div.) 1GHz Output Output Swing (50mV/div.) TA = 25°C VCC = 3.3V TIME (100ps/div.) M9999-012208 [email protected] or (408) 955-1690 10 Precision Edge® SY89828L MicreL, Inc. LVPECL/LVDS INPUTS VCC VCC 1.9k LVPECL_CLK 1.9k 1.4k 75k 75k 1.4k LVDS_CLK 100Ω /LVDS_CLK /LVPECL_CLK GND GND Figure 2. Simplified LVDS Input Stage Figure 1. Simplified LVPECL Input Stage LVDS OUTPUTS LVDS stands for Low Voltage Differential Swing. LVDS specifies a small swing of 350mV typical, on a nominal 1.25V common mode above ground. The common mode voltage has tight limits to permit large variations in ground vOD between an LVDS driver and receiver. Also, change in common mode voltage, as a function of data input, is also kept tight, to keep EMI low. 50Ω, ±1% 100Ω vOH, vOL vOH, vOL vOCM, ∆vOCM 50Ω, ±1% GND GND Figure 3. LVDS Differential Measurement Figure 4. LVDS Common Mode Measurement QOUT QOUT 750mV QOUT – /QOUT 350mV (typical) /QOUT /QOUT Figure 5. Output Driver Signal Levels (Single-Ended) M9999-012208 [email protected] or (408) 955-1690 Figure 6. Output Driver Signal Levels (Differential) 11 Precision Edge® SY89828L Micrel, Inc. DETAILED DESCRIPTION CLK_SEL1, CLK_SEL2 TTL Inputs The CLK_SEL1 Input is used to select either LVDS_CLKA (CLK_SEL1 is LOW) or LVPECL_CLKA (CLK_SEL1 is HIGH). In a similar manner, The CLK_SEL2 Input is used to select either LVDS_CLKB (CLK_SEL2 is LOW) or LVPECL_CLKB (CLK_SEL2 is HIGH). OE1, OE2 TTL Inputs The SY89828L’s output enable functions are designed to disable the outputs only when the outputs are LOW. The OE1 TTL Input controls the Q0-Q9 outputs and OE2 controls the Q10-Q19 outputs. This avoids the possibility of generating runt pulses. The OE1 and OE2 inputs are asynchronous inputs, but operate as synchronous enables. For synchronous operation, please adhere to the specific setup and hold times. When disabled, the Q outputs are LOW and the /Q outputs are HIGH. Q0-Q9, Q10-Q19 LVDS Outputs The SY89828L’s LVDS outputs swing typically 350mV around a 1.25V common mode voltage above ground. The common mode voltage has tight limits to permit large variations in ground between an LVDS driver and receiver. Also, change in common mode voltage, as a function of data input is kept tight to keep EMI low. Each of the SY89828L’s LVDS outputs should be terminated with a 100Ω termination resistor including any unused output pairs. This ensures the best jitter and skew performance of the device. In a similar manner, The SEL2 Input is used to select either CLKA (SEL2 is LOW)or CLKB (SEL2 is HIGH) for the Q10Q19 differential output pairs. The SY89828L is a precision dual 1:10 fanout buffer. It allows either LVPECL or LVDS inputs, selectable by an input muxes, and outputs 2 sets of 10 LVDS output pairs. The device features 2 synchronous output enables. The SY89828L provides extremely low skew across its outputs. LVPECL_CLKA, LVPECL_CLKB The SY89828L allows two inputs with standard LVPECL voltage swings. These inputs may be adjusted per the data sheet characteristics regarding the CMR and minimum input swing. As the SY89828L contains no appropriate internal termination, upstream devices need to be properly terminated to provide the proper LVPECL input swing. If not being used (CLK_SEL1 and CLK_SEL2 are LOW), these input pairs may be left floating, as they are internally terminated to ground via 75kΩ pull-down resistors. LVDS_CLKA, LVDS_CLKB The SY89828L allows two inputs with standard LVDS voltage swings. The SY89828L provides an appropriate internal 100Ω termination resistor. Hence, upstream LVDS devices do not require external termination to drive the SY89828L. If not being used (CLK_SEL1 and CLK_SEL2 are HIGH), these inputs pair may be left floating. SEL1, SEL2 TTL Inputs The SEL1 Input is used to select either CLKA (SEL1 is LOW) or CLKB (SEL1 is HIGH) for the Q0-Q9 differential output pairs. In a similar manner, The SEL2 Input is used to select either CLKA (SEL2 is LOW)or CLKB (SEL2 is HIGH) for the Q10-Q19 differential output pairs. RELATED MICREL PRODUCTS AND SUPPORT DOCUMENTATION Part Number Function Data Sheet Link SY55855V Dual CML/PECL/LVPECL-to-LVDS Translator www.micrel.com/product-info/products/sy55855v.shtml SY89825U 2.5/3.3V 1:22 High-Performance, Low-Voltage PECL Bus Clock Driver & Translator w/Internal Termination www.micrel.com/product-info/products/sy89825u.shtml 3.3V 1GHz Precision 1:22 LVDS Fanout Buffer with 2:1 Input Mux www.micrel.com/product-info/products/sy89826u.shtml 2.5/3.3V High-Performance, Dual 1:10 LVPECL Clock Driver w/Internal Termination & Redundant Switchover www.micrel.com/product-info/products/sy89829u.shtml M-0317 HBW Solutions www.micrel.com/product-info/products/solutions.shtml Exposed pad Amkor Exposed Pad Application Note www.amkor.com/products/notes_papers/ePad.pdf SY89826U SY89829U M9999-012208 [email protected] or (408) 955-1690 12 Precision Edge® SY89828L MicreL, Inc. 64-PIN EPAD-TQFP (DIE UP) (H64-1) +0.05 –0.05 +0.002 –0.002 +0.05 –0.05 +0.012 –0.012 +0.03 –0.03 +0.012 –0.012 +0.15 –0.15 +0.006 –0.006 +0.05 –0.05 +0.002 –0.002 Rev. 02 Package EP- Exposed Pad Die CompSide Island Heat Dissipation Heat Dissipation VEE Heavy Copper Plane VEE Heavy Copper Plane PCB Thermal Consideration for 64-Pin EPAD-TQFP Package Package Notes: Note 1. Package meets Level 3 qualifications. Note 2. All parts are 100% baked and dry-packed before shipment. Note 3. Exposed pad must be soldered to a ground for proper thermal management. MICREL, INC. TEL 2180 FORTUNE DRIVE SAN JOSE, CA 95131 USA + 1 (408) 944-0800 FAX + 1 (408) 944-0970 WEB http://www.micrel.com The information furnished by Micrel in this data sheet is believed to be accurate and reliable. However, no responsibility is assumed by Micrel for its use. Micrel reserves the right to change circuitry and specifications at any time without notification to the customer. Micrel Products are not designed or authorized for use as components in life support appliances, devices or systems where malfunction of a product can reasonably be expected to result in personal injury. Life support devices or systems are devices or systems that (a) are intended for surgical implant into the body or (b) support or sustain life, and whose failure to perform can be reasonably expected to result in a significant injury to the user. A Purchaser’s use or sale of Micrel Products for use in life support appliances, devices or systems is at Purchaser’s own risk and Purchaser agrees to fully indemnify Micrel for any damages resulting from such use or sale. © 2002 Micrel, Incorporated. M9999-012208 [email protected] or (408) 955-1690 13