1M x 32 SRAM MODULE SYS321000ZK/LK - 012/015/020/025 Issue 1.5 : December 1998 Description Features The SYS321000ZK/LK is a industry standard plastic 32Mbit Static RAM Module housed in a 72 pin plastic SIMM & ZIP package organised as 1M x 32. The module utilises fast SRAMs housed in SOJ packages, and uses double sided surface mount techniques to achieve a very high density module. • Access Times of 12/15/20/25 ns. • 72 Pin ZIP, SIMM package • 5 Volt Supply ± 10%. • Low Power Dissipation: Average (min cycle) 7.48 W (Max). Standby -L Version (CMOS) 22 mW (Max). The module has four Chip Selects, which allow reading and writing to individual bytes or words. The pins PD0-3, are used to identify module memory density in applications where alternative modules can be interchanged. • Completely Static Operation. • On-board Supply Decoupling Capacitors. • Equivalent to EDI part EDI8F321024C, IDT part IDT7MP4120, and Cypress part CYM1851. Block Diagram Pin Definition ZIP A0 - A19 WE OE 1M x 4 SRAM D0 - D3 1M x 4 SRAM D4 - D7 1M x 4 SRAM D8 - D11 1M x 4 SRAM D12 - D15 1M x 4 SRAM D16 - D19 1M x 4 SRAM D20 - D23 CS1 CS2 CS3 1M x 4 SRAM D24 - D27 1M x 4 SRAM CS4 Pin Functions Address Inputs A0 - A19 Data Input/Output D0 - D31 Chip Select CS1-4 Presence Detect PD0-3 Write Enable WE Output Enable OE No Connect NC Power (+5V) VCC Ground GND D28 - D31 SIMM TOP VIEW NC PD3 PD0 D0 D1 D2 D3 VCC A7 A8 A9 D4 D5 D6 D7 WE A14 CS1 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 CS3 A16 GND D16 D17 D18 D19 A10 A11 A12 A13 D20 D21 D22 D23 GND A19 NC 38 40 42 44 46 48 50 52 54 56 58 60 62 63 64 68 70 72 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 NC PD2 GND PD1 D8 D9 D10 D11 A0 A1 A2 D12 D13 D14 D15 GND A15 CS2 37 39 41 43 45 47 49 51 53 55 57 59 61 63 65 67 69 71 CS4 A17 OE D24 D25 D26 D27 A3 A4 A5 VCC A6 D28 D29 D30 D31 A18 NC PD0=PD2=GND PD1=PD3=OPEN NC NC PD2 PD3 GND PD0 PD1 D0 D8 D1 D9 D2 D10 D3 D11 VCC A0 A7 A1 A8 A2 A9 D12 D4 D13 D5 D14 D6 D15 D7 GND WE A15 A14 CS2 CS1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 CS4 CS3 A17 A16 OE GND D24 D16 D25 D17 D26 D18 D27 D19 A3 A10 A4 A11 A5 A12 VCC A13 A6 D20 D28 D21 D29 D22 D30 D23 D31 GND A18 A19 NC NC 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 Package Details Plastic 72 Pin SIMM Plastic 72 Pin ZIP ISSUE 1.5 : December 1998 SYS321000ZK/LK - 012/015/20/25 DC OPERATING CONDITIONS Absolute Maximum Ratings (1) Parameter Symbol (2) T Voltage on any pin relative to VSS Power Dissipation Storage Temperature V PT TSTG Min Typ Max Unit -0.3 -55 - 7.0 8.0 125 V W o C Notes : (1) Stresses above those listed may cause permanent damage to the device. This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. (2) VT can be -2.0V pulse of less than 10ns. Recommended Operating Conditions Parameter Supply Voltage Input High Voltage Input Low Voltage Operating Temperature (Commercial) (Industrial) Symbol Min Typ Max Unit VCC VIH VIL TA TAI 4.5 2.2 -0.3 0 -40 5.0 - 5.5 VCC+0.3 0.8 70 85 V V V o C o C TA 0 to 70 oC DC Electrical Characteristics (VCC=5V±10%) Parameter I/P Leakage Current Symbol Test Condition max Unit ILI 0V < VIN < VCC -16 - 16 µA ILO CS = VIH, VI/O = GND to VCC -16 - 16 µA ICC1 Min. Cycle, CS = VIL,VIL<VIN<VIH - - 1360 mA TTL ISB1 CS = VIH - - 480 mA CMOS ISB2 CS > VCC-0.2V, 0.2<VIN<VCC-0.2V - - 80 mA VOL IOL = 8.0mA - - 0.4 V VOH IOH = -4.0mA 2.4 - - V Address,OE,WE Output Leakage Current Min Typ Worst Case Average Supply Current Standby Supply Current Output Voltage Typical values are at VCC=5.0V,TA=25oC and specified loading. CS above refers to CS1~4. Capacitance (VCC=5V±10%,TA=25oC) Parameter Input Capacitance (Address,OE,WE) I/P Capacitance (other) I/O Capacitance Note: Capacitance calculated, not measured. Symbol Test Condition CIN1 CIN2 CI/O VIN = 0V VIN = 0V VI/O = 0V 2 max Unit 64 10 80 pF pF pF SYS321000ZK/LK - 012/015/20/25 ISSUE 1.5 : December 1998 AC Test Conditions Output Load * Input pulse levels: 0V to 3.0V I/O Pin 645Ω * Input rise and fall times: 3ns 1.76V * Input and Output timing reference levels: 1.5V 100pF * Output load: see diagram * VCC=5V±10% Operation Truth Table CS OE WE DATA PINS SUPPLY CURRENT MODE H X X High Impedance ISB1 , ISB2 , ISB3 Standby L L H Data Out ICC1 Read L H L Data In ICC1 Write L L L Data In ICC1 Write L H H High-Impedance ISB1 , ISB2 , ISB3 High-Z Notes : H = VIH : L =VIL : X = VIH or VIL 3 ISSUE 1.5 : December 1998 SYS321000ZK/LK - 012/015/20/25 AC OPERATING CONDITIONS Read Cycle -12 Parameter -15 -20 -25 Symbol min max min max min max min max Unit Read Cycle Time tRC 12 - 15 - 20 - 25 - ns Address Access Time tAA - 12 - 15 - 20 - 25 ns Chip Select Access Time tACS - 12 - 15 - 20 - 25 ns Output Enable to Output Valid tOE - 6 - 7 - 10 - 12 ns Output Hold from Address Change tOH 3 - 3 - 4 - 5 - ns Chip Selection to Output in Low Z tCLZ 3 - 3 - 3 - 3 - ns Output Enable to Output in Low Z tOLZ 0 - 0 - 0 - 0 - ns Chip Deselection to O/P in High Z tCHZ 0 7 0 7 0 8 0 10 ns Output Disable to Output in High Z tOHZ 0 7 0 7 0 8 0 10 ns Write Cycle -12 Parameter -15 -20 -25 Symbol min max min max min max min max Unit Write Cycle Time tWC 12 - 15 - 20 - 25 - ns Chip Selection to End of Write tCW 8 - 12 - 15 - 15 - ns Address Valid to End of Write tAW 8 - 12 - 15 - 15 - ns Address Setup Time tAS 0 - 0 - 0 - 0 - ns Write Pulse Width tWP 15 - 15 - 15 - 15 - ns Write Recovery Time tWR 0 - 0 - 0 - 0 - ns Write to Output in High Z tWHZ 0 6 0 7 0 8 0 10 ns Data to Write Time Overlap tDW 6 - 8 - 10 - 12 - ns Data Hold from Write Time tDH 0 - 0 - 0 - 0 - ns Output active from End of Write tOW 0 - 0 - 0 - 0 - ns 4 SYS321000ZK/LK - 012/015/20/25 ISSUE 1.5 : December 1998 Read Cycle Timing Waveform (1,2) t RC Address t AA OE t OE t OH t OLZ CS1~4 t ACS Don't care. t OHZ (3) t CLZ (4,5) Dout Data Valid t CHZ (3,4,5) AC Read Characteristics Notes (1) WE is High for Read Cycle. (2) All read cycle timing is referenced from the last valid address to the first transition address. (3) tCHZ and tOHZ are defined as the time at which the outputs achieve open circuit conditions and are not referenced to output voltage levels. (4) At any given temperature and voltage condition, tCHZ (max) is less than tCLZ (min) both for a given module and from module to module. (5) These parameters are sampled and not 100% tested. Write Cycle No.1 Timing Waveform(1,4) tWC Address t WR(7) OE t AS(6) t AW t CW CS1~4 Don't Care WE t OHZ(3,9) t OW t WP(2) High-Z Dout t DW Din High-Z t DH Data Valid 5 (8) ISSUE 1.5 : December 1998 SYS321000ZK/LK - 012/015/20/25 Write Cycle No.2 Timing Waveform (1,5) tWC Address t AS(6) t WR(7) t CW CS1~4 t AW t WP(2) WE tOH t WHZ(3,9) t OW High-Z Dout t DW Din (8) (4) Don't Care t DH High-Z Data Valid AC Write Characteristics Notes (1) All write cycle timing is referenced from the last valid address to the first transition address. (2) All writes occur during the overlap of CS1~4 and WE low. (3) If OE, CS1~4, and WE are in the Read mode during this period, the I/O pins are low impedance state. Inputs of opposite phase to the output must not be applied because bus contention can occur. (4) Dout is the Read data of the new address. (5) OE is continuously low. (6) Address is valid prior to or coincident with CS1~4 and WE low, too avoid inadvertant writes. (7) CS1~4 or WE must be high during address transitions. (8) When CS1~4 are low : I/O pins are in the output state. Input signals of opposite phase leading to the output should not be applied. (9) Defined as the time at which the outputs achieve open circuit conditions and are not referenced to output voltage levels. These parameters are sampled and not 100% tested. 6 SYS321000ZK/LK - 012/015/20/25 Package Information ISSUE 1.5 : December 1998 Dimensions in mm(inches) Plastic 72 Pin ZIP 8.89 MAX. 97.79 MAX 14.61 MAX. 6.35 TYP. 2.54 TYP. 2.54 TYP. Plastic 72 Pin SIMM 9.10 Max 15.00 Max. 1 08 .0 8 M ax. 6.35 Typ. 1.27 Typ. Ordering Information SYS 321000 ZK/LK I - 015 Speed 012 015 020 025 = 12 ns = 15 ns = 20 ns = 25 ns Temperature range Blank I = Commercial Temp. = Industrial Temp. Power Consumption Blank = Standard Part Package Organisation Memory Type ZK LK 321000 SYS = Plastic 72 Pin ZIP = Plastic 72 Pin SIMM = 1M X 32 = Static RAM Note : Although this data is believed to be accurate the information contained herein is not intended to and does not create any warranty of merchantibility or fitness for a particular purpose. Our products are subject to a constant process of development. Data may be changed without notice. Products are not authorised for use as critical components in life support devices without the express written approval of a company director. 7