TOSHIBA TB62725

TOSHIBA
T B 6 2 7 2 5 P / F / FN
TOSHIBA Bi-CMOS INTEGRATED CIRCIUTS SILICON MONOLITHIC
TB62725P/F/FN
8BIT CONSTANT CURRENT LED DRIVER OF OPERATING VOLTAGE 3.3V
TB62725 series is the constant current driver designed
for LED and the LED display. Output current value is
set with one resistor with the outside.
Then, all the output becomes the about same current.
This driver builds in the constant current output of
eight bits, the shift register of eight bits, the latch of
eight bits and gate circuit.
This driver is designed by using the BI-CMOS process.
FEATURE
*Output Current Capability and the number of the output :
90mA X 8 outputs
*Constant Current Range : 5 to 90mA
*Application Output Voltage :
0.7V (output current 40 to 80 mA)
0.4V (output current 5 to 40 mA)
*For Annode Common LED
*Input Signal Voltage Level :
3.3V CMOS Level (Shmitt Triggered Input)
*Power Supply Voltage Range VDD=3.0 to 3.6V
*Muximum output terminal voltage 17V
*Serial and Pararell Data Transfer Rate :
20MHz (max, Cascade Connection)
*Operation Temperature Range :
Topr= -40 to 85 degrees
*Package :
Type P : DIP16-P-300-2.56A
Type F : SSOP16-P-225-1.00
Type FN : SSOP16-P-225-0.65
*Package and Pin Layout : Same as the TB62705 series.
TB62725P
DIP16-P-300-2.56A
TB62725F
SSOP16-P-225-1.00
TB62725FN
SSOP16-P-225-0.65
*Constant Current Error bitween bits ( All Output On )
Output
Voltage
>= 0.4V
>= 0.7V
Current
Error
between bits
+/- 6%
Current
Error
between ICs
+/- 15%
Output
Current
2 to 40 mA
2 to 90 mA
Weight :
1.11 g(Typ.) - - - Type P
0.14 g(Typ.) - - - Type F
0.07 g(Typ.) - - - Type FN
Pin layout (TOP VIEW)
GND
SERIAL-IN
CLOCK
/LATCH
OUT0
OUT1
OUT2
OUT3
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VDD
R-EXT
SERIAL-OUT
/ENABLE
OUT7
OUT6
OUT5
OUT4
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TOSHIBA
T B 6 2 7 2 5 P / F / FN
BLOCK DIAGRAM
R-EXT
OUT0
OUT1
OUT7
I-REG
/ENABLE
Q
Q
Q
ST D
ST D
ST D
/LATCH
SERIAL-IN
D
Q
D
CK
Q
CK
D
SERIAL-OUT
Q
CK
CLOCK
TRUTH TABLE
CLOCK
UP
UP
UP
DOWN
DOWN
/LATCH
H
L
H
X
X
/ENABLE
L
L
L
L
H
SERIAL-IN
Dn
Dn+1
Dn+2
Dn+3
Dn+3
OUT0 --- OUT5 --- OUT7
Dn --- Dn-5 --- Dn-7
No Change
Dn+2 --- Dn-3 --- Dn-5
Dn+2 --- Dn-3 --- Dn-5
Off
SERIAL-OUT
Dn-7
Dn-6
Dn-5
Dn-5
Dn-5
Note) "OUT0 to 7 = On" in case of Dn= "H" Level and "OUT0 to 7 = Off" in case of Dn= "L" Level.
A resistor is connected with R-EXT and GND accompanied with outside, and it is necessary that a correct power
supply voltage is supplied.
TIMING DIAGRAM
CLOCK
SERIAL-IN
/LATCH
/ENABLE
OUT0
OUT1
OUT3
OUT7
SERTIAL-OUT
5V
0V
5V
0V
5V
0V
5V
0V
On
Off
On
Off
On
Off
On
Off
5V
0V
Note) Latches are level sensitive, not rising edge sensitive and not syncronus CLOCK.
Input of LATCH-terminal to "H" level, data passes latches and input to "L" level, data hold latches.
Input of ENABLE-terminal to "H" level, all output ( OUT0 to 7 ) off.
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T B 6 2 7 2 5 P / F / FN
TERMINAL DISCRIPTION
PIN No.
PIN NAME
FUNCTION
1
GND
2
SERIAL-IN
GND terminal for control logic.
3
CLOCK
4
/LATCH
5~12
OUT0 to 7
Output terminals.
13
/ENABLE
Input terminal of output enable. All outputs (OUT0 to 7) do off with "H" level input
of ENABLE-terminal, and do on with "L" level input.
14
SERIAL-OUT
15
R-EXT
16
VDD
Input terminal of a serial-data for shift-register
Input terminal of a clock for data shift to up-edge.
Input terminal of a data strobe. Latches passes data with "H" level input of
LATCH-terminal, and hold data with "L" level input.
Output terminal of a serial-data for next SERIAL-IN terminal.
Input terminal of connects with a resister for to set up all output current.
5V Supply voltage terminal
EQUIVALENT CIRCUIT OF INPUTS AND OUTPUTS
1. /ENABLE Terminal
VDD
2. /LATCH Terminal
R(UP)
VDD
/ENABLE
/LATCH
GND
GND
3. CLOCK,SERIAL-IN Terminal
R(DOWN)
4. SERIAL-OUT Terminal
VDD
VDD
CLOCK,
SERIAL - IN
8th DATA
GND
SERIAL - OUT
GND
5. OUT0 to 7 Terminal
OUT 0 to 7
GND
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TOSHIBA
T B 6 2 7 2 5 P / F / FN
MAXIMUM RATINGS ( Ta = 25degC )
CHARACTERISTICS
SYMBOL
RATING
UNIT
Supply Voltage
Input Voltage
VDD
0 to 7
V
VIN
-0.2 to VDD+0.2
Output Current
IOUT
+90
mA/ch
Output Voltage
VOUT
-0.5 to 17
V
Power Dissipation
Pd1
Type P : 1.47(Free Air)
W
Pd2
Type F and FN : 0.37 (Free Air), 0.78 (On PCB)
Rth(j-a)1
Type P : 85(Free Air)
Rth(j-a)2
Type F and FN : 330 (Free Air),160 (On PCB)
Oparating Temperature
Topr
-40 to 85
Storage Temperature
Tstg
-55 to 150
Thrmal Resistance
degC/W
degC
Note) Type P : Ambient temperature delated above 25degC in the proportion of 11.76 mW/degC.
Type F and FN : Ambient temperature delated above 25degC in the proportion of 7.69 mW/degC.
Condition) On PCB at 50 X 50 X 1.6mm Cu <= 40% ( Glass Epoxy PCB )
RECOMMENDED OPERATING CONDITION (Ta=-40 to 85degC unless otherwise noted)
CHARACTERISTICS
SYMBOL
Supply Voltage
VDD
CONDITION
Output Voltage
VOUT
Output Current
IOUT
Each DC 1 Circuit
IOH
SERIAL-OUT
MIN.
TYP.
MAX.
UNIT
3
3.3
3.6
V
0.7
2
IOL
Input Voltage
4
V
70
mA/ch
-1
mA
1
VIH
0.7VDD
VDD
+0.15
VIL
-0.15
0.3VDD
Clock Frequency
fCLK
/LATCH Pulse Width
tw /LATCH
CLOCK Pulse Width
tw CLOCK
/ENABLE Pulse Width
tw /ENABLE
Cascade Connected
20
MHz
50
25
Upper IOUT = 20 mA
2000
Lower IOUT = 20 mA
4500
Setup Time
for CLOCK Terminal
tsetup1
10
Hold Time
for CLOCK Terminal
thold
5
Setup Time
for /LATCH Terminal
tsetup2
50
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V
ns
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T B 6 2 7 2 5 P / F / FN
ELECTRICAL CHARACTERISTICS (VDD=3.3V, Ta=25degC unless otherwise noted)
SYMBOL
VDD
IOUT1
IOUT2
Output Current
dIOUT1
Error bitween bits
dIOUT2
Output Leakage
Current
IOZ
Input Voltage
VIH
0.7
VDD
VIL
GND
SOUT Terminal
Output Voltage
Output Currnet
Supply Voltage
Reguration
Pull up Resistor
Pull down Resistor
CONDITION
Normal Operation
VOUT=0.4V,REXT=490ohms
VOUT=0.7V,REXT=250ohms
VOUT>=0.4V,REXT=490ohms
All outout on.
VOUT>=0.7V,REXT=250ohms
All outout on.
M IN
3.0
31.9
62.6
CHARACTERISTICS
Supply Voltage
Output Current
VOUT=15.0V
VOL
VOH
IOH=+1mA
IOL=-1mA
%/VDD
VDD = 3V to 3.6V
R(up)
R(down)
IDD(OFF)1
/ENABLE Terminal
/LATCH Terminal
REXT=OPEN,VOUT=15.0V
REXT=490Ohms,
VOUT=15V,OUT0 to 7 are Off.
REXT=250Ohms,
VOUT=15V,OUT0 to 7 are Off.
REXT=490Ohms,
VOUT=0.7V,OUT0 to 7 are On.
Same as the avobe , Ta=-40degC
REXT=250Ohms,
VOUT=0.7V,OUT0 to 7 are On.
Same as the avobe , Ta=-40degC
IDD(OFF)2
Supply Current
IDD(OFF)3
IDD(ON)1
IDD(ON)2
TYP
3.3
37.5
73.6
MAX
3.6
43.1
84.6
UNIT
V
mA
+/-1.5
+/-6
%
+/-1.5
+/-6
1.0
5.0
uA
VDD
0.3
VDD
0.4
V
+/-1.5
+/-5.0
%
100
125
200
250
1
400
500
2
kohms
1
3
5
3
6
8
2.8
mA
7
14
13
25
SWITCHING CHARACTERISTICS (Ta=25degC unless otherwise noted)
CHARACTERISTICS
SYBOL
TEST CONDITION
CLK - OUTn,
/LATCH="H",/ENABLE="L"
/LATCH - OUTn, /ENABLE="L"
/ENABLE - OUTn, /LATCH="H"
CLK - SERIAL OUT
CLK - OUTn,
/LATCH="H",/ENABLE="L"
/LATCH - OUTn, /ENABLE="L"
tpLH1
Propagation
tpLH2
tpLH3
tpLH
Delay Time
tpHL1
Output Rise Time
Output Fall Time
Muximum CLOCK
Rise Time
Muximum CLOCK
Fall Time
tpHL2
tpHL3
tpHL
t or
t of
MIN
/ENABLE - OUTn, /LATCH="H"
CLK - SERIAL OUT
Voltage Waveform 10% to 90%
Voltage Waveform 90% to 10%
TYP
MAX
UNIT
140
140
140
5
170
170
170
6
70
90
ns
tr
Cascade connection isn't guarantee.
5
tf
(Note1)
5
us
Condition : (Refer to test circuit.)
Ta= 25 degC, VDD=VIH=3.3V, VOUT=0.7V, VIL=0V, REXT=490ohms, VL=3.0V, RL=60ohms, CL=10.5pF
Note 1 : When tf / tf of clock wave form is enlarged at the time as the cascade connection,
the timing condition which is necessary for the data transfer may not be able to be secured.
Give careful consideration to the timing condition.
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T B 6 2 7 2 5 P / F / FN
TEST CIRCUIT
IDD
VDD
VIH,VIL
/ENABLE
RL
OUT0
CLOCK
Function
Generator
IOL
/LATCH
SERIAL-IN
R-EXT
LOGIC
INPUT WAVEFORM
CL
OUT7
SERIAL-OUT
GND
CL
VL
Iref
VDD=VIH=3.3V
VIL=0V
tr = tf = 10ns
(10% to 90%)
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T B 6 2 7 2 5 P / F / FN
TIMING WAVEFORM
1. CLOCK ,SERIAL-IN, SERIAL-OUT
CLOCK
SERIAL IN
tw CLK
50%
50%
50%
t SETUP1
50%
t HOLD
SERIAL-OUT
50%
tpLH/tpHL
2. CLOCK, SERIAL-IN , /LATCH, /ENABLE, OUTn
CLOCK
50%
SERIAL IN
/LATCH
t SETUP2
50%
50%
tw LAT
tw ENA
/ENABLE
50%
t SETUP2
50%
OUTn
50%
tpHL1/LH1
tpHL2/LH2
tpHL3/LH3
3. OUTn
90%
90%
OUTn
10%
tof
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10%
tor
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T B 6 2 7 2 5 P / F / FN
OUTPUT CURRNET vs Duty (LED Turn On Rate)
DUTY(%)-IOUT(mA) On PCB
Topr=55degC
VDD=3.3V, Vce=1.0(V), Tj=120(degC max)
100
100
90
90
80
80
70
70
60
60
IOUT(mA)
IOUT(mA)
DUTY(%)-IOUT(mA) On PCB
Topr=25degC
VDD=3.3V, Vce=1.0(V), Tj=120(degC max)
50
40
50
40
30
30
20
20
TB62725F/FN
10
TB62725F/FN
TB62725P
10
TB62725P
0
0
0
20
40
60
80
100
0
20
DUTY - Turn On Rate (%)
40
60
80
100
DUTY - Turn On Rate (%)
DUTY(%)-IOUT(mA) On PCB
Topr=85degC
VDD=3.3V, Vce=1.0(V), Tj=120(degC max)
100
90
80
IOUT(mA)
70
60
50
40
30
20
TB62725F/FN
TB62725P
10
0
0
20
40
60
80
100
DUTY - Turn On Rate (%)
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TOSHIBA
T B 6 2 7 2 5 P / F / FN
OUTPUT CURRNET vs Duty (LED Turn On Rate)
** Comparison in VDD=5V of TB62705 and TB6272
TB62705 & 725 DUTY(%)-IOUT(mA) On PCB
Topr=55degC
VDD=5.0V, Vce=1.0(V), Tj=120(degC max)
100
100
90
90
80
80
70
70
60
60
IOUT(mA)
IOUT(mA)
TB62705 & 725 DUTY(%)-IOUT(mA) On PCB
Topr=25degC
VDD=5.0V, Vce=1.0(V), Tj=120(degC max)
50
40
30
50
40
30
TB62725F/FN
20
TB62705CF/CFN
TB62705CP
10
TB62725F/FN
20
TB62725P
TB62725P
TB62705CF/CFN
TB62705CP
10
0
0
0
20
40
60
80
100
0
20
DUTY - Turn On Rate (%)
60
80
100
TB62705 & 725 DUTY(%)-IOUT(mA) On PCB
Topr=85degC
VDD=5.0V, Vce=1.0(V), Tj=120(degC max)
Ta(degC) - Pd(w)
1.6
1: F/FN(OnPCB)
100
2: P(FreeAir)
1.4
40
DUTY - Turn On Rate (%)
90
80
70
1
0.8
IOUT(mA)
Power dissipation PD (W/IC)
1.2
0.6
60
50
40
30
0.4
TB62725F/FN
20
0.2
TB62725P
TB62705CF/CFN
10
0
0
10
20
30
40
50
60
70
80
90
100
110
120
Ambient Temperature Ta (deg)
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130
140
TB62705CP
0
150
0
20
40
60
80
100
DUTY - Turn On Rate (%)
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T B 6 2 7 2 5 P / F / FN
OUTPUT CURRNET vs REXT RESISTOR
TB62725P/F/FN REXT-IOUT (Topr)
VDD=3.3(V), VCE=0.7(V)
90
80
70
IOUT(mA)
60
Topr=-40(degC)
Topr=+25(degC)
Topr=+85(degC)
50
40
30
20
10
0
100
1000
10000
REXT(Ohms)
IOUT[mA]=(1.14/REXT[ohms])*16 -- Theory formula
APPLICATION NOTES(1 of 2)
TB62725P/F/FN application circuit (a general example)
TB62725 Series recommend VLED=VDD= 3.3(V min) and data transfer of fclk=20(MHz) is possible at cascade connection.
1 : Vf of LED is Vf=2.5 (V max).
2 : Output saturation Vce1 = 0.4(V min) at Iout <= 40(mA) of TB62725.
3 : Output saturation Vce2 = -0.25(V max) at Ic = -1(A) of TD62M8600F.
4 : TB62725 can move with VDDopr = 3 to 3.6(V).
5 : When a necessary voltage to 1 from 3 is summed up,
the total voltage is less than 3.3(V),
and this circuit can move with VLED = VDD = 3.3 (V min).
Example) TD62M8600F
8-bit Multi-Chip PNP Tr Array,
which is not used in Static Lighting System.
Not Connect Resistor
SCAN
S-IN
C.U.
ENA
LAT
CLK
O0
O1
O2
O5
O6
8-bit SIPO,Latches &
Constant Sink Current Drivers
TB62725P/F/FN
r2
r1
O7
S-OUT
S-IN
ENA
LAT
CLK
O0
O1
O2
O5
O6
8-bit SIPO,Latches &
Constant Sink Current Drivers
O7
VLED
S-OUT
TB62725P/F/FN
r1
r1 : Resistance for a setup of output current.
r2 : Resistance for the LED module brightness adjustment.
This device owns only one ground pin that means signal ground pin and power ground pin are common.
If ground pattern layout contains large inductance and impedance, and the voltage between ground and LATCH, CLOCK terminals
exceeds 0.5*Vdd by switching noise in operation, this device may miss-operate.
So we would lile you to pay attention to pattern layout to minimize inductance.
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TOSHIBA
T B 6 2 7 2 5 P / F / FN
APPLICATION NOTES(2 of 2)
TB62725P/F/FN application circuit (the case of VLED>17(V) )
Example :
An unnecessary voltage in the case of VLED>17(V)
makes a voltage descend by the Zener diode.
Example) TD62M8600F
8-bit Multi-Chip PNP Tr Array,
which is not used in Static Lighting System.
SCAN
S-IN
ENA
C.U.
LAT
CLK
O0
O1
O2
O5
O6
O7
O0
S-OUT
8-bit SIPO,Latches &
Constant Sink Current Drivers
S-IN
ENA
LAT
TB62725P/F/FN
O1
O2
O5
O7
VLED
S-OUT
TB62725P/F/FN
CLK
r1
r2
O6
8-bit SIPO,Latches &
Constant Sink Current Drivers
r1
r1 : Resistance for a setup of output current.
r2 : Resistance for the LED module brightness adjustment.
TB62725P/F/FN application circuit (with VLED<=17(V), the case of the over-saturation)
Example :
An over-saturation voltage makes a voltage descend by the resistance with the outside.
Condition :
1 : Turn on LED with Iout=20(mA).
2 : LED of Vf=2.5( V max).
3 : saturation voltage =0.4(V min) at Ic= 20(mA) of TB62725
4 : saturation voltage =0.25(V min) at Ic= 320(mA) of TD62M8600F
Connect R1, and decrease the heat losses of the IC.
r3= ( 15-0.4-LED Vf*1 - 0.25 ) /20mA =592.5(Ohms)
Example) TD62M8600F
8-bit Multi-Chip PNP Tr Array,
which is not used in Static Lighting System.
r3
r3
SCAN
S-IN
C.U.
ENA
O0
O1
O2
O5
O6
8-bit SIPO,Latches &
Constant Sink Current Drivers
LAT
CLK
r2
TB62725P/F/FN
r1
O7
O0
S-OUT
S-IN
ENA
LAT
CLK
O1
O2
O5
O6
8-bit SIPO,Latches &
Constant Sink Current Drivers
O7
VLED
S-OUT
TB62725P/F/FN
r1
r1 : Resistance for a setup of output current.
r2 : Resistance for the LED module brightness adjustment.
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Toll Free: (800) 98-4LEDS• Fax: (518) 432-7454
TOSHIBA
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T B 6 2 7 2 5 P / F / FN
120 Broadway • Menands, New York 12204
Toll Free: (800) 98-4LEDS• Fax: (518) 432-7454
TOSHIBA
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T B 6 2 7 2 5 P / F / FN
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TOSHIBA
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T B 6 2 7 2 5 P / F / FN
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TOSHIBA
T B 6 2 7 2 5 P / F / FN
The information contained herein is subject to change without notice.
The information contained herein is presented only as a guide for the applications of our
products. No responsibility is assumed by TOSHIBA for any infringements of patens or other
rights of the third parties which may result from its use. No license is granted by implication
or otherwise under any patent or patent rights of TOSHIBA or others.
TOSHIBA is continually working to improve the quality and the reliability of its products.
Nevertheless, semiconductor devices in general can malfunction or fail due to their inherent
electrical sensitivity and vulnerability to physical stress. It is the responsibility of the buyer,
when utilizing TOSHIBA products, to observe standards of safety, and to avoid situations in
which a malfunction or failure of a TOSHIBA product could cause loss of human life, bodily
injury or damage to property.
In developing your designs, please ensure that TOSHIBA products are used within spacified
operating ranges as set forth in the most recent products spacifications. Also, please keep in
mind the precautions and conditions set forth in the TOSHIBA Semiconductor Reliability
Handbook.
The products described in the document may include products subject to foreign exchange
and foreign trade control laws.
(C) 2000 TOSHIBA CORPORATION
ALL RIGHT Reserved
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