MARKTECH TB62725BPG

TB62725BPG/BFG/BFNG TOSHIBA Bi­CMOS Integrated Circuit Silicon Monolithic TB62725BPG, TB62725BFG, TB62725BFNG 8­bit Constant­Current LED Driver of the 3.3­V and 5­V Power Supply Voltage Operation
The TB62725BPG/BFG/BFNG are comprised of
constant­current drivers designed for LEDs and LED displays.
The output current value can be set using an external resistor.
As a result, all outputs will have virtually the same current
levels.
This driver incorporates an 8­bit constant­current output, an
8­bit shift register, an 8­bit latch circuit and an 8­bit AND­gate
circuit.
These drivers have been designed using the Bi­CMOS process.
This devices are a product for the Pb free. TB62725BPG TB62725BFG Features
Output current capability and number of outputs:
90 mA × 8 outputs
Constant current range: 5 to 80 mA
Application output voltage:
0.7 V (output current 5 to 80 mA)
0.4 V (output current 5 to 40 mA)
For anode­common LEDs
Input signal voltage level: 3.3­V and 5­V CMOS level (Schmitt
trigger input)
TB62725BFNG Maximum output terminal voltage: 17 V
Serial data transfer rate: 20 MHz (max, cascade connection)
Operating temperature range: Topr = −40 to 85°C
Package:
Type BPG:
DIP16­P­300­2.54A
Type BFG:
SSOP16­P­225­1.00A
Type BFNG:
SSOP16­P­225­0.65B
Package and pin layout: Pin layout and functionality are similar
to those of the TB62705C series and TB62725A series.
(Each characteristic value is different.)
Constant­current accuracy (all outputs on) Output Voltage > 0.4 V =
> 0.7 V
=
Company Headquarters
3 Northway Lane North
Latham, New York 12110
Toll Free: 800.984.5337
Fax: 518.785.4725
Current Error between Bits Current Error between ICs ±6%
±15% Weight DIP16­P­300­2.54A: 1.11 g (typ.) SSOP16­P­225­1.00A: 0.14 g (typ.) SSOP16­P­225­0.65B: 0.07 g (typ.)
Output Current
5 to 40 mA
5 to 90 mA Web: www.marktechopto.com | Email: [email protected]
California Sales Office:
950 South Coast Drive, Suite 225
Costa Mesa, California 92626
Toll Free: 800.984.5337
Fax: 714.850.9314
TB62725BPG/BFG/BFNG Pin Assignment (top view)
Pin layout and functionality are similar to those of the TB62705C. (each characteristic value is different.) VDD GND R­EXT SERIAL­IN CLOCK SERIAL­OUT LATCH OUT0 ENABLE OUT7 OUT1 OUT6 OUT2 OUT5 OUT3 OUT4
Block Diagram OUT1 OUT0 R­EXT OUT7 I­REG ENABLE Q Q L D L D Q L D LATCH D Q SERIAL­IN CK D Q CK D Q SERIAL­OUT CK CLOCK Truth Table CLOCK LATCH ENABLE SERIAL­IN OUT0 ­­­ OUT5 ­­­ OUT7 SERIAL­OUT H L Dn Dn ­­­ Dn - 5 ­­­ Dn - 7 Dn - 7 L L Dn + 1 No change Dn - 6 H L Dn + 2 Dn + 2 ­­­ Dn - 3 ­­­ Dn - 5 Dn - 5 X L Dn + 3 Dn + 2 ­­­ Dn - 3 ­­­ Dn - 5 Dn - 5 X H Dn + 3 Off Dn - 5 Note 1: OUT0 to OUT7 = On when Dn = H; to OUT0 to OUT7 = Off when Dn = L. In order to ensure that the level of the power supply voltage is correct, an external resistor must be connected between R­EXT and GND. 2 2005­04­20 TB62725BPG/BFG/BFNG Timing Diagram n = 0 1 2 3 4 5 6 7 3.3 V/5 V CLOCK 0 V 3.3 V/5 V SERIAL­IN 0 V 3.3 V/5 V LATCH 0 V 3.3 V/5 V ENABLE 0 V On OUT0 Off OUT1 Off Off Off Off On On Off Off On OUT3 Off Off Off Off On OUT7 Off
On Off Off 3.3 V/5 V SERIAL­OUT 0 V Warning: Latch circuit is leveled­latch circuit. Be careful because it is not triggered­latch circuit. Note 2: The latches circuit holds data by pulling the LATCH terminal Low. And, when LATCH terminal is a high­level, latch circuit doesn’t hold data, and it passes from the input to the output. When ENABLE terminal is a low­level, output terminal OUT0 to OUT7 respond to the data, and on and off does. Attention: This IC can be used in 3.3 V or 5.0 V. However, use the VDD power supply and the input level in the same voltage system. 3 2005­04­20 TB62725BPG/BFG/BFNG Terminal Description Pin No. Pin Name 1 GND 2 SERIAL­IN 3 CLOCK 4 LATCH Function GND terminal for control logic. Input terminal for serial data for data shift register. Input terminal for clock for data shift on rising edge. Input terminal for data strobe. When the LATCH input is driven High, data is latched. When it is pulled Low, data is hold. OUT0 to OUT7 5 to 12 Constant­current output terminals. Input terminal for output enable. 13 ENABLE All outputs ( OUT0 to OUT7 ) be turned off, when the ENABLE terminal is driven High. And are turned on, when the terminal is driven Low. 14 SERIAL­OUT 15 R­EXT 16 VDD Output terminal for serial data input on SERIAL­IN terminal. Input terminal used to connect an external resistor. This regulated the output current. 3.3­V and 5­V supply voltage terminal. Equivalent Circuits for Inputs and Outputs ENABLE Terminal LATCH Terminal R (UP) VDD 200 kW
VDD LATCH 100 W
GND GND R (DOWN) CLOCK, SERIAL­IN Terminal SERIAL­OUT Terminal VDD CLOCK, SERIAL­IN 100 W
250 kW
ENABLE VDD SERIAL­OUT 100 W
100 W
GND GND OUT0 to OUT7 Terminals OUT0 to OUT7 Parasitic Diode GND
4 2005­04­20 TB62725BPG/BFG/BFNG Maximum Ratings (Topr = 25°C) Characteristics Supply voltage Input voltage Symbol Rating Unit VDD 6 V VIN
-0.2 to VDD + 0.2 V Output current IOUT 90 mA/ch Output voltage VOUT
-0.2 to 17 V Pd1 1.47 BPG­type (when not mounted) Power dissipation BFG/BFNG­type (when not mounted) (Note 3) Thermal resistance (Note 3) BFG/BFNG­type (on PCB) 0.37 W Pd2 0.78 BPG­type (when not mounted) Rth (j­a) 1 85 BFG/BFNG­type (when not mounted) Rth (j­a) 2 330 BFG/BFNG­type (on PCB) Rth (j­a) 3 160 °C/W Operating temperature Topr
-40 to 85 °C Storage temperature Tstg
-55 to 150 °C Note 3: BPG­type: Power dissipation is delated by 11.76 mW/°C if device is mounted on PCB and ambient temperature is above 25°C. BFG and BFNG­type: Power dissipation is delated by 7.69 mW/°C if device is mounted on PCB and ambient temperature is above 25°C. With device mounted on glass­epoxy PCB of less than 40% Cu and of dimensions 50 mm ´ 50 mm ´ 1.6 mm Recommended Operating Conditions (Topr = -40°C to 85°C unless otherwise specified) Characteristics Symbol Test Condition Supply voltage VDD
¾
3 Output voltage VOUT
¾
¾
0.7 Each DC 1 circuit 5
IOH SERIAL­OUT
IOL SERIAL­OUT
IOUT Output current VIH Input voltage ¾
VIL
Clock frequency fCLK LATCH pulse width Cascade Connected
t w LATCH Unit 5.5 V 4 V ¾
80 mA/ch ¾
¾
-1 ¾
¾
1 0.7 ´
VDD
¾
VDD +
0.15 -0.15
¾
0.3 ´
VDD ¾
¾
20 MHz ns 50
¾
¾
¾
¾
IOUT < 20 mA 3000
¾
¾
25
¾
¾
10
¾
¾
tHOLD 10
¾
¾
tSETUP2
50
¾
¾
t w ENABLE twCLOCK Set­up time for CLOCK terminal tSETUP1 Set­up time for LATCH terminal Max 2000
CLOCK pulse width Hold time for CLOCK terminal Typ. IOUT >
= 20 mA ENABLE pulse width (Note 4) Min ¾
¾
mA mA ns ns Note 4: When the pulse of the low level is inputted to the ENABLE terminal held in the high level.
5 2005­04­20 TB62725BPG/BFG/BFNG Electrical Characteristics (VDD = 5 V, Ta = 25°C unless otherwise specified) Characteristics Supply voltage Symbol VDD Output leakage current Normal operation Output voltage Typ. Max Unit 4.5 5 5.5 V VOUT = 0.4 V,
VDD = 3.3 V REXT = 490 W
29.84 35.10 40.36 IOUT2 VOUT = 0.4 V,
VDD = 5 V REXT = 250 W
29.58 34.80 40.02 IOUT3 VOUT = 0.7 V,
VDD = 3.3 V REXT = 490 W
58.40 68.70 79.00 IOUT4 VOUT = 0.7 V,
VDD = 5 V REXT = 250 W
57.55 67.70 77.85 DIOUT1 VOUT = 0.4 V,
All outputs ON REXT = 490 W
¾
±1.5
±6 DIOUT2 VOUT = 0.7 V,
All outputs ON REXT = 250 W
IOZ mA
% VOUT = 15 V
¾
±1.5
±6 ¾
1 5
VIH
¾
0.7 VDD
¾
VDD VIL
¾
GND
¾
0.3 VDD IOH = 1.0 mA, VDD = 3.3 V
¾
¾
0.3 IOH = 1.0 mA, VDD = 5 V
¾
¾
0.3 IOL = -1.0 mA, VDD = 3.3 V 3
¾
¾
IOH = 1.0 mA, VDD = 5 V 4.7
¾
¾
Input voltage SOUT terminal Min IOUT1 Output current Output current Error between bits
Test Condition VOL VOH mA V V V Output current Supply voltage Regulation %/VDD VDD = 3 V ® 5.5 V
¾
±1.5
±5.0 % Pull­up resistor R (Up) ENABLE terminal 100 200 400 kW
LATCH terminal 125 250 500 kW
Pull­down resistor R (Down) IDD (OFF) 1 VOUT = 15.0 V REXT = OPEN
¾
0.1 0.5 IDD (OFF) 2 VOUT = 15.0 V, All outputs OFF REXT = 490 W
1 3 5 IDD (OFF) 3 VOUT = 15.0 V, All outputs OFF REXT = 250 W
3 6 8 VOUT = 0.7 V, All outputs ON REXT = 490 W
¾
6 9 Same as the above, Topr = -40°C
¾
¾
15 VOUT = 0.7 V, All outputs ON
¾
12 17 ¾
¾
29 Supply current IDD (ON) 1 IDD (ON) 2 Same as the above, Topr = -40°C 6 mA
REXT = 250 W
2005­04­20 TB62725BPG/BFG/BFNG Switching Characteristics (Topr = 25°C unless otherwise specified) Characteristics Symbol Test Condition Typ. Max ¾
150 300 CLK to OUTn , LATCH = “H”, tpLH1 Propagation delay time Min ENABLE = “L”
tpLH2 LATCH to OUTn , ENABLE = “L”
¾
140 300 tpLH3 ENABLE to OUTn , LATCH = “H”
¾
140 300 tpLH CLK to SERIAL OUT 2 5
¾
¾
170 340 CLK to OUTn , LATCH = “H”, tpHL1 ENABLE = “L”
tpHL2 LATCH to OUTn , ENABLE = “L”
¾
170 340 tpHL3 ENABLE to OUTn , LATCH = “H”
¾
170 340 tpHL CLK to SERIAL OUT 2 5
¾
Unit ns Output rise time tor 10 to 90% of voltage waveform 40 85 150 ns Output fall time tof 90 to 10% of voltage waveform 40 70 150 ns Maximum clock rise time tr
Cascade connection isn’t guarantee. ¾
¾
5 us Maximum clock fall time tf ¾
¾
5 us (Note 5)
Conditions: (refer to test circuit.) Topr = 25°C, VDD = VIH = 5 V, VOUT = 0.7 V, VIL = 0 V, REXT = 490 W, VL = 5.0 V, RL = 100 W, CL = 10.5 pF Note 5: If the device is connected in a cascade and tr/tf for the waveform is large, it may not be possible to achieve the timing required for data transfer. Please consider the timings carefully. Test Circuit IDD
VIH , VHL ENABLE RL VDD OUT0 CL Function generator CLOCK IOL LATCH OUT7 SERIAL­IN SERIAL­OUT R­EXT Logic input waveform VL GND CL Iref VDD = VIH = 5 V VIL = 0 V tr = tf = 10 ns (10% to 90%) 7 2005­04­20 TB62725BPG/BFG/BFNG Timing Waveforms 1. CLOCK, SERIAL­IN, SERIAL­OUT twCLK CLOCK 50% 50% tSETUP1 SERIAL­IN 50% 50% tHOLD SERIAL­OUT 50% tpLH/tpHL 2. CLOCK, SERIAL­IN, LATCH , ENABLE , OUTn CLOCK 50% SERIAL­IN tSETUP2 LATCH 50% 50% twLAT ENABLE twENA 50% tSETUP3 50% 50% OUTn
tpHL1/LH1 tpHL2/LH2 tpHL3/LH3 3. OUTn 90% 90% OFF OUTn 10% 10% tof ON tof 8 2005­04­20 TB62725BPG/BFG/BFNG Output Current – Duty (LED turn­on rate) IOUT – DUTY On PCB (recommended) 100 100 80 80 60 60 IOUT (mA) IOUT (mA) IOUT – DUTY On PCB ( recommended ) 40 Topr = 25°C 20 VDD = 5.0 V VCE = 1.0 V 20 Topr = 55°C 20 VDD = 5.0 V VCE = 1.0 V BFG/BFNG BPG Tj = 120°C (max) 0 0 40 60 40 BFG/BFNG BPG Tj = 120°C (max) 80 0 0 100 20 40 60 80 DUTY – Turn on rate (%) DUTY – Turn on rate (%) Pd –Topr IOUT – DUTY On PCB (recommended) 1.6 100 100 1.2 80 BPG (Free air)
1.0 IOUT (mA) Power dissipation PD (W/IC) 1.4 0.8 0.6 BFG/BFNG (mounted PCB) 60 40 0.4 Topr = 85°C 20 VDD = 5.0 V 0.2 BFG/BFNG BPG VCE = 1.0 V 0 0 20 60 40 80 Tj = 120°C (max) 100 0 0 Ambient temperature Ta (°C) 20 40 60 80 100 DUTY – Turn on rate (%) IOUT – REXT 90 IOUT (mA) = (1.15 ¸ REXT (W)) ´ 14.9 80 70 IOUT (mA) 60 50 40 Topr = 25°C 30 20 10 VCE = 0.7 V 0 100 500 1000 5000 10000 REXT (W) 9 2005­04­20 TB62725BPG/BFG/BFNG Application Circuit (example 1): The general composition in static lighting of LED.
More than VLED (V) >
= Vf (total max) +0.7 is recommended with the following application circuit with the LED power supply VLED.
r1: The setup resistance for the setup of output current of every IC.
r2: The variable resistance for the brightness control of every LED module. Example) TD62M8600: 8­bit multi­chip PNP transistor array, which is not used in static lighting system. VLED SCAN O1 O2 O5 SERIAL­IN O1 O2 O7 SERIAL­OUT 8­bit SIPO, Latches and Constant­sink­current drivers ENABLE LATCH O5 O6 O7
SERIAL­OUT SERIAL­IN ENABLE 8­bit SIPO, Latches and Constant­sink­current drivers LATCH TB62725BPG/BFG/BFNG r2 CLOCK TB62725BPG/BFG/BFNG r1 = 100 W
(min) CLOCK r1 =
100 W
(min) C.U. O6 10 2005­04­20 TB62725BPG/BFG/BFNG Application Circuit (example 2): When the condition of VLED is VLED > 17 V.
The unnecessary voltage is one effective technique as to making the voltage descend with the zennor diode. Example) TD62M8600: 8­bit multi­chip PNP transistor array, which is not used in static lighting system. VLED SCAN O1 O2 O5 SERIAL­IN O1 O2 O7 SERIAL­OUT 8­bit SIPO, Latches and Constant­sink­current drivers ENABLE LATCH O5 O6 O7
SERIAL­OUT SERIAL­IN ENABLE 8­bit SIPO, Latches and Constant­sink­current drivers LATCH TB62725BPG/BFG/BFNG r2 CLOCK TB62725BPG/BFG/BFNG r1 =
100 W
CLOCK r1 =
100 W
C.U. O6 11 2005­04­20 TB62725BPG/BFG/BFNG Application Circuit (example 3): When the condition of VLED is Vf + 0.7 < VLED < 17 V.
VOUT = VLED - Vf = 0.7 to 1.0 V is the most suitable for VOUT.
Surplus VOUT causes an IC fever and the useless consumption electric power.
It is the one way of being effective to build in the r3 in this problem.
r3 can make a calculation to the formula r3 (ohms) = surplus VOUT/IOUT.
Though the resistance parts increase, the fixed constant current performance is kept. Example) TD62M8600: 8­bit multi­chip PNP transistor array, which is not used in static lighting system. r3 r3 VLED = 15 V SCAN O1 O2 O5 SERIAL­IN O7 O1 O2 SERIAL­OUT 8­bit SIPO, Latches and Constant­sink­current drivers ENABLE LATCH O5 O6 O7 SERIAL­OUT SERIAL­IN ENABLE 8­bit SIPO, Latches and Constant­sink­current drivers LATCH TB62725BPG/BFG/BFNG r2 CLOCK TB62725BPG/BFG/BFNG
r1 =
100 W
CLOCK r1 =
100 W
C.U. O6 12 2005­04­20 TB62725BPG/BFG/BFNG Notes
Operation may become unstable due to the electromagnetic interference caused by the wiring and other phenomena.
To counter this, it is recommended that the IC be situated as close as possible to the LED module.
If overvoltage is caused by inductance between the LED and the output terminals, both the LED and the
terminals may suffer damage as a result.
There is only one GND terminal on this device when the inductance in the GND line and the resistor are large, the
device may malfunction due to the GND noise when output switching by the circuit board pattern and wiring.
To achieve stable operation, it is necessary to connect a resistor between the REXT terminal and the GND line.
Fluctuation in the output waveform is likely to occur when the GND line is unstable or when a capacitor (of
more than 50 pF) is used.
Therefore, take care when designing the circuit board pattern layout and the wiring from the controller.
This application circuit is a reference example and is not guaranteed to work in all conditions.
Be sure to check the operation of your circuits.
This device does not include protection circuits for over voltage, over current or over temperature.
If protection is necessary, it must be incorporated into the control circuitry.
The device is likely to be destroyed if a short­circuit occurs between either of the power supply pins and any of the
output terminals when designing circuits, pay special attention to the positions of the output terminals and the
power supply terminals (VDD and VLED), and to the design of the GND line.
13 2005­04­20 TB62725BPG/BFG/BFNG Package Dimensions Weight: 1.11 g (typ.)
14 2005­04­20 TB62725BPG/BFG/BFNG Package Dimensions Weight: 0.14 g (typ.)
15 2005­04­20 TB62725BPG/BFG/BFNG Package Dimensions Weight: 0.07 g (typ.)
16 2005­04­20 TB62725BPG/BFG/BFNG About solderability, following conditions were confirmed Solderability Use of Sn­63Pb solder Bath ∙ solder bath temperature = 230°C ∙ dipping time = 5 seconds ∙ the number of times = once ∙ use of R­type flux Use of Sn­3.0Ag­0.5Cu solder Bath ∙ solder bath temperature = 245°C ∙ dipping time = 5 seconds ∙ the number of times = once ∙ use of R­type flux
RESTRICTIONS ON PRODUCT USE 000707EBA TOSHIBA is continually working to improve the quality and reliability of its products. Nevertheless, semiconductor devices in general can malfunction or fail due to their inherent electrical sensitivity and vulnerability to physical stress. It is the responsibility of the buyer, when utilizing TOSHIBA products, to comply with the standards of safety in making a safe design for the entire system, and to avoid situations in which a malfunction or failure of such TOSHIBA products could cause loss of human life, bodily injury or damage to property. In developing your designs, please ensure that TOSHIBA products are used within specified operating ranges as set forth in the most recent TOSHIBA products specifications. Also, please keep in mind the precautions and conditions set forth in the “Handling Guide for Semiconductor Devices,” or “TOSHIBA Semiconductor Reliability Handbook” etc.. The TOSHIBA products listed in this document are intended for usage in general electronics applications (computer, personal equipment, office equipment, measuring equipment, industrial robotics, domestic appliances, etc.). These TOSHIBA products are neither intended nor warranted for usage in equipment that requires extraordinarily high quality and/or reliability or a malfunction or failure of which may cause loss of human life or bodily injury (“Unintended Usage”). Unintended Usage include atomic energy control instruments, airplane or spaceship instruments, transportation instruments, traffic signal instruments, combustion control instruments, medical instruments, all types of safety devices, etc.. Unintended Usage of TOSHIBA products listed in this document shall be made at the customer’s own risk. The products described in this document are subject to the foreign exchange and foreign trade laws. The information contained herein is presented only as a guide for the applications of our products. No responsibility is assumed by TOSHIBA CORPORATION for any infringements of intellectual property or other rights of the third parties which may result from its use. No license is granted by implication or otherwise under any intellectual property or other rights of TOSHIBA CORPORATION or others. The information contained herein is subject to change without notice. 17 2005­04­20