TC59LM814/06CFT-50,-55,-60
TOSHIBA MOS DIGITAL INTEGRATED CIRCUIT SILICON MONOLITHIC
TM
4,194,304-WORDS × 4 BANKS × 16-BITS Network FCRAM
TM
8,388,608-WORDS × 4 BANKS × 8-BITS Network FCRAM
DESCRIPTION
Network FCRAMTM is Double Data Rate Fast Cycle Random Access Memory. TC59LM814/06CFT are Network
FCRAMTM containing 268,435,456 memory cells. TC59LM814CFT is organized as 4,194,304-words × 4 banks s× 16
bits, TC59LM806CFT is organized as 8,388,608 words × 4 banks × 8 bits. TC59LM814/06CFT feature a fully
synchronous operation referenced to clock edge whereby all operations are synchronized at a clock input which
enables high performance and simple user interface coexistence. TC59LM814/06CFT can operate fast core cycle
using the FCRAMTM core architecture compared with regular DDR SDRAM.
TC59LM814/06CFT is suitable for Network, Server and other applications where large memory density and low
power consumption are required. The Output Driver for Network FCRAMTM is capable of high quality fast data
transfer under light loading condition.
FEATURES
PARAMETER
CL = 3
CL = 4
tRC
Random Read/Write Cycle Time (min)
tRAC Random Access Time (max)
IDD1S Operating Current (single bank) (max)
lDD2P Power Down Current (max)
lDD6 Self-Refresh Current (max)
tCK
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Clock Cycle Time (min)
-50
TC59LM814/06
-55
-60
5.5 ns
5 ns
25 ns
22 ns
190 mA
2 mA
3 mA
6 ns
5.5 ns
27.5 ns
24 ns
180 mA
2 mA
3 mA
6.5 ns
6 ns
30 ns
26 ns
170 mA
2 mA
3 mA
Fully Synchronous Operation
• Double Data Rate (DDR)
Data input/output are synchronized with both edges of DQS.
• Differential Clock (CLK and CLK ) inputs
CS , FN and all address input signals are sampled on the positive edge of CLK.
Output data (DQs and DQS) is aligned to the crossings of CLK and CLK .
Fast clock cycle time of 5 ns minimum
Clock: 200 MHz maximum
Data: 400 Mbps/pin maximum
Quad Independent Banks operation
Fast cycle and Short Latency
Bidirectional Data Strobe Signal
Distributed Auto-Refresh cycle in 7.8 µs
Self-Refresh
Power Down Mode
Variable Write Length Control
Write Latency = CAS Latency-1
Programable CAS Latency and Burst Length
CAS Latency = 3, 4
Burst Length = 2, 4
Organization
TC59LM814CFT: 4,194,304 words × 4 banks × 16 bits
TC59LM806CFT: 8,388,608 words × 4 banks × 8 bits
Power Supply Voltage VDD:
2.5 V ± 0.15 V
VDDQ: 2.5 V ± 0.15 V
2.5 V CMOS I/O comply with SSTL-2 (half strength driver)
Package:
400 × 875 mil, 66 pin TSOPII, 0.65 mm pin pitch (TSOPII66-P-400-0.65)
Notice: FCRAM is a trademark of Fujitsu Limited, Japan.
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TC59LM814/06CFT-50,-55,-60
PIN NAMES
PIN ASSIGNMENT (TOP VIEW)
PIN
NAME
TC59LM814CFT
A0~A14
Address Input
BA0, BA1
Bank Address
DQ0~DQ7 (×8)
Data Input/Output
DQ0~DQ15 (×16)
CS
Chip Select
FN
Function Control
PD
Power Down Control
CLK, CLK
Clock Input
DQS (×8)
Write/Read Data Strobe
UDQS/LDQS (×16)
VDD
Power (+2.5 V)
VSS
Ground
VDDQ
Power (+2.5 V)
(for I/O buffer)
VSSQ
Ground
(for I/O buffer)
VREF
1
Reference Voltage
2
NC , NC
TC59LM806CFT
VDD
DQ0
VDDQ
DQ1
DQ2
VSSQ
DQ3
DQ4
VDDQ
DQ5
DQ6
VSSQ
DQ71
NC
VDDQ
LDQS1
NC
VDD
NC11
NC
A14
A13
FN
CS1
NC
BA0
BA1
A10
A0
A1
A2
A3
VDD
VDD
DQ0
VDDQ
NC2
DQ1
VSSQ
NC2
DQ2
VDDQ
NC2
DQ3
VSSQ
NC21
NC
VDDQ
NC21
NC
VDD
NC11
NC
A14
A13
FN
CS
NC1
BA0
BA1
A10
A0
A1
A2
A3
VDD
1
2
3
4
5
6
7
8
9 400 mil width
10 875 mil length
11
12
13
14 66 pin TSOPII
15
16
17
18
0.65 mm
19
20 Lead pitch
21
22
23
24
25
26
27
28
29
30
31
32
33
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
VSS
VSS
DQ7 DQ15
VSSQ VSSQ
NC2 DQ14
DQ6 DQ13
VDDQ VDDQ
NC2 DQ12
DQ5 DQ11
VSSQ VSSQ
NC2 DQ10
DQ4 DQ9
VDDQ VDDQ
NC21 DQ8
NC
NC1
VSSQ VSSQ
DQS
UDQS
NC1 NC1
VREF VREF
VSS1 VSS1
NC
NC
CLK CLK
CLK CLK
PD 1 PD 1
NC
NC
A12 A12
A11 A11
A9
A9
A8
A8
A7
A7
A6
A6
A5
A5
A4
A4
VSS
VSS
Not Connected
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TC59LM814/06CFT-50,-55,-60
BLOCK DIAGRAM
CLK
CLK
PD
CS
FN
DLL
CLOCK
BUFFER
COMMAND
DECODER
To each block
CONTROL
SIGNAL
GENERATOR
BANK #3
BANK #2
BANK #1
BA0, BA1
ADDRESS
BUFFER
UPPER ADDRESS
LATCH
LOWER ADDRESS
LATCH
REFRESH
COUNTER
BURST
COUNTER
DATA
CONTROL and LATCH
CIRCUIT
A0~A14
ROW DECODER
BANK #0
MODE
REGISTER
MEMORY
CELL ARRAY
COLUMN DECODER
READ
DATA
BUFFER
WRITE ADDRESS
LATCH/
ADDRESS
COMPARATOR
DQS
WRITE
DATA
BUFFER
DQ BUFFER
DQ0~DQn
Note: The TC59LM806CFT configuration is 32768 × 256 × 8 of cell array with the DQ pins numbered DQ0~DQ7.
The TC59LM814CFT configuration is 32768 × 128 × 16 of cell array with the DQ pins numbered DQ0~DQ15.
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TC59LM814/06CFT-50,-55,-60
ABSOLUTE MAXIMUM RATINGS
SYMBOL
PARAMETER
RATING
UNIT
−0.3~ 3.3
V
VDD
Power Supply Voltage
VDDQ
Power Supply Voltage (for I/O buffer)
−0.3~VDD+ 0.3
V
VIN
Input Voltage
−0.3~VDD+ 0.3
V
VOUT
DQ pin Voltage
−0.3~VDDQ + 0.3
V
VREF
Input Reference Voltage
−0.3~3.3
V
Topr
Operating Temperature
0~70
°C
Tstg
Storage Temperature
−55~150
°C
Tsolder
Soldering Temperature (10 s)
260
°C
PD
Power Dissipation
1
W
IOUT
Short Circuit Output Current
±50
mA
NOTES
Caution: Conditions outside the limits listed under “ABSOLUTE MAXIMUM RATINGS” may cause permanent damage to the device.
The device is not meant to be operated under conditions outside the limits described in the operational section of this
specification.
Exposure to “ABSOLUTE MAXIMUM RATINGS” conditions for extended periods may affect device reliability.
RECOMMENDED DC, AC OPERATING CONDITIONS (Notes: 1)(Ta = 0°~70°C)
SYMBOL
PARAMETER
MIN
TYP.
MAX
UNIT
NOTES
VDD
Power Supply Voltage
2.35
2.5
2.65
V
VDDQ
Power Supply Voltage (for I/O buffer)
2.35
VDD
VDD
V
VREF
Input Reference Voltage
VDDQ/2 × 96%
VDDQ/2
VDDQ/2 × 104%
V
2
VIH (DC)
Input DC High Voltage
VREF + 0.2
VDDQ + 0.2
V
5
VIL (DC)
Input DC Low Voltage
−0.1
VREF − 0.2
V
5
VICK (DC)
Differential Clock DC Input Voltage
−0.1
VDDQ + 0.1
V
10
VID (DC)
Input Differential Voltage.
CLK and CLK inputs (DC)
0.4
VDDQ + 0.2
V
7, 10
VIH (AC)
Input AC High Voltage
VREF + 0.35
VDDQ + 0.2
V
3, 6
VIL (AC)
Input AC Low Voltage
−0.1
VREF − 0.35
V
4, 6
VID (AC)
Input Differential Voltage.
CLK and CLK inputs (AC)
0.7
VDDQ + 0.2
V
7, 10
VX (AC)
Differential AC Input Cross Point Voltage
VDDQ/2 − 0.2
VDDQ/2 + 0.2
V
8, 10
VISO (AC)
Differential Clock AC Middle Level
VDDQ/2 − 0.2
VDDQ/2 + 0.2
V
9, 10
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TC59LM814/06CFT-50,-55,-60
Note:
(1)
All voltages referenced to VSS, VSSQ.
(2)
VREF is expected to track variations in VDDQ DC level of the transmitting device.
Peak to peak AC noise on VREF may not exceed ±2% VREF (DC).
(3)
Overshoot limit: VIH (max) = VDDQ + 0.9 V with a pulse width ≤ 5 ns.
(4)
Undershoot limit: VIL (min) = −0.9 V with a pulse width ≤ 5 ns.
(5)
VIH (DC) and VIL (DC) are levels to maintain the current logic state.
(6)
VIH (AC) and VIL (AC) are levels to change to the new logic state.
(7)
VID is magnitude of the difference between CLK input level and CLK input level.
(8)
The value of VX (AC) is expected to equal VDDQ/2 of the transmitting device.
(9)
VISO means {VICK (CLK) + VICK ( CLK )} /2
(10)
Refer to the figure below.
CLK
Vx
Vx
Vx
Vx
Vx
VID (AC)
CLK
VICK
VICK
VICK
VISO (min)
VISO (max)
VICK
VSS
|VID (AC)|
0 V Differential
VISO
VSS
(11)
In the case of external termination, VTT (termination voltage) should be gone in the range of VREF (DC)
± 0.04 V.
CAPACITANCE (VDD, VDDQ = 2.5 V, f = 1 MHz, Ta = 25°C)
SYMBOL
PARAMETER
MIN
MAX
UNIT
CIN
Input pin Capacitance
2.5
4.0
pF
CINC
Clock pin (CLK, CLK ) Capacitance
2.5
4.0
pF
CI/O
I/O pin (DQ, DQS) Capacitance
4.0
6.0
pF
1.5
pF
4.0
6.0
pF
CNC
CNC
1
2
1
NC pin Capacitance
2
NC pin Capacitance
Note: These parameters are periodically sampled and not 100% tested.
2
The NC pins have additional capacitance for adjustment of the adjacent pin capacitance.
2
The NC pins have Power and Ground clamp.
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TC59LM814/06CFT-50,-55,-60
RECOMMENDED DC OPERATING CONDITIONS (VDD,VDDQ=2.5V ± 0.15V, Ta = 0°~70°C)
MAX
SYMBOL
PARAMETER
UNIT
NOTES
-50
-55
-60
IDD1S
Operating Current
tCK = min; IRC = min,
Read/Write command cycling,
0 V ≤ VIN ≤ VIL (AC) (max), VIH (AC) (min) ≤ VIN ≤ VDDQ,
1 bank operation, Burst length = 4,
Address change up to 2 times during minimum IRC.
190
180
170
1, 2
IDD2N
Standby Current
tCK = min, CS = VIH, PD = VIH,
0 V ≤ VIN ≤ VIL (AC) (max), VIH (AC) (min) ≤ VIN ≤ VDDQ,
All banks: inactive state,
Other input signals are changed one time during 4 × tCK.
40
40
35
1
IDD2P
Standby (power down) Current
tCK = min, CS = VIH, PD = VIL (power down),
0 V ≤ VIN ≤ VDDQ,
All banks: inactive state
2
2
2
1
IDD5
Auto-Refresh Current
tCK = min; IREFC = min, tREFI = min,
Auto-Refresh command cycling,
0 V ≤ VIN ≤ VIL (AC) (max), VIH (AC) (min) ≤ VIN ≤ VDDQ,
Address change up to 2 times during minimum IREFC.
65
65
60
1
IDD6
Self-Refresh Current
Self-Refresh mode
PD = 0.2 V, 0 V ≤ VIN ≤ VDDQ
3
3
3
MIN
MAX
UNIT
SYMBOL
PARAMETER
mA
NOTES
ILI
Input Leakage Current
( 0 V ≤ VIN ≤ VDDQ, all other pins not under test = 0 V)
−5
5
µA
ILO
Output Leakage Current
(Output disabled, 0 V ≤ VOUT ≤ VDDQ)
−5
5
µA
IREF
VREF Current
−5
5
µA
Output Source DC Current
VOH = VDDQ − 0.4 V
−10
3
Output Sink DC Current
VOL = 0.4 V
10
3
Output Source DC Current
Strong Output VOH = VDDQ − 0.4 V
Driver
Output Sink DC Current
VOL = 0.4 V
−11
3
11
Output Source DC Current
VOH = VDDQ − 0.4 V
−8
3
Output Sink DC Current
VOL = 0.4 V
8
3
Output Source DC Current
VOH = VDDQ − 0.4 V
−7
3
Output Sink DC Current
VOL = 0.4 V
7
3
IOH (DC)
Normal
Output Driver
IOL (DC)
IOH (DC)
IOL (DC)
IOH (DC)
Weaker
Output Driver
IOL (DC)
IOH (DC)
IOL (DC)
Weakest
Output Driver
3
mA
Notes: 1. These parameters depend on the cycle rate and these values are measured at a cycle rate with the minimum values of
tCK, tRC and IRC.
2. These parameters depend on the output loading. The specified values are obtained with the output open.
3. Refer to output driver characteristics for the detail. Output Driver Strength is selected by Extended Mode Register.
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TC59LM814/06CFT-50,-55,-60
AC CHARACTERISTICS AND OPERATING CONDITIONS (Notes: 1, 2)
-50
SYMBOL
-55
-60
PARAMETER
UNIT
NOTES
MIN
MAX
MIN
MAX
MIN
MAX
25
27.5
30
3
CL = 3
5.5
8.5
6
12
6.5
12
3
CL = 4
5
8.5
5.5
12
6
12
3
22
24
26
3
tRC
Random Cycle Time
tCK
Clock Cycle Time
tRAC
Random Access Time
tCH
Clock High Time
0.45 × tCK
0.45 × tCK
0.45 × tCK
3
tCL
Clock Low Time
0.45 × tCK
0.45 × tCK
0.45 × tCK
3
tCKQS
DQS Access Time from CLK
−0.65
0.65
−0.75
0.75
−0.85
0.85
3, 8
tQSQ
Data Output Skew from DQS
0.4
0.45
0.5
4
tAC
Data Access Time from CLK
−0.65
0.65
−0.75
0.75
−0.85
0.85
3, 8
tOH
Data Output Hold Time from CLK
−0.65
0.65
−0.75
0.75
−0.85
0.85
3, 8
tQSPRE
DQS (read) Preamble Pulse
Width
0.9 × tCK 1.1 × tCK
− 0.2
+ 0.2
0.9 × tCK
− 0.2
1.1 × tCK
+ 0.2
tHP
CLK half period (minimum of
Actual tCH, tCL)
min(tCH,
tCL)
min(tCH,
tCL)
min(tCH,
tCL)
3
tQSP
DQS (read) Pulse Width
tHP−
0.55
tHP− 0.6
tHP−
0.65
4, 8
tQSQV
Data Output Valid Time from DQS
tHP−
0.55
tHP− 0.6
tHP−
0.65
4, 8
tDQSS
DQS (write) Low to High Setup
Time
0.75 × tCK 1.25 × tCK 0.75 × tCK 1.25 × tCK 0.75 × tCK 1.25 × tCK
3
tDSPRE
DQS (write) Preamble Pulse Width
0.4 × tCK
0.4 × tCK
0.4 × tCK
4
tDSPRES
DQS First Input Setup Time
0
0
0
tDSPREH
DQS First Low Input Hold Time
0.25 × tCK
0.25 × tCK
0.25 × tCK
tDSP
DQS High or Low Input Pulse Width 0.45 × tCK 0.55 × tCK 0.45 × tCK 0.55 × tCK 0.45 × tCK 0.55 × tCK
tDSS
DQS Input Falling Edge
to Clock Setup Time
0.9 × tCK 1.1 × tCK
− 0.2
+ 0.2
3, 8
ns
3
3
4
CL = 3
1.3
1.4
1.5
3, 4
CL = 4
1.3
1.4
1.5
3, 4
0.45 × tCK
0.45 × tCK
4
tDSPST
DQS (write) Postamble Pulse Width 0.45 × tCK
tDSPSTH
DQS (write) Postamble
Hold Time
tDSSK
UDQS - LDQS Skew (x16)
tDS
Data Input Setup Time from DQS
0.5
0.5
0.6
4
tDH
Data Input Hold Time from DQS
0.5
0.5
0.6
4
tDIPW
Data Input Pulse Width
(for each device)
1.5
1.5
1.9
tIS
Command/Address Input Setup
Time
0.9
0.9
1.0
3
tIH
Command/Address Input Hold
Time
0.9
0.9
1.0
3
tIPW
Command/Address Input Pulse
Width (for each device)
2.0
2.0
2.2
tLZ
Data-out Low Impedance Time
from CLK
−0.65
−0.75
−0.85
3,6,8
tHZ
Data-out High Impedance Time
from CLK
0.65
0.75
0.85
3,7,8
CL = 3
1.3
1.4
1.5
3, 4
CL = 4
1.3
1.4
1.5
3, 4
-0.5 × tCK 0.5 × tCK -0.5 × tCK
0.5 × tCK -0.5 × tCK 0.5 × tCK
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TC59LM814/06CFT-50,-55,-60
AC CHARACTERISTICS AND OPERATING CONDITIONS (Notes: 1, 2) (continued)
-50
SYMBOL
-55
-60
PARAMETER
UNIT
MIN
MAX
MIN
MAX
MIN
MAX
NOTES
tQSLZ
DQS-out Low Impedance Time
from CLK
−0.65
−0.75
−0.85
3,6,8
tQSHZ
DQS-out High Impedance Time
from CLK
−0.65
0.65
−0.75
0.75
−0.85
0.85
3,7,8
tQPDH
Last output to PD High Hold
Time
0
0
0
tPDEX
Power Down Exit Time
2
2
2
tT
Input Transition Time
0.1
1
0.1
1
0.1
1
tFPDL
PD Low Input Window for
Self-Refresh Entry
−0.5 × tCK
5
−0.5 × tCK
5
−0.5 × tCK
5
tREFI
Auto-Refresh Average Interval
0.4
7.8
0.4
7.8
0.4
7.8
tPAUSE
Pause Time after Power-up
200
200
200
CL = 3
5
5
5
IRC
Random Read/Write
Cycle Time
(applicable to same
bank)
CL = 4
5
5
5
1
1
1
1
1
1
CL = 3
4
4
4
CL = 4
4
4
4
2
2
2
BL = 2
2
2
2
BL = 4
3
3
3
1
1
1
CL = 3
5
5
5
CL = 4
5
5
5
IRCD
RDA/WRA to LAL Command
Input Delay
(applicable to same bank)
IRAS
LAL to RDA/WRA
Command Input Delay
(applicable to same
bank)
IRBD
Random Bank Access Delay
(applicable to other bank)
IRWD
LAL following RDA to
WRA Delay
(applicable to other
bank)
IWRD
LAL following WRA to RDA Delay
(applicable to other bank)
IRSC
Mode Register Set
Cycle Time
IPD
PD Low to Inactive State of
Input Buffer
1
1
1
IPDA
PD High to Active State of Input
Buffer
1
1
1
Power down mode valid CL = 3
from REF command
CL = 4
15
15
15
IPDV
18
18
18
Auto-Refresh Cycle
Time
CL = 3
15
15
15
IREFC
CL = 4
18
18
18
ICKD
REF Command to Clock Input
Disable at Self-Refresh Entry
16
16
16
ILOCK
DLL Lock-on Time (applicable to
RDA command)
200
200
200
ns
3
3
µs
5
cycle
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TC59LM814/06CFT-50,-55,-60
AC TEST CONDITIONS
SYMBOL
PARAMETER
VALUE
UNIT
VIH (min)
Input High Voltage (minimum)
VREF + 0.35
V
VIL (max)
Input Low Voltage (maximum)
VREF − 0.35
V
VREF
Input Reference Voltage
VDDQ/2
V
VTT
Termination Voltage
VREF
V
VSWING
Input Signal Peak to Peak Swing
1.0
V
Vr
Differential Clock Input Reference Level
VX (AC)
V
VID (AC)
Input Differential Voltage
1.5
V
SLEW
Input Signal Minimum Slew Rate
1.0
V/ns
VOTR
Output Timing Measurement Reference Voltage
VDDQ/2
V
NOTES
VDDQ
VTT
VIH min (AC)
VSWING
VSS
∆T
VREF
Measurement point
VIL max (AC)
Output
RT = 50 Ω
Z = 50 Ω
CL = 30 pF
Output
VREF
∆T
SLEW = (VIH min (AC) − VIL max (AC))/∆T
AC Test Load
Note:
(1)
Transition times are measured between VIH min (DC) and VIL max (DC).
Transition (rise and fall) of input signals have a fixed slope.
(2)
If the result of nominal calculation with regard to tCK contains more than one decimal place, the result is
rounded up to the nearest decimal place.
(i.e., tDQSS = 0.75 × tCK, tCK = 5 ns, 0.75 × 5 ns = 3.75 ns is rounded up to 3.8 ns.)
(3)
There parameters are measured from the differential clock (CLK and CLK ) AC cross point.
(4)
These parameters are measured from signal transition point of DQS crossing VREF level.
(5)
Te tREFI (max) applies to equally distributed refresh method.
The tREFI (min) applies to both burst refresh method and distribted refresh method.
In such case, the average interval of eight consecutive Auto-Refresh commands has to be more than 400 ns
always. In other words, the number of Auto-Refresh cycles which can be performed within 3.2 µs (8 × 400 ns)
is to 8 times in the maximum.
(6)
Low Impedance State is specified at VDDQ/2 ± 0.2 V from steady state.
(7)
High Impedance State is specified where output buffer is no longer driven.
(8)
These parameters depend on the clock jitter. These parameters are measured at stable clock.
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TC59LM814/06CFT-50,-55,-60
POWER UP SEQUENCE
(1)
As for PD , being maintained by the low state (≤ 0.2 V) is desirable before a power-supply injection.
(2)
Apply VDD before or at the same time as VDDQ.
(3)
Apply VDDQ before or at the same time as VREF.
(4)
Start clock (CLK, CLK ) and maintain stable condition for 200 µs (min).
(5)
After stable power and clock, apply DESL and take PD =H.
(6)
Issue EMRS to enable DLL and to define driver strength. (Note: 1)
(7)
Issue MRS for set CAS latency (CL), Burst Type (BT), and Burst Length (BL). (Note: 1)
(8)
Issue two or more Auto-Refresh commands (Note: 1).
(9)
Ready for normal operation after 200 clocks from Extended Mode Register programming.
Note:
(1)
Sequence 6, 7 and 8 can be issued in random order.
(2)
L = Logic Low, H = Logic High
2.5V(TYP)
VDD
2.5V(TYP)
VDDQ
1.25V(TYP)
VREF
CLK
CLK
tPDEX
lPDA
200 us(min)
lRSC
lRSC
lREFC
lREFC
PD
200clock cycle(min)
Command
DESL
RDA MRS DESL
op-code
RDA MRS
DESL WRA REF
DESL
WRA REF
DESL
op-code
Address
EMRS
MRS
DQ
Hi-Z
DQS
EMRS
MRS
Auto Refresh cycle
Normal Operation
2002-08-19
10/38
TC59LM814/06CFT-50,-55,-60
TIMING DIAGRAMS
Input Timing
tCK
tCK
tCH
tCL
CLK
CLK
tIS
tIH
tIS
1st
CS
2nd
tIS
tIH
2nd
tIPW
tIS
A0~A14
BA0, BA1
tIPW
tIH
tIS
1st
FN
tIH
tIH
tIS
UA, BA
tIH
LA
tIPW
DQS
tDS tDH
tDS tDH
tDIPW
tDIPW
DQ (input)
Refer to the Command Truth Table.
Timing of the CLK, CLK
tCH
tCL
VIH
VIH (AC)
VIL (AC)
VIL
CLK
CLK
tT
tCK
tT
VIH
CLK
VID (AC)
CLK
VX
VX
VX
VIL
2002-08-19
11/38
TC59LM814/06CFT-50,-55,-60
Read Timing (Burst Length = 4)
tCH
tCL
tCK
CLK
CLK
tIS tIH
Input
(control &
addresses)
(DESL)
tIPW
tQSLZ
CAS latency = 3
DQS
(output)
LAL (after RDA)
tCKQS
tCKQS
tQSP
tCKQS
tQSPRE
Hi-Z
Hi-Z
Preamble
Postamble
tLZ
DQ
(output)
Hi-Z
tQSQ
tQSQV
tQSQ
tQSQV
Q0
Q1
Q2
tAC
tAC
tQSLZ
CAS latency = 4
DQS
(output)
tQSHZ
tQSP
tCKQS
tQSQ tHZ
Hi-Z
Q3
tAC tOH
tCKQS
tQSP
tCKQS
tQSPRE
Hi-Z
Preamble
Postamble
tLZ
DQ
(output)
tQSHZ
tQSP
Hi-Z
tQSQ
tQSQV
tQSQ
tQSQV
Q0
Q1
Q2
tAC
tAC
tQSQ tHZ
Q3
tAC tOH
Note: The correspondence of LDQS, UDQS to DQ. (TC59LM814CFT)
LDQS
DQ0~DQ7
UDQS
DQ8~DQ15
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TC59LM814/06CFT-50,-55,-60
Write Timing (Burst Length = 4)
tCH
tCL
tCK
CLK
CLK
tIS tIH
Input
(control &
addresses)
LAL (after WRA)
(DESL)
tIPW
tDSPSTH
tDQSS
tDSPRES
CAS latency = 3
tDSS
tDSP
tDSPREH tDSP
tDSP
tDSPST
DQS
(input)
tDSS
Preamble
tDSPRE
tDS
tDS
tDH tDIPW
DQ
(input)
Postamble
D0
tDS
tDH
D1
D2
tDH
D3
tDQSS
tDSPRES
CAS latency = 4
tDSS
tDSPSTH
tDSS
tDSPREH
tDSP
tDSP
tDSP
tDSPST
DQS
(input)
Preamble
tDSPRE
Postamble
tDS
tDS
tDH tDIPW
DQ
(input)
D0
tDQSS
D1
tDS
tDH
D2
tDH
D3
tDQSS
Note: the correspondence of LDQS, UDQS to DQ. (TC59LM814CFT)
LDQS
DQ0~DQ7
UDQS
DQ8~DQ15
tREFI, tPAUSE, IXXXX Timing
CLK
CLK
tREFI, tPAUSE, IXXXX
tIS tIH
Input
(control &
addresses)
tIS tIH
(DESL)
Command
Note: “IXXXX” means “IRC”, “IRCD”, “IRAS”, etc.
Command
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TC59LM814/06CFT-50,-55,-60
Write Timing (x16 device) (Burst Length = 4)
CLK
CLK
Input
(control &
addresses)
CAS latency = 3
WRA
LAL
(DESL)
tDSSK
tDSSK
tDSSK
tDSSK
tDS
tDS
tDS
LDQS
Preamble
tDS
Postamble
tDH
DQ0~DQ7
D0
tDH
tDH
D1
tDH
D2
D3
UDQS
Preamble
tDS
Postamble
tDS
tDH
DQ8~DQ15
CAS latency = 4
D0
tDS
tDH
tDH
D1
tDS
tDH
D2
D3
tDSSK
tDSSK
tDSSK
tDSSK
LDQS
Preamble
tDS
DQ0~DQ7
tDS
tDS
tDH
tDH
D0
tDS
tDH
tDH
D1
D2
D3
UDQS
Preamble
tDS
DQ8~DQ15
tDS
tDS
tDH
D0
D1
tDS
tDH
tDH
D2
2002-08-19
tDH
D3
14/38
TC59LM814/06CFT-50,-55,-60
FUNCTION TRUTH TABLE (Notes: 1, 2, 3)
Command Truth Table (Notes: 4)
• The First Command
SYMBOL
FUNCTION
CS
FN
BA1~BA0
A14~A9
A8
A7
A6~A0
DESL
Device Deselect
H
×
×
×
×
×
×
RDA
Read with Auto-close
L
H
BA
UA
UA
UA
UA
WRA
Write with Auto-close
L
L
BA
UA
UA
UA
UA
• The Second Command (The next clock of RDA or WRA command)
SYMBOL
FUNCTION
CS
FN
BA1~
BA0
A14~
A13
A12~
A11
A10~A9
A8
A7
A6~A0
LAL
Lower Address Latch (×16)
H
×
×
V
V
×
×
×
LA
LAL
Lower Address Latch (×8)
H
×
×
V
×
×
×
LA
LA
REF
Auto-Refresh
L
×
×
×
×
×
×
×
×
MRS
Mode Register Set
L
×
V
L
L
L
L
V
V
Notes: 1. L = Logic Low, H = Logic High, × = either L or H, V = Valid (specified value), BA = Bank Address, UA = Upper Address,
LA = Lower Address
2. All commands are assumed to issue at a valid state.
3. All inputs for command (excluding SELFX and PDEX) are latched on the crossing point of differential clock input where
CLK goes to High.
4. Operation mode is decided by the combination of 1st command and 2nd command. Refer to “STATE DIAGRAM” and
the command table below.
Read Command Table
COMMAND (SYMBOL)
CS
FN
BA1~BA0
A14~A9
A8
A7
A6~A0
RDA (1st)
L
H
BA
UA
UA
UA
UA
LAL (2nd)
H
×
×
×
×
LA
LA
NOTES
5
Notes: 5. For x16 device, A7 is "×" (either L or H).
Write Command Table
• TC59LM814CFT
COMMAND(SYMBOL)
CS
FN
BA1~
BA0
A14
A13
A12
A11
A10~
A9
A8
A7
A6~A0
WRA (1st)
L
L
BA
UA
UA
UA
UA
UA
UA
UA
UA
LAL (2nd)
H
×
×
LVW0
LVW1
UVW0
UVW1
×
×
×
LA
COMMAND(SYMBOL)
CS
FN
BA1~
BA0
A14
A13
A12
A11
A10~
A9
A8
A7
A6~A0
WRA (1st)
L
L
BA
UA
UA
UA
UA
UA
UA
UA
UA
LAL (2nd)
H
×
×
VW0
VW1
×
×
×
×
LA
LA
• TC59LM806CFT
Notes: 6. A14~ A11 are used for Variable Write Length (VW) control at Write Operation.
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TC59LM814/06CFT-50,-55,-60
FUNCTION TRUTH TABLE (continued)
VW Truth Table
SYMBOL
Function
VW0
VW1
Write All Words
L
×
Write First One Word
H
×
Reserved
L
L
Write All Words
H
L
Write First Two Words
L
H
Write First One Word
H
H
BL=2
BL=4
Notes: 7. For x16 device, LVW0 and LVW1 control DQ0~DQ7.
UVW0 and UVW1 control DQ8~DQ15.
Mode Register Set Command Table
COMMAND (SYMBOL)
CS
FN
BA1~BA0
A14~A9
A8
A7
A6~A0
RDA (1st)
L
H
×
×
×
×
×
MRS (2nd)
L
×
V
L
L
V
V
CS
FN
BA1~BA0
A14~A9
A8
A7
NOTES
8
Notes: 8. Refer to “MODE REGISTER TABLE”.
Auto-Refresh Command Table
COMMAND
(SYMBOL)
CURRENT
STATE
Active
WRA (1st)
Auto-Refresh
REF (2nd)
FUNCTION
PD
A6~A0 NOTES
n−1
n
Standby
H
H
L
L
×
×
×
×
×
Active
H
H
L
×
×
×
×
×
×
CS
FN
BA1~BA0
A14~A9
A8
A7
Self-Refresh Command Table
COMMAND
(SYMBOL)
CURRENT
STATE
Active
WRA (1st)
Self-Refresh Entry
FUNCTION
PD
A6~A0 NOTES
n−1
n
Standby
H
H
L
L
×
×
×
×
×
REF (2nd)
Active
H
L
L
×
×
×
×
×
×
Self-Refresh
L
L
×
×
×
×
×
×
×
SELFX
Self-Refresh
L
H
H
×
×
×
×
×
×
COMMAND
(SYMBOL)
CURRENT
STATE
CS
FN
BA1~BA0
A14~A9
A8
A7
PDEN
Self-Refresh
Continue
Self-Refresh Exit
9, 10
11
Power Down Table
FUNCTION
Power Down Entry
Power Down Continue
Power Down Exit
Notes: 9.
10.
PD
A6~A0 NOTES
n−1
n
Standby
H
L
H
×
×
×
×
×
×
Power Down
L
L
×
×
×
×
×
×
×
PDEX
Power Down
L
H
H
×
×
×
×
×
×
10
11
PD has to be brought to Low within tFPDL from REF command.
PD should be brought to Low after DQ’s state turned high impedance.
11. When PD is brought to High from Low, this function is executed asynchronously.
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TC59LM814/06CFT-50,-55,-60
FUNCTION TRUTH TABLE (continued)
CURRENT STATE
PD
n−1 n
CS
FN
ADDRESS
COMMAND
ACTION
NOTES
Idle
H
H
H
H
H
L
H
H
H
L
L
×
H
L
L
H
L
×
×
H
L
×
×
×
×
BA, UA
BA, UA
×
×
×
DESL
RDA
WRA
PDEN
Row Active for Read
H
H
H
H
L
H
H
L
L
×
H
L
H
L
×
×
×
×
×
×
LA
Op-code
×
×
×
LAL
MRS/EMRS
PDEN
MRS/EMRS
Row Active for Write
H
H
H
H
L
H
H
L
L
×
H
L
H
L
×
×
×
×
×
×
LA
×
×
×
×
LAL
REF
PDEN
REF (self)
Read
H
H
H
H
H
L
H
H
H
L
L
×
H
L
L
H
L
×
×
H
L
×
×
×
×
BA, UA
BA, UA
×
×
×
DESL
RDA
WRA
PDEN
H
H
H
×
×
DESL
H
H
H
H
L
H
H
L
L
×
L
L
H
L
×
H
L
×
×
×
BA, UA
BA, UA
×
×
×
RDA
WRA
PDEN
Data Write&Continue Burst Write to
End
Illegal
Illegal
Illegal
Illegal
Invalid
Auto-Refreshing
H
H
H
H
H
L
H
H
H
L
L
×
H
L
L
H
L
×
×
H
L
×
×
×
×
BA, UA
BA, UA
×
×
×
DESL
RDA
WRA
PDEN
NOP → Idle after IREFC
Illegal
Illegal
Self-Refresh Entry
Illegal
Refer to Self-Refreshing State
Mode Register
Accessing
H
H
H
H
H
L
H
H
H
L
L
×
H
L
L
H
L
×
×
H
L
×
×
×
×
BA, UA
BA, UA
×
×
×
DESL
RDA
WRA
PDEN
NOP → Idle after IRSC
Illegal
Illegal
Illegal
Illegal
Invalid
H
L
×
L
×
×
×
×
×
×
L
H
H
×
×
PDEX
L
H
L
×
×
Invalid
Maintain Power Down Mode
Exit Power Down Mode → Idle after
tPDEX
Illegal
H
L
L
L
×
L
H
H
×
×
H
L
×
×
×
×
×
×
×
×
SELFX
Invalid
Maintain Self-Refresh
Exit Self-Refresh → Idle after IREFC
Illegal
Write
Power Down
Self-Refreshing
NOP
Row activate for Read
Row activate for Write
Power Down Entry
Illegal
Refer to Power Down State
12
Begin Read
Access to Mode Register
Illegal
Illegal
Invalid
Begin Write
Auto-Refresh
Illegal
Self-Refresh Entry
Invalid
Continue Burst Read to End
Illegal
Illegal
Illegal
Illegal
Invalid
13
13
13
13
14
Notes: 12. Illegal if any bank is not idle.
13. Illegal to bank in specified states; Function may be legal in the bank inidicated by Bank Address (BA).
14. Illegal if tFPDL is not satisfied.
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TC59LM814/06CFT-50,-55,-60
MODE REGISTER TABLE
Regular Mode Register (Notes: 1)
*1
ADDRESS
Register
*1
BA1
BA0
0
0
A14~A8
A7
0
*3
A6~A4
A3
A2~A0
CL
BT
BL
TE
A7
TEST MODE (TE)
A3
BURST TYPE (BT)
0
Regular (default)
0
Sequential
1
Test Mode Entry
1
Interleave
A6
A5
A4
CAS LATENCY (CL)
0
0
×
Reserved
0
1
0
Reserved
0
1
1
3
1
0
0
4
1
0
1
Reserved
1
1
×
Reserved
*2
*2
A2
A1
A0
BURST LENGTH (BL)
0
0
0
0
0
1
2
0
1
0
4
0
1
1
1
×
×
Reserved
Reserved
*2
*2
*2
*2
Extended Mode Register (Notes: 4)
ADDRESS
Register
*4
*4
BA1
BA0
0
1
A14~A7
A6
A5~A2
A1
0
DIC
0
DIC
A0
*5
DS
A6
A1
OUTPUT DRIVE IMPEDANCE CONTROL (DIC)
0
0
Normal Output Driver
0
1
Strong Output Driver
1
0
Weaker Output Driver
1
1
Weakest Output Driver
A0
DLL SWITCH (DS)
0
DLL Enable
1
DLL Disable
Notes: 1. Regular Mode Register is chosen using the combination of BA0 = 0 and BA1 = 0.
2. “Reserved” places in Regular Mode Register should not be set.
3. A7 in Regular Mode Register must be set to “0” (low state).
Because Test Mode is specific mode for supplier.
4. Extended Mode Register is chosen using the combination of BA0 = 1 and BA1 = 0.
5. A0 in Extended Mode Register must be set to "0" to enable DLL for normal operation.
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TC59LM814/06CFT-50,-55,-60
STATE DIAGRAM
SELFREFRESH
POWER
DOWN
SELFX
( PD = H)
PDEX
( PD = H)
PD = L
PDEN
( PD = L)
STANDBY
(IDLE)
PD = H
AUTOREFRESH
MODE
REGISTER
WRA
RDA
REF
MRS
ACTIVE
(RESTORE)
ACTIVE
LAL
LAL
WRITE
(BUFFER)
READ
Command input
Automatic return
The second command at Active state
must be issued 1 clock after RDA or
WRA command input.
2002-08-19
19/38
TC59LM814/06CFT-50,-55,-60
TIMING DIAGRAMS
SINGLE BANK READ TIMING (CL = 3)
0
1
2
3
4
5
6
7
8
9
10
11
RDA
LAL
CLK
CLK
IRC = 5 cycles
Command
BL = 2
DQS
(output)
RDA
LAL
IRC = 5 cycles
DESL
RDA
IRAS = 4 cycles
IRCD=1 cycle
LAL
DESL
IRAS = 4 cycles
IRCD=1 cycle
Hi-Z
Hi-Z
CL = 3
DQ
(output)
Hi-Z
CL = 3
Hi-Z
Hi-Z
Q0 Q1
Hi-Z
Q0 Q1
BL = 4
DQS
(output)
Hi-Z
Hi-Z
CL = 3
DQ
(output)
Hi-Z
CL = 3
Hi-Z
Hi-Z
Q0 Q1 Q2 Q3
Q0 Q1 Q2 Q3
Hi-Z
SINGLE BANK READ TIMING (CL = 4)
0
1
2
3
4
5
6
7
8
9
10
11
RDA
LAL
CLK
CLK
IRC = 5 cycles
Command
BL = 2
DQS
(output)
RDA
LAL
IRCD = 1 cycle
DESL
IRAS = 4 cycles
IRC = 5 cycles
RDA
LAL
IRCD = 1 cycle
Hi-Z
IRAS = 4 cycles
IRCD = 1 cycle
Hi-Z
CL = 4
DQ
(output)
DESL
Hi-Z
CL = 4
Q0 Q1
Hi-Z
Q0 Q1
BL = 4
DQS
(output)
Hi-Z
Hi-Z
CL = 4
DQ
(output)
Hi-Z
CL = 4
Q0 Q1 Q2 Q3
Hi-Z
Q0 Q1 Q2
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TC59LM814/06CFT-50,-55,-60
SINGLE BANK WRITE TIMING (CL = 3)
0
1
2
3
4
5
6
7
8
9
10
11
WRA
LAL
10
11
WRA
LAL
CLK
CLK
IRC = 5 cycles
Command
WRA
LAL
DESL
IRCD = 1 cycle
BL = 2
IRC = 5 cycles
WRA
IRAS = 4 cycles
LAL
DESL
IRCD = 1 cycle
IRAS = 4 cycles
DQS
(input)
tDQSS
WL = 2
DQ
(input)
WL = 2
D0 D1
D0 D1
tDQSS
BL = 4
tDQSS
DQS
(input)
WL = 2
DQ
(input)
WL = 2
D0 D1 D2 D3
D0 D1 D2 D3
SINGLE BANK WRITE TIMING (CL = 4)
0
1
2
3
4
5
6
7
8
9
CLK
CLK
IRC = 5 cycles
Command
WRA
LAL
IRCD = 1 cycle
BL = 2
IRC = 5 cycles
DESL
WRA
IRAS = 4 cycles
LAL
IRCD = 1 cycle
DESL
IRAS = 4 cycles
IRCD = 1 cycle
DQS
(input)
WL = 3
DQ
(input)
WL = 3
D0 D1
D0 D1
tDQSS
BL = 4
tDQSS
DQS
(input)
WL = 3
DQ
(input)
WL = 3
D0 D1 D2 D3
Note:
D0 D1 D2 D3
means H or L
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TC59LM814/06CFT-50,-55,-60
SINGLE BANK READ-WRITE TIMING (CL = 3)
0
1
2
3
4
5
6
7
8
9
10
11
RDA
LAL
CLK
CLK
IRC = 5 cycles
Command
RDA
LAL
DESL
IRCD = 1 cycle
BL = 2
DQS
IRC = 5 cycles
WRA
IRAS = 4 cycles
LAL
IRCD = 1 cycle
Hi-Z
IRAS = 4 cycles
Hi-Z
CL = 3
DQ
DESL
Hi-Z
WL = 2
Hi-Z
Hi-Z
Q0 Q1
Hi-Z
D0 D1
tDQSS
BL = 4
DQS
Hi-Z
Hi-Z
CL = 3
DQ
Hi-Z
WL = 2
Hi-Z
Hi-Z
Q0 Q1 Q2 Q3
Hi-Z
D0 D1 D2 D3
SINGLE BANK READ-WRITE TIMING (CL = 4)
0
1
2
3
4
5
6
7
8
9
10
11
RDA
LAL
CLK
CLK
IRC = 5 cycles
Command
RDA
BL = 2
DQS
LAL
DESL
IRCD = 1 cycle
IRAS = 4 cycles
IRC = 5 cycles
WRA
LAL
DESL
IRCD = 1 cycle
IRAS = 4 cycles
Hi-Z
Hi-Z
CL = 4
DQ
Hi-Z
WL = 3
Q0 Q1
Hi-Z
D0 D1
tDQSS
BL = 4
DQS
Hi-Z
Hi-Z
CL = 4
DQ
Hi-Z
WL = 3
Q0 Q1 Q2 Q3
Hi-Z
D0 D1 D2 D3
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TC59LM814/06CFT-50,-55,-60
MULTIPLE BANK READ TIMING (CL = 3)
0
1
2
3
4
5
6
7
8
9
10
11
CLK
CLK
Command
IRC = 5 cycles
RDAa
LALa
RDAb
IRCD = 1 cycle
Bank Add.
(BA0, BA1)
Bank “a”
LALb
DESL
RDAa
IRAS = 4 cycles
RDAc
IRCD = 1 cycle
×
Bank “b”
LALa
IRCD = 1 cycle
×
Bank “a”
Hi-Z
RDAb
IRBD = 2 cycles
×
×
Bank “d”
Bank “b”
CL = 3
Hi-Z
Hi-Z
Qa0 Qa1
Hi-Z
Qb0 Qb1
Hi-Z
Qa0 Qa1
CL = 3
Qc0
CL = 3
Hi-Z
CL = 3
DQ
(output)
LALd
Hi-Z
BL = 4
DQS
(output)
RDAd
IRBD = 2 cycles
Bank “c”
CL = 3
DQ
(output)
LALc
IRCD = 1 cycle
IRBD = 2 cycles
BL = 2
DQS
(output)
×
IRBD = 2 cycles
CL = 3
Hi-Z
Qa0 Qa1 Qa2 Qa3 Qb0 Qb1 Qb2 Qb3
Hi-Z
Qa0 Qa1 Qa2 Qa3 Qc0
MULTIPLE BANK READ TIMING (CL = 4)
0
1
2
3
4
5
6
7
8
9
10
11
CLK
CLK
Command
IRC = 5 cycles
RDAa
LALa
RDAb
IRCD = 1 cycle
Bank Add.
(BA0, BA1)
Bank “a”
LALb
DESL
RDAa
IRAS = 4 cycles
×
Bank “b”
LALa
RDAc
IRCD = 1 cycle
Bank “a”
×
RDAd
LALd
RDAb
IRBD = 2 cycles
×
×
Bank “d”
Bank “b”
Hi-Z
Hi-Z
CL = 4
Qa0 Qa1
Hi-Z
Qb0 Qb1
Hi-Z
CL = 4
Qa0 Qa1
CL = 4
Hi-Z
CL = 4
DQ
(output)
IRCD = 1 cycle
IRBD = 2 cycles
Hi-Z
BL = 4
DQS
(output)
LALc
Bank “c”
CL = 4
DQ
(output)
IRCD = 1 cycle
IRBD = 2 cycles
BL = 2
DQS
(output)
×
IRBD = 2 cycles
Hi-Z
CL = 4
Qa0 Qa1 Qa2 Qa3 Qb0 Qb1 Qb2 Qb3
Hi-Z
Qa0 Qa1 Qa2
Note: “×” is don’t care.
IRC to the same bank must be satisfied.
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MULTIPLE BANK WRITE TIMING (CL = 3)
0
1
2
3
4
5
6
7
8
9
10
11
CLK
CLK
Command
IRC = 5 cycles
WRAa
LALa
WRAb
IRCD = 1 cycle
Bank Add.
(BA0, BA1)
Bank “a”
×
IRBD = 2 cycles IRCD = 1 cycle
LALb
DESL
IRAS = 4 cycles
×
Bank “b”
LALa
WRAc
IRCD = 1 cycle
×
Bank “a”
IRBD = 2 cycles
BL = 2
WRAa
LALc
WRAd
LALd
WRAb
IRBD = 2 cycles
IRBD = 2 cycles
×
×
Bank “c”
tDQSS
IRCD = 1 cycle
Bank “d”
Bank “b”
tDQSS
DQS
(input)
WL = 2
DQ
(input)
WL = 2
Da0 Da1
Db0 Db1
tDQSS
BL = 4
Da0 Da1
tDQSS
Dc0 Dc1
tDQSS
DQS
(input)
WL = 2
DQ
(input)
WL = 2
Da0 Da1 Da2 Da3 Db0 Db1 Db2 Db3
Da0 Da1 Da2 Da3 Dc0 Dc1 Dc2
MULTIPLE BANK WRITE TIMING (CL = 4)
0
1
2
3
4
5
6
7
8
9
10
11
CLK
CLK
Command
IRC = 5 cycles
WRAa
LALa
WRAb
IRCD = 1 cycle
Bank Add.
(BA0, BA1)
Bank “a”
×
IRBD = 2 cycles
LALb
DESL
WRAa
IRAS = 4 cycles
Bank “b”
WRAc
IRCD = 1 cycle
×
×
Bank “a”
IRBD = 2 cycles
BL = 2
LALa
IRCD = 1 cycle
LALc
IRCD = 1 cycle
WRAd
LALd
WRAb
IRBD = 2 cycles
IRBD = 2 cycles
×
×
Bank “c”
tDQSS
Bank “d”
Bank “b”
tDQSS
DQS
(input)
WL = 3
DQ
(input)
WL = 3
Da0 Da1
tDQSS
BL = 4
Db0 Db1
tDQSS
Da0 Da1
Dc0 Dc1
tDQSS
DQS
(input)
WL = 3
DQ
(input)
Da0 Da1 Da2 Da3 Db0 Db1 Db2 Db3
Note:
WL = 3
Da0 Da1 Da2 Da3 Dc0 Dc1
means H or L.
“×” is don’t care
IRC to the same bank must be satisfied.
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MULTIPLE BANK READ-WRITE TIMING (BL = 2)
0
1
2
3
4
5
6
7
8
9
10
11
CLK
CLK
IRBD = 2 cycles
Command
WRAa
LALa
IRCD = 1 cycle
IRWD = 2 cycles
RDAb
LALb
DESL
IRCD = 1 cycle IWRD = 1 cycle
Bank Add.
(BA0, BA1)
CL = 3
DQS
Bank “a”
×
WRAc
LALc
RDAd
LALd
×
Bank “b”
×
Bank “c”
×
Bank “d”
tDQSS
DQS
×
Bank “c”
Hi-Z
Hi-Z
CL = 3
WL = 2
Hi-Z
Da0 Da1
Qb0 Qb1
CL = 3
Hi-Z
Dc0 Dc1
Hi-Z
Hi-Z
Hi-Z
WL = 3
CL = 4
Hi-Z
Qd0
tDQSS
WL = 3
DQ
LALc
tDQSS
Hi-Z
Hi-Z
WRAc
IRCD = 1 cycle
tDQSS
CL = 4
DESL
IRCD = 1 cycle IWRD = 1 cycle
WL = 2
DQ
IRC = 5 cycles
IRBD = 2 cycles
IRWD = 2 cycles
Hi-Z
Da0 Da1
CL = 4
Qb0 Qb1
Hi-Z
Dc0 Dc1
MULTIPLE BANK READ-WRITE TIMING (BL = 4)
0
1
2
3
4
5
6
7
8
9
10
11
CLK
CLK
Command
IRBD = 2 cycles
WRAa
LALa
IRCD = 1 cycle
RDAb
IRWD = 3 cycles IRBD = 2 cycles IRCD = 1 cycle
LALb
DESL
IRCD = 1 cycle IWRD = 1 cycle
Bank Add.
(BA0, BA1)
Bank “a”
×
WRAc
LALc
RDAd
DQS
×
Bank “b”
Bank “c”
×
CL = 4
DQS
×
Bank “d”
tDQSS
Hi-Z
WL = 2
DQ
DESL
IRCD = 1 cycle IWRD = 1 cycle
tDQSS
CL = 3
LALd
Hi-Z
CL = 3
Da0 Da1 Da2 Da3
WL = 2
Qb0 Qb1 Qb2 Qb3
Dc0 Dc1 Dc2 Dc3
tDQSS
tDQSS
Hi-Z
WL = 3
WL = 3
CL = 4
DQ
Hi-Z
Da0 Da1 Da2 Da3
Qb0 Qb1 Qb2 Qb3
Dc0 Dc1 Dc2
Note: “×” is don’t care
IRC to the same bank must be satisfied.
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SINGLE BANK WRITE with VARIABLE WRITE LENGTH (VW) CONTROL
(CL = 3, BL = 4, Sequential mode)
0
1
2
3
4
5
6
7
8
9
10
11
WRA
LAL
UA
LA=#3
VW=2
CLK
CLK
IRC = 5cycles
x8
Command
Address
WRA
LAL
IRC = 5cycles
DESL
WRA
LA=#3
VW=2
(Write First Two Words)
LAL
DESL
LA=#1
VW=1
(Write First One Word)
UA
UA
DQS
(input)
Last two data are masked.
DQ
(input)
D0 D1
Last three data are
D0
Address #3 #0 (#1) (#2)
#1 (#2) (#3) (#0)
x16
Command
Address
WRA
LAL
UA
LA =#3
UVW=2
LVW=1
DESL
WRA
LAL
UA
LA=#1
UVW=1
LVW=1
Upper byte: Write First Two Words
Lower byte: Write First One Word
DESL
WRA
LAL
UA
LA=#3
UVW=2
LVW=1
Upper byte: Write First One Word
Lower byte: Write First One Word
UDQS
(input)
Last two data are masked.
DQ8~DQ15
(input)
D0 D1
Last three data are
D0
Address #3 #0 (#1) (#2)
#1 (#2) (#3) (#0)
UDQS
(input)
Last three data are
DQ0~DQ7
(input)
D0
Address #3 (#0) (#1) (#2)
Note:
Last three data are
D0
#1 (#2) (#3) (#0)
DQS input must be continued till end of burst count even if some of laster data is masked.
Refer to "VW Truth Table".
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MODE REGISTER SET TIMING (CL = 3, BL = 2)
0
1
2
3
4
5
6
7
8
9
10
11
CLK
CLK
IRC = 5 cycles
Command
A14~A0
BA0, BA1
DQS
(output)
RDA
IRSC = 5 cycles
LAL
DESL
IRCD = 1 cycle
IRAS = 4 cycles
BA, UA
RDA
DESL
RDA
or
WRA
×
BA, UA
IRCD = 1 cycle
Valid
(opcode)
×
LA
MRS
Hi-Z
Hi-Z
CL = 3
DQ
(output)
Hi-Z
Hi-Z
Q0 Q1
POWER DOWN TIMING (CL = 3, BL = 2)
Read cycle to Power Down Mode
0
1
2
3
4
5
6
7
n−1
n
n+1
n+2
CLK
CLK
IPDA = 1 cycle
Command
RDA
LAL
×
DESL
IRCD = 1 cycle
DESL
RDA
or
WRA
tIH tIS IPD = 1 cycle
PD
tQPDH
DQS
(output)
Hi-Z
lRC(min), tREFI(max)
tPDEX
Hi-Z
CL = 3
DQ
(output)
Hi-Z
Q0 Q1
Hi-Z
Power Down Entry
Power Down Exit
Note: “×” is don’t care
IPD is defined from the first clock rising edge after PD is brought to “Low”.
IPDA is defined from the first clock rising edge after PD is brought to “High”.
PD must be kept "High" level until end of Burst data output.
PD should be brought to high within tREFI(max) to maintain the data written into cell.
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POWER DOWN TIMING (CL = 4)
Write cycle to Power Down Mode
0
1
2
3
4
5
6
7
8
n−1
9
n
n+1
n+2
CLK
CLK
IPDA = 1 cycle
Command
WRA
LAL
×
DESL
DESL
RDA
or
WRA
tIH tIS IPD = 1 cycle
PD
WL=3
2 clock cycles
lRC(min), tREFI(max)
tPDEX
BL = 4
DQS
(Input)
Hi-Z
DQ
(Input)
Hi-Z
Hi-Z
D0 D1 D2 D3
Hi-Z
BL = 2
DQS
(Input)
Hi-Z
DQ
(Input)
Hi-Z
Hi-Z
D0 D1
Hi-Z
Power Down Entry
Power Down Exit
Note: “×” is don’t care
PD must be kept "High" level until WL+2 clock cycles from LAL command.
PD should be brought to high within tREFI(max) to maintain the data written into cell.
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AUTO-REFRESH TIMING (CL = 3, BL = 4)
0
1
2
3
4
5
6
7
n−1
n
n+1
n+2
RDA
or
WRA
LAL or
MRS or
REF
CLK
CLK
IRC = 5 cycles
Command
RDA
LAL
IRCD = 1 cycle
DQS
(output)
IREFC = 15 cycles
DESL
WRA
IRAS = 4 cycles
REF
DESL
IRCD = 1 cycle
Hi-Z
Hi-Z
CL = 3
DQ
(output)
Hi-Z
Q0 Q1 Q2 Q3
Hi-Z
Note: In case of CL = 3, IREFC must be meet 15 clock cycles.
When the Auto-Refresh operation is performed, the synthetic average interval of Auto-Refresh
command specified by tREFI must be satisfied.
tREFI is average interval time in 8 Refresh cycles that is sampled randomly.
t1
t2
t3
t7
t8
CLK
WRA REF
WRA REF
WRA REF
WRA REF
WRA REF
8 Refresh cycle
tREFI =
Total time of 8 Refresh cycle
8
=
t1 + t2 + t3 + t4 + t5 + t6 + t7 + t8
8
tREFI is specified to avoid partly concentrated current of Refresh operation that is activated larger area
than Read / Write operation.
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SELF-REFRESH ENTRY TIMING (CL = 3)
0
1
2
3
4
m−1
5
m
m+1
CLK
CLK
Command
IRCD = 1 cycle
WRA
IREFC
REF
tFPDL (min)
×
DESL
*1
tFPDL (max)
Auto Refresh
PD
Self Refresh Entry
IPDV *2
ICKD = 16 cycles*3
tQPDH
DQS
(output)
DQ
(output)
Hi-Z
Hi-Z
Qx
Notes: 1. “×” is don’t care.
2. PD must be brought to "Low" within the timing between tFPDL(min) and tFPDL(max) to Self
TM
Refresh mode.When PD is brought to "Low" after lPDV, FCRAM perform Auto Refresh and
enter Power down mode.
3. It is necessary that clock input is continued at least 16 clock cycles from REF command even
though PD is brought to “Low” for Self-Refresh Entry.
SELF-REFRESH EXIT TIMING
0
1
2
m−1
m+1
m
m+2
n−1
n
n+1
p−1
p
CLK
CLK
*2
IREFC
Command
×
*1
*3
DESL
IPDA = 1 cycle*4
IREFC
WRA
*5
REF
*5
Command (1st)*6
Command (2nd)*6
DESL
IRCD = 1 cycle
RDA
*7
LAL
*7
IRCD = 1 cycle
PD
tPDEX
ILOCK
DQS
(output)
Hi-Z
DQ
(output)
Hi-Z
Self-Refresh Exit
Notes: 1.
2.
3.
4.
5.
“×” is don’t care.
Clock should be stable prior to PD = “High” if clock input is suspended in Self-Refresh mode.
DESL command must be asserted during IREFC after PD is brought to “High”.
IPDA is defined from the first clock rising edge after PD is brought to “High”.
It is desirable that one Auto-Refresh command is issued just after Self-Refresh Exit before any
other operation.
6. Any command (except Read command) can be issued after IREFC.
7. Read command (RDA + LAL) can be issued after ILOCK.
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FUNCTIONAL DESCRIPTION
Network FCRAM
TM
The FCRAMTM is an acronym of Fast Cycle Random Access Memory. The Network FCRAMTM is competent to
perform fast random core access, low latency, low consumption and high-speed data transfer.
PIN FUNCTIONS
CLOCK INPUTS: CLK & CLK
The CLK and CLK inputs are used as the reference for synchronous operation. CLK is master clock input.
The CS , FN and all address input signals are sampled on the crossing of the positive edge of CLK and the
negative edge of CLK . The DQS and DQ output data are referenced to the crossing point of CLK and CLK .
The timing reference point for the differential clock is when the CLK and CLK signals cross during a
transition.
POWER DOWN: PD
The PD input controls the entry to the Power Down or Self-Refresh modes. The PD input does not have a
Clock Suspend function like a CKE input of a standard SDRAMs, therefore it is illegal to bring PD pin into
low state if any Read or Write operation is being performed.
CHIP SELECT & FUNCTION CONTROL: CS & FN
The CS and FN inputs are a control signal for forming the operation commands on FCRAMTM. Each
operation mode is decided by the combination of the two consecutive operation commands using the CS and
FN inputs.
BANK ADDRESSES: BA0 & BA1
The BA0 and BA1 inputs are latched at the time of assertion of the RDA or WRA command and are selected
the bank to be used for the operation.
BA0
BA1
Bank #0
0
0
Bank #1
1
0
Bank #2
0
1
Bank #3
1
1
ADDRESS INPUTS: A0~A14
Address inputs are used to access the arbitrary address of the memory cell array within each bank. The Upper
Addresses with Bank addresses are latched at the RDA or WRA command and the Lower Addresses are latched
at the LAL command. The A0 to A14 inputs are also used for setting the data in the Regular or Extended Mode
Register set cycle.
UPPER ADDRESS
LOWER ADDRESS
TC59LM806CFT
A0~A14
A0~A7
TC59LM814CFT
A0~A14
A0~A6
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DATA INPUT/OUTPUT: DQ0~DQ7 or DQ15
The input data of DQ0 to DQ15 are taken in synchronizing with the both edges of DQS input signal. The
output data of DQ0 to DQ15 are outputted synchronizing with the both edges of DQS output signal.
DATA STROBE: DQS or LDQS, UDQS
The DQS is bi-directional signal. Both edges of DQS are used as the reference of data input or output. The
LDQS is allotted for Lower Byte (DQ0 to DQ7) Data. The UDQS is allotted for Upper Byte (DQ8 to DQ15) Data.
In write operation, the DQS used as an input signal is utilized for a latch of write data. In read operation, the
DQS that is an output signal provides the read data strobe.
POWER SUPPLY: VDD, VDDQ, VSS, VSSQ
VDD and VSS are power supply pins for memory core and peripheral circuits.
VDDQ and VSSQ are power supply pins for the output buffer.
REFERENCE VOLTAGE: VREF
VREF is reference voltage for all input signals.
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COMMAND FUNCTIONS and OPERATIONS
TC59LM814/06CFT are introduced the two consecutive command input method. Therefore, except for Power
Down mode, each operation mode decided by the combination of the first command and the second command from
stand-by states of the bank to be accessed.
Read Operation (1st command + 2nd command = RDA + LAL)
Issuing the RDA command with Bank Addresses and Upper Addresses to the idle bank puts the bank
designated by Bank Address in a read mode. When the LAL command with Lower Addresses is issued at the
next clock of the RDA command, the data is read out sequentially synchronizing with the both edges of DQS
output signal (Burst Read Operation). The initial valid read data appears after CAS latency from the issuing
of the LAL command. The valid data is outputted for a burst length. The CAS latency, the burst length of read
data and the burst type must be set in the Mode Register beforehand. The read operated bank goes back
automatically to the idle state after lRC.
Write Operation (1st command + 2nd command = WRA + LAL)
Issuing the WRA command with Bank Addresses and Upper Addresses to the idle bank puts the bank
designated by Bank Address in a write mode. When the LAL command with Lower Addresses is issued at the
next clock of the WRA command, the input data is latched sequentially synchronizing with the both edges of
DQS input signal (Burst Write Operation). The data and DQS inputs have to be asserted in keeping with clock
input after CAS latency-1 from the issuing of the LAL command. The DQS have to be provided for a burst
length. The CAS latency and the burst type must be set in the Mode Register beforehand. The write operated
bank goes back automatically to the idle state after lRC.
Auto-Refresh Operation (1st command + 2nd command = WRA + REF)
TC59LM814/06CFT are required to refresh like a standard SDRAM. The Auto-Refresh operation is begun
with the REF command following to the WRA command. The Auto-Refresh mode can be effective only when all
banks are in the idle state and all outputs are in Hi-Z states. In a point to notice, the write mode started with
the WRA command is canceled by the REF command having gone into the next clock of the WRA command
instead of the LAL command. The minimum period between the Auto-Refresh command and the next command
is specified by lREFC. However, about a synthetic average interval of Auto-Refresh command, it must be careful.
In case of equally distributed refresh, Auto-Refresh command has to be issued within once for every 7.8 µs by
the maximum. In case of burst refresh or random distributed refresh, the average interval of eight consecutive
Auto-Refresh command has to be more than 400 ns always. In other words, the number of Auto-Refresh cycles
which can be performed within 3.2 µs (8 × 400 ns) is to 8 times in the maximum.
Self-Refresh Operation (1st command + 2nd command = WRA + REF with PD = “L”)
It is the function of Self-Refresh operation that refresh operation can be performed automatically by using an
internal timer. When all banks are in the idle state and all outputs are in Hi-Z states, the TC59LM814/06CFT
become Self-Refresh mode by issuing the Self-Refresh command. PD has to be brought to “Low” within tFPDL
from the REF command following to the WRA command for a Self-Refresh mode entry. In order to satisfy the
refresh period, the Self-Refresh entry command should be asserted within 7.8 µs after the latest Auto-Refresh
command. Once the device enters Self-Refresh mode, the DESL command must be continued for lREFC period.
In addition, it is necessary that clock input is kept in lCKD period. The device is in Self-Refresh mode as long as
PD held “Low”. During Self-Refresh mode, all input and output buffers except for PD are disabled, therefore
the power dissipation lowers. Regarding a Self-Refresh mode exit, PD has to be changed over from “Low” to
“High” along with the DESL command, and the DESL command has to be continuously issued in the number of
clocks specified by lREFC. The Self-Refresh exit function is asynchronous operation. It is required that one
Auto-Refresh command is issued to avoid the violation of the refresh period just after lREFC from Self-Refresh
exit.
Power Down Mode ( PD = “L”)
When all banks are in the idle state and all outputs are in Hi-Z states, the TC59LM814/06CFT become Power
Down Mode by asserting PD is “Low”. When the device enters the Power Down Mode, all input and output
buffers except for PD are disabled after specified time. Therefore, the power dissipation lowers. To exit the
Power Down Mode, PD has to be brought to “High” and the DESL command has to be issued at next CLK
rising edge after PD goes high. The Power Down exit function is asynchronous operation.
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Mode Register Set (1st command + 2nd command = RDA + MRS)
When all banks are in the idle state, issuing the MRS command following to the RDA command can program
the Mode Register. In a point to notice, the read mode started with the RDA command is canceled by the MRS
command having gone into the next clock of the RDA command instead of the LAL command. The data to be set
in the Mode Register is transferred using A0 to A14, BA0 and BA1 address inputs. The TC59LM814/06CFT
have two mode registers. These are Regular and Extended Mode Register. The Regular or Extended Mode
Register is chosen by BA0 and BA1 in the MRS command. The Regular Mode Register designates the operation
mode for a read or write cycle. The Regular Mode Register has four function fields.
The four fields are as follows:
(R-1) Burst Length field to set the length of burst data
(R-2) Burst Type field to designate the lower address access sequence in a burst cycle
(R-3) CAS Latency field to set the access time in clock cycle
(R-4) Test Mode field to use for supplier only.
The Extended Mode Register has two function fields.
The two fields are as follows:
(E-1) DLL Switch field to choose either DLL enable or DLL disable
(E-2) Output Driver Impedance Control field.
Once those fields in the Mode Register are set up, the register contents are maintained until the Mode
Register is set up again by another MRS command or power supply is lost. The initial value of the Regular or
Extended Mode Register after power-up is undefined, therefore the Mode Register Set command must be issued
before proper operation.
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•
Regular Mode Register/Extended Mode Register change bits (BA0, BA1)
These bits are used to choose either Regular MRS or Extended MRS
BA1
BA0
A14~A0
0
0
Regular MRS Cycle
0
1
Extended MRS Cycle
1
×
Reserved
Regular Mode Register Fields
(R-1) Burst Length field (A2 to A0)
This field specifies the data length for column access using the A2 to A0 pins and sets the Burst Length
to be 2 or 4 words.
A2
A1
A0
BURST LENGTH
0
0
0
Reserved
0
0
1
2 words
0
1
0
4 words
0
1
1
Reserved
1
×
×
Reserved
(R-2) Burst Type field (A3)
The Burst Type can be chosen Interleave mode or Sequential mode. When the A3 bit is “0”, Sequential
mode is selected. When the A3 bit is “1”, Interleave mode is selected. Both burst types support burst
length of 2 and 4 words.
•
A3
BURST TYPE
0
Sequential
1
Interleave
Addressing sequence of Sequential mode (A3)
A column access is started from the inputted lower address and is performed by incrementing the lower
address input to the device. The address is varied by the Burst Length as the following.
CAS Latency = 3
CLK
CLK
Command
RDA
LAL
DQS
Data Data Data Data
0
1
2
3
DQ
Addressing sequence for Sequential mode
DATA
ACCESS ADDRESS
Data 0
n
Data 1
n+1
Data 2
n+2
Data 3
n+3
BURST LENGTH
2 words (address bits is LA0)
not carried from LA0~LA1
4 words (address bits is LA1, LA0)
not carried from LA1~LA2
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•
Addressing sequence of Interleave mode
A column access is started from the inputted lower address and is performed by interleaving the address bits
in the sequence shown as the following.
Addressing sequence for Interleave mode
DATA
(R-3)
ACCESS ADDRESS
BURST LENGTH
Data 0
ּּּA8 A7 A6 A5 A4 A3 A2 A1 A0
Data 1
ּּּA8 A7 A6 A5 A4 A3 A2 A1 A0
Data 2
ּּּA8 A7 A6 A5 A4 A3 A2 A1 A0
Data 3
ּּּA8 A7 A6 A5 A4 A3 A2 A1 A0
2 words
4 words
CAS Latency field (A6 to A4)
This field specifies the number of clock cycles from the assertion of the LAL command following the RDA
command to the first data read. The minimum values of CAS Latency depends on the frequency of CLK.
In a write mode, the place of clock which should input write data is CAS Latency cycles − 1.
A6
A5
A4
CAS LATENCY
0
0
0
Reserved
0
0
1
Reserved
0
1
0
Reserved
0
1
1
3
1
0
0
4
1
0
1
Reserved
1
1
0
Reserved
1
1
1
Reserved
(R-4) Test Mode field (A7)
This bit is used to enter Test Mode for supplier only and must be set to “0” for normal operation.
(R-5) Reserved field in the Regular Mode Register
• Reserved bits (A8 to A14)
These bits are reserved for future operations. They must be set to “0” for normal operation.
Extended Mode Register fields
(E-1) DLL Switch field (A0)
This bit is used to enable DLL. When the A0 bit is set “0”, DLL is enabled.
(E-2) Output Driver Impedance Control field (A1 / A6)
This bit is used to choose Output Driver Strength. Four types of Driver Strength are supported.
A6
A1
OUTPUT DRIVER IMPEDANCE CONTROL
0
0
Normal Output Driver
0
1
Strong Output Driver
1
0
Weaker Output Driver
1
1
Weakest Output Driver
(E-3) Reserved field (A2 to A5, A7 to A14)
These bits are reserved for future operations and must be set to “0” for normal operation.
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TC59LM814/06CFT-50,-55,-60
PACKAGE DIMENSIONS
Weight:
0.51 g (typ.)
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TC59LM814/06CFT-50,-55,-60
RESTRICTIONS ON PRODUCT USE
000707EBA
•
TOSHIBA is continually working to improve the quality and reliability of its products. Nevertheless, semiconductor
devices in general can malfunction or fail due to their inherent electrical sensitivity and vulnerability to physical
stress. It is the responsibility of the buyer, when utilizing TOSHIBA products, to comply with the standards of
safety in making a safe design for the entire system, and to avoid situations in which a malfunction or failure of
such TOSHIBA products could cause loss of human life, bodily injury or damage to property.
In developing your designs, please ensure that TOSHIBA products are used within specified operating ranges as
set forth in the most recent TOSHIBA products specifications. Also, please keep in mind the precautions and
conditions set forth in the “Handling Guide for Semiconductor Devices,” or “TOSHIBA Semiconductor Reliability
Handbook” etc..
•
The TOSHIBA products listed in this document are intended for usage in general electronics applications
(computer, personal equipment, office equipment, measuring equipment, industrial robotics, domestic appliances,
etc.). These TOSHIBA products are neither intended nor warranted for usage in equipment that requires
extraordinarily high quality and/or reliability or a malfunction or failure of which may cause loss of human life or
bodily injury (“Unintended Usage”). Unintended Usage include atomic energy control instruments, airplane or
spaceship instruments, transportation instruments, traffic signal instruments, combustion control instruments,
medical instruments, all types of safety devices, etc.. Unintended Usage of TOSHIBA products listed in this
document shall be made at the customer’s own risk.
•
•
•
The products described in this document are subject to the foreign exchange and foreign trade laws.
The information contained herein is presented only as a guide for the applications of our products. No
responsibility is assumed by TOSHIBA CORPORATION for any infringements of intellectual property or other
rights of the third parties which may result from its use. No license is granted by implication or otherwise under
any intellectual property or other rights of TOSHIBA CORPORATION or others.
The information contained herein is subject to change without notice.
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