TC59LM913AMB-50
TENTATIVE
TOSHIBA MOS DIGITAL INTEGRATED CIRCUIT SILICON MONOLITHIC
512Mbits Network FCRAM1 (SSTL_2 Interface)
− 4,194,304-WORDS × 8 BANKS × 16-BITS
DESCRIPTION
Network FCRAMTM is Double Data Rate Fast Cycle Random Access Memory. TC59LM913AMB is Network
FCRAMTM containing 536,870,912 memory cells. TC59LM913AMB is organized as 4,194,304-words × 8 banks × 16
bits. TC59LM913AMB feature a fully synchronous operation referenced to clock edge whereby all operations are
synchronized at a clock input which enables high performance and simple user interface coexistence.
TC59LM913AMB can operate fast core cycle compared with regular DDR SDRAM.
TC59LM913AMB is suitable for Network, Server and other applications where large memory density and low
power consumption are required. The Output Driver for Network FCRAMTM is capable of high quality fast data
transfer under light loading condition.
FEATURES
PARAMETER
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
TC59LM913AMB-50
CL = 4
tCK
Clock Cycle Time (min)
tRC
Random Read/Write Cycle Time (min)
tRAC
Random Access Time (max)
5.0 ns
25.0 ns
22.0 ns
IDD1S Operating Current (single bank) (max)
240 mA
lDD2P Power Down Current (max)
80 mA
lDD6
20 mA
Self-Refresh Current (max)
Fully Synchronous Operation
• Double Data Rate (DDR)
Data input/output are synchronized with both edges of DQS.
• Differential Clock (CLK and CLK ) inputs
CS , FN and all address input signals are sampled on the positive edge of CLK.
Output data (DQs and DQS) is aligned to the crossings of CLK and CLK .
Fast clock cycle time of 5 ns minimum
Clock: 200 MHz maximum
Data: 400 Mbps/pin maximum
Fast cycle and Short Latency
Eight independent banks operation
When BA2 input assign to A14 input, TC59LM913AMB can function as 4bank device
(Keep backward compatibility to 256Mb)
Bidirectional Data Strobe Signal
Distributed Auto-Refresh cycle in 3.9 µs
Self-Refresh
Power Down Mode
Variable Write Length Control
Write Latency = CAS Latency-1
Programable CAS Latency and Burst Length
CAS Latency = 4
Burst Length = 2, 4
Organization: TC59LM913AMB : 4,194,304 words × 8 banks × 16 bits
Power Supply Voltage VDD:
2.5 V ± 0.15V
VDDQ:
2.5 V ± 0.15 V
2.5 V CMOS I/O comply with SSTL_2 (half strength driver)
Package: 60Ball BGA, 1mm × 1mm Ball pitch (P−BGA64−1317−1.00AZ)
Keep backward compatibility for TC59LM814CFT(256Mbits) except package design.
Notice : FCRAM is trademark of Fujitsu Limited, Japan.
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TC59LM913AMB-50
TC59LM913AMB
PIN NAMES
PIN
NAME
PIN
NAME
A0~A13
Address Input
UDQS/LDQS Write/Read Data Strobe
BA0~BA2
Bank Address
VDD
Power (+2.5 V)
DQ0~DQ15
Data Input/Output
VSS
Ground
CS
Chip Select
VDDQ
Power (+2.5 V) (for I/O buffer)
FN
Function Control
VSSQ
Ground (for I/O buffer)
PD
Power Down Control
VREF
Reference Voltage
CLK, CLK
Clock Input
NC
Not Connected
4 bank operation can be performed using BA2 as A14.
PIN ASSIGNMENT (TOP VIEW)
ball pitch=1.0 x 1.0mm
x 16
1
2
5
6
VSS
DQ15
DQ0
VDD
B
DQ14
VSSQ
VDDQ
DQ1
C
DQ13
VDDQ
VSSQ
DQ2
D
DQ12
DQ11
DQ4
DQ3
E
DQ10
VSSQ
VDDQ
DQ5
DQ9
VDDQ
VSSQ
DQ6
G
DQ8
VSSQ
VDDQ
DQ7
H
NC
UDQS
LDQS
NC
J
VREF
VSS
VDD
BA2
CLK
CLK
FN
A13
L
A12
PD
CS
NC
M
A11
A9
BA1
BA0
N
A8
A7
A0
A10
P
A5
A6
A2
A1
R
VSS
A4
A3
VDD
A
F
K
Index
NC
NC
3
4
NC
NC
: Depopulated ball
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TC59LM913AMB-50
BLOCK DIAGRAM
CLK
CLK
PD
CS
FN
DLL
CLOCK
BUFFER
COMMAND
DECODER
To each block
BANK #7
BANK #6
BANK #5
BANK #4
BANK #3
BANK #2
BANK #1
CONTROL
SIGNAL
GENERATOR
BA0~BA2
ADDRESS
BUFFER
UPPER ADDRESS
LATCH
LOWER ADDRESS
LATCH
REFRESH
COUNTER
BURST
COUNTER
DATA
CONTROL and LATCH
CIRCUIT
A0~A13
ROW DECODER
BANK #0
MODE
REGISTER
MEMORY
CELL ARRAY
COLUMN DECODER
READ
DATA
BUFFER
WRITE ADDRESS
LATCH/
ADDRESS
COMPARATOR
DQS
WRITE
DATA
BUFFER
DQ BUFFER
DQ0~DQ15
Note: The TC59LM913AMB configuration is 8 Bank of 16384 × 256 × 16 of cell array with the DQ pins numbered DQ0~DQ15.
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TC59LM913AMB-50
ABSOLUTE MAXIMUM RATINGS
SYMBOL
PARAMETER
RATING
UNIT
−0.3~3.3
V
VDD
Power Supply Voltage
VDDQ
Power Supply Voltage (for I/O buffer)
−0.3~VDD+ 0.3
V
VIN
Input Voltage
−0.3~VDD+ 0.3
V
VOUT
Output and I/O pin Voltage
−0.3~VDDQ + 0.3
V
VREF
Input Reference Voltage
−0.3~VDD+ 0.3
V
TCASE
Operating Temperature (case)
0~85
°C
Tstg
Storage Temperature
−55~150
°C
Tsolder
Soldering Temperature (10 s)
260
°C
PD
Power Dissipation
2
W
IOUT
Short Circuit Output Current
±50
mA
NOTES
Caution: Conditions outside the limits listed under “ABSOLUTE MAXIMUM RATINGS” may cause permanent damage to the device.
The device is not meant to be operated under conditions outside the limits described in the operational section of this
specification.
Exposure to “ABSOLUTE MAXIMUM RATINGS” conditions for extended periods may affect device reliability.
RECOMMENDED DC, AC OPERATING CONDITIONS (Notes: 1)(TCASE = 0~85°C)
SYMBOL
PARAMETER
MIN
TYP.
MAX
UNIT
NOTES
VDD
Power Supply Voltage
2.35
2.5
2.65
V
VDDQ
Power Supply Voltage (for I/O buffer)
2.35
VDD
VDD
V
VREF
Input Reference Voltage
VDDQ/2 × 96%
VDDQ/2
VDDQ/2 × 104%
V
2
VIH (DC)
Input DC High Voltage
VREF + 0.2
VDDQ + 0.2
V
5
VIL (DC)
Input DC Low Voltage
−0.1
VREF − 0.2
V
5
VICK (DC)
Differential Clock DC Input Voltage
−0.1
VDDQ + 0.1
V
10
VID (DC)
Input Differential Voltage.
CLK and CLK inputs (DC)
0.4
VDDQ + 0.2
V
7, 10
VIH (AC)
Input AC High Voltage
VREF + 0.35
VDDQ + 0.2
V
3, 6
VIL (AC)
Input AC Low Voltage
−0.1
VREF − 0.35
V
4, 6
VID (AC)
Input Differential Voltage.
CLK and CLK inputs (AC)
0.7
VDDQ + 0.2
V
7, 10
VX (AC)
Differential AC Input Cross Point Voltage
VDDQ/2 − 0.2
VDDQ/2 + 0.2
V
8, 10
VISO (AC)
Differential Clock AC Middle Level
VDDQ/2 − 0.2
VDDQ/2 + 0.2
V
9, 10
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TC59LM913AMB-50
NOTES:
(1)
All voltages referenced to VSS, VSSQ.
(2)
VREF is expected to track variations in VDDQ DC level of the transmitting device.
Peak to peak AC noise on VREF may not exceed ±2% VREF (DC).
(3)
Overshoot limit: VIH (max) = VDDQ + 0.9 V with a pulse width ≤ 5 ns.
(4)
Undershoot limit: VIL (min) = −0.9 V with a pulse width ≤ 5 ns.
(5)
VIH (DC) and VIL (DC) are levels to maintain the current logic state.
(6)
VIH (AC) and VIL (AC) are levels to change to the new logic state.
(7)
VID is magnitude of the difference between CLK input level and CLK input level.
(8)
The value of VX (AC) is expected to equal VDDQ/2 of the transmitting device.
(9)
VISO means {VICK (CLK) + VICK ( CLK )} /2
(10)
Refer to the figure below.
CLK
Vx
Vx
Vx
Vx
Vx
VID (AC)
CLK
VICK
VICK
VICK
VISO (min)
VISO (max)
VICK
VSS
|VID (AC)|
0 V Differential
VISO
VSS
(11)
In the case of external termination, VTT (termination voltage) should be gone in the range of VREF (DC)
± 0.04 V.
CAPACITANCE (VDD = 2.5V, VDDQ = 2.5 V, f = 1 MHz, Ta = 25°C)
SYMBOL
PARAMETER
MIN
MAX
Delta
UNIT
CIN
Input pin Capacitance
1.5
2.5
0.25
pF
CINC
Clock pin (CLK, CLK ) Capacitance
1.5
2.5
0.25
pF
CI/O
DQ, DQS, UDQS, LDQS Capacitance
2.5
4.0
0.5
pF
CNC
NC pin Capacitance
4.0
pF
Note: These parameters are periodically sampled and not 100% tested.
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TC59LM913AMB-50
RECOMMENDED DC OPERATING CONDITIONS
(VDD=2.5V ± 0.15V, VDDQ=2.5V ± 0.15V, TCASE = 0~85°C)
SYMBOL
PARAMETER
MAX
UNIT
NOTES
Operating Current
IDD1S
tCK = min, IRC = min ;
Read/Write command cycling ;
0 V ≤ VIN ≤ VIL (AC) (max), VIH (AC) (min) ≤ VIN ≤ VDDQ ;
1 bank operation, Burst length = 4 ;
Address change up to 2 times during minimum IRC.
240
1, 2
100
1, 2
80
1, 2
Standby Current
IDD2N
tCK = min, CS = VIH, PD = VIH ;
0 V ≤ VIN ≤ VIL (AC) (max), VIH (AC) (min) ≤ VIN ≤ VDDQ ;
All banks: inactive state ;
Other input signals are changed one time during 4 × tCK.
Standby (power down) Current
IDD2P
tCK = min, CS = VIH, PD = VIL (Power Down) ;
0 V ≤ VIN ≤ VDDQ ;
All banks: inactive state
Write Operation Current (4 Banks)
IDD4W
8 Bank Interleaved continuous burst write operation ;
tCK = min, IRC = min ;
Burst Length = 4, CAS Latency = 4 ;
0 V ≤ VIN ≤ VIL (AC) (max), VIH (AC) (min) ≤ VIN ≤ VDDQ ;
DQ and DQS inputs change twice per clock cycle
350
1, 2
mA
Read Operation Current (4 Banks)
IDD4R
8 Bank Interleaved contious burst read operation ;
tCK = min, IRC = min, IOUT = 0mA ;
Burst Length = 4, CAS Latency = 4 ;
0 V ≤ VIN ≤ VIL (AC) (max), VIH (AC) (min) ≤ VIN ≤ VDDQ ;
Address inputs change once per clock cycle.
Read data change twice per clock cycle.
350
1, 2
250
1, 2, 3
20
2
Burst Auto Refresh Current
IDD5B
Refresh command at every IREFC interval ;
tCK = min, IREFC = min ;
CAS Latency = 4 ;
0 V ≤ VIN ≤ VIL (AC) (max), VIH (AC) (min) ≤ VIN ≤ VDDQ ;
Address inputs change up to 2 times during minimum IREFC.
DQ and DQS inputs change twice per clock cycle.
Self-Refresh Current
IDD6
Self-Refresh mode ;
PD = 0.2 V, 0 V ≤ VIN ≤ VDDQ
Notes: 1. These parameters depend on the cycle rate and these values are measured at a cycle rate with the minimum values of
tCK, tRC and IRC.
2. These parameters defines the current between VDD and VSS.
3. IDD5B is specified under burst refresh condition. Actual system should use distributed refresh that meet tREFI
specification.
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TC59LM913AMB-50
RECOMMENDED DC OPERATING CONDITIONS (continued)
(VDD=2.5V ± 0.15V, VDDQ=2.5V ± 0.15V, TCASE = 0~85°C)
SYMBOL
PARAMETER
MIN
MAX
UNIT
ILI
Input Leakage Current
( 0 V ≤ VIN ≤ VDDQ, all other pins not under test = 0 V)
−5
5
µA
ILO
Output Leakage Current
(Output disabled, 0 V ≤ VOUT ≤ VDDQ)
−5
5
µA
IREF
VREF Current
−5
5
µA
−10
10
Output Source DC Current
VOH = VDDQ − 0.4V
Strong
Output Driver Output Sink DC Current
VOL = 0.4V
−11
11
Output Source DC Current
VOH = VDDQ − 0.4V
−8
8
−7
7
IOH (DC)
IOL (DC)
IOH (DC)
IOL (DC)
IOH (DC)
IOL (DC)
IOH (DC)
IOL (DC)
Output Source DC Current
VOH = VDDQ − 0.4V
Normal
Output Driver Output Sink DC Current
VOL = 0.4V
Weaker
Output Driver Output Sink DC Current
VOL = 0.4V
Output Source DC Current
VOH = VDDQ − 0.4V
Weakest
Output Driver Output Sink DC Current
VOL = 0.4V
NOTES
mA
1
Notes: 1. Refer to output driver characteristics for the detail. Output Driver Strength is selected by Extended Mode Register.
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TC59LM913AMB-50
AC CHARACTERISTICS AND OPERATING CONDITIONS (Notes: 1, 2)
(VDD = 2.5V ± 0.15V, VDDQ = 2.5V ± 0.15V, TCASE = 0~85°C)
SYMBOL
PARAMETER
MIN
MAX
UNIT
NOTES
tRC
Random Cycle Time
25
3
tCK
Clock Cycle Time ( CL = 4 )
5.0
8.5
3
tRAC
Random Access Time
22.0
3
tCH
Clock High Time
0.45 × tCK
3
tCL
Clock Low Time
0.45 × tCK
3
tCKQS
QS Access Time from CLK
−0.65
0.65
3, 8
tQSQ
Data Output Skew from DQS
0.4
4
tAC
Data Access Time from CLK
−0.65
0.65
3, 8
tOH
Data Output Hold Time from CLK
−0.65
0.65
3, 8
tQSPRE
DQS (read) Preamble Pulse Width
0.9 × tCK − 0.2
1.1 × tCK + 0.2
3, 8
tHP
CLK half period (minimum of Actual tCH, tCL)
min(tCH, tCL)
3
tQSP
DQS (read) Pulse Width
tHP− tQHS
4, 8
tQSQV
Data Output Valid Time from DQS
tHP− tQHS
4, 8
tQHS
DQ Hold Skew factor
0.55
tDQSS
DQS (write) Low to High Setup Time
0.75 × tCK
1.25 × tCK
3
tDSPRE
DQS (write) Preamble Pulse Width
0.4 × tCK
4
tDSPRES
DQS First Input Setup Time
0
3
tDSPREH
DQS First Low Input Hold Time
0.25 × tCK
3
tDSP
DQS High or Low Input Pulse Width
0.45 × tCK
0.55 × tCK
4
tDSS
DQS Input Falling Edge to Clock Setup Time
1.3
3, 4
tDSPST
DQS (write) Postamble Pulse Width
0.45 × tCK
4
tDSPSTH
DQS (write) Postamble Hold Time
1.3
3, 4
ns
tDSSK
UDQS – LDQS Skew (×16)
−0. 5 × tCK
0. 5 × tCK
tDS
Data Input Setup Time from DQS
0.5
4
tDH
Data Input Hold Time from DQS
0.5
4
tIS
Command/Address Input Setup Time
0.9
3
tIH
Command/Address Input Hold Time
0.9
3
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TC59LM913AMB-50
AC CHARACTERISTICS AND OPERATING CONDITIONS (Notes: 1, 2) (continued)
SYMBOL
PARAMETER
MIN
MAX
UNIT
NOTES
tLZ
Data-out Low Impedance Time from CLK
−0.65
3,6,8
tHZ
Data-out High Impedance Time from CLK
0.65
3,7,8
tQSLZ
DQS-out Low Impedance Time from CLK
−0.65
3,6,8
tQSHZ
DQS-out High Impedance Time from CLK
−0.65
0.65
3,7,8
tQPDH
Last output to PD High Hold Time
0
tPDEX
Power Down Exit Time
0.9
tT
Input Transition Time
0.1
1
tFPDL
PD Low Input Window for Self-Refresh Entry
−0.5 × tCK
5
tREFI
Auto-Refresh Average Interval
0.4
3.9
tPAUSE
Pause Time after Power-up
200
IRC
Random Read/Write Cycle Time
(applicable to same bank)
5
IRCD
RDA/WRA to LAL Command Input Delay
(applicable to same bank)
1
1
IRAS
LAL to RDA/WRA Command Input Delay
(applicable to same bank)
4
IRBD
Random Bank Access Delay
(applicable to other bank)
2
LAL following RDA to WRA Delay
(applicable to other bank)
BL = 2
2
IRWD
BL = 4
3
1
5
IWRD
LAL following WRA to RDA Delay
(applicable to other bank)
Mode Register Set Cycle Time
IRSC
CL = 3
IPD
PD Low to Inactive State of Input Buffer
1
IPDA
PD High to Active State of Input Buffer
1
IPDV
Power down mode valid from REF command
18
IREFC
Auto-Refresh Cycle Time
18
ICKD
REF Command to Clock Input Disable at Self-Refresh Entry
16
ILOCK
DLL Lock-on Time (applicable to RDA command)
200
ns
3
3
5
µs
cycle
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TC59LM913AMB-50
AC TEST CONDITIONS
SYMBOL
PARAMETER
VALUE
UNIT
VIH (min)
Input High Voltage (minimum)
VREF + 0.35
V
VIL (max)
Input Low Voltage (maximum)
VREF − 0.35
V
VREF
Input Reference Voltage
VDDQ/2
V
VTT
Termination Voltage
VREF
V
VSWING
Input Signal Peak to Peak Swing
1.0
V
Vr
Differential Clock Input Reference Level
VX (AC)
V
VID (AC)
Input Differential Voltage
1.5
V
SLEW
Input Signal Minimum Slew Rate
1.0
V/ns
VOTR
Output Timing Measurement Reference Voltage
VDDQ/2
V
NOTES
9
VDDQ
VIH min (AC)
VTT
25 Ω
VREF
VSWING
Output
VIL max (AC)
Measurement point
VSS
∆T
∆T
AC Test Load
SLEW = (VIH min (AC) − VIL max (AC))/∆T
NOTES:
(1)
Transition times are measured between VIH min (DC) and VIL max (DC).
Transition (rise and fall) of input signals have a fixed slope.
(2)
If the result of nominal calculation with regard to tCK contains more than one decimal place, the result is
rounded up to the nearest decimal place.
(i.e., tDQSS = 0.75 × tCK, tCK = 5 ns, 0.75 × 5 ns = 3.75 ns is rounded up to 3.8 ns.)
(3)
These parameters are measured from the differential clock (CLK and CLK ) AC cross point.
(4)
These parameters are measured from signal transition point of DS crossing VREF level.
(5)
The tREFI (max) applies to equally distributed refresh method.
The tREFI (min) applies to both burst refresh method and distributed refresh method.
In such case, the average interval of eight consecutive Auto-Refresh commands has to be more than 400 ns
always. In other words, the number of Auto-Refresh cycles which can be performed within 3.2 µs (8 × 400 ns)
is to 8 times in the maximum.
(6)
Low Impedance State is specified at VDDQ/2 ± 0.2 V from steady state.
(7)
High Impedance State is specified where output buffer is no longer driven.
(8)
These parameters depend on the clock jitter. These parameters are measured at stable clock.
(9)
Output timing is measured by using Normal driver strength.
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TC59LM913AMB-50
POWER UP SEQUENCE
(1)
As for PD , being maintained by the low state (≤ 0.2 V) is desirable before a power-supply injection.
(2)
Apply VDD before or at the same time as VDDQ.
(3)
Apply VDDQ before or at the same time as VREF.
(4)
Start clock (CLK, CLK ) and maintain stable condition for 200 µs (min).
(5)
After stable power and clock, apply DESL and take PD =H.
(6)
Issue EMRS to enable DLL and to define driver strength. (Note: 1)
(7)
Issue MRS for set CAS latency (CL), Burst Type (BT), and Burst Length (BL). (Note: 1)
(8)
Issue two or more Auto-Refresh commands (Note: 1).
(9)
Ready for normal operation after 200 clocks from Extended Mode Register programming.
NOTES:
(1)
Sequence 6, 7 and 8 can be issued in random order.
(2)
L = Logic Low, H = Logic High
2.5V(TYP)
VDD
2.5V(TYP)
VDDQ
1.25V(TYP)
VREF
CLK
CLK
200us(min)
tPDEX
lRSC
lRSC
lREFC
lREFC
PD
lPDA
Command
200clock cycle(min)
DESL RDA MRS
DESL
op-code
RDA MRS
DESL WRA REF
DESL
WRA REF
DESL
op-code
Address
EMRS
MRS
DQ
Hi-Z
DQS
EMRS
MRS
Auto Refresh cycle
Normal Operation
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TC59LM913AMB-50
TIMING DIAGRAMS
Input Timing
Command and Address
tCK
tCK
tCH
tCL
CLK
CLK
tIS
tIH
tIS
1st
CS
tIS
2nd
tIH
tIS
1st
FN
tIS
A0~A13
BA0~BA2
tIH
tIH
2nd
tIH
tIS
UA, BA
tIH
LA
Data
DQS
tDS tDH
tDS tDH
DQ (input)
Refer to the Command Truth Table.
Timing of the CLK, CLK
tCH
tCL
VIH
VIH (AC)
VIL (AC)
VIL
CLK
CLK
tT
tCK
tT
VIH
CLK
VID (AC)
CLK
VX
VX
VX
VIL
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TC59LM913AMB-50
Read Timing (Burst Length = 4)
tCH
tCL
tCK
CLK
CLK
tIS tIH
LAL (after RDA)
Input
(control &
addresses)
DESL
tCKQS
tQSLZ
CAS latency = 4
DQS
(output)
tCKQS
tCKQS
tQSP tQSP
tQSPRE
tQSHZ
Hi-Z
Preamble
Postamble
tLZ
tQSQV
tQSQ
tQSQ tQSQ tQSQV
DQ
(output)
Hi-Z
Q0
tAC
Q1
Q2
tAC
tHZ
Q3
tAC
tOH
Note: DQ0 to DQ15 are aligned with DQS or LDQS/UDQS.
The correspondence of LDQS, UDQS to DQ. (TC59LM913AMB)
LDQS
DQ0∼DQ7
UDQS
DQ8∼DQ15
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TC59LM913AMB-50
Write Timing (Burst Length = 4)
tCH
tCL
tCK
CLK
CLK
tIS tIH LAL (after WRA)
Input
(control &
addresses)
DESL
tDSS
CAS latency = 4
tDSPSTH
tDSS
tDSPRES
tDSP
tDSP tDSP tDSPST
tDSPREH
DQS
(input)
Preamble
tDSPRE
Postamble
tDS
tDS
tDH
DQ
(input)
D0
tDQSS
tDS
tDH
D1
D2
tDH
D3
tDQSS
Note: DQ0 to DQ15 are sampled at both edges of DQS or LDQS / UDQS.
The correspondence of LDQS, UDQS to DQ. (TC59LM913AMB)
LDQS
DQ0∼DQ7
UDQS
DQ8∼DQ15
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TC59LM913AMB-50
tREFI, tPAUSE, Ixxxx Timing
CLK
CLK
tREFI, tPAUSE, IXXXX
tIS tIH
tIS tIH
Input
(control &
addresses)
Command
Command
Note: “IXXXX” means “IRC”, “IRCD”, “IRAS”, etc.
Rev 1.1
2005-08-19
15/46
TC59LM913AMB-50
Write Timing (x16 device) (Burst Length =4)
CLK
CLK
Input
(control &
addresses)
WRA
LAL
DESL
CAS latency = 4
tDSSK tDSSK tDSSK tDSSK
LDQS
Preamble
Postamble
tDS
tDS
tDH
tDH
DQ0~DQ7
tDS
D0
tDS
tDH
tDH
D1
D2
D3
UDQS
Preamble
Postamble
tDS
tDH
DQ8~DQ15
tDS
tDS
tDH
D0
D1
tDS
tDH
D2
tDH
D3
Rev 1.1
2005-08-19
16/46
TC59LM913AMB-50
FUNCTION TRUTH TABLE (Notes: 1, 2, 3)
Command Truth Table (Notes: 4)
• The First Command
SYMBOL
FUNCTION
CS
FN
BA2~BA0
A13~A9
A8
A7
A6~A0
DESL
Device Deselect
H
×
×
×
×
×
×
RDA
Read with Auto-close
L
H
BA
UA
UA
UA
UA
WRA
Write with Auto-close
L
L
BA
UA
UA
UA
UA
• The Second Command (The next clock of RDA or WRA command)
SYMBOL
FUNCTION
CS
FN
BA1
~BA0
BA2
A13
A12
~A11
A10
~A9
A8
A7
A6~A0
LAL
Lower Address Latch (x16)
H
×
×
V
V
V
×
×
LA
LA
REF
Auto-Refresh
L
×
×
×
×
×
×
×
×
×
MRS
Mode Register Set
L
×
V
L
L
L
L
L
V
V
Notes: 1. L = Logic Low, H = Logic High, × = either L or H, V = Valid (specified value), BA = Bank Address, UA = Upper Address,
LA = Lower Address
2. All commands are assumed to issue at a valid state.
3. All inputs for command (excluding SELFX and PDEX) are latched on the crossing point of differential clock input where
CLK goes to High.
4. Operation mode is decided by the combination of 1st command and 2nd command. Refer to “STATE DIAGRAM” and
the command table below.
Read Command Table
COMMAND (SYMBOL)
CS
FN
BA2~BA0
A13~A9
A8
A7
A6~A0
RDA (1st)
L
H
BA
UA
UA
UA
UA
LAL (2nd)
H
×
×
×
LA
LA
LA
NOTES
5
Note 5 : For x16 device, A8 is “X” (either L or H).
Write Command Table
• TC59LM913AMB
COMMAND(SYMBOL)
CS
FN
BA1~
BA0
BA2
A13
A12
A11
A10~
A9
A8
A7
A6~A0
WRA (1st)
L
L
BA
UA
UA
UA
UA
UA
UA
UA
UA
LAL (2nd)
H
×
×
LVW0
LVW1
UVW0
UVW1
×
×
LA
LA
Notes: 6. BA2, A13 ~ A11 are used for Variable Write Length (VW) control at Write Operation.
Rev 1.1
2005-08-19
17/46
TC59LM913AMB-50
FUNCTION TRUTH TABLE (continued)
VW Truth Table
Burst Length
Function
VW0
VW1
Write All Words
L
×
Write First One Word
H
×
Reserved
L
L
Write All Words
H
L
Write First Two Words
L
H
Write First One Word
H
H
BL=2
BL=4
Note 7 : LVW0 and LVW1 control DQ0~DQ7.
UVW0 and UVW1 control DQ8~DQ15.
Mode Register Set Command Table
COMMAND (SYMBOL)
CS
FN
BA2~BA0
A13~A9
A8
A7
A6~A0
RDA (1st)
L
H
×
×
×
×
×
MRS (2nd)
L
×
V
V
V
V
V
CS
FN
BA2~BA0
A13~A9
A8
A7
NOTES
8
Notes: 8. Refer to “MODE REGISTER TABLE”.
Auto-Refresh Command Table
COMMAND
(SYMBOL)
CURRENT
STATE
Active
WRA (1st)
Auto-Refresh
REF (2nd)
FUNCTION
PD
A6~A0 NOTES
n−1
n
Standby
H
H
L
L
×
×
×
×
×
Active
H
H
L
×
×
×
×
×
×
CS
FN
BA2~BA0
A13~A9
A8
A7
Self-Refresh Command Table
COMMAND
(SYMBOL)
CURRENT
STATE
Active
WRA (1st)
Self-Refresh Entry
FUNCTION
Self-Refresh Continue
Self-Refresh Exit
PD
A6~A0 NOTES
n−1
n
Standby
H
H
L
L
×
×
×
×
×
REF (2nd)
Active
H
L
L
×
×
×
×
×
×
Self-Refresh
L
L
×
×
×
×
×
×
×
SELFX
Self-Refresh
L
H
H
×
×
×
×
×
×
COMMAND
(SYMBOL)
CURRENT
STATE
CS
FN
BA2~BA0
A13~A9
A8
A7
PDEN
9, 10
11
Power Down Table
FUNCTION
Power Down Entry
Power Down Continue
Power Down Exit
PD
A6~A0 NOTES
n−1
n
Standby
H
L
H
×
×
×
×
×
×
Power Down
L
L
×
×
×
×
×
×
×
PDEX
Power Down
L
H
H
×
×
×
×
×
×
10
11
Notes: 9. PD has to be brought to Low within tFPDL from REF command.
10. PD should be brought to Low after DQ’s state turned high impedance.
11. When PD is brought to High from Low, this function is executed asynchronously.
Rev 1.1
2005-08-19
18/46
TC59LM913AMB-50
FUNCTION TRUTH TABLE (continued)
CURRENT STATE
PD
n−1 n
CS
FN
ADDRESS
COMMAND
ACTION
NOTES
Idle
H
H
H
H
H
L
H
H
H
L
L
×
H
L
L
H
L
×
×
H
L
×
×
×
×
BA, UA
BA, UA
×
×
×
DESL
RDA
WRA
PDEN
Row Active for Read
H
H
H
H
L
H
H
L
L
×
H
L
H
L
×
×
×
×
×
×
LA
Op-code
×
×
×
LAL
MRS/EMRS
PDEN
MRS/EMRS
Row Active for Write
H
H
H
H
L
H
H
L
L
×
H
L
H
L
×
×
×
×
×
×
LA
×
×
×
×
LAL
REF
PDEN
REF (self)
Read
H
H
H
H
H
L
H
H
H
L
L
×
H
L
L
H
L
×
×
H
L
×
×
×
×
BA, UA
BA, UA
×
×
×
DESL
RDA
WRA
PDEN
H
H
H
×
×
DESL
H
H
H
H
L
H
H
L
L
×
L
L
H
L
×
H
L
×
×
×
BA, UA
BA, UA
×
×
×
RDA
WRA
PDEN
Data Write & Continue Burst Write to
End
Illegal
Illegal
Illegal
Illegal
Invalid
Auto-Refreshing
H
H
H
H
H
L
H
H
H
L
L
×
H
L
L
H
L
×
×
H
L
×
×
×
×
BA, UA
BA, UA
×
×
×
DESL
RDA
WRA
PDEN
NOP → Idle after IREFC
Illegal
Illegal
Self-Refresh Entry
Illegal
Refer to Self-Refreshing State
Mode Register
Accessing
H
H
H
H
H
L
H
H
H
L
L
×
H
L
L
H
L
×
×
H
L
×
×
×
×
BA, UA
BA, UA
×
×
×
DESL
RDA
WRA
PDEN
NOP → Idle after IRSC
Illegal
Illegal
Illegal
Illegal
Invalid
H
L
×
L
×
×
×
×
×
×
L
H
H
×
×
PDEX
L
H
L
×
×
Invalid
Maintain Power Down Mode
Exit Power Down Mode → Idle after
tPDEX
Illegal
H
L
L
L
×
L
H
H
×
×
H
L
×
×
×
×
×
×
×
×
SELFX
Invalid
Maintain Self-Refresh
Exit Self-Refresh → Idle after IREFC
Illegal
Write
Power Down
Self-Refreshing
NOP
Row activate for Read
Row activate for Write
Power Down Entry
Illegal
Refer to Power Down State
12
Begin Read
Access to Mode Register
Illegal
Illegal
Invalid
Begin Write
Auto-Refresh
Illegal
Self-Refresh Entry
Invalid
Continue Burst Read to End
Illegal
Illegal
Illegal
Illegal
Invalid
13
13
13
13
14
Notes: 12. Illegal if any bank is not idle.
13. Illegal to bank in specified states; Function may be legal in the bank inidicated by Bank Address (BA).
14. Illegal if tFPDL is not satisfied.
Rev 1.1
2005-08-19
19/46
TC59LM913AMB-50
MODE REGISTER TABLE
Regular Mode Register (Notes: 1)
*1
ADDRESS
*1
BA1
BA0
0
0
Register
0
A7
*3
A6~A4
A3
A2~A0
CL
BT
BL
TE
A7
TEST MODE (TE)
A3
BURST TYPE (BT)
0
Regular (default)
0
Sequential
1
Test Mode Entry
1
Interleave
A6
A5
A4
0
0
×
Reserved
0
1
0
Reserved
0
1
1
Reserved
1
0
0
1
BA2, A13~A8
0
CAS LATENCY (CL)
*2
*2
*2
4
1
Reserved
1
1
0
Reserved
1
1
1
Reserved
*2
A2
A1
A0
0
0
0
0
0
1
2
0
1
0
4
0
1
1
×
1
BURST LENGTH (BL)
Reserved
Reserved
×
*2
*2
*2
*2
Extended Mode Register (Notes: 4)
ADDRESS
Register
*4
*4
BA1
BA0
0
1
BA2,
A13~A12
A11
A10~A7
A6
A5~A2
A1
0
0
0
DIC
0
DIC
A6
A1
OUTPUT DRIVE IMPEDANCE CONTROL (DIC)
0
0
Normal Output Driver
0
1
Strong Output Driver
1
0
Weaker Output Driver
1
1
Weakest Output Driver
A0
*5
DS
A0
DLL SWITCH (DS)
0
DLL Enable
1
DLL Disable
Notes: 1. Regular Mode Register is chosen using the combination of BA0 = 0 and BA1 = 0.
2. “Reserved” places in Regular Mode Register should not be set.
3. A7 in Regular Mode Register must be set to “0” (low state).
Because Test Mode is specific mode for supplier.
4. Extended Mode Register is chosen using the combination of BA0 = 1 and BA1 = 0.
5. A0 in Extended Mode Register must be set to "0" to enable DLL for normal operation.
Rev 1.1
2005-08-19
20/46
TC59LM913AMB-50
STATE DIAGRAM
SELFREFRESH
POWER
DOWN
SELFX
( PD = H)
PDEX
( PD = H)
PD = L
PDEN
( PD = L)
STANDBY
(IDLE)
PD = H
AUTOREFRESH
MODE
REGISTER
WRA
RDA
REF
MRS
ACTIVE
(RESTORE)
ACTIVE
LAL
LAL
WRITE
(BUFFER)
READ
Command input
Automatic return
The second command at Active state
must be issued 1 clock after RDA or
WRA command input.
Rev 1.1
2005-08-19
21/46
TC59LM913AMB-50
TIMING DIAGRAMS
SINGLE BANK READ TIMING (CL = 4)
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
CLK
CLK
IRC = 5 cycles
IRC = 5 cycles
Command
RDA
LAL
IRCD=1 cycle
Address
UA
Bank Add.
#0
DESL
IRAS = 4 cycles
LA
RDA
LAL
IRCD=1
UA
DESL
IRAS = 4 cycles
LA
IRC = 5 cycles
RDA
IRCD=1 cycle
UA
#0
LAL
DESL
RDA
IRAS = 4 cycles
LA
UA
#0
#0
BL = 2
DQS
(output)
Hi-Z
CL = 4
DQ
(output)
Hi-Z
CL = 4
Q0 Q1
CL = 4
Q0 Q1
Q0
BL = 4
DQS
(output)
Hi-Z
CL = 4
DQ
(output)
Hi-Z
CL = 4
Q0 Q1 Q2 Q3
CL = 4
Q0 Q1 Q2 Q3
Q0
Rev 1.1
2005-08-19
22/46
TC59LM913AMB-50
SINGLE BANK WRITE TIMING (CL = 4)
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
CLK
CLK
IRC = 5 cycles
IRC = 5 cycles
WRA
LAL
Address
UA
LA
Bank Add.
#0
Command
DESL
WRA
LAL
UA
LA
DESL
IRC = 5 cycles
WRA
LAL
UA
LA
#0
DESL
WRA
UA
#0
#0
BL = 2
DQS
(input)
WL = 3
DQ
(input)
WL = 3
WL = 3
D0 D1
D0 D1
D0 D1
BL = 4
DQS
(input)
WL = 3
DQ
(input)
WL = 3
WL = 3
D0 D1 D2 D3
D0 D1 D2 D3
D0 D1 D2 D3
Rev 1.1
2005-08-19
23/46
TC59LM913AMB-50
SINGLE BANK READ-WRITE TIMING (CL = 4)
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
CLK
CLK
IRC = 5 cycles
RDA
LAL
Address
UA
LA
Bank Add.
#0
Command
DESL
IRC = 5 cycles
WRA
LAL
UA
LA
DESL
IRC = 5 cycles
RDA
LAL
UA
LA
#0
DESL
WRA
UA
#0
#0
BL = 2
DQS
Hi-Z
CL = 4
DQ
WL = 3
CL = 4
Hi-Z
Q0 Q1
D0 D1
Q0
BL = 4
DQS
Hi-Z
CL = 4
DQ
Hi-Z
WL = 3
Q0 Q1 Q2 Q3
CL = 4
D0 D1 D2 D3
Q0
Rev 1.1
2005-08-19
24/46
TC59LM913AMB-50
MULTIPLE BANK READ TIMING (CL = 4)
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
CLK
CLK
IRBD = 2 cycles
Command
Address
Bank Add.
IRBD = 2 cycles IRBD = 2 cyclesIRBD = 2 cycles IRBD = 2 cycles
RDA
LAL
RDA
LAL
UA
LA
UA
LA
Bank
"a"
DESL RDA
Bank
"b"
UA
LAL
RDA
LAL
RDA
LAL
RDA
LAL
RDA
LAL
RDA
LA
UA
LA
UA
LA
UA
LA
UA
LA
UA
Bank
"a"
Bank
"b"
Bank
"c"
Bank
"d"
Bank
"b"
Bank
"a"
IRC (Bank"a") = 5 cycles
IRC (Bank"b") = 5 cycles
BL = 2
DQS
(output)
Hi-Z
CL = 4
CL = 4
DQ
(output)
Hi-Z
Qa0Qa1
Qb0Qb1
Qa0Qa1
Qb0Qb1
Qc0Qc1
BL = 4
DQS
(output)
Hi-Z
CL = 4
CL = 4
DQ
(output)
Hi-Z
Qa0Qa1Qa2Qa3Qb0Qb1Qb2Qb3
Qa0Qa1Qa2Qa3Qb0Qb1Qb2Qb3Qc0Qc1Qc2
Note: lRC to the same bank must be satisfied.
Rev 1.1
2005-08-19
25/46
TC59LM913AMB-50
MULTIPLE BANK WRITE TIMING (CL = 4)
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
CLK
CLK
IRBD = 2 cycles
Command
Address
Bank Add.
IRBD = 2 cycles IRBD = 2 cycles IRBD = 2 cycles IRBD = 2 cycles
WRA
LAL
WRA
LAL
UA
LA
UA
LA
Bank
"a"
DESL WRA
UA
Bank
"b"
LAL
WRA
LAL
WRA
LAL
WRA
LAL
WRA
LAL
WRA
LA
UA
LA
UA
LA
UA
LA
UA
LA
UA
Bank
"a"
Bank
"b"
Bank
"c"
Bank
"d"
Bank
"a"
Bank
"b"
IRC (Bank"a") = 5 cycles
IRC (Bank"b") = 5 cycles
BL = 2
DQS
(input)
WL = 3
WL = 3
DQ
(input)
Da0 Da1
Db0Db1
Da0Da1
Db0Db1
Dc0 Dc1
Dd0Dd1
BL = 4
DQS
(input)
WL = 3
WL = 3
DQ
(input)
Da0 Da1 Da2Da3Db0Db1Db2Db3
Da0Da1Da2Da3Db0Db1 Db2 Db3 Dc0 Dc1 Dc2 Dc3 Dd0Dd1
Note: lRC to the same bank must be satisfied.
Rev 1.1
2005-08-19
26/46
TC59LM913AMB-50
MULTIPLE BANK READ-WRITE TIMING (BL = 2)
0
1
2
3
4
5
6
7
8
LAL
RDA
LAL
9
10
11
12
13
14
15
LAL
RDA
LAL DESL WRA
LA
UA
LA
CLK
CLK
IRBD = 2 cycles
Command
WRA
LAL
RDA
IWRD = 1 cycle
Address
Bank Add.
UA
Bank
"a"
LA
UA
Bank
"b"
LAL
DESL WRA
IRWD = 2 cycles IWRD = 1 cycle
LA
UA
Bank
"c"
LA
UA
DESL WRA
IRWD = 2 cycles
LA
Bank
"d"
UA
Bank
"a"
UA
Bank
"b"
Bank
"c"
IRC (Bank"a")
IRC (Bank"b")
CL = 4
DQS
Hi-Z
CL = 4
WL = 3
DQ
Hi-Z
Da0 Da1
Qb0 Qb1
Dc0 Dc1
Qd0 Qd1
Da0 Da1
Note: lRC to the same bank must be satisfied.
Rev 1.1
2005-08-19
27/46
TC59LM913AMB-50
MULTIPLE BANK READ-WRITE TIMING (BL = 4)
0
1
2
3
4
5
6
7
8
9
WRA
LAL
RDA
LAL
10
11
12
13
14
15
WRA
LAL
RDA
LAL
CLK
CLK
Command
IRBD = 2 cycles
WRA
LAL
RDA
LAL
IWRD = 1 cycle
Address
Bank Add.
UA
Bank
"a"
LA
UA
DESL
IRWD = 3 cycles
IWRD = 1 cycle
LA
UA
Bank
"b"
LA
Bank
"c"
UA
DESL
IRWD = 3 cycles
IWRD = 1 cycle
LA
Bank
"d"
UA
Bank
"a"
LA
UA
LA
Bank
"b"
IRC (Bank"a")
IRC (Bank"b")
CL = 4
DQS
Hi-Z
CL = 4
WL = 3
DQ
Hi-Z
Da0 Da1 Da2 Da3
Qb0 Qb1 Qb2 Qb3
Dc0 Dc1 Dc2 Dc3
Qd0 Qd1 Qd2 Qd3
Note: lRC to the same bank must be satisfied.
Rev 1.1
2005-08-19
28/46
TC59LM913AMB-50
WRITE with VARIAVLE WRITE LENGTH (VW) CONTROL (CL = 4)
0
1
2
3
4
5
6
WRA
LAL
UA
LA=#1
VW=1
7
8
9
10
11
12
13
14
15
CLK
CLK
BL = 2, SEQUENTIAL MODE
Command
Address
WRA
LAL
UA
LA=#3
VW=All
DESL
VW0 = Low
VW1 = don't care
Bank Add.
Bank
"a"
DESL
VW0 = High
VW1 = don't care
Bank
"a"
DQS
(input)
DQ
(input)
Lower Address
D0 D1
D0
#3 #2
#1 (#0)
Last one data is masked.
BL = 4, SEQUENTIAL MODE
Command
Address
WRA
LAL
UA
LA=#3
VW=All
DESL
WRA
LAL
UA
LA=#1
VW=1
VW0 = High
VW1 = Low
Bank Add.
Bank
"a"
DESL
WRA
LAL
UA
LA=#2
VW=2
VW0 = High
VW1 = High
DESL
VW0 = Low
VW1 = High
Bank
"a"
Bank
"a"
DQS
(input)
DQ
(input)
Lower Address
D0 D1 D2 D3
D0
D0 D1
#3 #0 #1 #2
#1(#2)(#3)(#0)
#2 #3 (#0)(#1)
Last three data are masked.
Last two data are masked.
Note: DQS input must be continued till end of burst count even if some of laster data is masked.
Rev 1.1
2005-08-19
29/46
TC59LM913AMB-50
POWER DOWN TIMING (CL = 4, BL = 4)
Read cycle to Power Down Mode
0
1
2
3
4
5
6
7
8
9
10
n-2
n-1
n
n+1
n+2
CLK
CLK
IPDA
Command
Address
RDA
LAL
UA
LA
DESL
RDA
or
WRA
DESL
UA
tIS
IPD = 1 cycle
tIH
PD
tQPDH
tPDEX
lRC(min) , tREFI(max)
DQS
(output)
Hi-Z
CL = 4
DQ
(output)
Hi-Z
Hi-Z
Q0 Q1 Q2 Q3
Power Down Entry
Power Down Exit
Note: PD must be kept "High" level until end of Burst data output.
PD should be brought to "High" within tREFI(max.) to maintain the data written into cell.
In Power Down Mode, PD "Low" and a stable clock signal must be maintained.
When PD is brought to "High", a valid executable command may be applied lPDA cycles later.
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TC59LM913AMB-50
POWER DOWN TIMING (CL = 4, BL = 4)
Write cycle to Power Down Mode
0
1
2
3
4
5
6
7
8
9
10
n-2
n-1
n
n+1
n+2
CLK
CLK
IPDA
Command
Address
WRA
LAL
UA
LA
DESL
RDA
or
WRA
DESL
UA
tIS
IPD = 1 cycle
tIH
PD
WL = 3
2 clock cycles
tPDEX
lRC(min) , tREFI(max)
DQS
(input)
WL = 3
DQ
(input)
D0 D1 D2 D3
Note: PD must be kept "High" level until WL+2 clock cycles from LAL command.
PD should be brought to "High" within tREFI(max.) to maintain the data written into cell.
In Power Down Mode, PD "Low" and a stable clock signal must be maintained.
When PD is brought to "High", a valid executable command may be applied lPDA cycles later.
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TC59LM913AMB-50
MODE REGISTER SET TIMING (CL = 4, BL = 2)
From Read operation to Mode Register Set operation.
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
RDA
or
WRA
LAL
Valid
(opcode)
UA
LA
BA0="0"
BA1="0"
BA2="0"
BA
CLK
CLK
IRSC
RDA
LAL
A13~A0
UA
LA
BA0~BA2
BA
Command
DESL
RDA
MRS
DESL
CL + BL/2
DQS
(output)
DQ
(output)
Hi-Z
Q0 Q1
Note: Minimum delay from LAL following RDA to RDA of MRS operation is CL+BL/2.
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TC59LM913AMB-50
MODE REGISTER SET TIMING (CL = 4, BL = 4)
From Write operation to Mode Register Set operation.
0
1
2
3
4
5
6
14
15
RDA
or
WRA
LAL
Valid
(opcode)
UA
LA
BA0="0"
BA1="0"
BA2="0"
BA
7
8
9
10
11
12
13
CLK
CLK
IRSC
Command
WRA
LAL
A13~A0
UA
LA
BA0~BA2
BA
DESL
RDA
MRS
DESL
WL+BL/2
DQS
(input)
DQ
(input)
D0 D1 D2 D3
Note: Minimum delay from LAL following WRA to RDA of MRS operation is WL+BL/2.
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TC59LM913AMB-50
EXTENDED MODE REGISTER SET TIMING (CL = 4, BL = 2)
From Read operation to Extended Mode Register Set operation.
0
1
2
3
4
5
6
14
15
RDA
or
WRA
LAL
Valid
(opcode)
UA
LA
BA0="1"
BA1="0"
BA2="0"
BA
7
8
9
10
11
12
13
CLK
CLK
IRSC
RDA
LAL
A13~A0
UA
LA
BA0~BA2
BA
Command
DESL
RDA
MRS
DESL
CL + BL/2
DQS
(output)
Hi-Z
DQ
(output)
Q0 Q1
Note:
Minimum delay from LAL following RDA to RDA of EMRS operation is CL+BL/2.
DLL switch in Extended Mode Register must be set to enable mode for normal operation.
DLL lock-on time is needed after initial EMRS operation. See Power Up Sequence.
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TC59LM913AMB-50
EXTENDED MODE REGISTER SET TIMING (CL = 4, BL = 4)
From Write operation to Extended Mode Register Set operation.
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
RDA
or
WRA
LAL
Valid
(opcode)
UA
LA
BA0="1"
BA1="0"
BA2="0"
BA
CLK
CLK
IRSC
WRA
LAL
A13~A0
UA
LA
BA0~BA2
BA
Command
DESL
RDA
MRS
DESL
WL+BL/2
DQS
(input)
DQ
(input)
D0 D1 D2 D3
Note:
DLL switch in Extended Mode Register must be set to enable mode for normal operation.
DLL lock-on time is needed after initial EMRS operation. See Power Up Sequence.
Minimum delay from LAL following WRA to RDA of EMRS operation is WL+BL/2.
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TC59LM913AMB-50
AUTO-REFRESH TIMING (CL = 4, BL = 4)
0
1
2
3
4
5
6
7
n−1
n
n+1
n+2
RDA
or
WRA
LAL or
MRS or
REF
CLK
CLK
IRC = 5 cycles
Command
RDA
LAL
Bank, Address
Bank,
UA
LA
IRCD=1 cycle
DQS
(output)
Hi-Z
DQ
(output)
Hi-Z
IREFC = 18 cycles
DESL
WRA
IRAS = 4 cycles
REF
DESL
IRCD=1 cycle
Hi-Z
CL = 4
Hi-Z
Q0 Q1 Q2 Q3
Note: In case of CL = 4, IREFC must be meet 18 clock cycles.
When the Auto-Refresh operation is performed, the synthetic average interval of Auto-Refresh command
specified by tREFI must be satisfied.
tREFI is average interval time in 8 Refresh cycles that is sampled randomly.
t1
t2
t3
t7
t8
CLK
WRA REF
WRA REF
WRA REF
WRA REF
WRA REF
8 Refresh cycle
tREFI =
Total time of 8 Refresh cycle
8
=
t1 + t2 + t3 + t4 + t5 + t6 + t7 + t8
8
tREFI is specified to avoid partly concentrated current of Refresh operation that is activated larger area
than Read / Write operation.
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TC59LM913AMB-50
SELF-REFRESH ENTRY TIMING
0
1
2
3
4
m−1
5
m+1
m
CLK
CLK
Command
IRCD = 1 cycle
WRA
IREFC
REF
DESL
tFPDL (min) tFPDL (max)
PD
Self Refresh Entry
tQPDH
IPDV *2
ICKD
Hi-Z
DQS
(output)
DQ
(output)
Auto Refresh
Hi-Z
Qx
Notes: 1.
2.
3.
4.
is don’t care.
PD must be brought to "Low" within the timing between tFPDL(min) and tFPDL(max) to Self
Refresh mode. When PD is brought to "Low" after lPDV, TC59LM913AMB perform Auto Refresh
and enter Power down mode. In case of PD fall between tFPDL(max) and lPDV, TC59LM913AMB
will either entry Self-Refresh mode or Power down mode after Auto-Refresh operation. It can’t be
specified which mode TC59LM913AMB operates.
It is desirable that clock input is continued at least lCKD from REF command even though PD is
brought to “Low” for Self-Refresh Entry.
In case of Self-Refresh entry after Write Operation, the delay time from the LAL command
following WRA to the REF command is Write latency (WL)+3 clock cycles minimum.
SELF-REFRESH EXIT TIMING
0
1
2
m−1
m+1
m
m+2
n−1
n
n+1
p−1
p
CLK
CLK
*2
IREFC
*3
DESL
Command
IREFC
WRA
*4
REF
*4
Command (1st)*5
Command (2nd)*5
DESL
IRCD = 1 cycle
RDA
*6
LAL
*6
IRCD = 1 cycle
PD
tPDEX
ILOCK
DQS
(output)
Hi-Z
DQ
(output)
Hi-Z
Self-Refresh Exit
Notes: 1.
is don’t care.
2. Clock should be stable prior to PD = “High” if clock input is suspended in Self-Refresh mode.
3. DESL command must be asserted during IREFC after PD is brought to “High”.
4. It is desirable that one Auto-Refresh command is issued just after Self-Refresh Exit before any
other operation.
5. Any command (except Read command) can be issued after IREFC.
6. Read command (RDA + LAL) can be issued after ILOCK.
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TC59LM913AMB-50
FUNCTIONAL DESCRIPTION
TM
Network FCRAM
FCRAMTM is an acronym of Fast Cycle Random Access Memory. The Network FCRAMTM
perform fast random core access, low latency and high-speed data transfer.
is competent to
PIN FUNCTIONS
CLOCK INPUTS: CLK & CLK
The CLK and CLK inputs are used as the reference for synchronous operation. CLK is master clock input.
The CS , FN and all address input signals are sampled on the crossing of the positive edge of CLK and the
negative edge of CLK . The DQS and DQ output are aligned to the crossing point of CLK and CLK . The timing
reference point for the differential clock is when the CLK and CLK signals cross during a transition.
POWER DOWN: PD
The PD input controls the entry to the Power Down or Self-Refresh modes. The PD input does not have a
Clock Suspend function like a CKE input of a standard SDRAMs, therefore it is illegal to bring PD pin into
low state if any Read or Write operation is being performed.
CHIP SELECT & FUNCTION CONTROL: CS & FN
The CS and FN inputs are a control signal for forming the operation commands on FCRAMTM. Each
operation mode is decided by the combination of the two consecutive operation commands using the CS and
FN inputs.
BANK ADDRESSES: BA0~BA2
The BA0 to BA2 inputs are latched at the time of assertion of the RDA or WRA command and are selected the
bank to be used for the operation. BA0 and BA1 also define which mode register is loaded during the Mode
Register Set command (MRS or EMRS).
BA0
BA1
BA2
Bank #0
0
0
0
Bank #1
1
0
0
Bank #2
0
1
0
Bank #3
1
1
0
Bank #4
0
0
1
Bank #5
1
0
1
Bank #6
0
1
1
Bank #7
1
1
1
Also, when BA2 input assign to A14 input, TC59LM913AMB can function as 4bank devices and can keep
backward compatibility to 256Mb(4bank) Network FCRAM.
ADDRESS INPUTS: A0~A13
Address inputs are used to access the arbitrary address of the memory cell array within each bank. The
Upper Addresses with Bank addresses are latched at the RDA or WRA command and the Lower Addresses are
latched at the LAL command. The A0 to A13 inputs are also used for setting the data in the Regular or
Extended Mode Register set cycle.
I/O Organization
UPPER ADDRESS
LOWER ADDRESS
8 bank operation
16 bits
A0~A13
A0~A7
4 bank operation
16 bits
A0~A13, BA2(A14)
A0~A7
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TC59LM913AMB-50
DATA INPUT/OUTPUT: DQ0~DQ7 or DQ15
The input data of DQ0 to DQ15 are taken in synchronizing with the both edges of DQS input signal. The
output data of DQ0 to DQ15 are outputted synchronizing with the both edges of DQS signal.
DATA STROBE: DQS, LDQS / UDQS
The DQS is bi-directional signal. Both edges of DQS are used as the reference of data input or output. In write
operation, the DQS used as an input signal is utilized for a latch of write data. In read operation, the DQS is an
output signal provides the read data strobe.
POWER SUPPLY: VDD, VDDQ, VSS, VSSQ
VDD and VSS are power supply pins for memory core and peripheral circuits.
VDDQ and VSSQ are power supply pins for the output buffer.
REFERENCE VOLTAGE: VREF
VREF is reference voltage for all input signals.
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TC59LM913AMB-50
COMMAND FUNCTIONS and OPERATIONS
TC59LM913AMB are introduced the two consecutive command input method. Therefore, except for Power Down
mode, each operation mode decided by the combination of the first command and the second command from
stand-by states of the bank to be accessed.
Read Operation (1st command + 2nd command = RDA + LAL)
Issuing the RDA command with Bank Addresses and Upper Addresses to the idle bank puts the bank
designated by Bank Address in a read mode. When the LAL command with Lower Addresses is issued at the
next clock of the RDA command, the data is read out sequentially synchronizing with the both edges of DQS
output signal (Burst Read Operation). The initial valid read data appears after CAS latency from the issuing
of the LAL command. The valid data is outputted for a burst length. The CAS latency, the burst length of read
data and the burst type must be set in the Mode Register beforehand. The read operated bank goes back
automatically to the idle state after lRC.
Write Operation (1st command + 2nd command = WRA + LAL)
Issuing the WRA command with Bank Addresses and Upper Addresses to the idle bank puts the bank
designated by Bank Address in a write mode. When the LAL command with Lower Addresses is issued at the
next clock of the WRA command, the input data is latched sequentially synchronizing with the both edges of
DQS input signal (Burst Write Operation). The data and DQS inputs have to be asserted in keeping with clock
input after CAS latency-1 from the issuing of the LAL command. The DQS has to be provided for a burst
length. The CAS latency and the burst type must be set in the Mode Register beforehand. The write operated
bank goes back automatically to the idle state after lRC. Write Burst Length is controlled by VW0 and VW1
inputs with LAL command. See VW truth table.
Auto-Refresh Operation (1st command + 2nd command = WRA + REF)
TC59LM913AMB are required to refresh like a standard SDRAM. The Auto-Refresh operation is begun with
the REF command following to the WRA command. The Auto-Refresh mode can be effective only when all banks
are in the idle state. In a point to notice, the write mode started with the WRA command is canceled by the REF
command having gone into the next clock of the WRA command instead of the LAL command. The minimum
period between the Auto-Refresh command and the next command is specified by lREFC. However, about a
synthetic average interval of Auto-Refresh command, it must be careful. In case of equally distributed refresh,
Auto-Refresh command has to be issued within once for every 3.9 µs by the maximum. In case of burst refresh
or random distributed refresh, the average interval of eight consecutive Auto-Refresh commands has to be more
than 400 ns always. In other words, the number of Auto-Refresh cycles that can be performed within 3.2 µs (8 ×
400 ns) is to 8 times in the maximum.
Self-Refresh Operation (1st command + 2nd command = WRA + REF with PD = “L”)
In case of Self-Refresh operation, refresh operation can be performed automatically by using an internal timer.
When all banks are in the idle state and all outputs are in Hi-Z states, the TC59LM913AMB become
Self-Refresh mode by issuing the Self-Refresh command. PD has to be brought to “Low” within tFPDL from the
REF command following to the WRA command for a Self-Refresh mode entry. In order to satisfy the refresh
period, the Self-Refresh entry command should be asserted within 3.9 µs after the latest Auto-Refresh command.
Once the device enters Self-Refresh mode, the DESL command must be continued for lREFC period. In addition,
it is desirable that clock input is kept in lCKD period. The device is in Self-Refresh mode as long as PD held
“Low”. During Self-Refresh mode, all input and output buffers are disabled except for PD , therefore the power
dissipation lowers. Regarding a Self-Refresh mode exit, PD has to be changed over from “Low” to “High” along
with the DESL command, and the DESL command has to be continuously issued in the number of clocks
specified by lREFC. The Self-Refresh exit function is asynchronous operation. It is required that one
Auto-Refresh command is issued to avoid the violation of the refresh period just after lREFC from Self-Refresh
exit.
Power Down Mode ( PD = “L”)
When all banks are in the idle state and DQ outputs are in Hi-Z states, the TC59LM913AMB become Power
Down Mode by asserting PD is “Low”. When the device enters the Power Down Mode, all input and output
buffers are disabled after specified time except for PD . Therefore, the power dissipation lowers. To exit the
Power Down Mode, PD has to be brought to “High” and the DESL command has to be issued for two clocks
cycle after PD goes high. The Power Down exit function is asynchronous operation.
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TC59LM913AMB-50
Mode Register Set (MRS) and Extended Mode Register Set (EMRS)
(1st command + 2nd command = RDA + MRS)
When all banks are in the idle state, issuing the MRS command following to the RDA command can program
the Mode Register. In a point to notice, the read mode started with the RDA command is canceled by the MRS
command having gone into the next clock of the RDA command instead of the LAL command. The data to be set
in the Mode Register is transferred using A0 to A14, BA0 to BA1 address inputs. The TC59LM913AMB have
two mode registers. These are Regular and Extended Mode Register. The Regular or Extended Mode Register is
chosen by BA0 and BA1 in the MRS command. The Regular Mode Register designates the operation mode for a
read or write cycle. The Regular Mode Register has four function fields.
The four fields are as follows:
(R-1) Burst Length field to set the length of burst data
(R-2) Burst Type field to designate the lower address access sequence in a burst cycle
(R-3) CAS Latency field to set the access time in clock cycle
(R-4) Test Mode field to use for supplier only.
The Extended Mode Register has three function fields.
The three fields are as follows:
(E-1) DLL Switch field to choose either DLL enable or DLL disable
(E-2) Output Driver Impedance Control field.
(E-3) DQS enable field.
Once those fields in the Mode Register are set up, the register contents are maintained until the Mode
Register is set up again by another MRS command or power supply is lost. The initial value of the Regular or
Extended Mode Register after power-up is undefined, therefore the Mode Register Set command must be issued
before proper operation.
•
Regular Mode Register/Extended Mode Register change bits (BA0, BA1).
These bits are used to choose either Regular MRS or Extended MRS
BA1
BA0
Mode Register Set
0
0
Regular MRS
0
1
Extended MRS
1
×
Reserved
Regular Mode Register Fields
(R-1) Burst Length field (A2 to A0)
This field specifies the data length for column access using the A2 to A0 pins and sets the Burst
Length to be 2 or 4 words.
A2
A1
A0
BURST LENGTH
0
0
0
Reserved
0
0
1
2 words
0
1
0
4 words
0
1
1
Reserved
1
×
×
Reserved
(R-2) Burst Type field (A3)
The Burst Type can be chosen Interleave mode or Sequential mode. When the A3 bit is “0”,
Sequential mode is selected. When the A3 bit is “1”, Interleave mode is selected. Both burst types
support burst length of 2 and 4 words.
A3
BURST TYPE
0
Sequential
1
Interleave
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TC59LM913AMB-50
•
Addressing sequence of Sequential mode (A3)
A column access is started from the inputted lower address and is performed by incrementing the lower
address input to the device.
CAS Latency = 4
CLK
CLK
Command
RDA
LAL
DQS
Data Data Data Data
0
1
2
3
DQ
Addressing sequence for Sequential mode
•
DATA
ACCESS ADDRESS
Data 0
n
Data 1
n+1
Data 2
n+2
Data 3
n+3
BURST LENGTH
2 words (address bits is LA0)
not carried from LA0~LA1
4 words (address bits is LA1, LA0)
not carried from LA1~LA2
Addressing sequence of Interleave mode
A column access is started from the inputted lower address and is performed by interleaving the address
bits in the sequence shown as the following.
Addressing sequence for Interleave mode
DATA
ACCESS ADDRESS
BURST LENGTH
Data 0
ּּּA8 A7 A6 A5 A4 A3 A2 A1 A0
Data 1
ּּּA8 A7 A6 A5 A4 A3 A2 A1
A0
Data 2
ּּּA8 A7 A6 A5 A4 A3 A2
A1
A0
Data 3
ּּּA8 A7 A6 A5 A4 A3 A2
A1
A0
2 words
4 words
(R-3) CAS Latency field (A6 to A4)
This field specifies the number of clock cycles from the assertion of the LAL command following the
RDA command to the first data read. The minimum values of CAS Latency depends on the frequency
of CLK. In a write mode, the place of clock that should input write data is CAS Latency cycles − 1.
A6
A5
A4
CAS LATENCY
0
0
0
Reserved
0
0
1
Reserved
0
1
0
Reserved
0
1
1
Reserved
1
0
0
4
1
0
1
Reserved
1
1
0
Reserved
1
1
1
Reserved
(R-4) Test Mode field (A7)
This bit is used to enter Test Mode for supplier only and must be set to “0” for normal operation.
(R-5) Reserved field in the Regular Mode Register
• Reserved bits (A8 to A13, BA2)
These bits are reserved for future operations. They must be set to “0” for normal operation.
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TC59LM913AMB-50
Extended Mode Register fields
(E-1) DLL Switch field (A0)
This bit is used to enable DLL. When the A0 bit is set “0”, DLL is enabled. This bit must be set to “0”
for normal operation.
(E-2) Output Driver Impedance Control field (A1, A6)
This field is used to choose Output Driver Strength. Four types of Driver Strength are supported.
(E-3)
A6
A1
OUTPUT DRIVER IMPEDANCE CONTROL
0
0
Normal Output Driver
0
1
Strong Output Driver
1
0
Weaker Output Driver
1
1
Weakest Output Driver
DQS enable (A10)
DQS is not supported. This bit must be always set “0”.
(E-4) Reserved field (A2 to A5, A7 to A9, A11 to A13, BA2)
These bits are reserved for future operations and must be set to “0” for normal operation.
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TC59LM913AMB-50
PACKAGE DIMENSIONS
P-BGA64-1317-1.00AZ
0.2 S B
0.2 S A
16.5
0
13.086 -0.15
12.7
0
10.975 -0.15
0.15
1.20MAX
0.2 S
S
0.4 0.05
0.15MIN
0.1 S
0.5 0.05
0.08
S AB
1.25
B
R
P
N
M
L
K
J
H
G
F
E
D
C
B
A
3.85
INDEX
A
1.0
4 5 6
1.5 1.5
1 2 3
3.85
1.85
1.0
2.0
Note: In order to support a package, four outer balls located on F and K row are required to assembly to board.
These four ball is not connected to any electrical level.
Weight: 0.23g (typ.)
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TC59LM913AMB-50
REVISION HISTORY
− Rev.0.9 ( Feb.27th ’2004 )
− Rev0.91 ( Mar.16th ‘2004 )
• Corrected TYPO(page50). Pin name is changed from “Q” to “R”.
− Rev0.92 ( Apr.21th ‘2004 )
• IDD6 spec changed from 20mA to 40mA (page 1, 7).
• IDD5B spec changed as below (page 7).
“−50”: 250mA → 420mA, “−55”: 240mA → 400mA, “−60”: 230mA → 380mA
• Corrected TYPO (page 7). CAS Latency condition is changed from CL5 to CL4.
− Rev0.93 ( Jun. 9th ‘2004 )
• Auto-Refresh Average Interval (tREFI) changed from 7.8µs to 3.9µs (page 1, 10, 46).
• IDD6 spec changed from 40mA to 20mA (page 1, 7).
• IDD5B spec changed as below (page 7).
“−50” : 420mA → 250mA, “−55”: 400mA → 240mA, “−60”: 380mA → 230mA
− Rev1.0 ( Aug. 20th ‘2004 )
• “-60” version dropped.
• Package name (P−BGA64−1317−1.00AZ) added (page 1).
• Some Note in the page 8 moved to page 7 (page 7, 8).
• Note 2 changed as below (page 7).
Before: These parameters depend on the output loading. The specified values are obtained with the
output open.
After:
These parameters define the current between VDD and VSS.
• Corrected TYPO (page 14, 15, 17).
• Package weight (0.23g) added (page 50).
− Rev1.1 ( Aug. 19th ‘2005 )
• CAS Latency=3 feature dropped.
• 8 I/O feature dropped.
• “-55” speed version dropped.
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TC59LM913AMB-50
RESTRICTIONS ON PRODUCT USE
030619EBA
• The information contained herein is subject to change without notice.
• The information contained herein is presented only as a guide for the applications of our products. No
responsibility is assumed by TOSHIBA for any infringements of patents or other rights of the third parties which
may result from its use. No license is granted by implication or otherwise under any patent or patent rights of
TOSHIBA or others.
• TOSHIBA is continually working to improve the quality and reliability of its products. Nevertheless, semiconductor
devices in general can malfunction or fail due to their inherent electrical sensitivity and vulnerability to physical
stress. It is the responsibility of the buyer, when utilizing TOSHIBA products, to comply with the standards of
safety in making a safe design for the entire system, and to avoid situations in which a malfunction or failure of
such TOSHIBA products could cause loss of human life, bodily injury or damage to property.
In developing your designs, please ensure that TOSHIBA products are used within specified operating ranges as
set forth in the most recent TOSHIBA products specifications. Also, please keep in mind the precautions and
conditions set forth in the “Handling Guide for Semiconductor Devices,” or “TOSHIBA Semiconductor Reliability
Handbook” etc..
• The TOSHIBA products listed in this document are intended for usage in general electronics applications
(computer, personal equipment, office equipment, measuring equipment, industrial robotics, domestic appliances,
etc.). These TOSHIBA products are neither intended nor warranted for usage in equipment that requires
extraordinarily high quality and/or reliability or a malfunction or failure of which may cause loss of human life or
bodily injury (“Unintended Usage”). Unintended Usage include atomic energy control instruments, airplane or
spaceship instruments, transportation instruments, traffic signal instruments, combustion control instruments,
medical instruments, all types of safety devices, etc.. Unintended Usage of TOSHIBA products listed in this
document shall be made at the customer’s own risk.
• The products described in this document are subject to the foreign exchange and foreign trade laws.
• TOSHIBA products should not be embedded to the downstream products which are prohibited to be produced
and sold, under any law and regulations.
Rev 1.1
2005-08-19
46/46