TC9WMA1FK TOSHIBA CMOS Digital Integrated Circuits Silicon Monolithic TC9WMA1FK 2 1,024-Bit (128 × 8 Bit) Serial E PROM The TC9WMA1FK is electrically erasable/programmable nonvolatile memory (E2PROM). Features · Serial data input/output · Programmable in units of one word and collectively erasable in one operation · Automatically set programming time (built-in timer) · Programming time: 10 ms (max) (VCC = 3.0 to 3.6 V) · Overwriting enabled or disabled by software · Single power supply and low power consumption · Operating power supply voltage (2.7 to 3.6 V) · Wide operating temperature range (−40 to 85°C) 13 ms (max) (VCC = 2.7 to 3.6 V) Product Marking Weight: 0.01 g (typ.) Pin Assignment (top view) CS CLK DI 8 7 6 US8 Type name DO 5 1 2 3 4 VCC NC RST GND 1 2001-10-16 TC9WMA1FK Block Diagram Chip select CS Clock input CLK Timing generator Control circuit Power supply (booster circuit) VCC Power supply Reset input RST Command register Data Input DI Memory cell Input/Output circuit GND Ground Address Address register decoder Data Output DO Data register Pin Function Pin Name Input/Output CS Input Chip select A low on CS selects the chip. Always return CS high temporarily before executing instructions. CLK Input Clock input The data on DI is latched by a rising edge of CLK . Data is output to DO by a falling edge of CLK . CLK is effective when CS is low. DI Input Serial data input This pin is used to enter addresses, commands, and data into the chip. DO Output Serial data output This pin outputs data from the chip. RST Input Reset input A low on this input resets the chip. NC ¾ VCC GND Function No connection (not connected internally) 2.7 V~3.6 V Power supply 0 V (GND) 2 2001-10-16 TC9WMA1FK Functional Description 1. Types of Instructions Operation Address Command C0 C1 C2 C3 Data Read A0~A6, 0 1 0 0 0 0 0 0 0 Program A0~A6, 0 0 1 1 0 0 0 0 0 All erase ******** 0 0 1 1 0 0 0 0 Busy monitor ******** 1 0 1 1 0 0 0 0 Overwrite enable ******** 1 0 0 1 0 0 0 0 Overwrite disable ******** 1 1 0 1 0 0 0 0 D0~D7 *: Don’t care 2. Operation Method Be sure to return CS and CLK high temporarily before entering instructions. After CS is asserted low, CLK becomes effective, acting as a serial transfer synchronizing signal. The data on DI is latched by a rising edge of CLK , while data is output to DO by a falling edge of CLK . Instructions can only be executed when the chip is not being programmed or collectively erased (i.e., when the ready/busy status signal is high). However, the Busy Monitor instruction can be entered at any time. Only the commands listed in the above table can be used. Do not use any other command. (1) (2) (3) (4) (5) Read When the Read instruction is entered, memory data at the specified address is read out and is serially output from the DO pin. Program When the Program instruction is entered, overwrite operation automatically starts internally in the chip, and memory data at the specified address is overwritten with the input data. After the instruction is entered, CS can be returned high even while overwrite operation is in progress internally. All Erase When the All Erase instruction is entered, erase operation automatically starts internally in the chip, and memory data at all addresses are erased. After the instruction is entered, CS can be returned high even while erase operation is in progress internally. Execution of this command clears the memory data to 0. Busy Monitor When the Busy Monitor instruction is entered, a ready/busy status signal is output from the DO pin. This output signal is low while the chip is being programmed or collectively erased, and is high after programming or collective erase operation is completed. The ready/busy status signal is output continuously until CS is returned high. Overwrite Enable/Disable When the Overwrite Enable instruction is entered, the chip is placed in overwrite enable mode, where the Program and All Erase instructions are enabled. When the Overwrite Disable instruction is entered, the chip is placed in overwrite disable mode, where the Program and All Erase instructions both are disabled. Once the chip is placed in overwrite disable mode, it remains disabled against overwriting unless the Overwrite Enable instruction is entered. 3 2001-10-16 TC9WMA1FK 3. Precautions to be Taken at Power ON/OFF (1) (2) (3) A wait time of 1 ms is required before the chip starts operation after it is powered on. RST must be pulled low when the power to the chip turns ON or OFF. The chip is placed in overwrite disable mode by reset. 4. Timing Chart (1) Read CS 1 2 7 A0 A1 A6 8 9 10 11 12 13 14 15 16 17 23 24 CLK DI 0 1 Address 0 0 0 0 0 0 0 Command D0 DO D6 D7 Hi-Z Hi-Z Data (2) Program CS 1 2 7 A0 A1 A6 8 9 10 11 12 13 14 15 16 17 23 24 CLK DI Address 0 0 1 1 0 0 0 0 0 D0 D6 D7 Command DO Hi-Z 4 2001-10-16 TC9WMA1FK (3) All Erase CS 1 2 7 8 9 10 11 12 13 14 15 16 CLK 0 DI 0 1 1 0 0 0 0 Command DO Hi-Z (4) Busy Monitor CS 1 2 7 8 9 10 11 12 13 14 15 16 CLK 1 DI 0 1 1 0 0 0 0 Command DO Hi-Z (5) Hi-Z Overwrite Enable/Disable CS 1 2 7 8 9 10 11 12 13 14 15 16 CLK 1 Enable 0 0 1 0 0 0 0 1 0 0 0 0 Command DI 1 Disable 1 0 Command DO Hi-Z 5 2001-10-16 TC9WMA1FK Maximum Ratings (GND = 0 V) Characteristics Symbol Rating Unit Power supply voltage VCC -0.3~4.6 V Input voltage VIN -0.3~VCC + 0.3 V VOUT -0.3~VCC + 0.3 V Power dissipation PD 200 (25°C) mW Soldering temperature (in time) Tsld 260 (10 s) °C Storage temperature Tstg -55~125 °C Operating temperature Topr -40~85 °C Output voltage Recommended Operating Conditions (GND = 0 V, Topr = -40~85°C) Characteristics Power supply voltage Symbol Test Condition VCC Min Max Unit 2.7 3.6 V Recommended Operating Conditions (GND = 0 V, VCC = 2.7~3.6 V, Topr = -40~85°C) Characteristics Low level input voltage High level input voltage Operating frequency Symbol Pin VIL Test Condition Min Max Unit VCC = 2.7 V 0 0.45 V VIH1 CS , DI, RST VCC = 3.6 V 1.6 VCC VIH2 CLK VCC = 3.6 V 2.2 VCC 0 1 fCLK 6 V MHz 2001-10-16 TC9WMA1FK Electrical Characteristics D.C. Characteristics (GND = 0 V, VCC = 2.7~3.6 V, Topr = -40~85°C) Characteristics Symbol Min Typ. Max Unit ILI ¾ ¾ ±5 mA Output leakage current ILO ¾ ¾ ±5 mA High level output voltage VOH VCC = 2.7 V, IOH = -1 mA VCC 0.4 ¾ ¾ V Low level output voltage VOL VCC = 2.7 V, IOL = 2 mA ¾ ¾ 0.4 V ICC1 (Note1) ¾ ¾ 5 mA ICC2 (Note2) ¾ ¾ 1.5 mA ¾ ¾ 1.0 mA Input current Quiescent supply current Supply current during read Supply current during all erase/program Note 1: Test Condition ICC3 (Note3) CS = 1 (except when busy, however) Note 2: Current that flows for a period from a fall of the 14th to a fall of the 17th CLK pulse when executing the read instruction. Note 3: Current that flows while executing the all erase or program instruction. A.C. Characteristics (GND = 0 V, VCC = 2.7~3.6 V, Topr = -40~85°C) Characteristics Symbol Maximum clock frequency Test Condition fMAX Min Max Unit 0 1 MHz 400 ¾ ns twCLK (L) Minimum clock pulse width twCLK (H) Minimum reset pulse width tWRST 1 ¾ ms Minimum chip select pulse width tWCS 1 ¾ ms Reset setup time tRSS RST setup time when CS is switched over 1 ¾ ms Clock setup time tCKS CLK setup time when CS is switched over 250 ¾ ns CS setup time tCSS CS setup time when CLK is switched over 250 ¾ ns ¾ 250 tpLH tpHL Propagation delay time (Note4) tpZH Time from CLK switchover until valid data is output ns tpZL tpLZ tpHZ Time from CS switchover until output data goes Hi-Z ¾ 500 Input data setup time ts Input data setup time when CLK is switched over 250 ¾ ns Input data hold time th Input data hold time when CLK is switched over 250 ¾ ns Note 4: CL = 100 pF, RL = 1 kW 7 2001-10-16 TC9WMA1FK 2 < 3.6 V, Topr = -40~85°C) < VCC = E PROM Characteristics (GND = 0 V, 3.0 V = Characteristics Symbol Test Condition Min Typ. Max Unit 6 10 ms 6 10 ms All erase time tE ¾ Program time tP ¾ 5 Endurance NEW 1 ´ 10 ¾ ¾ Times Data retention time tRET 10 ¾ ¾ Year Min Typ. Max Unit 7 13 ms 7 13 ms 2 < VCC = < 3.6 V, Topr = -40~85°C) E PROM Characteristics (GND = 0 V, 2.7 V = Characteristics Symbol Test Condition All erase time tE ¾ Program time tP ¾ 5 Endurance NEW 1 ´ 10 ¾ ¾ Times Data retention time tRET 10 ¾ ¾ Year VCC (V) Typ. Unit 3.3 4 pF 3.3 3 pF 3.3 8.5 pF Capacitance Characteristics (Ta = 25°C) Characteristics Input capacitance Symbol Test Condition CIN Output capacitance CO Equivalent Internal capacitance CPD fIN = 1 MHz (Note5) Note 5: CPD denotes the IC’s internal equivalent capacitance calculated from the amount of current it consumes while operating. The average current consumption during non-loaded operation is obtained from the equations below. ICC (Read) = fCLK･CPD･VCC + ICC1 + ICC2･3.5/24 ICC (Prog) = fCLK･CPD･VCC + ICC1 + ICC3 8 2001-10-16 TC9WMA1FK A.C. Characteristics Timing Chart tCSS tCKS tCKS tCSS VCC VCC/2 CS GND VCC CLK VCC/2 GND ts th VCC VCC/2 CLK GND DI VCC/2 tPLH tPHL tPLH tPHL VCC VCC/2 CLK GND DO VCC/2 tPLZ tPHZ VCC VCC/2 CS GND VCC CLK GND HiZ DO VCC/2 tPZH tPZL VCC VCC/2 CLK GND HiZ DO VCC/2 tWCLK (L) tWCLK (H) VCC CLK VCC/2 VCC/2 GND tWRST VCC RST VCC/2 VCC/2 GND tRSS VCC RST VCC/2 GND VCC/2 CS tWCS VCC CS VCC/2 VCC/2 GND 9 2001-10-16 TC9WMA1FK Input/Output Circuits of Pins Pin Name Type Input/Output Circuit Remarks CS DI RST Input CLK Input Hysteresis input Output control signal DO VCC Output Initial “HiZ” 10 2001-10-16 TC9WMA1FK Package Dimensions Weight: 0.01 g (typ.) 11 2001-10-16 TC9WMA1FK RESTRICTIONS ON PRODUCT USE 000707EBA · TOSHIBA is continually working to improve the quality and reliability of its products. Nevertheless, semiconductor devices in general can malfunction or fail due to their inherent electrical sensitivity and vulnerability to physical stress. It is the responsibility of the buyer, when utilizing TOSHIBA products, to comply with the standards of safety in making a safe design for the entire system, and to avoid situations in which a malfunction or failure of such TOSHIBA products could cause loss of human life, bodily injury or damage to property. In developing your designs, please ensure that TOSHIBA products are used within specified operating ranges as set forth in the most recent TOSHIBA products specifications. Also, please keep in mind the precautions and conditions set forth in the “Handling Guide for Semiconductor Devices,” or “TOSHIBA Semiconductor Reliability Handbook” etc.. · The TOSHIBA products listed in this document are intended for usage in general electronics applications (computer, personal equipment, office equipment, measuring equipment, industrial robotics, domestic appliances, etc.). These TOSHIBA products are neither intended nor warranted for usage in equipment that requires extraordinarily high quality and/or reliability or a malfunction or failure of which may cause loss of human life or bodily injury (“Unintended Usage”). Unintended Usage include atomic energy control instruments, airplane or spaceship instruments, transportation instruments, traffic signal instruments, combustion control instruments, medical instruments, all types of safety devices, etc.. Unintended Usage of TOSHIBA products listed in this document shall be made at the customer’s own risk. · The products described in this document are subject to the foreign exchange and foreign trade laws. · The information contained herein is presented only as a guide for the applications of our products. No responsibility is assumed by TOSHIBA CORPORATION for any infringements of intellectual property or other rights of the third parties which may result from its use. No license is granted by implication or otherwise under any intellectual property or other rights of TOSHIBA CORPORATION or others. · The information contained herein is subject to change without notice. 12 2001-10-16