INTEGRATED CIRCUITS DATA SHEET TDA4856 I2C-bus autosync deflection controller for PC monitors Product specification Supersedes data of 1998 Oct 02 File under Integrated Circuits, IC02 1999 Jul 13 Philips Semiconductors Product specification I2C-bus autosync deflection controller for PC monitors TDA4856 FEATURES Concept features • Full horizontal plus vertical autosync capability • Extended horizontal frequency range from 15 to 130 kHz • Comprehensive set of I2C-bus driven geometry adjustments and functions, including standby mode Vertical section • I2C-bus controllable vertical picture size, picture position, linearity (S-correction) and linearity balance • Very good vertical linearity • Moire cancellation • Output for the I2C-bus controllable vertical sawtooth and parabola (for pin unbalance and parallelogram) • Start-up and switch-off sequence for safe operation of all power components • Vertical picture size independent of frequency • X-ray protection • Power dip recognition • Differential current outputs for DC coupling to vertical booster • Flexible switched mode B+ supply function block for feedback and feed forward converter • 50 to 160 Hz vertical autosync range. • Internally stabilized voltage reference East-West (EW) section • Drive signal for focus amplifiers with combined horizontal and vertical parabola waveforms • I2C-bus controllable output for horizontal pincushion, horizontal size, corner and trapezium correction • DC controllable inputs for Extremely High Tension (EHT) compensation • Optional tracking of EW drive waveform with line frequency selectable by the I2C-bus. • SDIP32 package. Focus section Synchronization • I2C-bus controllable output for horizontal and vertical parabolas • Can handle all sync signals (horizontal, vertical, composite and sync-on-video) • Vertical parabola is independent of frequency and tracks with vertical adjustments • Output for video clamping (leading/trailing edge selectable by the I2C-bus), vertical blanking and protection blanking • Horizontal parabola independent of frequency • Adjustable pre-correction of delay in focus output stage. • Output for fast unlock status of horizontal synchronization and blanking on grid 1 of picture tube. Horizontal section • I2C-bus controllable wide range linear picture position, pin unbalance and parallelogram correction via horizontal phase • Frequency-locked loop for smooth catching of horizontal frequency • Simple frequency preset of fmin and fmax by external resistors • Low jitter • Soft start for horizontal and B+ control drive signals. 1999 Jul 13 2 Philips Semiconductors Product specification I2C-bus autosync deflection controller for PC monitors GENERAL DESCRIPTION TDA4856 The TDA4856 provides extended functions e.g. as a flexible B+ control, an extensive set of geometry control facilities, and a combined output for horizontal and vertical focus signals. The TDA4856 is a high performance and efficient solution for autosync monitors. All functions are controllable by the I2C-bus. Together with the I2C-bus driven Philips TDA488x video processor family, a very advanced system solution is offered. The TDA4856 provides synchronization processing, horizontal and vertical synchronization with full autosync capability and very short settling times after mode changes. External power components are given a great deal of protection. The IC generates the drive waveforms for DC-coupled vertical boosters such as the TDA486x and TDA835x. QUICK REFERENCE DATA SYMBOL PARAMETER MIN. TYP. MAX. UNIT V CC supply voltage 9.2 − 16 V ICC supply current − 70 − mA ICC(stb) supply current during standby mode − 9 − mA VSIZE vertical size 60 − 100 % VGA VGA overscan for vertical size − 16.8 − % VPOS vertical position − ±11.5 − % VLIN vertical linearity (S-correction) −2 − −46 % VLINBAL vertical linearity balance − ±1.25 − % VHSIZE horizontal size 0.13 − 3.6 V VHPIN horizontal pincushion (EW parabola) 0.04 − 1.42 V VHEHT horizontal size modulation 0.02 − 0.69 V VHTRAP horizontal trapezium correction − ±0.5 − V VHCORT horizontal corner correction at top of picture −0.64 − +0.2 V VHCORB horizontal corner correction at bottom of picture −0.64 − +0.2 V HPOS horizontal position − ±13 − % HPARAL horizontal parallelogram − ±1.5 − % HPINBAL EW pin unbalance − ±1.5 − % Tamb operating ambient temperature −20 − +70 °C ORDERING INFORMATION TYPE NUMBER TDA4856 1999 Jul 13 PACKAGE NAME SDIP32 DESCRIPTION plastic shrink dual in-line package; 32 leads (400 mil) 3 VERSION SOT232-1 This text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here in _white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here inThis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader. white to force landscape pages to be ... 14 clamping blanking CLBL HUNLOCK 16 17 VERTICAL SYNC INPUT AND POLARITY CORRECTION 7V EHT compensation via horizontal size 150 nF 1.2 V VREF VCAP VAGC VSMOD HSMOD EWDRV 23 24 22 21 31 11 VERTICAL OSCILLATOR AND AGC VERTICAL SYNC INTEGRATOR EHT COMPENSATION HORIZONTAL AND VERTICAL SIZE EW OUTPUT VERTICAL OUTPUT HORIZONTAL PINCUSHION HORIZONTAL CORNER HORIZONTAL TRAPEZIUM HORIZONTAL SIZE VERTICAL LINEARITY BALANCE 19 4 SCL 18 VCC 10 PGND 7 SGND 25 HSYNC 15 VOUT2 VOUT1 VERTICAL POSITION VERTICAL SIZE AND VERTICAL OVERSCAN VIDEO CLAMPING AND VERTICAL BLANK HUNLOCK OUTPUT ASYMMETRIC EW-CORRECTION OUTPUT 20 ASCOR FOCUS HORIZONTAL AND VERTICAL 32 FOCUS or PROTECTION AND SOFT START TDA4856 SDA 12 13 VERTICAL LINEARITY I2C-BUS RECEIVER I2C-BUS REGISTERS 6 BDRV 9.2 to 16 V (TTL level) 4 BSENS SUPPLY AND REFERENCE X-RAY PROTECTION COINCIDENCE DETECTOR FREQUENCY DETECTOR H/C SYNC INPUT AND POLARITY CORRECTION PLL1 AND HORIZONTAL POSITION (video) 3.3 kΩ 100 nF B+ CONTROL HORIZONTAL OSCILLATOR PLL2, PARALLELOGRAM, PIN UNBALANCE AND SOFT START HORIZONTAL OUTPUT 27 28 29 30 1 9 2 HPLL1 HBUF HREF HCAP HPLL2 HFLB XSEL XRAY 8.2 nF RHBUF (1) RHREF (2) B+ CONTROL APPLICATION 5 BIN 26 10 nF (2%) 3 BOP Philips Semiconductors VSYNC (TTL level) 100 nF (5%) I2C-bus autosync deflection controller for PC monitors 22 kΩ (1%) BLOCK DIAGRAM ook, full pagewidth 1999 Jul 13 EHT compensation via vertical size 8 HDRV MGS272 12 nF (1%) Product specification Fig.1 Block diagram and application circuit. TDA4856 (1) For the calculation of fH range see Section “Calculation of line frequency range”. (2) See Figs 22 and 23. Philips Semiconductors Product specification I2C-bus autosync deflection controller for PC monitors TDA4856 PINNING SYMBOL PIN DESCRIPTION HFLB 1 horizontal flyback input XRAY 2 X-ray protection input BOP 3 B+ control OTA output BSENS 4 B+ control comparator input BIN 5 B+ control OTA input BDRV 6 B+ control driver output PGND 7 power ground HDRV 8 horizontal driver output XSEL 9 select input for X-ray reset VCC 10 supply voltage EWDRV 11 EW waveform output VOUT2 12 vertical output 2 (ascending sawtooth) VOUT1 13 vertical output 1 (descending sawtooth) VSYNC 14 vertical synchronization input HSYNC 15 horizontal/composite synchronization input CLBL 16 video clamping pulse/vertical blanking output HUNLOCK 17 horizontal synchronization unlock/protection/vertical blanking output SCL 18 I2C-bus clock input SDA 19 I2C-bus data input/output ASCOR 20 output for asymmetric EW corrections VSMOD 21 input for EHT compensation (via vertical size) VAGC 22 external capacitor for vertical amplitude control VREF 23 external resistor for vertical oscillator VCAP 24 external capacitor for vertical oscillator SGND 25 signal ground HPLL1 26 external filter for PLL1 HBUF 27 buffered f/v voltage output HREF 28 reference current for horizontal oscillator HCAP 29 external capacitor for horizontal oscillator HPLL2 30 external filter for PLL2/soft start HSMOD 31 input for EHT compensation (via horizontal size) FOCUS 32 output for horizontal and vertical focus 1999 Jul 13 5 Philips Semiconductors Product specification I2C-bus autosync deflection controller for PC monitors TDA4856 Vertical sync integrator Normalized composite sync signals from HSYNC are integrated on an internal capacitor in order to extract vertical sync pulses. The integration time is dependent on the horizontal oscillator reference current at HREF (pin 28). The integrator output directly triggers the vertical oscillator. handbook, halfpage HFLB 1 32 FOCUS XRAY 2 31 HSMOD BOP 3 30 HPLL2 BSENS 4 29 HCAP BIN 5 28 HREF BDRV 6 27 HBUF PGND 7 26 HPLL1 Vertical sync slicer and polarity correction Vertical sync signals (TTL) applied to VSYNC (pin 14) are sliced at 1.4 V. The output signal of the sync slicer is integrated on an internal capacitor to detect and normalize the sync polarity. The output signals of vertical sync integrator and sync normalizer are disjuncted before they are fed to the vertical oscillator. 25 SGND HDRV 8 TDA4856 XSEL 9 24 VCAP VCC 10 23 VREF EWDRV 11 22 VAGC VOUT2 12 21 VSMOD VOUT1 13 20 ASCOR VSYNC 14 19 SDA HSYNC 15 18 SCL CLBL 16 Video clamping/vertical blanking generator The video clamping/vertical blanking signal at CLBL (pin 16) is a two-level sandcastle pulse which is especially suitable for video ICs such as the TDA488x family, but also for direct applications in video output stages. The upper level is the video clamping pulse, which is triggered by the horizontal sync pulse. Either the leading or trailing edge can be selected by setting control bit CLAMP via the I2C-bus. The width of the video clamping pulse is determined by an internal single-shot multivibrator. 17 HUNLOCK MGS273 Fig.2 Pin configuration. The lower level of the sandcastle pulse is the vertical blanking pulse, which is derived directly from the internal oscillator waveform. It is started by the vertical sync and stopped with the start of the vertical scan. This results in optimum vertical blanking. Two different vertical blanking times are accessible, by control bit VBLK, via the I2C-bus. FUNCTIONAL DESCRIPTION Horizontal sync separator and polarity correction HSYNC (pin 15) is the input for horizontal synchronization signals, which can be DC-coupled TTL signals (horizontal or composite sync) and AC-coupled negative-going video sync signals. Video syncs are clamped to 1.28 V and sliced at 1.4 V. This results in a fixed absolute slicing level of 120 mV related to top sync. Blanking will be activated continuously if one of the following conditions is true: Soft start of horizontal and B+ drive [voltage at HPLL2 (pin 30) pulled down externally or by the I2C-bus] PLL1 is unlocked while frequency-locked loop is in search mode For DC-coupled TTL signals the input clamping current is limited. The slicing level for TTL signals is 1.4 V. No horizontal flyback pulses at HFLB (pin 1) X-ray protection is activated The separated sync signal (either video or TTL) is integrated on an internal capacitor to detect and normalize the sync polarity. Supply voltage at VCC (pin 10) is low (see Fig.24). Horizontal unlock blanking can be switched off, by control bit BLKDIS, via the I2C-bus while vertical blanking is maintained. Normalized horizontal sync pulses are used as input signals for the vertical sync integrator, the PLL1 phase detector and the frequency-locked loop. 1999 Jul 13 6 Philips Semiconductors Product specification I2C-bus autosync deflection controller for PC monitors TDA4856 Frequency-locked loop Horizontal oscillator The frequency-locked loop can lock the horizontal oscillator over a wide frequency range. This is achieved by a combined search and PLL operation. The frequency range is preset by two external resistors and the f max 6.5 recommended maximum ratio is --------- = -------1 f min The horizontal oscillator is of the relaxation type and requires a capacitor of 10 nF at HCAP (pin 29). For optimum jitter performance the value of 10 nF must not be changed. The minimum oscillator frequency is determined by a resistor from HREF to ground. A resistor connected between pins HREF and HBUF defines the frequency range. This can, for instance, be a range from 15.625 to 90 kHz with all tolerances included. The reference current at pin HREF also defines the integration time constant of the vertical sync integration. Without a horizontal sync signal the oscillator will be free-running at fmin. Any change of sync conditions is detected by the internal coincidence detector. A deviation of more than 4% between horizontal sync and oscillator frequency switches the horizontal section into search mode. This means that PLL1 control currents are switched off immediately. The internal frequency detector then starts tuning the oscillator. Very small DC currents at HPLL1 (pin 26) are used to perform this tuning with a well defined change rate. When coincidence between horizontal sync and oscillator frequency is detected, the search mode is first replaced by a soft-lock mode which lasts for the first part of the next vertical period. The soft-lock mode is then replaced by a normal PLL operation. This operation ensures smooth tuning and avoids fast changes of horizontal frequency during catching. Calculation of line frequency range The oscillator frequencies fmin and fmax must first be calculated. This is achieved by adding the spread of the relevant components to the highest and lowest sync frequencies fsync(min) and fsync(max). The oscillator is driven by the currents in RHREF and RHBUF. The following example is a 31.45 to 90 kHz application: Table 1 Calculation of total spread spread of for fmax for fmin IC ±3% ±5% CHCAP ±2% ±2% RHREF, RHBUF ±2% ±2% Total ±7% ±9% In this concept it is not allowed to load HPLL1. The frequency dependent voltage at this pin is fed internally to HBUF (pin 27) via a sample-and-hold and buffer stage. The sample-and-hold stage removes all disturbances caused by horizontal sync or composite vertical sync from the buffered voltage. An external resistor connected between pins HBUF and HREF defines the frequency range. Thus the typical frequency range of the oscillator in this example is: Out-of-lock indication (pin HUNLOCK) f sync ( min ) f min = ---------------------- = 28.4 kHz 1.09 f max = f sync ( max ) × 1.07 = 96.3 kHz Pin HUNLOCK is floating during search mode, or if a protection condition is true. All this can be detected by the microcontroller if a pull-up resistor is connected to its own supply voltage. The resistors RHREF and RHBUFpar can be calculated using the following formulae: 78 × kHz × k Ω R HREF = ----------------------------------------------------------------= 2.61 kΩ 2 f min + 0.0012 × f min [ kHz ] For an additional fast vertical blanking at grid 1 of the picture tube a 1 V signal referenced to ground is available at this output. The continuous protection blanking (see Section “Video clamping/vertical blanking generator”) is also available at this pin. Horizontal unlock blanking can be switched off, by control bit BLKDIS via the I2C-bus while vertical blanking is maintained. 1999 Jul 13 78 × kHz × k Ω R HBUFpar = ------------------------------------------------------------------- = 726 Ω . 2 f max + 0.0012 × f max [ kHz ] The resistor RHBUFpar is calculated as the value of RHREF and RHBUF in parallel. 7 Philips Semiconductors Product specification I2C-bus autosync deflection controller for PC monitors TDA4856 The formulae for RHBUF also takes into account the voltage swing across this resistor: R HREF × R HBUFpar R HBUF = ---------------------------------------------- × 0.8 = 805 Ω R HREF – R HBUFpar An external modulation of the PLL2 phase is not allowed, because this would disturb the pre-correction of the horizontal focus parabola. PLL1 phase detector If HPLL2 is pulled to ground, either by an external DC current or by resetting register SOFTST, the horizontal output pulses and B+ control driver pulses will be inhibited. This means that HDRV (pin 8) and BDRV (pin 6) are floating in this state. In both cases PLL2 and the frequency-locked loop are disabled, and CLBL (pin 16) provides a continuous blanking signal and HUNLOCK (pin 17) is floating. Soft start and standby The phase detector is a standard type using switched current sources, which are independent of horizontal frequency. It compares the middle of horizontal sync with a fixed point on the oscillator sawtooth voltage. The PLL1 loop filter is connected to HPLL1 (pin 26). See also Section “Horizontal position adjustment and corrections”. This option can be used for soft start, protection and power-down modes. When pin HPLL2 is released again, an automatic soft start sequence on the horizontal drive as well as on the B-drive output will be performed (see Fig.24). Horizontal position adjustment and corrections A linear adjustment of the relative phase between the horizontal sync and the oscillator sawtooth (in PLL1 loop) is achieved via register HPOS. Once adjusted, the relative phase remains constant over the whole frequency range. A soft start can only be performed if the supply voltage for the IC is a minimum of 8.6 V. Correction of pin unbalance and parallelogram is achieved by modulating the phase between oscillator sawtooth and horizontal flyback (in loop PLL2) via registers HPARAL and HPINBAL. If those asymmetric EW corrections are performed in the deflection stage, both registers can be disconnected from the horizontal phase via control bit ACD. This does not change the output at pin ASCOR. The soft start timing is determined by the filter capacitor at HPLL2 (pin 30), which is charged with a constant current during soft start. In the beginning the horizontal driver stage generates very small output pulses. The width of these pulses increases with the voltage at HPLL2 until the final duty cycle is reached. The voltage at HPLL2 increases further and performs a soft start at BDRV (pin 6) as well. After BDRV has reached full duty cycle, the voltage at HPLL2 continues to rise until HPLL2 enters its normal operating range. The internal charge current is now disabled. Finally PLL2 and the frequency-locked loop are activated. If both functions reach normal operation, HUNLOCK (pin 17) switches from the floating status to normal vertical blanking, and continuous blanking at CLBL (pin 16) is removed. Horizontal moire cancellation To achieve a cancellation of horizontal moire (also known as ‘video moire’), the horizontal frequency is divided-by-two to achieve a modulation of the horizontal phase via PLL2. The amplitude is controlled by register HMOIRE. To avoid a visible structure on screen the polarity changes with half of the vertical frequency. Control bit MOD disables the moire cancellation function. Output stage for line drive pulses [HDRV (pin 8)] PLL2 phase detector An open-collector output stage allows direct drive of an inverting driver transistor because of a low saturation voltage of 0.3 V at 20 mA. To protect the line deflection transistor, the output stage is disabled (floating) for a low supply voltage at VCC (see Fig.23). The PLL2 phase detector is similar to the PLL1 detector and compares the line flyback pulse at HFLB (pin 1) with the oscillator sawtooth voltage. The control currents are independent of the horizontal frequency. The PLL2 detector thus compensates for the delay in the external horizontal deflection circuit by adjusting the phase of the HDRV (pin 8) output pulse. 1999 Jul 13 The duty cycle of line drive pulses is slightly dependent on the actual horizontal frequency. This ensures optimum drive conditions over the whole frequency range. 8 Philips Semiconductors Product specification I2C-bus autosync deflection controller for PC monitors Table 2 X-ray protection The X-ray protection input XRAY (pin 2) provides a voltage detector with a precise threshold. If the input voltage at XRAY exceeds this threshold for a certain time, then control bit SOFTST is reset, which switches the IC into protection mode. In this mode several pins are forced into defined states: TDA4856 Calculation of ffr(V) total spread Contributing elements Minimum frequency offset between ffr(V) and lowest trigger frequency 10% Spread of IC ±3% Spread of RVREF ±1% HUNLOCK (pin 17) is floating Spread of CVCAP ±5% The capacitor connected to HPLL2 (pin 30) is discharged Total 19% Horizontal output stage (HDRV) is floating Result for 50 to 160 Hz application: 50 Hz f fr(V) = --------------- = 42 Hz 1.19 B+ control driver stage (BDRV) is floating CLBL provides a continuous blanking signal. The AGC of the vertical oscillator can be disabled by setting control bit AGCDIS via the I2C-bus. A precise external current has to be injected into VCAP (pin 24) to obtain the correct vertical size. This special application mode can be used when the vertical sync pulses are serrated (shifted); this condition is found in some display modes, e.g. when using a 100 Hz up converter for video signals. There are two different methods of restarting ways the IC: 1. XSEL (pin 9) is open-circuit or connected to ground. The control bit SOFTST must be set to logic 1 via the I2C-bus. Then the IC returns to normal operation via soft start. 2. XSEL (pin 9) is connected to VCC via an external resistor. The supply voltage of the IC must be switched off for a certain period of time, before the IC can be restarted again using the standard power-on procedure. Application hint: VAGC (pin 22) has a high input impedance during scan. Therefore, the pin must not be loaded externally otherwise non-linearities in the vertical output currents may occur due to the changing charge current during scan. Vertical oscillator and amplitude control This stage is designed for fast stabilization of vertical size after changes in sync frequency conditions. The free-running frequency ffr(V) is determined by the resistor RVREF connected to pin 23 and the capacitor CVCAP connected to pin 24. The value of RVREF is not only optimized for noise and linearity performance in the whole vertical and EW section, but also influences several internal references. Therefore the value of RVREF must not be changed. Capacitor CVCAP should be used to select the free-running frequency of the vertical oscillator in accordance with the following formula: 1 f fr(V) = ----------------------------------------------------------10.8 × R VREF × C VCAP Adjustment of vertical size, VGA overscan and EHT compensation There are four different ways to adjust the amplitude of the differential output currents at VOUT1 and VOUT2. 1. Register VGAIN changes the vertical size without affecting any other output signal of the IC. This adjustment is meant for factory alignments. 2. Register VSIZE changes not only the vertical size, but also provides the correct tracking of all other related waveforms (see Section “Tracking of vertical adjustments”). This register should be used for user adjustments. To achieve a stabilized amplitude the free-running frequency ffr(V), without adjustment, should be at least 10% lower than the minimum trigger frequency. The contributions shown in Table 2 can be assumed. 1999 Jul 13 3. For the VGA350 mode register VOVSCN can activate a +17% step in vertical size. 4. VSMOD (pin 21) can be used for a DC controlled EHT compensation of vertical size by correcting the differential output currents at VOUT1 and VOUT2. The EW waveforms, vertical focus, pin unbalance and parallelogram corrections are not affected by VSMOD. 9 Philips Semiconductors Product specification I2C-bus autosync deflection controller for PC monitors Adjustment of vertical position, vertical linearity and vertical linearity balance TDA4856 The pincushion (EW parabola) amplitude, corner and trapezium correction track with the vertical picture size (VSIZE) and also with the adjustment for vertical picture position (VPOS). The corner correction does not track with the horizontal pincushion (HPIN). Register VOFFS provides a DC shift at the sawtooth outputs VOUT1 and VOUT2 (pins 13 and 12) without affecting any other output waveform. This adjustment is meant for factory alignments. Further the horizontal pincushion amplitude, corner and trapezium correction track with the horizontal picture size, which is adjusted via register HSIZE and the analog modulation input HSMOD. If the DC component in the EWDRV output signal is increased via HSIZE or IHSMOD, the pincushion, corner and trapezium component of the EWDRV output will be reduced by a factor of V HSIZE V HSIZE + V HEHT 1 – --------------- 14.4 V 1 – ------------------------------------------------------------------------14.4 V Register VPOS provides a DC shift at the sawtooth output VOUT1 and VOUT2 with correct tracking of all other related waveforms (see Section “Tracking of vertical adjustments”). This register should be used for user adjustments. Due to the tracking the whole picture moves vertically while maintaining the correct geometry. Register VLIN is used to adjust the amount of the vertical S-correction in the output signal. This function can be switched off by control bit VSC. The value 14.4 V is a virtual voltage for calculation only. The output pin can not reach this value, but the gain (and DC bias) of the external application should be such that the horizontal deflection is reduced to zero when EWDRV reaches 14.4 V. Register VLINBAL is used to correct the unbalance of vertical S-correction in the output signal. Tracking of vertical adjustments The adjustments via registers VSIZE, VOVSCN and VPOS also affect the waveforms of horizontal pincushion, vertical linearity (S-correction), vertical linearity balance, focus parabola, pin unbalance and parallelogram correction. The result of this interaction is that no readjustment of these parameters is necessary after an user adjustment of vertical picture size and vertical picture position. HSMOD (pin 31) can be used for a DC controlled EHT compensation by correcting horizontal size, horizontal pincushion, corner and trapezium. The control range at this pin tracks with the actual value of HSIZE. For an increasing DC component VHSIZE in the EWDRV output signal, the DC component VHEHT caused by IHSMOD will be V HSIZE reduced by a factor of 1 – ---------------- as shown in the equation 14.4 V above. Adjustment of vertical moire cancellation To achieve a cancellation of vertical moire (also known as ‘scan moire’) the vertical picture position can be modulated by half the vertical frequency. The amplitude of the modulation is controlled by register VMOIRE and can be switched off via control bit MOD. The whole EWDRV voltage is calculated as follows: VEWDRV = 1.2 V + [VHSIZE + VHEHT × f(HSIZE) + (VHPIN + VHCOR + VHTRAP) × g(HSIZE, HSMOD)] × h(IHREF) Where: I HSMOD V HEHT = -------------------- × 0.69 120 µA Horizontal pincushion (including horizontal size, corner correction and trapezium correction) V HSIZE f(HSIZE) = 1 – ---------------14.4 V EWDRV (pin 11) provides a complete EW drive waveform. The components horizontal pincushion, horizontal size, corner correction and trapezium correction are controlled by the registers HPIN, HSIZE, HCORT, HCORB and HTRAP. V HSIZE V HSIZE + V HEHT 1 – --------------- 14.4 V g(HSIZE, HSMOD) = 1 – -------------------------------------------------------------------------14.4 V The corner correction can be adjusted separately for the top (HCORT) and bottom (HCORB) part of the picture. I HREF h ( I HREF ) = ------------------------------I HREF f = 70kHz 1999 Jul 13 10 Philips Semiconductors Product specification I2C-bus autosync deflection controller for PC monitors Dynamic focus section [FOCUS (pin 32)] Two different modes of operation can be chosen for the EW output waveform via control bit FHMULT: This section generates a complete drive signal for dynamic focus applications. The amplitude of the horizontal parabola is internally stabilized, thus it is independent of the horizontal frequency. The amplitude can be adjusted via register HFOCUS. Changing horizontal size may require a correction of HFOCUS. To compensate for the delay in external focus amplifiers a ‘pre-correction’ for the phase of the horizontal parabola has been implemented (see Fig.28). The amount of this pre-correction can be adjusted via register HFOCAD. The amplitude of the vertical parabola is independent of frequency and tracks with all vertical adjustments. The amplitude can be adjusted via register VFOCUS. 1. Mode 1 Horizontal size is controlled via register HSIZE and causes a DC shift at the EWDRV output. The complete waveform is also multiplied internally by a signal proportional to the line frequency [which is detected via the current at HREF (pin 28)]. This mode is to be used for driving EW diode modulator stages which require a voltage proportional to the line frequency. 2. Mode 2 The EW drive waveform does not track with the line frequency. This mode is to be used for driving EW modulators which require a voltage independent of the line frequency. FOCUS (pin 32) is designed as a voltage output for the superimposed vertical and horizontal parabolas. Output stage for asymmetric correction waveforms [ASCOR (pin 20)] B+ control function block The B+ control function block of the TDA4856 consists of an Operational Transconductance Amplifier (OTA), a voltage comparator, a flip-flop and a discharge circuit. This configuration allows easy applications for different B+ control concepts. See also Application Note AN96052: “B+ converter Topologies for Horizontal Deflection and EHT with TDA4855/58”. This output is designed as a voltage output for superimposed waveforms of vertical parabola and sawtooth. The amplitude and polarity of both signals can be changed by registers HPARAL and HPINBAL via the I2C-bus. Application hint: The TDA4856 offers two possibilities to control registers HPINBAL and HPARAL. 1. Control bit ACD = 1 GENERAL DESCRIPTION The two registers now control the horizontal phase by means of internal modulation of the PLL2 horizontal phase control. The ASCOR output (pin 20) can be left unused, but it will always provide an output signal because the ASCOR output stage is not influenced by the control bit ACD. The non-inverting input of the OTA is connected internally to a high precision reference voltage. The inverting input is connected to BIN (pin 5). An internal clamping circuit limits the maximum positive output voltage of the OTA. The output itself is connected to BOP (pin 3) and to the inverting input of the voltage comparator. The non-inverting input of the voltage comparator can be accessed via BSENS (pin 4). 2. Control bit ACD = 0 The internal modulation via PLL2 is disconnected. In order to obtain the required effect on the screen, pin ASCOR must now be fed to the DC amplifier which controls the DC shift of the horizontal deflection. This option is useful for applications which already use a DC shift transformer. B+ drive pulses are generated by an internal flip-flop and fed to BDRV (pin 6) via an open-collector output stage. This flip-flop is set at the rising edge of the signal at HDRV (pin 8). The falling edge of the output signal at BDRV has a defined delay of td(BDRV) to the rising edge of the HDRV pulse. When the voltage at BSENS exceeds the voltage at BOP, the voltage comparator output resets the flip-flop and, therefore, the open-collector stage at BDRV is floating again. If the tube does not need HPINBAL and HPARAL, then pin ASCOR can be used for other purposes, i.e. for a simple dynamic convergence. 1999 Jul 13 TDA4856 11 Philips Semiconductors Product specification I2C-bus autosync deflection controller for PC monitors Supply voltage stabilizer, references, start-up procedures and protection functions An internal discharge circuit allows a well defined discharge of capacitors at BSENS. BDRV is active at a LOW-level output voltage (see Figs 22 and 23), thus it requires an external inverting driver stage. The TDA4856 provides an internal supply voltage stabilizer for excellent stabilization of all internal references. An internal gap reference, especially designed for low-noise, is the reference for the internal horizontal and vertical supply voltages. All internal reference currents and drive current for the vertical output stage are derived from this voltage via external resistors. The B+ function block can be used for B+ deflection modulators in many different ways. Two popular application combinations are as follows: • Boost converter in feedback mode (see Fig.22) In this application the OTA is used as an error amplifier with a limited output voltage range. The flip-flop is set on the rising edge of the signal at HDRV. A reset will be generated when the voltage at BSENS, taken from the current sense resistor, exceeds the voltage at BOP. If either the supply voltage is below 8.3 V or no data from the I2C-bus has been received after power-up, the internal soft start and protection functions do not allow any of those outputs [HDRV, BDRV, VOUT1, VOUT2 and HUNLOCK (see Fig.24)] to be active. If no reset is generated within a line period, the rising edge of the next HDRV pulse forces the flip-flop to reset. The flip-flop is set immediately after the voltage at BSENS has dropped below the threshold voltage VRESTART(BSENS). For supply voltages below 8.3 V the internal I2C-bus will not generate an acknowledge and the IC is in standby mode. This is because the internal protection circuit has generated a reset signal for the soft start register SOFTST. Above 8.3 V data is accepted and all registers can be loaded. If the register SOFTST has received a set from the I2C-bus, the internal soft start procedure is released, which activates all above mentioned outputs. • Buck converter in feed forward mode (see Fig.23) This application uses an external RC combination at BSENS to provide a pulse width which is independent from the horizontal frequency. The capacitor is charged via an external resistor and discharged by the internal discharge circuit. For normal operation the discharge circuit is activated when the flip-flop is reset by the internal voltage comparator. The capacitor will now be discharged with a constant current until the internally controlled stop level VSTOP(BSENS) is reached. This level will be maintained until the rising edge of the next HDRV pulse sets the flip-flop again and disables the discharge circuit. If during normal operation the supply voltage has dropped below 8.1 V, the protection mode is activated and HUNLOCK (pin 17) changes to the protection status and is floating. This can be detected by the microcontroller. This protection mode has been implemented in order to protect the deflection stages and the picture tube during start-up, shut-down and fault conditions. This protection mode can be activated as shown in Table 3. If no reset is generated within a line period, the rising edge of the next HDRV pulse automatically starts the discharge sequence and resets the flip-flop. When the voltage at BSENS reaches the threshold voltage VRESTART(BSENS), the discharge circuit will be disabled automatically and the flip-flop will be set immediately. This behaviour allows a definition of the maximum duty cycle of the B+ control drive pulse by the relationship of charge current to discharge current. 1999 Jul 13 TDA4856 12 Philips Semiconductors Product specification I2C-bus autosync deflection controller for PC monitors Table 3 Power dip recognition Activation of protection mode ACTIVATION In standby mode the I2C-bus will only answer with an acknowledge, when data is sent to control register with subaddress 1AH. This register contains the standby and soft start control bit. RESET Low supply voltage at pin 10 increase supply voltage; reload registers; soft start via I2C-bus Power dip, below 8.1 V reload registers; soft start via I2C-bus or via supply voltage X-ray protection XRAY (pin 2) triggered reload registers; soft start via I2C-bus HPLL2 (pin 30) externally pulled to ground release pin 30 If the I2C-bus master transmits data to another register, an aknowledge is given after the chip address and the subaddress; an acknowledge is not given after the data. This indicates that only in soft start mode data can be stored into normal registers. If the supply voltage dips under 8.1 V the TDA4856 leaves normal operation mode and changes into standby mode. The microcontroller can check this state by sending data into a register with the subaddress 0XH. The acknowledge will only be given on the data if the TDA4856 is active. When the protection mode is active, several pins of the TDA4856 are forced into a defined state: Due to this behaviour the start-up of the TDA4856 is defined as follows. The first data that is transferred to the TDA4856 must be sent to the control register with subaddress 1AH. Any other subaddress will not lead to an acknowledge. This is a limitation in checking the I2C-busses of the monitor during start-up. HDRV (horizontal driver output) is floating BDRV (B+ control driver output) is floating HUNLOCK (indicates, that the frequency-to-voltage converter is out of lock) is floating (HIGH-level via external pull-up resistor) CLBL provides a continuous blanking signal The capacitor at HPLL2 is discharged. If the soft start procedure is activated via the I2C-bus, all of these actions will be performed in a well defined sequence (see Figs 24 and 25). 1999 Jul 13 TDA4856 13 Philips Semiconductors Product specification I2C-bus autosync deflection controller for PC monitors TDA4856 LIMITING VALUES In accordance with the Absolute Maximum Rating System (IEC 134); all voltages measured with respect to ground. SYMBOL PARAMETER VCC supply voltage Vi(n) input voltage on pins: Vo(n) CONDITIONS MIN. −0.5 MAX. +16 UNIT V BIN −0.5 +6.0 V HSYNC, VSYNC, VREF, HREF, VSMOD and HSMOD −0.5 +6.5 V SDA and SCL −0.5 +8.0 V XRAY −0.5 +8.0 V VOUT2, VOUT1 and HUNLOCK −0.5 +6.5 V BDRV and HDRV −0.5 +16 V output voltage on pins: VI/O(n) input/output voltages at pins BOP and BSENS −0.5 +6.0 V Io(HDRV) horizontal driver output current − 100 mA Ii(HFLB) horizontal flyback input current −10 +10 mA Io(CLBL) video clamping pulse/vertical blanking output current − −10 mA Io(BOP) B+ control OTA output current − 1 mA Io(BDRV) B+ control driver output current − 50 mA Io(EWDRV) EW driver output current − −5 mA Io(FOCUS) focus driver output current − −5 mA Tamb operating ambient temperature −20 +70 °C Tj junction temperature − 150 °C Tstg storage temperature −55 +150 °C VESD electrostatic discharge for all pins note 1 −150 +150 V note 2 −2000 +2000 V Notes 1. Machine model: 200 pF; 0.75 µH; 10 Ω. 2. Human body model: 100 pF; 7.5 µH; 1500 Ω. THERMAL CHARACTERISTICS SYMBOL Rth(j-a) PARAMETER CONDITIONS thermal resistance from junction to ambient VALUE UNIT 55 K/W in free air QUALITY SPECIFICATION In accordance with “URF-4-2-59/601”; EMC emission/immunity test in accordance with “DIS 1000 4.6” (IEC 801.6). SYMBOL VEMC PARAMETER CONDITIONS MIN. TYP. MAX. emission test note 1 − 1.5 − mV immunity test note 1 − 2.0 − V Note 1. Tests are performed with application reference board. Tests with other boards will have different results. 1999 Jul 13 UNIT 14 Philips Semiconductors Product specification I2C-bus autosync deflection controller for PC monitors TDA4856 CHARACTERISTICS VCC = 12 V; Tamb = 25 °C; peripheral components in accordance with Fig.1; unless otherwise specified. SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT Horizontal sync separator INPUT CHARACTERISTICS FOR DC-COUPLED TTL SIGNALS: PIN HSYNC Vi(HSYNC) sync input signal voltage 1.7 − − V VHSYNC(sl) slicing voltage level 1.2 1.4 1.6 V tr(HSYNC) rise time of sync pulse 10 − 500 ns tf(HSYNC) fall time of sync pulse 10 − 500 ns tW(HSYNC)(min) minimum width of sync pulse 0.7 − − µs Ii(HSYNC) input current VHSYNC = 0.8 V − − −200 µA VHSYNC = 5.5 V − − 10 µA INPUT CHARACTERISTICS FOR AC-COUPLED VIDEO SIGNALS (SYNC-ON-VIDEO, NEGATIVE SYNC POLARITY) VHSYNC sync amplitude of video input signal voltage Rsource = 50 Ω − 300 − mV VHSYNC(sl) slicing voltage level (measured from top sync) Rsource = 50 Ω 90 120 150 mV Vclamp(HSYNC) top sync clamping voltage level Rsource = 50 Ω 1.1 1.28 1.5 V Ich(HSYNC) charge current for coupling capacitor VHSYNC > Vclamp(HSYNC) 1.7 2.4 3.4 µA tW(HSYNC)(min) minimum width of sync pulse 0.7 − − µs Rsource(max) maximum source resistance duty cycle = 7% − − 1500 Ω Ri(diff)(HSYNC) differential input resistance during sync − 80 − Ω Automatic polarity correction for horizontal sync t P(H) ----------tH horizontal sync pulse width related to line period − − 25 % td(HPOL) delay time for changing polarity 0.3 − 1.8 ms fH = 15.625 kHz; IHREF = 0.52 mA 14 20 26 µs fH = 31.45 kHz; IHREF = 1.052 mA 7 10 13 µs fH = 64 kHz; IHREF = 2.141 mA 3.9 5.7 6.5 µs fH = 100 kHz; IHREF = 3.345 mA 2.5 3.8 4.5 µs Vertical sync integrator tint(V) integration time for generation of a vertical trigger pulse Vertical sync slicer (DC-coupled, TTL compatible): pin VSYNC Vi(VSYNC) sync input signal voltage 1.7 − − V VVSYNC(sl) slicing voltage level 1.2 1.4 1.6 V Ii(VSYNC) input current − − ±10 µA 1999 Jul 13 0 V < VSYNC < 5.5 V 15 Philips Semiconductors Product specification I2C-bus autosync deflection controller for PC monitors SYMBOL PARAMETER TDA4856 CONDITIONS MIN. TYP. MAX. UNIT Automatic polarity correction for vertical sync tW(VSYNC)(max) maximum width of vertical sync pulse − − 400 µs td(VPOL) delay for changing polarity 0.45 − 1.8 ms 0.6 0.7 0.8 µs Video clamping/vertical blanking output: pin CLBL tclamp(CLBL) width of video clamping pulse Vclamp(CLBL) top voltage level of video clamping pulse 4.32 4.75 5.23 V TCclamp temperature coefficient of Vclamp(CLBL) − 4 − mV/K STPSclamp steepness of slopes for clamping pulse RL = 1 MΩ; CL = 20 pF − 50 − ns/V td(HSYNCt-CLBL) delay between trailing edge of horizontal sync and start of video clamping pulse − 130 − ns tclamp1(max) maximum duration of video clamping pulse referenced to end of horizontal sync clamping pulse triggered on trailing edge of horizontal sync; control bit CLAMP = 0; measured at VCLBL = 3 V − − 1.0 µs td(HSYNCl-CLBL) delay between leading edge of clamping pulse triggered horizontal sync and start of on leading edge of video clamping pulse horizontal sync; control bit CLAMP = 1; maximum duration of video measured at VCLBL = 3 V clamping pulse referenced to − 300 − ns − − 0.15 µs 1.7 1.9 2.1 V 260 300 µs tclamp2(max) measured at VCLBL = 3 V end of horizontal sync Vblank(CLBL) top voltage level of vertical blanking pulse tblank(CLBL) width of vertical blanking pulse control bit VBLK = 0 at pins CLBL and HUNLOCK control bit VBLK = 1 220 305 350 395 µs TCblank temperature coefficient of Vblank(CLBL) − 2 − mV/K Vscan(CLBL) output voltage during vertical scan 0.59 0.63 0.67 V TCscan temperature coefficient of Vscan(CLBL) − −2 − mV/K Isink(CLBL) internal sink current 2.4 − − mA IL(CLBL) external load current − − −3.0 mA 1999 Jul 13 notes 1 and 2 ICLBL = 0 16 Philips Semiconductors Product specification I2C-bus autosync deflection controller for PC monitors SYMBOL PARAMETER TDA4856 CONDITIONS MIN. TYP. MAX. UNIT Horizontal oscillator: pins HCAP and HREF ffr(H) free-running frequency without RHBUF = ∞; PLL1 action (for testing only) RHREF = 2.4 kΩ; CHCAP = 10 nF; note 3 30.53 31.45 32.39 kHz ∆ffr(H) spread of free-running frequency (excluding spread of external components) − − ±3.0 % TCfr temperature coefficient of free-running frequency −100 0 +100 10−6/K fH(max) maximum oscillator frequency − − 130 kHz VHREF voltage at input for reference current 2.43 2.55 2.68 V − − 250 mV Unlock blanking detection: pin HUNLOCK Vscan(HUNLOCK) low level of HUNLOCK saturation voltage in case of locked PLL1; internal sink current = 1 mA Vblank(HUNLOCK) blanking level of HUNLOCK external load current = 0 0.9 1 1.1 V TCblank temperature coefficient of Vblank(HUNLOCK) − −0.9 − mV/K TCsink temperature coefficient of Isink(HUNLOCK) − 0.15 − %/K Isink(int) internal sink current for blanking pulses; PLL1 locked 1.4 2.0 2.6 mA IL(HUNLOCK) maximum external load current VHUNLOCK = 1 V − − −2 mA IL leakage current VHUNLOCK = 5 V in case of unlocked PLL1 and/or protection active − − ±5 µA − − 25 % − 40 80 ms − 15 − µA PLL1 phase comparator and frequency-locked loop: pins HPLL1 and HBUF tW(HSYNC)(max) maximum width of horizontal sync pulse (referenced to line period) tlock(HPLL1) total lock-in time of PLL1 Ictrl(HPLL1) control currents notes 4 and 5 locked mode; level 1 − 145 − µA minimum horizontal frequency − 2.55 − V maximum horizontal frequency − 0.5 − V locked mode; level 2 VHBUF 1999 Jul 13 buffered f/v voltage at HBUF (pin 27) 17 Philips Semiconductors Product specification I2C-bus autosync deflection controller for PC monitors SYMBOL PARAMETER TDA4856 CONDITIONS MIN. TYP. MAX. UNIT Phase adjustments and corrections via PLL1 and PLL2 HPOS HPINBAL HPARAL HMOIRE HMOIREoff register HPOS = 0 − −13 − % register HPOS = 127 − 0 − % register HPOS = 255 − 13 − % register HPINBAL = 0; note 6 − −1.2 − % register HPINBAL = 63; note 6 − 1.2 − % register HPINBAL = 32; note 6 − 0.02 − % register HPARAL = 0; note 6 − −1.2 − % register HPARAL = 63; note 6 − 1.2 − % register HPARAL = 32; note 6 − 0.02 − % relative modulation of horizontal position by 0.5fH; phase alternates with 0.5fV register HMOIRE = 0; control bit MOD = 0 − 0 − % register HMOIRE = 63; control bit MOD = 0 − 0.07 − % moire cancellation off control bit MOD = 1 − 0 − % 36 − − % − 7 − % horizontal position (referenced to horizontal period) horizontal pin unbalance correction via HPLL2 (referenced to horizontal period) horizontal parallelogram correction (referenced to horizontal period) PLL2 phase detector: pins HFLB and HPLL2 φPLL2 PLL2 control (advance of maximum advance; horizontal drive with respect to register HPINBAL = 32; middle of horizontal flyback) register HPARAL = 32 minimum advance; register HPINBAL = 32; register HPARAL = 32 Ictrl(PLL2) PLL2 control current − 75 − µA ΦPLL2 relative sensitivity of PLL2 phase shift related to horizontal period − 28 − mV/% VPROT(HPLL2)(max) maximum voltage for PLL2 protection mode/soft start − 4.6 − V Ich(HPLL2) charge current for external capacitor during soft start VHPLL2 < 3.7 V − 1 − µA Idch(HPLL2) discharge current for external capacitor during soft down VHPLL2 < 3.7 V − −1 − µA 1999 Jul 13 18 Philips Semiconductors Product specification I2C-bus autosync deflection controller for PC monitors SYMBOL PARAMETER TDA4856 CONDITIONS MIN. TYP. MAX. UNIT HORIZONTAL FLYBACK INPUT: PIN HFLB Vpos(HFLB) positive clamping level IHFLB = 5 mA − 5.5 − V Vneg(HFLB) negative clamping level IHFLB = −1 mA − −0.75 − V Ipos(HFLB) positive clamping current − − 6 mA Ineg(HFLB) negative clamping current − − −2 mA Vsl(HFLB) slicing level − 2.8 − V IHDRV = 20 mA − − 0.3 V IHDRV = 60 mA − − 0.8 V VHDRV = 16 V − − 10 µA IHDRV = 20 mA; 42 fH = 31.45 kHz; see Fig.16 45 48 % IHDRV = 20 mA; fH = 58 kHz; see Fig.16 45.5 48.5 51.5 % IHDRV = 20 mA; fH = 110 kHz; see Fig.16 49 52 55 % 6.22 6.39 6.56 V Output stage for line driver pulses: pin HDRV OPEN-COLLECTOR OUTPUT STAGE Vsat(HDRV) saturation voltage ILO(HDRV) output leakage current AUTOMATIC VARIATION OF DUTY CYCLE tHDRV(OFF)/tH relative tOFF time of HDRV output; measured at VHDRV = 3 V; HDRV duty cycle is modulated by the relation IHREF/IVREF X-ray protection: pin XRAY VXRAY(sl) slicing voltage level for latch tW(XRAY)(min) minimum width of trigger pulse Ri(XRAY) input resistance at XRAY (pin 2) XRAYrst reset of X-ray latch − − 30 µs VXRAY < 6.38 V + VBE 500 − − kΩ VXRAY > 6.38 V + VBE − 5 − kΩ standby mode − 5 − kΩ pin 9 open-circuit or connected to GND set control bit SOFTST via I2C-bus pin 9 connected to VCC via switch off VCC, then re-apply VCC RXSEL VCC(XRAY)(min) minimum supply voltage for correct function of the X-ray latch pin 9 connected to VCC via − RXSEL − 4 V VCC(XRAY)(max) maximum supply voltage for reset of the X-ray latch pin 9 connected to VCC via 2 RXSEL − − V RXSEL external resistor at pin 9 no reset via I2C-bus − 130 kΩ 1999 Jul 13 19 56 Philips Semiconductors Product specification I2C-bus autosync deflection controller for PC monitors SYMBOL PARAMETER TDA4856 CONDITIONS MIN. TYP. MAX. UNIT Vertical oscillator [oscillator frequency in application without adjustment of free-running frequency ffr(V)] ffr(V) free-running frequency RVREF = 22 kΩ; CVCAP = 100 nF fcr(V) vertical frequency catching range constant amplitude; note 7 50 VVREF voltage at reference input for vertical oscillator td(scan) delay between trigger pulse and start of ramp at VCAP (pin 24) (width of vertical blanking pulse) currents of amplitude control IVAGC CVAGC 42 43.3 Hz − 160 Hz − 3.0 − V control bit VBLK = 0 220 260 300 µs control bit VBLK = 1 305 350 395 µs control bit AGCDIS = 0 ±120 ±200 ±300 µA control bit AGCDIS = 1 − 0 − µA 150 − 220 nF external capacitor at VAGC (pin 22) 40 Differential vertical current outputs ADJUSTMENT OF VERTICAL SIZE INCLUDING VGA AND EHT COMPENSATION; see Figs 3 and 4 VGAIN VSIZE VSIZEVGA VSMODEHT Ii(VSMOD) register VGAIN = 0; register VSIZE = 127; bit VOVSCN = 0; note 8 − 70 − % register VGAIN = 63; register VSIZE = 127; bit VOVSCN = 0; note 8 − 100 − % vertical size (size) without VGA register VSIZE = 0; overscan (referenced to register VGAIN = 63; nominal vertical size) bit VOVSCN = 0; note 8 − 60 − % register VSIZE = 127; register VGAIN = 63; bit VOVSCN = 0; note 8 − 100 − % register VSIZE = 0; register VGAIN = 63; bit VOVSCN = 1; note 8 − 70 − % register VSIZE = 127; register VGAIN = 63; bit VOVSCN = 1; note 8 115.9 116.8 117.7 % EHT compensation on vertical size via VSMOD (pin 21) (referenced to 100% vertical size) IVSMOD = 0 − 0 − % IVSMOD = −120 µA − −7 − % input current (pin 21) VSMOD = 0 − 0 − µA VSMOD = −7% − −120 − µA vertical size (gain) without VGA overscan (referenced to nominal vertical size) vertical size with VGA overscan (referenced to nominal vertical size) Ri(VSMOD) input resistance 300 − 500 Ω Vref(VSMOD) reference voltage at input − 5.0 − V 1999 Jul 13 20 Philips Semiconductors Product specification I2C-bus autosync deflection controller for PC monitors SYMBOL fro(VSMOD) PARAMETER TDA4856 CONDITIONS MIN. TYP. MAX. UNIT IVSMOD = −60 µA + 15 µA (RMS value) 1 − − MHz register VOFFS = 0 − −4 − % register VOFFS = 15 − 4 − % register VOFFS = 8 − 0.25 − % register VPOS = 0 − −11.5 − % register VPOS = 127 − 11.5 − % register VPOS = 64 − 0.09 − % register VLIN = 0; control bit VSC = 0; note 8 − 2 − % 46 − % − 0 − % − − ±0.7 % register VLINBAL = 0; note 8 −1.85 −1.40 −0.95 % register VLINBAL = 15; note 8 0.95 1.40 1.85 % register VLINBAL = 8; note 8 − 0.08 − % modulation of vertical picture position by 1⁄2 vertical frequency (related to 100% vertical size) register VMOIRE = 0; control bit MOD = 0 − 0 − % register VMOIRE = 63; control bit MOD = 0 − 0.08 − % moire cancellation off control bit MOD = 1 − 0 − % roll-off frequency (−3 dB) ADJUSTMENT OF VERTICAL POSITION (see Fig.5) VOFFS VPOS vertical position (referenced to 100% vertical size) vertical position (referenced to 100% vertical size) ADJUSTMENT OF VERTICAL LINEARITY; see Fig.6 VLIN vertical linearity (S-correction) register VLIN = 15; control − bit VSC = 0; note 8 register VLIN = X; control bit VSC = 1; note 8 δVLIN symmetry error of S-correction maximum VLIN ADJUSTMENT OF VERTICAL LINEARITY BALANCE; see Fig.7 VLINBAL VMOIRE vertical linearity balance (referenced to 100% vertical size) Vertical output stage: pins VOUT1 and VOUT2; see Fig.27 ∆IVOUT(nom)(p-p) nominal differential output current (peak-to-peak value) ∆IVOUT = IVOUT1 − IVOUT2; nominal settings; note 8 0.76 0.85 0.94 mA Io(VOUT)(max) maximum output current at pins VOUT1 and VOUT2 control bit VOVSCN = 1 0.54 0.6 0.66 mA VVOUT allowed voltage at outputs 0 − 4.2 V δIos(vert)(max) maximum offset error of vertical output currents nominal settings; note 8 − − ±2.5 % δIlin(vert)(max) maximum linearity error of vertical output currents nominal settings; note 8 − − ±1.5 % 1999 Jul 13 21 Philips Semiconductors Product specification I2C-bus autosync deflection controller for PC monitors SYMBOL PARAMETER TDA4856 CONDITIONS MIN. TYP. MAX. UNIT EW drive output EW DRIVE OUTPUT STAGE: pin EWDRV; see Figs 8 to 11 Vconst(EWDRV) bottom output voltage at pin EWDRV (internally stabilized) register HPIN = 0; register HTRAP = 32; register HSIZE = 255; control bit VSC = 1 Vo(EWDRV)(max) maximum output voltage note 9 7.0 − − V IL(EWDRV) load current − − ±2 mA TCEWDRV temperature coefficient of output signal − − 600 10−6/K VHPIN(EWDRV) horizontal pincushion − 0.04 − V register HPIN = 63; − control bit VSC = 1; note 8 1.42 − V register HCORT = 0; − control bit VSC = 0; note 8 0.2 − V register HCORT = 63; − control bit VSC = 0; note 8 −0.64 − V register HCORT = X; − control bit VSC = 1; note 8 0 − V register HCORB = 0; − control bit VSC = 0; note 8 0.2 − V register HCORB = 63; − control bit VSC = 0; note 8 −0.64 − V register HCORB = X; − control bit VSC = 1; note 8 0 − V − −0.5 − V register HTRAP = 0; note 8 − 0.5 − V register HTRAP = 32; note 8 − −0.01 − V register HSIZE = 255; note 8 − 0.13 − V 3.6 − V VHCORT(EWDRV) VHCORB(EWDRV) VHTRAP(EWDRV) VHSIZE(EWDRV) horizontal corner correction at top of picture horizontal corner correction at bottom of picture register HPIN = 0; control bit VSC = 1; note 8 horizontal trapezium correction register HTRAP = 63; note 8 horizontal size 1.05 register HSIZE = 0; note 8 − VHEHT(EWDRV) Ii(HSMOD) 1.2 1.35 V EHT compensation on horizontal size via HSMOD (pin 31) IHSMOD = 0; note 8 − 0.02 − V IHSMOD = −120 µA; note 8 − 0.69 − V input current (pin 31) VHEHT = 0.02 V − 0 − µA VHEHT = 0.69 V − −120 − µA 300 − 500 Ω Ri(HSMOD) input resistance Vref(HSMOD) reference voltage at input IHSMOD = 0 − 5.0 − V fro(HSMOD) roll-off frequency (−3 dB) IHSMOD = −60 µA + 15 µA (RMS) 1 − − MHz 1999 Jul 13 22 Philips Semiconductors Product specification I2C-bus autosync deflection controller for PC monitors SYMBOL PARAMETER TDA4856 CONDITIONS MIN. TYP. MAX. UNIT TRACKING OF EWDRV OUTPUT SIGNAL WITH HORIZONTAL FREQUENCY PROPORTIONAL VOLTAGE fH(MULTI) horizontal frequency range for tracking 15 − 80 kHz VPAR(EWDRV) parabola amplitude at EWDRV IHREF = 1.052 mA; (pin 11) fH = 31.45 kHz; control bit FHMULT = 1; note 10 − 0.72 − V IHREF = 2.341 mA; fH = 70 kHz; control bit FHMULT = 1; note 10 − 1.42 − V function disabled; control bit FHMULT = 0; note 10 − 1.42 − V − − 8 % register HPARAL = 0; note 8 − −0.825 − V register HPARAL = 63; note 8 − 0.825 − V register HPARAL = 32; note 8 − 0.05 − V register HPINBAL = 0; note 8 − −1.0 − V register HPINBAL = 63; note 8 − 1.0 − V register HPINBAL = 32; note 8 − 0.05 − V LEEWDRV linearity error of horizontal frequency tracking Output for asymmetric EW corrections: pin ASCOR VHPARAL(ASCOR) VHPINBAL(ASCOR) vertical sawtooth voltage for EW parallelogram correction vertical parabola for pin unbalance correction Vo(ASCOR)(max)(p-p) maximum output voltage swing (peak-to-peak value) − 4 − V Vo(ASCOR)(max) maximum output voltage − 6.5 − V Vc(ASCOR) centre voltage − 4.0 − V Vo(ASCOR)(min) minimum output voltage − 1.9 − V Io(ASCOR)(max) maximum output current VASCOR ≥ 1.9 V − −1.5 − mA Io(sink)(ASCOR)(max) maximum output sink current VASCOR ≥ 1.9 V − 50 − µA register HFOCAD = 0 − 300 − ns register HFOCAD = 1 − 350 − ns register HFOCAD = 2 − 400 − ns register HFOCAD = 3 Focus section: pin FOCUS; see Figs 15 and 28 tprecor pre-correction of phase for horizontal focus parabola − 450 − ns tW(hfb)(min) minimum horizontal flyback pulse width 1.9 − − µs tW(hfb)(max) maximum horizontal flyback pulse width − − 5.5 µs 1999 Jul 13 23 Philips Semiconductors Product specification I2C-bus autosync deflection controller for PC monitors SYMBOL PARAMETER tW(hfb)(off) minimum width of horizontal flyback pulse for operation without pre-correction VHFOCUS(p-p) amplitude of horizontal focus parabola (peak-to-peak value) amplitude of vertical parabola (peak-to-peak value) VVFOCUS(p-p) TDA4856 CONDITIONS MIN. TYP. MAX. UNIT − 7.5 − µs register HFOCUS = 0 − 0.06 − V register HFOCUS = 31 − 3.3 − V register VFOCUS = 0; note 8 − 0.02 − V register VFOCUS = 15; note 8 − 1.1 − V Vo(FOCUS)(max) maximum output voltage IFOCUS = 0 6.15 6.4 6.65 V Vo(FOCUS)(min) minimum output voltage IFOCUS = 0 1.0 1.3 1.6 V Io(FOCUS)(max) maximum output current ±1.5 − − mA CL(FOCUS)(max) maximum capacitive load − − 20 pF B+ control section; see Figs 22 and 23 TRANSCONDUCTANCE AMPLIFIER: PINS BIN AND BOP Vi(BIN) input voltage 0 − 5.25 V Ii(BIN)(max) maximum input current − − ±1 µA Vref(int) reference voltage at internal non-inverting input of OTA 2.37 2.5 2.58 V Vo(BOP)(min) minimum output voltage − − 0.5 V Vo(BOP)(max) maximum output voltage Io(BOP)(max) maximum output current gm(OTA) transconductance of OTA Gv(ol) open-loop voltage gain CBOP(min) minimum value of capacitor at BOP IBOP < 1 mA 5.0 5.3 5.6 V − ±500 − µA note 11 30 50 70 mS note 12 − 86 − dB 10 − − nF VOLTAGE COMPARATOR: PIN BSENS Vi(BSENS) voltage range of positive comparator input 0 − 5 V Vi(BOP) voltage range of negative comparator input 0 − 5 V IL(BSENS)(max) maximum leakage current discharge disabled − − −2 µA note 13 20 − − mA OPEN-COLLECTOR OUTPUT STAGE: PIN BDRV Io(BDRV)(max) maximum output current ILO(BDRV) output leakage current VBDRV = 16 V − − 3 µA Vsat(BDRV) saturation voltage IBDRV < 20 mA − − 300 mV toff(BDRV)(min) minimum off-time − 250 − ns td(BDRV-HDRV) delay between BDRV pulse and HDRV pulse − 500 − ns 1999 Jul 13 measured at VHDRV = VBDRV = 3 V 24 Philips Semiconductors Product specification I2C-bus autosync deflection controller for PC monitors SYMBOL PARAMETER TDA4856 CONDITIONS MIN. TYP. MAX. UNIT BSENS DISCHARGE CIRCUIT: PIN BSENS VSTOP(BSENS) discharge stop level capacitive load; IBSENS = 0.5 mA 0.85 1.0 1.15 V Idch(BSENS) discharge current VBSENS > 2.5 V 4.5 6.0 7.5 mA Vth(BSENS)(restart) threshold voltage for restart fault condition 1.2 1.3 1.4 V CBSENS(min) minimum value of capacitor at BSENS (pin 4) 2 − − nF Internal reference, supply voltage, soft start and protection VCC(stab) external supply voltage for complete stabilization of all internal references 9.2 − 16 V ICC supply current − 70 − mA ICC(stb) standby supply current STDBY = 1; VPLL2 < 1 V; 3.5 V < VCC < 16 V − 9 − mA PSRR power supply rejection ratio of internal supply voltage f = 1 kHz 50 − − dB VCC(blank) supply voltage level for activation of continuous blanking VCC decreasing from 12 V 8.2 8.6 9.0 V VCC(blank)(min) minimum supply voltage level for function of continuous blanking VCC decreasing from 12 V 2.5 3.5 4.0 V Von(VCC) supply voltage level for activation of HDRV, BDRV, VOUT1, VOUT2 and HUNLOCK VCC increasing from below 7.9 typical 8.1 V 8.3 8.7 V Voff(VCC) supply voltage level for deactivation of BDRV, VOUT1, VOUT2 and HUNLOCK; also sets register SOFTST VCC decreasing from above typical 8.3 V 7.7 8.1 8.5 V THRESHOLDS DERIVED FROM HPLL2 VOLTAGE VHPLL2(blank)(ul) upper limit voltage for continuous blanking − 4.6 − V VHPLL2(bduty)(ul) upper limit voltage for variation of BDRV duty cycle − 4.0 − V VHPLL2(bduty)(ll) lower limit voltage for variation of BDRV duty cycle − 3.2 − V VHPLL2(hduty)(ul) upper limit voltage for variation of HDRV duty cycle − 3.2 − V VHPLL2(hduty)(ll) lower limit voltage for variation of HDRV duty cycle − 1.8 − V VHPLL2(stb)(ul) upper limit voltage for standby voltage − 1 − V 1999 Jul 13 25 Philips Semiconductors Product specification I2C-bus autosync deflection controller for PC monitors TDA4856 Notes 1. For duration of vertical blanking pulse see subheading ‘Vertical oscillator [oscillator frequency in application without adjustment of free-running frequency ffr(V)]’. 2. Continuous blanking at CLBL (pin 16) will be activated, if one of the following conditions is true: a) No horizontal flyback pulses at HFLB (pin 1) within a line b) X-ray protection is triggered c) Voltage at HPLL2 (pin 30) is low during soft start d) Supply voltage at VCC (pin 10) is low e) PLL1 unlocked while frequency-locked loop is in search mode. 3. Oscillator frequency is fmin when no sync input signal is present (continuous blanking at pins 16 and 17). 4. Loading of HPLL1 (pin 26) is not allowed. 5. Voltage at HPLL1 (pin 26) is fed to HBUF (pin 27) via a buffer. Disturbances caused by horizontal sync are removed by an internal sample-and-hold circuit. 6. All vertical and EW adjustments according note 8, but VSIZE = 80% (register VSIZE = 63, VGAIN = 63 and control bit VOVSCN = 0). 7. Value of resistor at VREF (pin 23) may not be changed. 8. All vertical and EW adjustments are specified at nominal vertical settings; unless otherwise specified, which means: a) VSIZE = 100% (register VSIZE = 127, VGAIN = 63 and control bit VOVSCN = 0) b) VSMOD = 0 (no EHT compensation) c) VPOS centred (register VPOS = 64) d) VLIN = 0 (register VLIN = X and control bit VSC = 1) e) VLINBAL = 0 (register VLINBAL = 8) f) FHMULT = 0 g) HPARAL = 0 (register HPARAL = 32) h) HPINBAL = 0 (register HPINBAL = 32) i) Vertical oscillator synchronized. 9. The output signal at EWDRV (pin 11) may consist of horizontal pincushion + corner correction + DC shift + trapezium correction. If the control bit VOVSCN is set, and the VPOS adjustment is set to an extreme value, the tip of the parabola may be clipped at the upper limit of the EWDRV output voltage range. The waveform of corner correction will clip if the vertical sawtooth adjustment exceeds 110% of the nominal setting. 10. If fH tracking is enabled, the amplitude of the complete EWDRV output signal (horizontal pincushion + corner correction + DC shift + trapezium) will be changed proportional to IHREF. The EWDRV low level of 1.2 V remains fixed. 11. First pole of transconductance amplifier is 5 MHz without external capacitor (will become the second pole, if the OTA operates as an integrator). V BOP 12. Open-loop gain is -------------- at f = 0 with no resistive load and CBOP = 10 nF [from BOP (pin 3) to GND]. V BIN 13. The recommended value for the pull-up resistor BDRV (pin 6) is 1 kΩ. 1999 Jul 13 26 Philips Semiconductors Product specification I2C-bus autosync deflection controller for PC monitors TDA4856 Vertical and EW adjustments MBG590 handbook, halfpage MGS274 handbook, halfpage IVOUT1 IVOUT1 IVOUT2 IVOUT2 ∆l2 ∆l1(1) ∆I1(1) ∆I2 t t (1) ∆I1 is the maximum amplitude setting at register VSIZE = 127, register VGAIN = 63, control bit VOVSCN = 0. (1) ∆I1 is the maximum amplitude setting at register VSIZE = 127, register VGAIN = 63, control bit VOVSCN = 0. ∆I 2 ∆I 2 VSIZE = -------- × 100% , VSMOD = -------- × 100% ∆I 1 ∆I 1 ∆I 2 VGAIN = -------- × 100% ∆I 1 Fig.3 Adjustment of vertical size (VSIZE). Fig.4 Adjustment of vertical size (VGAIN). MBG592 handbook, halfpage MBG594 handbook, halfpage IVOUT1 IVOUT1 ∆l2/∆t IVOUT2 IVOUT2 ∆l1(1) ∆l2 ∆l1(1)/∆t t t (1) ∆I1 is the maximum amplitude setting at register VSIZE = 127 and VLIN = 0%. (1) ∆I1 is the maximum amplitude setting at register VSIZE = 127 and register VGAIN = 63. ∆I 1 – ∆I 2 VLIN = ---------------------- × 100% ∆I 1 ∆I 2 – ∆I 1 ∆I 2 – ∆I 1 VPOS = ---------------------- × 100% , VOFFS = ---------------------- × 100% 2 × ∆I 1 2 × ∆I 1 Fig.6 Fig.5 Adjustment of vertical position. 1999 Jul 13 27 Adjustment of vertical linearity (vertical S-correction). Philips Semiconductors Product specification I2C-bus autosync deflection controller for PC monitors MGM068 handbook, halfpage TDA4856 MGM069 handbook, halfpage IVOUT1 VEWDRV IVOUT2 VHPIN(EWDRV) ∆I2 ∆I1(1) t t (1) ∆I1 is the maximum amplitude setting at register VSIZE = 127 and register VOVSCN = 0. ∆I 1 – ∆I 2 VLINBAL = ---------------------- × 100% 2 × ∆I 1 Fig.8 Fig.7 Adjustment of vertical linearity balance. MGM070 handbook, halfpage VEWDRV Adjustment of parabola amplitude at pin EWDRV. MGM071 handbook, halfpage VEWDRV VHCOR(EWDRV) VHTRAP(EWDRV) t t Fig.9 Influence of corner correction at pin EWDRV. 1999 Jul 13 Fig.10 Influence of trapezium at pin EWDRV. 28 Philips Semiconductors Product specification I2C-bus autosync deflection controller for PC monitors MGM072 handbook, halfpage TDA4856 MGM073 handbook, halfpage VASCOR VEWDRV Vc(ASCOR) VHPARAL(ASCOR) VHSIZE(EWDRV) + VHEHT(EWDRV) t t Fig.11 Influence of HSIZE and EHT compensation at pin EWDRV. handbook, halfpage Fig.12 Adjustment of parallelogram at pin ASCOR. MGM074 VASCOR Vc(ASCOR) VHPINBAL(ASCOR) t Fig.13 Adjustment of pin balance at pin ASCOR. 1999 Jul 13 29 Philips Semiconductors Product specification I2C-bus autosync deflection controller for PC monitors TDA4856 Pulse diagrams handbook, full pagewidth 4.0 V automatic trigger level 3.8 V synchronized trigger level vertical oscillator sawtooth at VCAP (pin 24) 1.4 V vertical sync pulse inhibited internal trigger inhibit window (typical 4 ms) vertical blanking pulse at CLBL (pin 16) vertical blanking pulse at HUNLOCK (pin 17) IVOUT1 differential output currents VOUT1 (pin 13) and VOUT2 (pin 12) IVOUT2 7.0 V maximum EW drive waveform at EWDRV (pin 11) DC shift 3.6 V maximum low-level 1.2 V fixed MGM075 Fig.14 Pulse diagram for vertical part. 1999 Jul 13 30 Philips Semiconductors Product specification I2C-bus autosync deflection controller for PC monitors TDA4856 handbook, full pagewidth horizontal oscillator sawtooth at HCAP (pin 29) horizontal sync pulse PLL1 control current at HPLL1 (pin 26) + - video clamping pulse at CLBL (pin 16) triggered on trailing edge of horizontal sync vertical blanking level line flyback pulse at HFLB (pin 1) PLL2 control current at HPLL2 (pin 30) + – PLL2 control range line drive pulse at HDRV (pin 8) 45 to 52% of line period horizontal focus parabola at FOCUS (pin 32) MGS275 Fig.15 Pulse diagram for horizontal part. 1999 Jul 13 31 Philips Semiconductors Product specification I2C-bus autosync deflection controller for PC monitors handbook, full pagewidth TDA4856 MGM077 relative tHDRV(OFF)/tH (%) 52 45 15 30 110 130 f (kHz) H Fig.16 Relative tOFF time of HDRV versus H-frequency. handbook, fullcomposite pagewidth sync (TTL) at HSYNC (pin 15) internal integration of composite sync internal vertical trigger pulse PLL1 control voltage at HPLL1 (pin 26) clamping and blanking pulses at CLBL (pin 16) MGC947 a. Reduced influence of vertical sync on horizontal phase. handbook, full pagewidth composite sync (TTL) at HSYNC (pin 15) clamping and blanking pulses at CLBL (pin 16) MBG596 b. Generation of video clamping pulses during vertical sync with serration pulses. Fig.17 Pulse diagrams for composite sync applications. 1999 Jul 13 32 Philips Semiconductors Product specification I2C-bus autosync deflection controller for PC monitors TDA4856 I2C-BUS PROTOCOL Data format Table 4 S(1) Data format SLAVE ADDRESS(2) A(3) SUB-ADDRESS(4) A(3) DATA(5) A(3) P(6) Notes 1. S = START condition. 2. SLAVE ADDRESS (MAD) = 1000 1100. 3. A = acknowledge, generated by the slave. No acknowledge, if the supply voltage is below 8.2 V for start-up and 8.0 V for shut-down procedure. 4. SUBADDRESS (SAD). 5. DATA byte. If more than 1 byte of DATA is transmitted, then no auto-increment of the significant subaddress is performed. 6. P = STOP condition. It should be noted that clock pulses according to the 400 kHz specification are accepted for 3.3 and 5 V applications (reference level = 1.8 V). This mode should be used if many register values have to be changed subsequently, i.e. during start-up, mode change, etc., and while there is no picture visible on the screen (blanked). The number of transmissions per V-period is not limited. Default register values after power-up are random. All registers have to be preset via software before the soft start is enabled. Buffered mode Important: If register contents are changed during the vertical scan, this might result in a visible interference on the screen. The cause for this interference is the abrupt change of picture geometry which takes effect at random locations within the visible picture. To avoid this kind of interference, at least the adjustment of some critical geometry parameters should be synchronized with the vertical flyback. The TDA4856 offers a feature to synchronize any I2C-bus adjustment with the internal vertical flyback pulse. For this purpose the IC offers two different modes for the handling of I2C-bus data: The buffered mode is selected by setting the MSB of the I2C-bus register subaddress to logic 1. This mode is designed to avoid visible interferences on the screen during the I2C-bus adjustments. This mode should be used, if a single register has to be changed while the picture is visible, so i.e. for user adjustments. One received I2C-bus data byte is stored in an internal 8-bit buffer before it is passed to the DAC section. The first internal vertical blanking pulse (VBL) after end of transmission is used to synchronize the adjustment change with the vertical flyback. So the actual change of the picture size, position, geometry, etc. will take place during the vertical flyback period, and will thus be invisible. • Direct mode • Buffered mode. Direct mode The IC gives acknowledge for chip address, subaddress and data of a buffered transmission. Only one I2C-bus transmission is accepted after each vertical blank. After one buffered transmission, the IC gives no acknowledge for further transmissions until next VBL pulse has occurred. The buffered mode is disabled while the IC is in standby mode. The direct mode is selected by setting the MSB of the I2C-bus register subaddress to logic 0. Any I2C-bus command is executed immediately after it was received, so the adjustment takes effect immediately after the end of I2C-bus transmission. 1999 Jul 13 33 Philips Semiconductors Product specification I2C-bus autosync deflection controller for PC monitors TDA4856 List of I2C-bus controlled switches I2C-bus data can be transmitted in direct or buffered mode and is defined by the MSB of the register subaddress: • SAD1 is the register subaddress to be used for transmissions in direct mode • SAD2 is the register subaddress to be used for transmissions in buffered mode. Table 5 Controlled switches; notes 1 and 2 CONTROL BIT BLKDIS REGISTER ASSIGNMENT SAD1 SAD2 (HEX) (HEX) D7 D6 D5 D4 D3 D2 D1 D0 FUNCTION 0: vertical, protection and horizontal unlock blanking available on pins CLBL and HUNLOCK 0A 8A X D6 # # # # # # 0B 8B # D6 # # # # # # 0B 8B D7 # # # # # # # 02 82 X D6 # # # # # # 08 88 D7 # # # # # # # 0F 8F X D6 # # # # # # 09 89 # D6 # # # # # # 09 89 D7 # # # # # # # 04 84 X D6 # # # # # # 1A 9A # X X X X X # D0 1A 9A # X X X X X D1 # 1: only vertical and protection blanking available on pins CLBL and HUNLOCK AGCDIS 0: AGC in vertical oscillator active 1: AGC in vertical oscillator inhibited FHMULT 0: EW output independent of horizontal frequency 1: EW output tracks with horizontal frequency VSC 0: VLIN, HCORT and HCORB adjustments enabled 1: VLIN, HCORT and HCORB adjustments forced to centre value MOD 0: horizontal and vertical moire cancellation enabled 1: horizontal and vertical moire cancellation disabled VOVSCN 0: vertical size 100% 1: vertical size 116.8% for VGA350 CLAMP 0: trailing edge for horizontal clamp 1: leading edge for horizontal clamp VBLK 0: vertical blanking = 260 µs 1: vertical blanking = 340 µs ACD 0: ASCOR disconnected from PLL2 1: ASCOR internally connected with PLL2 STDBY(3) 0: internal power supply enabled 1: internal power supply disabled SOFTST(3) 0: soft start not released (pin HPLL2 pulled to ground) 1: soft start is released (power-up via pin HPLL2) Notes 1. X = don’t care. 2. # = this bit is occupied by another function. If the register is addressed, the bit values for both functions must be transferred. 3. Bits STDBY and SOFTST can be reset by the internal protection circuit. 1999 Jul 13 34 This text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here in _white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here inThis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader. white to force landscape pages to be ... • SAD1 is the register subaddress to be used for transmissions in direct mode • SAD2 is the register subaddress to be used for transmissions in buffered mode. Table 6 Controlled functions; notes 1 and 2 REGISTER ASSIGNMENT SAD1 SAD2 CONTROL (HEX) (HEX) D7 D6 D5 D4 D3 D2 D1 D0 BIT FUNCTION TRACKS WITH 35 BITS Horizontal size HSIZE 8 01 81 D7 D6 D5 D4 D3 D2 D1 D0 − 0.1 to 3.6 V − Horizontal position HPOS 8 07 87 D7 D6 D5 D4 D3 D2 D1 D0 − ±13% of horizontal period − Horizontal pincushion HPIN 6 0F 8F X # D5 D4 D3 D2 D1 D0 − 0 to 1.42 V VSIZE, VOVSCN, VPOS, HSIZE and HSMOD Horizontal trapezium correction HTRAP 6 03 83 X X D5 D4 D3 D2 D1 D0 − ±500 mV (p-p) VSIZE, VOVSCN, VPOS, HSIZE and HSMOD Horizontal corner correction at top of picture HCORT 6 04 84 X # D5 D4 D3 D2 D1 D0 VSC +15 to −46% of parabola amplitude VSIZE, VOVSCN, VPOS, HSIZE and HSMOD Horizontal corner correction at bottom of picture HCORB 6 02 82 X # D5 D4 D3 D2 D1 D0 VSC +15 to −46% of parabola amplitude VSIZE, VOVSCN, VPOS, HSIZE and HSMOD Horizontal parallelogram HPARAL 6 09 89 # # D5 D4 D3 D2 D1 D0 ACD ±1.2% of horizontal period VSIZE, VOVSCN and VPOS EW pin balance HPINBAL 6 0B 8B # # D5 D4 D3 D2 D1 D0 ACD ±1.2% of horizontal period VSIZE, VOVSCN and VPOS VSIZE 7 08 88 # D6 D5 D4 D3 D2 D1 D0 − 60 to 100% VSMOD D6 D5 D4 D3 D2 D1 D0 − ±11.5% VSMOD − 70 to 100% − − ±4% − −2 to −46% VSIZE, VOVSCN, VPOS and VSMOD ±1.4% of 100% vertical size VSIZE, VOVSCN, VPOS and VSMOD Vertical size Vertical position VPOS 7 0D 8D X Vertical gain VGAIN 6 0A 8A X # Vertical offset VOFFS 4 0E 8E # # Vertical linearity VLIN 4 05 85 Vertical linearity balance VLINBAL 4 05 85 D5 D4 D3 D2 D1 D0 # # D7 D6 D5 D4 # # # # D3 D2 D1 D0 # # # # D3 D2 D1 D0 VSC − RANGE Product specification NAME TDA4856 FUNCTION Philips Semiconductors I2C-bus data can be transmitted in direct or buffered mode and is defined by the MSB of the register subaddress: I2C-bus autosync deflection controller for PC monitors 1999 Jul 13 List of I2C-bus controlled functions This text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here in _white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here inThis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader. white to force landscape pages to be ... BITS Moire cancellation via vertical position VMOIRE 6 00 80 X X D5 D4 D3 D2 D1 D0 MOD 0 to 0.08% of vertical amplitude − Moire cancellation via horizontal position HMOIRE 6 06 86 X X D5 D4 D3 D2 D1 D0 MOD 0.07% of horizontal period − Vertical focus VFOCUS 4 0E 8E − 0 to 1.1 V VSIZE, VOVSCN and VPOS Horizontal focus HFOCUS 5 0C 8C − 0 to 3.3 V − Horizontal focus pre-correction HFOCAD 2 0C 8C − 300 to 450 ns − D7 D6 D5 D4 # # D7 D6 X X # # # # D4 D3 D2 D1 D0 # # # # # RANGE Notes 1. X = don’t care. 2. # = this bit is occupied by another function. If the register is addressed, the bit values for both functions must be transferred. Philips Semiconductors FUNCTION TRACKS WITH NAME 36 I2C-bus autosync deflection controller for PC monitors 1999 Jul 13 REGISTER ASSIGNMENT SAD1 SAD2 CONTROL (HEX) (HEX) D7 D6 D5 D4 D3 D2 D1 D0 BIT FUNCTION Product specification TDA4856 Philips Semiconductors Product specification I2C-bus autosync deflection controller for PC monitors TDA4856 Start-up procedure VCC < 8.3 V: START • As long as the supply voltage is too low for correct operation, the IC will give no acknowledge due to internal Power-on reset (POR) L1 Power-down mode (XXXX XXXX) no acknowledge is given by IC all register contents are random • Supply current is 9 mA or less. VCC > 8.3 V VCC > 8.3 V: • The internal POR has ended and the IC is in standby mode L2 Standby mode (XXXX XX01) STDBY = 1 SOFTST = 0 all other register contents are random S 8CH A 1AH A 00H • Control bits STDBY and SOFTST are reset to their start values • All other register contents are random A P • Pin HUNLOCK is at HIGH-level. Setting control bit STDBY = 0: Protection mode (XXXX XX00) • Enables internal power supply STDBY = 0 SOFTST = 0 all other register contents are random • Supply current increases from 9 to 70 mA • When VCC < 8.6 V register SOFTST cannot be set by the I2C-bus S 8CH A SAD A DATA A P • Output stages are disabled, except the vertical output • Pin HUNLOCK is at HIGH-level. Protection mode (XXXX XX00) Setting all registers to defined values: STDBY = 0 SOFTST = 0 registers are pre-set no • Due to the hardware configuration of the IC (no auto-increment) any register setting needs a complete 3-byte I2C-bus data transfer as follows: START - IC address - subaddress - data - STOP. all registers defined? yes S 8CH A 1AH A Setting control bit SOFTST = 1: 02H • Before starting the soft-start sequence a delay of minimum 80 ms is necessary to obtain correct function of the horizontal drive L3 A P Soft-start sequence (XXXX XX10) • HDRV duty cycle increases STDBY = 0 SOFTST = 1 • BDRV duty cycle increases • PLL1 and PLL2 are enabled. Operating mode (XXXX XX10) IC in full operation: STDBY = 0 SOFTST = 1 no change/refresh of data? SOFTST = 0? yes S 8CH A SAD A • Pin HUNLOCK is at LOW-level when PLL1 is locked • Any change of the register content will result in immediate change of the output behaviour no • Setting control bit SOFTST = 0 is the only way (except power-down via pin VCC) to leave the operating mode. yes DATA A P L4 (1) Soft-down sequence: MGL791 • See L4 of Fig.19 for starting the soft-down sequence. (1) See Fig.19. Fig.18 I2C-bus flow for start-up. 1999 Jul 13 37 Philips Semiconductors Product specification I2C-bus autosync deflection controller for PC monitors TDA4856 Protection and standby mode Soft-down sequence: L4 • Start the sequence by setting control bit SOFTST = 0 S 8CH A 1AH A 00H • BDRV duty cycle decreases A P • HDRV duty cycle decreases. Soft-down sequence (XXXX XX00) Protection mode: STDBY = 0 SOFTST = 0 • Pins HDRV and BDRV are floating • Continuous blanking at pin CLBL is active • Pin HUNLOCK is floating Protection mode (XXXX XX00) • PLL1 and PLL2 are disabled STDBY = 0 SOFTST = 0 registers are set • Register contents are kept in internal memory. Protection mode can be left by 3 ways: no STDBY = 1? 1. Entering standby mode by setting control bit SOFTST = 0 and control bit STDBY = 1 no SOFTST = 1? 2. Starting the soft-start sequence by setting control bit SOFTST = 1 (bit STDBY = don’t care); see L3 of Fig.18 for continuation yes yes L3 (1) 3. Decreasing the supply voltage below 8.1 V. S 8CH A 1AH A 01H A P Standby mode: • Set control bit STDBY = 1 Standby mode (XXXX XX01) • Driver outputs are floating (same as protection mode) STDBY = 1 SOFTST = 0 all other register contents are random L2 (1) • Supply current is 9 mA • Only the I2C-bus section and protection circuits are operative • Contents of all registers except the value of bit STDBY and bit SOFTST are lost MGL790 (1) See Fig.18. Fig.19 I2C-bus • See L2 of Fig.18 for continuation. flow for protection and standby mode. 1999 Jul 13 38 Philips Semiconductors Product specification I2C-bus autosync deflection controller for PC monitors handbook, full pagewidth TDA4856 (ANY Mode) VCC < 8.1 V Power-Down Mode VCC no acknowledge is given by IC all register contents are random 8.6 V a soft-down sequency followed by a soft start sequence is generated internally. 8.1 V VCC 8.6 V 8.1 V L1 (1) IC enters standby mode. MGM079 (1) See Fig.18. Fig.20 I2C-bus flow for any mode. Power-down mode Power dip of VCC < 8.6 V: • The soft-down sequence is started first. Normal operation • Then the soft-start sequence is generated internally. Power dip of VCC < 8.1 V or VCC shut-down: I2C-bus transmission • This function is independent from the operating mode, so it works under any condition. chip address S 8CH subaddress A 0XH data A XXH A P A P • All driver outputs are immediately disabled • IC enters standby mode. yes acknowledge was given on data? Standby mode detection Execute data transmission twice to assure that there was no data transfer error. no I2C-bus transmission chip address S yes 8CH subaddress A 0XH data A XXH acknowledge was given on data? no Standby mode MGS276 Fig.21 Possible standby mode detection. 1999 Jul 13 39 Philips Semiconductors Product specification I2C-bus autosync deflection controller for PC monitors TDA4856 APPLICATION INFORMATION VCC handbook, full pagewidth Vi 2 VHDRV VHPLL2 R6(1) 6 SOFT START S 3 VBDRV D2 Q OTA 2.5 V L TR1 R Q INVERTING BUFFER HORIZONTAL OUTPUT STAGE DISCHARGE 1 horizontal flyback pulse D1 5 3 VBIN VBOP 4 R5 4 VBSENS R1 R4 C4 C1 R2 C2 R3 MGM080 CBOP >10 nF EWDRV For f < 50 kHz and C2 < 47 nF calculation formulas and behaviour of the OTA are the same as for an OP. An exception is the limited output current at BOP (pin 3). See Chapter “Characteristics”, Row Head “B+ control section; see Figs 22 and 23”. (1) The recommended value for R6 is 1 kΩ. a. Feedback mode application. handbook, full pagewidth 1 horizontal flyback pulse 2 VHDRV ton 3 VBDRV td(BDRV) toff(min) VBSENS = VBOP VRESTART(BSENS) 4 VBSENS VSTOP(BSENS) MBG600 b. Waveforms for normal operation. c. Waveforms for fault condition. Fig.22 Application and timing for feedback mode. 1999 Jul 13 40 Philips Semiconductors Product specification I2C-bus autosync deflection controller for PC monitors TDA4856 VCC 2 VHDRV VHPLL2 horizontal flyback pulse 1 R4(1) 6 INVERTING BUFFER SOFT START S Q R Q OTA 2.5 V 3 VBDRV HORIZONTAL OUTPUT STAGE EHT transformer D2 5 IMOSFET DISCHARGE 5 EHT adjustment 3 R1 TR1 4 VBOP R2 VBIN R3 D1 4 VBSENS C1 CBSENS MGM081 TR2 power-down >2 nF CBOP > 10 nF (1) The recommended value for R4 is 1 kΩ. a. Forward mode application. handbook, pagewidth 1 full horizontal flyback pulse 2 VHDRV ton 3 VBDRV toff td(BDRV) VBOP (discharge time of CBSENS) VBOP 4 VBSENS VRESTART(BSENS) VSTOP(BSENS) 5 IMOSFET MBG602 b. Waveforms for normal operation. c. Waveforms for fault condition. Fig.23 Application and timing for feed forward mode. 1999 Jul 13 41 Philips Semiconductors Product specification I2C-bus autosync deflection controller for PC monitors TDA4856 Start-up sequence and shut-down sequence MGS277 handbook, full pagewidth VCC 8.6 V continuous blanking off PLL2 soft start/soft-down enabled(1) 8.3 V 3.5 V data accepted from I2C-bus video clamping pulse and vertical outputs enabled if control bit STDBY = 0 continuous blanking activated on pins CLBL and HUNLOCK time a. Start-up sequence. MGS278 handbook, full pagewidth VCC 8.6 V continuous blanking activated on pins CLBL and HUNLOCK PLL2 soft-down sequence is triggered(2) 8.1 V no data accepted from I2C-bus video clamping pulse and vertical outputs disabled 3.5 V continuous blanking disappears time b. Shut-down sequence. (1) See Fig.25a. (2) See Fig.25b. Fig.24 Activation of start-up sequence and shut-down sequence via supply voltage. 1999 Jul 13 42 Philips Semiconductors Product specification I2C-bus autosync deflection controller for PC monitors TDA4856 PLL2 soft start sequence and PLL2 soft-down sequence MGS279 handbook, full pagewidth VHPLL2 4.6 V continuous blanking off PLL2 enabled frequency detector enabled HDRV/HFLB protection enabled BDRV duty cycle has reached nominal value in cr ea se s 4.0 V du ty cy cl e 3.2 V 1.8 V BDRV duty cycle begins to increase HDRV duty cycle has reached nominal value HDRV duty cycle begins to increase time a. PLL2 soft start sequence, if VCC > 8.6 V. MGS280 handbook, full pagewidth VHPLL2 4.6 V continuous blanking activated on pins CLBL and HUNLOCK PLL2 disabled frequency detector disabled HDRV/HFLB protection disabled 4.0 V BDRV duty cycle begins to decrease(1) ty du cy 2.8 V e cl s se ea cr de BDRV floating HDRV duty cycle begins to decrease(1) 1.8 V HDRV floating time b. PLL2 soft-down sequence, if VCC > 8.6 V. (1) HDRV and BDRV are floating for VCC < 8.6 V. Fig.25 Activation of PLL2 soft-start sequence and PLL2 soft-down sequence via the I2C-bus. 1999 Jul 13 43 Philips Semiconductors Product specification I2C-bus autosync deflection controller for PC monitors TDA4856 X-ray latch triggered handbook, full pagewidth VXRAY VHUNLOCK BDRV duty cycle floating HDRV duty cycle floating MGS281 Fig.26 Activation of soft-down sequence via pin XRAY. Vertical linearity error Horizontal focus pre-correction handbook, halfpage handbook, halfpage I (1) VOUT (µA) MBG551 +415 I1(2) 0 I2(3) −415 (1) (2) I3(4) VVCAP (1) (2) (3) (4) IVOUT = IVOUT1 − IVOUT2. I1 = IVOUT at VVCAP = 1.9 V. I2 = IVOUT at VVCAP = 2.6 V. I3 = IVOUT at VVCAP = 3.3 V. MGS282 t precor = 450 ns t precor = 300 ns I1 – I3 Which means: I 0 = -------------2 I2 – I3 I1 – I2 Vertical linearity error = 1 – max -------------- or -------------- I0 I0 (1) Line flyback pulse at HFLB (pin 1). (2) Horizontal focus parabola at FOCUS (pin 32). Fig.27 Definition of vertical linearity error. 1999 Jul 13 Fig.28 Definition of horizontal focus pre-correction. 44 Philips Semiconductors Product specification I2C-bus autosync deflection controller for PC monitors TDA4856 Printed-circuit board layout further connections to other components or ground paths are not allowed 17 18 19 20 22 23 24 25 external components of vertical section 26 27 28 29 30 31 32 external components of horizontal section 21 handbook, full pagewidth pin 25 should be the 'star point' for all small signal components external components of horizontal section no external ground tracks connected here 16 15 14 13 12 10 9 8 7 6 5 4 47 pF 11 TDA4856 2.2 nF 3 2 1 47 nF 100 µF 12 V external components of driver stages B-drive line in parallel to ground only this path may be connected to general ground of PCB MGS283 SMD For optimum performance of the TDA4856 the ground paths must be routed as shown. Only one connection to other grounds on the PCB is allowed. Note: The tracks for HDRV and BDRV should be kept separate. Fig.29 Hints for printed-circuit board (PCB) layout. 1999 Jul 13 45 Philips Semiconductors Product specification I2C-bus autosync deflection controller for PC monitors TDA4856 INTERNAL PIN CONFIGURATION PIN 1 SYMBOL INTERNAL CIRCUIT HFLB 1.5 kΩ 1 7x MBG561 2 XRAY 5 kΩ 2 6.25 V MBG562 3 BOP 5.3 V 3 MBG563 4 BSENS 4 MBG564 1999 Jul 13 46 Philips Semiconductors Product specification I2C-bus autosync deflection controller for PC monitors PIN 5 SYMBOL TDA4856 INTERNAL CIRCUIT BIN 5 MBG565 6 BDRV 6 MBG566 7 PGND 8 HDRV power ground, connected to substrate 8 MGM089 9 XSEL 4 kΩ 9 MBK381 10 VCC 10 MGM090 11 EWDRV 108 Ω 11 108 Ω MBG570 1999 Jul 13 47 Philips Semiconductors Product specification I2C-bus autosync deflection controller for PC monitors PIN 12 13 14 SYMBOL TDA4856 INTERNAL CIRCUIT VOUT2 12 MBG571 13 MBG572 VOUT1 VSYNC 100 Ω 1.4 V 14 2 kΩ 7.3 V MBG573 15 HSYNC 1.28 V 85 Ω 1.4 V 15 7.3 V MBG574 16 CLBL 16 MBG575 1999 Jul 13 48 Philips Semiconductors Product specification I2C-bus autosync deflection controller for PC monitors PIN 17 SYMBOL TDA4856 INTERNAL CIRCUIT HUNLOCK 17 MGM091 18 SCL 18 MGM092 19 SDA 19 MGM093 20 ASCOR 480 Ω 20 MGM094 21 VSMOD 250 Ω 21 5V MGM095 1999 Jul 13 49 Philips Semiconductors Product specification I2C-bus autosync deflection controller for PC monitors PIN 22 SYMBOL TDA4856 INTERNAL CIRCUIT VAGC 22 MBG581 23 VREF 23 3V MBG582 24 VCAP 24 MBG583 25 SGND 26 HPLL1 signal ground 26 4.3 V MGM096 1999 Jul 13 50 Philips Semiconductors Product specification I2C-bus autosync deflection controller for PC monitors PIN 27 SYMBOL TDA4856 INTERNAL CIRCUIT HBUF 5V 27 MGM097 28 HREF 29 HCAP 76 Ω 2.525 V 28 7.7 V 29 MBG585 30 HPLL2 7.7 V 30 HFLB 6.25 V MGM098 1999 Jul 13 51 Philips Semiconductors Product specification I2C-bus autosync deflection controller for PC monitors PIN 31 SYMBOL TDA4856 INTERNAL CIRCUIT HSMOD 250 Ω 5V 31 MGM099 32 FOCUS 120 Ω 32 200 Ω 120 Ω MGM100 Electrostatic discharge (ESD) protection pin 7.3 V pin 7.3 V MBG559 MBG560 Fig.31 ESD protection for pins 2, 3, 5, 18 to 24 and 26 to 32. Fig.30 ESD protection for pins 4, 11 to 13, 16 and 17. 1999 Jul 13 52 Philips Semiconductors Product specification I2C-bus autosync deflection controller for PC monitors TDA4856 PACKAGE OUTLINE SDIP32: plastic shrink dual in-line package; 32 leads (400 mil) SOT232-1 ME seating plane D A2 A A1 L c e Z (e 1) w M b1 MH b 17 32 pin 1 index E 1 16 0 5 10 mm scale DIMENSIONS (mm are the original dimensions) UNIT A max. A1 min. A2 max. b b1 c D (1) E (1) e e1 L ME MH w Z (1) max. mm 4.7 0.51 3.8 1.3 0.8 0.53 0.40 0.32 0.23 29.4 28.5 9.1 8.7 1.778 10.16 3.2 2.8 10.7 10.2 12.2 10.5 0.18 1.6 Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION REFERENCES IEC JEDEC EIAJ ISSUE DATE 92-11-17 95-02-04 SOT232-1 1999 Jul 13 EUROPEAN PROJECTION 53 Philips Semiconductors Product specification I2C-bus autosync deflection controller for PC monitors TDA4856 The total contact time of successive solder waves must not exceed 5 seconds. SOLDERING Introduction to soldering through-hole mount packages The device may be mounted up to the seating plane, but the temperature of the plastic body must not exceed the specified maximum storage temperature (Tstg(max)). If the printed-circuit board has been pre-heated, forced cooling may be necessary immediately after soldering to keep the temperature within the permissible limit. This text gives a brief insight to wave, dip and manual soldering. A more in-depth account of soldering ICs can be found in our “Data Handbook IC26; Integrated Circuit Packages” (document order number 9398 652 90011). Wave soldering is the preferred method for mounting of through-hole mount IC packages on a printed-circuit board. Manual soldering Apply the soldering iron (24 V or less) to the lead(s) of the package, either below the seating plane or not more than 2 mm above it. If the temperature of the soldering iron bit is less than 300 °C it may remain in contact for up to 10 seconds. If the bit temperature is between 300 and 400 °C, contact may be up to 5 seconds. Soldering by dipping or by solder wave The maximum permissible temperature of the solder is 260 °C; solder at this temperature must not be in contact with the joints for more than 5 seconds. Suitability of through-hole mount IC packages for dipping and wave soldering methods SOLDERING METHOD PACKAGE DIPPING DBS, DIP, HDIP, SDIP, SIL WAVE suitable(1) suitable Note 1. For SDIP packages, the longitudinal axis must be parallel to the transport direction of the printed-circuit board. 1999 Jul 13 54 Philips Semiconductors Product specification I2C-bus autosync deflection controller for PC monitors TDA4856 DEFINITIONS Data sheet status Objective specification This data sheet contains target or goal specifications for product development. Preliminary specification This data sheet contains preliminary data; supplementary data may be published later. Product specification This data sheet contains final product specifications. Limiting values Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information Where application information is given, it is advisory and does not form part of the specification. LIFE SUPPORT APPLICATIONS These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such improper use or sale. PURCHASE OF PHILIPS I2C COMPONENTS Purchase of Philips I2C components conveys a license under the Philips’ I2C patent to use the components in the I2C system provided the system conforms to the I2C specification defined by Philips. This specification can be ordered using the code 9398 393 40011. 1999 Jul 13 55 Philips Semiconductors – a worldwide company Argentina: see South America Australia: 3 Figtree Drive, HOMEBUSH, NSW 2140, Tel. +61 2 9704 8141, Fax. +61 2 9704 8139 Austria: Computerstr. 6, A-1101 WIEN, P.O. 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Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights. Printed in The Netherlands 545004/02/pp56 Date of release: 1999 Jul 13 Document order number: 9397 750 04963