PHILIPS TDA9151B

INTEGRATED CIRCUITS
DATA SHEET
TDA9151B
Programmable deflection controller
Preliminary specification
Supersedes data of June 1993
File under Integrated Circuits, IC02
Philips Semiconductors
July 1994
Philips Semiconductors
Preliminary specification
Programmable deflection controller
TDA9151B
FEATURES
General
• 6.75, 13.5 and 27 MHz clock frequency
• Few external components
• Synchronous logic
• I2C-bus controlled
Horizontal deflection
• Easy interfacing
• Phase 2 loop with low jitter
• Low power
• Internal loop filter
• ESD protection
• Dual slicer horizontal flyback input
• Flash detection with restart
• Soft start by I2C-bus
• Two-level sandcastle pulse.
• Over voltage protection/detection with selection and
status bit.
Vertical deflection
EHT correction
• 16-bit precision vertical scan
• Input selection between aquadag or EHT bleeder
• Self adaptive or programmable fixed slope mode
• Internal filter.
• DC coupled deflection to prevent picture bounce
• Programmable fixed compression to 75%
GENERAL DESCRIPTION
• Programmable vertical expansion in the fixed slope
mode
The TDA9151B is a programmable deflection controller
contained in a 20-pin DIP package and constructed using
BIMOS technology. This high performance
synchronization and DC deflection processor has been
especially designed for use in both digital and analog
based TV receivers and monitors, and serves horizontal
and vertical deflection functions for all TV standards. The
TDA9151B uses a line-locked clock at 6.75, 13.5 or
27 MHz, depending on the line frequency and application,
and requires only a few external components. The device
can be programmed in a self-adaptive mode or in a
programmable fixed slope mode. Selection of these
modes and a large number of other functions is fully
programmable via the I2C-bus.
• S-correction can be preset
• S-correction setting independent of the field frequency
• Differential output for high DC stability
• Current source outputs for high EMC immunity
• Programmable de-interlace phase.
East-West correction
• DC coupled EW correction to prevent picture bounce
• 2nd and 4th order geometry correction can be preset
• Trapezium correction
• Geometry correction settings are independent of field
frequency
• Self adaptive Bult generator prevents ringing of the
horizontal deflection
• Current source output for high EMC immunity.
ORDERING INFORMATION
PACKAGE
TYPE NUMBER
TDA9151B
July 1994
PINS
PIN POSITION
MATERIAL
CODE
20
DIP
plastic
SOT146-1
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Philips Semiconductors
Preliminary specification
Programmable deflection controller
TDA9151B
QUICK REFERENCE DATA
SYMBOL
PARAMETER
VCC
supply voltage
ICC
supply current
Ptot
Tamb
CONDITIONS
MIN.
TYP.
MAX.
UNIT
7.2
8.0
8.8
V
−
27
−
mA
total power dissipation
−
220
−
mW
operating ambient temperature
−25
−
+70
°C
V14
line-locked clock (LLC) logic level
−
TTL
−
fclk = 6.75 MHz
Inputs
V13
horizontal sync (HA) logic level
−
TTL
−
V12
vertical sync (VA) logic level
−
TTL
−
V5
line-locked clock select (LLCS)
logic level
−
CMOS 5 V −
V18
serial clock (SCL) logic level
−
CMOS 5 V −
V17
serial data input (SDA) logic level
V1
horizontal flyback (HFB) phase
slicing level
note 1
−
CMOS 5 V −
FBL = logic 0
−
3.9
−
V
FBL = logic 1
−
1.3
−
V
V1
horizontal flyback (HFB) blanking
slicing level
−
100
−
mV
V3
over voltage protection (PROT)
level
−
3.9
−
V
V9
EHT flash detection level
−
1.5
−
V
−
−
0.5
V
475
510
µA
Outputs
V20
horizontal output (HOUT) voltage
(open drain)
I20 = 10 mA
I11−I10(M)
vertical differential (VOUTA, B)
output current (peak value)
vertical amplitude = 100%; 440
I8 = −120 µA; note 2
V10,11
vertical output voltage
0
−
3.9
V
I6(M)
EW (EWOUT) total output current I8 = −120 µA
(peak value)
−
−
930
µA
V6
EW (EWOUT) output voltage
1.0
−
5.5
V
SANDCASTLE OUTPUT LEVELS (DSC)
V2
base voltage level
−
0.5
−
V
V2
horizontal and vertical blanking
voltage level
−
2.5
−
V
V2
video clamping voltage level
−
4.5
−
V
0
−
VCC
V
HORIZONTAL OFF-CENTRE SHIFT (OFCS)
V19
output voltage
I19 = 2 mA
Notes
1. Hard wired to ground or VCC is highly recommended.
2. DAC values: vertical amplitude = 31; EHT = 0; SHIFT = 3; SCOR = 0.
July 1994
3
Philips Semiconductors
Preliminary specification
Programmable deflection controller
TDA9151B
BLOCK DIAGRAM
Fig.1 Block diagram.
July 1994
4
Philips Semiconductors
Preliminary specification
Programmable deflection controller
TDA9151B
PINNING
SYMBOL
PIN
DESCRIPTION
HFB
1
horizontal flyback input
DSC
2
display sandcastle input/output
PROT
3
over voltage protection input
AGND
4
analog ground
LLCS
5
line-locked clock selection input
EWOUT
6
east-west geometry output
EHT
7
EHT compensation
RCONV
8
external resistive conversion
FLASH
9
flash detection input
VOUTB
10
vertical output B
VOUTA
11
vertical output A
VA
12
vertical information input
HA
13
horizontal information input
LLC
14
line-locked clock input
DGND
15
digital ground
VCC
16
supply input (+8 V)
SDA
17
serial data input/output
SCL
18
serial clock input
OFCS
19
off-centre shift output
HOUT
20
horizontal output
Fig.2 Pin configuration.
present the outputs will be switched off and all operations
discarded (if the LLC is not present the line drive will be
inhibited within 2 µs, the EW output current will drop to
zero and the vertical output current will drop to 20% of the
adjusted value within 100 µs). The SDA and SCL inputs
meet the I2C-bus specification, the other three inputs are
TTL compatible.
FUNCTIONAL DESCRIPTION
Input signals (pins 12, 13, 14, 17 and 18)
The TDA9151B requires three signals for minimum
operation (apart from the supply). These signals are the
line-locked clock (LLC) and the two I2C-bus signals (SDA
and SCL). Without the LLC the device will not operate
because the internal synchronous logic uses the LLC as
the system clock.
The LLC frequency can be divided-by-two internally by
connecting LLCS (pin 5) to ground thereby enabling the
prescaler.
I2C-bus transmissions are required to enable the device to
perform its required tasks. Once started the IC will use the
HA and/or VA inputs for synchronization. If the LLC is not
July 1994
The LLC timing is given in the Chapter “Characteristics”.
5
Philips Semiconductors
Preliminary specification
Programmable deflection controller
TDA9151B
• Logic 0:
I2C-bus commands
– after a successful read of the status byte.
Slave address: 8C HEX = 1000110X BIN
READ MODE
PROT is the over voltage detection for the scaled EHT
input:
The format of the status byte is: PON PROT 0 0 0 0 0 0
• Logic 1:
– if the scaled EHT rises above the reference value of
3.9 V
Where:
PON is the status bit for power-on reset (POR) and after
power failure:
• Logic 0:
– after a successful read of the status byte and EHT
<3.9 V.
• Logic 1:
– after the first POR and after power failure; also set to
1 after a severe voltage dip that may have disturbed
the various settings
Remark: a read action is considered successful when an
End Of Data signal has been detected (i.e. no master
acknowledge).
– POR 1 to 0 transition, VCC = 6.25 V (typ.)
– POR 0 to 1 transition, VCC = 5.75 V (typ.)
Table 1 Write mode with auto increment; subaddress and data byte format.
DATA BYTE
FUNCTION
SUBADDRESS
D7
D6
D5
D4
D3
D2
D1
D0
Vertical amplitude
00
X(1)
X
A5
A4
A3
A2
A1
A0
Vertical S-correction
01
X
X
A5
A4
A3
A2
A1
A0
Vertical start scan
02
X
X
A5
A4
A3
A2
A1
A0
Vertical off-centre shift
03
X
note 2
note 2
note 2
X
A2
A1
A0
EW trapezium correction
03
X
A6
A5
A4
X
note 2
note 2
note 2
EW width/width ratio
04
X
X
A5
A4
A3
A2
A1
A0
EW parabola/width ratio
05
X
X
A5
A4
A3
A2
A1
A0
EW corner/parabola ratio
06
X
X
A5
A4
A3
A2
A1
A0
EHT compensation
07
X
X
A5
A4
A3
A2
A1
A0
Horizontal phase
08
X
X
A5
A4
A3
A2
A1
A0
Horizontal off-centre shift
09
X
X
A5
A4
A3
A2
A1
A0
Clamp shift
0A
X
X
X
X
X
A2
A1
A0
Control 1
0B
MS
WS
FBL
VAP
BLDS
LFSS
DINT
GBS
Vertical slope MSB
0C
A7
A6
A5
A4
A3
A2
A1
A0
Vertical slope LSB
0D
A7
A6
A5
A4
A3
A2
A1
A0
Vertical wait
0E
A7
A6
A5
A4
A3
A2
A1
A0
Control 2
0F
X
X
X
VPR
CPR
DIP
PRD
CSU
Notes
1. X = don’t care.
2. Data bit used in another function.
July 1994
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Philips Semiconductors
Preliminary specification
Programmable deflection controller
TDA9151B
Table 2 Control bits.
CONTROL BIT
LFSS
LOGIC
FUNCTION
0
Line stop: EW output current becomes zero and the vertical output current is reduced
to 20% of the adjusted value. LFSS becomes logic 0 after a HIGH on PON.
1
Line start enabled: the soft start mechanism is now activated.
0
De-interlace on: the VA pulse is sampled at a position selected with control bit DIP.
1
De-interlace off: the VA pulse is sampled with the system clock and the detected rising
edge is used as vertical reset.
0
Aquadag selected.
1
Bleeder selected.
0
Becomes logic 0 after power-on.
1
Guard band 48/12 lines.
VAP
0
Positive VA edge detection.
1
Negative VA edge detection.
FBL
0
Horizontal flyback slicing level = 3.9 V.
1
Horizontal flyback slicing level = 1.3 V.
DINT
BLDS
GBS
WS
MS
CSU
PRD
DIP
CPR
VPR
July 1994
0
No wait state.
1
Programmable wait state (only in constant slope mode; MS = logic 1).
0
Adaptive mode with guardband amplitude control.
1
Constant slope mode (programmable).
0
No clamping suppression, standard mode of operation.
1
Clamping suppression in wait, stop and protection modes
(used in systems with e.g. TDA4680/81).
0
No defeat of HOUT, the over voltage information is only written in the PROT status bit.
1
HOUT is defeated and status bit PROT is set when over voltage is detected.
0
VA is sampled 42 clock pulses after the leading edge of HA.
1
VA is sampled 258 clock pulses after the leading edge of HA.
0
Nominal amplitude.
1
Compression to 75% of adjusted amplitude, used for display of 16 : 9 standard pictures
on 4 : 3 displays.
0
Nominal amplitude (100%) during wait, stop and clipping.
1
Amplitude reduced to 20% during wait, stop and clipping.
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Philips Semiconductors
Preliminary specification
Programmable deflection controller
TDA9151B
Table 3 Explanation of control bits shown in Table 2.
CONTROL BITS
DESCRIPTION
LFSS
line frame start/stop
DINT
de-interlace
BLDS
bleeder mode selection
GBS
guard band selection
VAP
polarity of VA edge detection
FBL
flyback slicing level
WS
wait state on/off
MS
mode select
CSU
clamping suppression mode
PRD
protection/detection mode
DIP
de-interlace phase
CPR
compression on/off
VPR
vertical power reduction mode
Table 4 Clock frequency control bit (pin 5; note 1).
CONTROL BIT
LOGIC
FUNCTION
LLCS
0
prescaler on: the internal clock frequency fclk = 1⁄2fLLC
1
prescaler off (default by internal pull-up resistor): the internal clock frequency fclk = fLLC
Note
1. Switching of the prescaler is only allowed when LFSS is LOW. It is highly recommended to hard wire LLCS to ground
or VCC. Active switching may damage the output power transistor due to the changing HOUT pulse. This may cause
very high currents and large flyback pulses. The permitted combinations of LLC and the prescaler are shown in
Table 5.
Table 5 Line duration with prescaler.
LLC (MHz)
ON (µs)
OFF (µs)
6.75
note 1
64
13.5
64
32
27
32
note 1
Note
1. Combination not allowed.
July 1994
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Philips Semiconductors
Preliminary specification
Programmable deflection controller
TDA9151B
Fig.3 Timing relations between LLC, HA and line counter.
July 1994
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Philips Semiconductors
Preliminary specification
Programmable deflection controller
TDA9151B
Horizontal part (pins 1, 2, 13, 19 and 20
CLAMPING PULSE
SYNCHRONIZATION PULSE
The clamping pulse width is 21 internal clock periods. The
shift, with respect to HA can be varied from 35 to 49 clock
periods in 7 steps via the I2C-bus, clamp shift byte
subaddress 0A, as illustrated in Fig.9. It is possible to
suppress the clamping pulse during wait, stop and
protection modes with control bit CSU. This will avoid
unwanted reset of the TDA4680/81 (only used in those
circuits).
The HA input (pin 13) is a TTL-compatible CMOS input.
Pulses on this input have to fulfil the timing requirements
as illustrated in Fig.6. For correct detection the minimum
pulse width for both the HIGH and LOW periods is 2
internal clock periods.
FLYBACK INPUT PULSE
HORIZONTAL BLANKING
The HFB input (pin 1) is a CMOS input. The delay of the
centre of the flyback pulse to the leading edge of the HA
pulse can be set via the I2C-bus with the horizontal phase
byte (subaddress 08), as illustrated in Fig.7.
The resolution is 6-bit.
The start of the horizontal blanking pulse is minimum 38
and maximum 41 clock periods before the centre of the
flyback pulse, depending on the fclk/fH ratio K in
accordance with 41 − (432 − K).
Stop of the horizontal blanking pulse is determined by the
trailing edge of the HFB pulse at the horizontal blanking
slicing level crossing as illustrated in Fig.10.
OUTPUT PULSE
The HOUT pulse (pin 20) is an open-drain NMOS output.
The duty factor for this output is typically 52⁄48
(conducting/non-conducting) during normal operation. A
soft start causes the duty factor to increase linearly from 5
to 52% over a minimum period of 2000 lines in 2000 steps.
VERTICAL BLANKING
The vertical blanking pulse starts two internal clock pulses
after the rising edge of the VA pulse. During this interval a
small guard pulse, generated during flyback by the vertical
power output stage, must be inserted. Stop vertical
blanking is effected at the end of the blanking interval only
when the guard pulse is present (see Section “Vertical
guard”).
OFF-CENTRE SHIFT
The OFCS output (pin 19) is a push-pull CMOS output
which is driven by a pulse-width modulated DAC.
By using a suitable interface, the output signal can be used
for off-centre shift correction in the horizontal output stage.
This correction is required for HDTV tubes with a 16 × 9
aspect ratio and is useful for high performance flat square
tubes to obtain the required horizontal linearity. For
applications where off-centre correction is not required,
the output can be used as an auxiliary DAC. The OFCS
signal is phase-locked with the line frequency. The
off-centre shift can be set via the I2C-bus, subaddress 09,
with a 6-bit resolution as illustrated in Fig.8.
The start scan setting determines the end of vertical
blanking with a 6-bit resolution in steps of one line via the
I2C-bus subaddress 02 (see Figs 11, 12 and 13).
VERTICAL GUARD
In the vertical blanking interval a small unblanking pulse is
inserted. This pulse must be filled-in by a blanking pulse or
guard pulse from the vertical power output stage which
was generated during the flyback period. In this condition
the sandcastle output acts as guard detection input and
requires a minimum 800 µA input current. This current is
sensed during the unblanking period. Vertical blanking is
only stopped at the end of the blanking interval when the
inserted pulse is present. In this way the picture tube is
protected against damage in the event of missing or
malfunctioning vertical deflection (see Figs 11, 12 and 13).
SANDCASTLE
The DSC input/output (pin 2) acts as a sandcastle
generating output and a guard sensing input. As an output
it provides 2 levels (apart from the base level), one for the
horizontal and vertical blanking and the other for the video
clamping. As an input it acts as a current sensor during the
vertical blanking interval for guard detection.
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Philips Semiconductors
Preliminary specification
Programmable deflection controller
TDA9151B
Vertical place generator in constant slope mode
(MS = logic 1)
Vertical part (pins 6, 8, 10, 11 and 12)
SYNCHRONIZATION PULSE
In this mode the slope can be programmed directly with a
two byte value on subaddress 0C (MSB) and 0D (LSB).
When the actual number of lines is greater than the
programmed number of lines, the circuit will enter the stop
state in which the differential vertical output current
remains 100% or drops to 20% (programmable with
control bit VPR). The programmed value for the slope is
the required number of lines multiplied by 72. The
programming limits are; minimum 200 × 72 and maximum
910 × 72.
The VA input (pin 12) is a TTL-compatible CMOS input.
Pulses at this input have to fulfil the timing requirements as
illustrated in Fig.6. For correct detection the minimum
pulse width for both the HIGH and LOW period is 2 internal
clock periods. For further requirements on minimum pulse
width see also Section “De-interlace”.
VERTICAL PLACE GENERATOR
An overview of the various modes of operation of the
vertical place generator is illustrated in Fig.13.
A vertical expansion is obtained with a combination of
slope data and a programmable wait status, at
subaddress 0E. The wait status is selected with control bit
MS and can only be activated in the constant slope mode.
The wait state is an 8-bit value, programmable from 0 to
255. The actual wait state is one line longer than the
programmed value. If blanking is applied during stop and
wait status the differential output current will be the same
with VPR selected value (20 or 100%).
With control bit CPR a compress to 75% of the adjusted
values is possible in all modes of operation. This control bit
is used to display 16 : 9 standard pictures on 4 : 3
displays. No new adjustment of other corrections, such as
corner and S-correction, is required.
With control bit VPR a reduction of the current during
clipping, wait and stop modes to 20% of the nominal value
can be selected, which will reduce the dissipation in the
vertical drive circuits.
DE-INTERLACE
With de-interlace on (DINT = logic 0), the VA pulse is
sampled with LLC at a position supplied by control bit DIP
(de-interlace phase).
Vertical place generator in adaptive mode (MS = logic 0)
The vertical start-scan data (subaddress 02) determines
the vertical placement in the total range of 64 × 432 clock
periods in 63 steps. The maximum number of
synchronized lines per scan is 910 with an equivalent field
frequency of 17.2 or 34.4 Hz for fH = 15625 or 31250 Hz
respectively.
When DIP = logic 0 sampling takes place 42 clock pulses
after the leading edge of HA (T = Tline × 42/432).
When DIP = logic 1 sampling takes place 258 clock pulses
after the leading edge of HA (T = Tline × 258/432).
The minimum number of synchronized lines per scan is
200 with an equivalent field frequency of 78 or 156 Hz for
fH = 15 625 or 31250 Hz respectively.
The distance between the two selectable sampling points
is (Tline × (258 − 42)/432) which is exactly half a line, thus
de-interlace is possible in two directions.
If the VA pulse is not present, the number of lines per scan
will increase to 910.2. If the LLC is not present the vertical
blanking will start within 2 µs.
The duration of the VA pulse must, therefore, be sufficient
to enable the HA pulse to caught, in this event an active
time of minimum of half a line (see Fig.14 which has an
integration time of Tline × 1⁄4 for the VA pulse).
Amplitude control is automatic, with a settling time of 1 to
2 new fields and an accuracy of either 16/12 or 48/12 lines
depending on the value of the GBS bit.
With de-interlace off, the VA pulse is sampled with the
system clock. The leading edge is detected and used as
the vertical reset. Selection of the positive or negative
leading edge is achieved by the control bit VAP.
Differences in the number of lines per field, as can occur in
TXT or in multi-head VTR, will not affect the amplitude
setting providing the differences are less than the value
selected with GBS. This is called amplitude control
guardband. The difference sequence and the difference
sequence length are not important.
July 1994
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Philips Semiconductors
Preliminary specification
Programmable deflection controller
TDA9151B
Two modes of protection are available with the aid of
control bit PRD.
VERTICAL GEOMETRY PROCESSING
The vertical geometry processing is DC-coupled and
therefore independent of field frequency. The external
resistive conversion (RCONV) at pin 8 sets the reference
current for both the vertical and EW geometry processing.
A useful range is 100 to 150 µA, the recommended value
is 120 µA.
• With PRD = logic 1 the protection mode is selected,
HOUT will be defeated and the PROT bit in the status
word is set if the input voltage is above 3.9 V. Thus the
deflection stops and EW output current is zero, while the
vertical output current is reduced to 20% of the adjusted
value. A new start of the circuit is I2C-bus controlled with
the user software.
VERTICAL OUTPUTS
• With PRD = logic 0 the detection mode is selected,
HOUT will not be defeated and the over voltage
information is only written in the PROT status bit and can
be read by the I2C-bus.
The vertical outputs VOUTA and VOUTB on pins 10 and 11
together form a differential current output. The vertical
amplitude can be varied over the range 80 to 120% in
63 steps via the I2C-bus (subaddress 00). Vertical
S-correction is also applied to these outputs and can be
set from 0 to 16% by subaddress 01 with a 6-bit resolution.
All further actions, such as a write of the LFSS bit, are
achieved by the I2C-bus. They depend on the
configuration used and are defined by user software.
The vertical off-centre shift (OFCS) shifts the vertical
deflection current zero crossing with respect to the EW
parabola bottom. The control range is −1.5 to +1.5%
(±1⁄8 × I8) in 7 steps set by the least significant nibble at
subaddress 03.
Flash detection/protection input (pin 9)
The FLASH input is a CMOS input with an internal pull-up
current of approximately 8 µA.
When a negative-going edge crosses the 0.75 V level a
restart will be executed with a soft start of approximately
2000 lines, such as in the soft-start mode. When the
function is not used pin 9 can be connected to ground, VCC
or left open-circuit, the internal pull-up current source will
prevent any problems. However a hard wired connection
to VCC or ground is recommended when the function is not
used.
EW GEOMETRY PROCESSING
The EW geometry processing is DC coupled and therefore
independent of field frequency. RCONV sets the reference
current for both the vertical and EW geometry processing.
The EW output is an ESD-protected single-ended current
output.
The EW width/width ratio can be set from 100 to 80% in
63 steps via subaddress 04 and the EW parabola/width
ratio from 0 to 20% via subaddress 05. The EW
corner/EW parabola ratio has a control range of −40 to 0%
in 63 steps via subaddress 06.
EHT compensation (pin 7)
The EHT input is a CMOS input.
The EHT compensation input permits scan amplitude
modulation should the EHT supply not be perfect. For
correct tracking of the vertical and horizontal deflection the
gain of the EW output stage, provided by the ratio
RCONV-EW/RCONV, must be 1⁄16Vscan × Vref (see Fig.15).
The EW trapezium correction can be set from
−1.5 to +1.5% in 7 steps via the most significant nibble at
subaddress 03.
The input for EHT compensation can be derived from an
EHT bleeder or from the picture tubes aquadag
(subaddress 0B, bit BLDS).
BULT GENERATOR
The Bult generator makes the EW waveform continuous
(see Fig.21).
EHT compensation can be set via subaddress 07 in
63 steps allowing a scan modulation range from
−10 to +9.7%.
Protection input (pin 3)
The protection input (PROT) is a CMOS input.
The input voltage must be EHT scaled and has the
following characteristics:
July 1994
12
July 1994
1
300 Ω
19
2
300 Ω
18
3
300 Ω
17
4 5
300 Ω
TDA9151B
15
6
14
300 Ω
7
300 Ω
13
300 Ω
8
12
300 Ω
9
300 Ω
11
10
MBD906
Programmable deflection controller
13
Fig.4 Internal circuitry.
300 Ω
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handbook, full pagewidth
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Philips Semiconductors
Preliminary specification
TDA9151B
INTERNAL CIRCUITRY
July 1994
14
VCC
( 8 V)
SCL
SDA
HOUT
R77
1 kΩ
R76
R75
100 Ω
100 Ω
20
19
18
17
16
OFCS
100 nF
22 µF
1
2
3
4
5
15
VCC
( 8 V)
6
14
LLC
TDA9151B
7
C89
8
13
HA
C95
9
12
VA
10
HFB
23 V (peak)
R85
15 kΩ
R84
3.3 kΩ
R99
3.3 kΩ
100 nF
C97
R88
R87
4.7 kΩ
39 kΩ
100
nF
Zener
diode
R107
82 kΩ
100 µF
C105
45 V (vert)
100 µF
C105
16 V (vert)
R105
3 kΩ
13
12
11
10
9
8
7 TDA8350
6
5
4
3
2
1
IE5
3
2
1
MBD907
100 nF
C110
R113
330 Ω
R113
IE5
vertical
deflection coil
33 V
EW-OUT
LV
R117
Programmable deflection controller
Fig.5 Application diagram.
DSC
VCC
( 8 V)
EHT
flash detection input
handbook, full pagewidth
11
Philips Semiconductors
Preliminary specification
TDA9151B
APPLICATION INFORMATION
Philips Semiconductors
Preliminary specification
Programmable deflection controller
TDA9151B
TIMING DIAGRAMS
Fig.6 Timing requirements for LLC, HA and VA.
NNNNNNN
NNNNNNN
Fig.7 Horizontal phase and HOUT control range.
July 1994
15
Philips Semiconductors
Preliminary specification
Programmable deflection controller
TDA9151B
Fig.8 OFCS duty factor.
Fig.9 DSC clamping pulse.
July 1994
16
Philips Semiconductors
Preliminary specification
Programmable deflection controller
TDA9151B
Fig.10 DSC line blanking.
Fig.11 DCS vertical blanking with unblanking.
July 1994
17
Philips Semiconductors
Preliminary specification
Programmable deflection controller
TDA9151B
Vertical blanking LOW period: during scan, during unblanking.
Vertical blanking HIGH period (2.5 V): during STSC, stop and wait.
Vertical blanking continuously HIGH: POR = logic 1, LFSS = logic 0, no guard detected.
Fig.12 DSC with guard interval; start scan = 24.
July 1994
18
Philips Semiconductors
Preliminary specification
TDA9151B
tub = unblanking pulse width.
Fig.13 Vertical deflection operating modes.
Programmable deflection controller
July 1994
19
Philips Semiconductors
Preliminary specification
Programmable deflection controller
TDA9151B
I = start VA for DINT = logic 1.
D = start VA for DINT = logic 0.
Fig.14 De-interlace timing.
Fig.15 Explanation of RCONV-EW/RCONV ratio.
July 1994
20
Philips Semiconductors
Preliminary specification
Programmable deflection controller
TDA9151B
LIMITING VALUES
In accordance with the Absolute Maximum Rating System (IEC134).
SYMBOL
PARAMETER
MIN.
MAX.
UNIT
VCC
supply voltage
−0.5
8.8
V
ICC
supply current
−10
+50
mA
Ptot
total power dissipation
−
500
mW
Tstg
storage temperature
−65
+150
°C
Tamb
operating ambient temperature
−25
+70
°C
Vsupply
voltage supplied to pins 1 to 3, 5 to 14 and 17 to 20
−0.5
VCC + 0.5
V
II/O
current in or out of any pin except pins 4, 15 and 16
−20
+20
mA
VESD
electrostatic handling for all pins (note 1)
−
±2000
V
Note
1. Equivalent to discharging a 100 pF capacitor via a 1.5 kΩ series resistor.
THERMAL CHARACTERISTICS
SYMBOL
Rth j-a
July 1994
PARAMETER
thermal resistance from junction to ambient in free air
21
VALUE
UNIT
70
K/W
Philips Semiconductors
Preliminary specification
Programmable deflection controller
TDA9151B
CHARACTERISTICS
VCC = 8 V; Tamb = 25 °C; DGND = AGND = 0 V; unless otherwise specified.
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
Supply
VCC
supply voltage
ICC
supply current
Ptot
total power dissipation
Vpor
power-on reset
7.2
8.0
8.8
V
−
27
−
mA
−
220
−
mW
POR 1-to-0
transition
−
6.25
7.0
V
POR 0-to-1
transition
5.0
5.75
−
V
note 1;
fclk = 6.75 MHz
SDA and SCL (pins 17 and 18)
V17
SDA input voltage
0
−
5.5
V
VIL
LOW level input voltage (pin 17)
−
−
1.5
V
VIH
HIGH level input voltage (pin 17)
3.5
−
−
V
IIL
LOW level input current (pin 17)
V17 = VSSD
−
−
−10
µA
IIH
HIGH level input current (pin 17)
V17 = VCC
−
−
10
µA
VOL
LOW level output voltage (pin 17) IIL = 3 mA
−
−
0.4
V
V18
SCL input voltage
0
−
5.5
V
VIL
LOW level input voltage (pin 18)
−
−
1.5
V
VIH
HIGH level input voltage (pin 18)
3.5
−
−
V
IIL
LOW level input current (pin 18)
V18 = VSSD
−
−
−10
µA
IIH
HIGH level input current (pin 18)
V18 = VCC
−
−
10
µA
Line-locked clock and line-locked clock select (pins 14 and 5)
VIL
LOW level input voltage (pin 14)
−
−
0.8
V
VIH
HIGH level input voltage (pin 14)
2.0
−
−
V
I14
input current
−10
−
+10
µA
2tLLC
2tLLC
V14 = <5.5 V
tr
rise time
0
−
1⁄
tf
fall time
0
−
1⁄
δ0
duty factor
LLCS = logic 0;
at 1.4 V; note 2
40
50
60
%
δ1
duty factor
LLCS = logic 1;
at 1.4 V; note 2
25
50
75
%
12.4
−
29.2
MHz
TIMING (PRESCALER ON; fclk = 1⁄2fLLC WHERE fclk = INTERNAL CLOCK)
fLLC
line-locked clock frequency
K
line-locked clock frequency ratio
between fLLC and fH
H locked
856
864
865
H unlocked
−
866
−
line-locked clock frequency ratio
between fclk and fH
H locked
428
432
432.5
H unlocked
−
433
−
July 1994
22
Philips Semiconductors
Preliminary specification
Programmable deflection controller
SYMBOL
PARAMETER
TDA9151B
CONDITIONS
MIN.
TYP.
MAX.
UNIT
TIMING (PRESCALER OFF; fclk = fLLC WHERE fclk = INTERNAL CLOCK)
fLLC
line-locked clock frequency
6.2
−
15.5
K
line-locked clock frequency ratio
between fLLC and fH
H locked
428
432
432
H unlocked
−
433
−
line-locked clock frequency ratio
between fclk and fH
H locked
428
432
432
H unlocked
−
433
−
0
−
8.8
MHz
V5
LLCS input voltage
V
VIL
LOW level input voltage (pin 5)
−
−
1.5
V
VIH
HIGH level input voltage (pin 5)
3.5
−
−
V
IIL
LOW level input current (pin 5)
V5 = VSSD
−
−
−150
µA
IIH
HIGH level input current (pin 5)
V5 = VCC
−
−
100
µA
−
−
0.8
V
2.0
−
−
V
−10
−
+10
µA
−
1⁄
2tLLC
ns
2tLLC
ns
Horizontal part
INPUT SIGNALS
HA (pin 13)
VIL
LOW level input voltage
VIH
HIGH level input voltage
I13
input current
tr
V13 = 5.5 V
rise time
0
tf
fall time
0
−
1⁄
tWH
pulse width HIGH
2 × tclk
−
−
tWL
pulse width LOW
2 × tclk
−
−
FBL = logic 0
3.7
3.9
4.1
V
FBL = logic 1
1.1
1.3
1.5
V
HFB (pin 1)
VPSL
phase slicing level;
Vblank
blanking slicing level
0
0.1
0.2
V
I1
input current
−10
−
+10
µA
Horizontal phase (delay centre flyback pulse to leading edge of HA; where N = horizontal phase data)
CR
control range
0
N × tclk
N + (432 − K)
× tclk
number of steps
−
63
−
OUTPUT SIGNALS
HOUT (pin 20)
V20
output voltage
I20 = 0
0
−
VCC
V
VOL
LOW level output voltage
I20 = 10 mA
−
−
0.5
V
I20
input current
output off
−10
−
+10
µA
δ
duty factor
normal operation
51
52
53
%
July 1994
23
Philips Semiconductors
Preliminary specification
Programmable deflection controller
SYMBOL
PARAMETER
TDA9151B
CONDITIONS
MIN.
TYP.
MAX.
UNIT
Soft start (duty factor controlled line drive)
tW
initial pulse width soft start
−
−
5
%
CR
control range
5
−
53
%
tss
soft start time
1500
−
3000
lines
0
−
160 −
(432 − K)
× tclk
Switch-off time to the centre of the flyback pulse
CR
control range
note 3
Φ
control sensitivity (loop gain)
400
1000
−
k
correction factor
note 4
−
0.5
−
σ
sigma value of phase jitter
note 5
−
750
−
ps
PSRR
power supply rejection ratio
−
−
10
ns/V
0
−
VCC
V
µs/µs
Horizontal off-centre shift (pin 19; N = off-centre shift data)
V19
output voltage
VOL
LOW level output voltage
I19 = 2 mA
−
−
0.5
V
VOH
HIGH level output voltage
I19 = −2 mA
VCC − 0.5
−
−
V
δ(max)
maximum duty factor
N <54
1/K
(8N+1)/K
425/K
%
δ
duty factor
N ≥54
−
1
−
%
−
54
−
number of steps
SANDCASTLE (PIN 2)
DSC output voltage
Vclamp
video clamping voltage
4.0
4.5
5.0
V
Vblank
horizontal and vertical blanking
voltage level
2.0
2.5
3.0
V
Vbase
base voltage level
0
0.5
1.0
V
I2
output current
−1.0
−
+0.35
mA
0.8
−
2.5
mA
tr
rise time
−
60
−
ns
tf
fall time
−
60
−
ns
guard not detected
guard detected
Clamping pulse (N = clamp pulse shift data)
tW
clamping pulse width
−
21 × tclk
−
tclamp
clamp pulse shift w.r.t HA
35
(2N + 35)
× tclk
49
number of steps
−
7
−
start of horizontal blanking before
middle of flyback pulse
38
41 −
(432 − K)
× tclk
41
tstart
July 1994
24
Philips Semiconductors
Preliminary specification
Programmable deflection controller
SYMBOL
PARAMETER
TDA9151B
CONDITIONS
MIN.
TYP.
MAX.
UNIT
Vertical blanking width (N = vertical start-scan data)
CR
control range
K = 432
number of steps
1 × 432tclk
(N + 1)
× 432tclk
64 × 432tclk
1
−
64
−
63
−
lines
Guard detection (N = vertical start-scan data)
tstart
start interval w.r.t VA
no wait
{48(N+1) +2} −
× tclk
−
tstop
stop interval w.r.t VA
no wait
{96(N+1) +2} −
× tclk
−
Vertical section
INPUT SIGNALS (PIN
12; VA)
VIL
LOW level input voltage
−
−
0.8
V
VIH
HIGH level input voltage
2.0
−
−
V
I12
input current
−10
−
+10
µA
tr
rise time
V12 <5.5 V
0
−
1⁄
2tLLC
ns
tf
fall time
0
−
1⁄
2tLLC
ns
tWH
pulse width HIGH
2 × tclk
−
−
tWL
pulse width LOW
2 × tclk
−
−
tWH
pulse width HIGH
de-interlace mode
0.5 × tline
−
−
tWL
pulse width LOW
de-interlace mode
0.5 × tline
−
−
1 × 432tclk
(N + 1)
× 432tclk
64 × 432tclk
Vertical place generator in adaptive mode (N = vertical start-scan data)
CR
control range
1
−
64
number of steps
−
63
−
Lmax
maximum number of
synchronized lines per scan
−
910
−
lines/
scan
feq
equivalent field frequency at 910
lines/scan
fH = 15625 Hz
−
17.2
−
Hz
fH = 31250 Hz
−
34.4
−
Hz
−
200
−
lines/
scan
fH = 15625 Hz
−
78
−
Hz
fH = 31250 Hz
−
156
−
Hz
−
automatic
−
GBS = logic 0
−
16/12
−
lines
GBS = logic 1
−
48/12
−
lines
1
1.5
2
new
fields
K = 432
Lmin
minimum number of
synchronized lines per scan
feq
equivalent field frequency at 200
lines/scan
CA
amplitude control
CAg
amplitude control guardband
settling time
July 1994
25
lines
Philips Semiconductors
Preliminary specification
Programmable deflection controller
SYMBOL
PARAMETER
TDA9151B
CONDITIONS
MIN.
TYP.
MAX.
UNIT
Vertical place generator in constant slope mode (N = vertical wait data)
CR
1 × 432tclk
(N + 1)
× 432tclk
64 × 432tclk
1
−
64
number of steps
−
255
−
programmable slope
200
−
910
lines/
scan
2-byte instruction;
200 × 72
−
910 × 72
lines
VA = 100%;
note 6;
I8 = −120 µA
440
475
510
µA
control range
K = 432
programmable slope data
(number of lines × 72)
lines
Vertical geometry processing
∆I(M)
vertical differential output current
between VOUTA and VOUTB
(peak value)
D/∆T
drift over temperature range
−
−
10−4
K−1
amplitude error due to
S-correction setting
−
−
2
%
vertical output signal bias current I8 = −120 µA
275
325
375
µA
vertical output offset current
−
−
1
%
K−1
1⁄
2(I10+I11)
Ios
note 7
OS/∆T
offset over temperature range
−
−
10−4
V10
vertical output voltage (pin 10)
0
−
3.9
V
V11
vertical output voltage (pin 11)
0
−
3.9
V
CMRR
common mode rejection ratio
LE
linearity error
−
−
1
%/V
adjacent blocks;
note 8
−
−
2.0
%
non-adjacent
blocks; note 8
−
−
3.0
%
note 9
81
−
119
%
−
63
−
0
−
15
−
63
−
control range
−1⁄8I8
−
+1⁄8I8
number of steps
−
7
−
Vertical amplitude (N = vertical amplitude data)
CR
control range
number of steps
Vertical S-correction (N = S-correction data)
CR
control range
note 9
number of steps
%
Vertical shift
CR
µA
EW output (pin 6)
V6
output voltage
note 10
1.0
−
5.5
V
I6
output current
I8 = −120 µA;
note 11
15
−
930
µA
RR
output ripple rejection
−
0.15
1
%/V
−
5.10−4
K−1
D/∆T
July 1994
−
output drift over temperature
range
26
Philips Semiconductors
Preliminary specification
Programmable deflection controller
SYMBOL
PARAMETER
TDA9151B
CONDITIONS
MIN.
TYP.
MAX.
UNIT
EW WIDTH/WIDTH RATIO
CR
control range
note 9
100
−
81
%
Ieq(typ)
typical equivalent output current
V6 = 3 V
15
−
440
µA
−
63
−
1
−
19
number of steps
EW PARABOLA/WIDTH RATIO
CR
control range
Ieq(typ)
typical equivalent output current
note 9
%
width = 100%
10
−
430
µA
width = 80%
10
−
345
µA
−
63
−
number of steps
EW CORNER/EW PARABOLA RATIO
CR
control range
notes 9 and 12
40
−
0
%
Ieq(typ)
typical equivalent output current
width = 100%
0
−
200
µA
µA
0
−
160
−
63
−
−1.5
−
+1.5
−
7
−
BLDS = logic 1
−
3.9
−
V
BLDS = logic 0
−
VCC
−
V
width = 80%
number of steps
EW TRAPEZIUM CORRECTION
EW trapezium/width ratio
note 9
number of steps
%
EHT input (pin 7)
Vref
reference voltage
VI
input voltage w.r.t Vref
BLDS = logic 1
−20
0
+20
%
VI
input voltage w.r.t VCC
BLDS = logic 0
0
−
−2Vref
V
mscan
scan modulation
−10
0
+9.7
%
mGC
modulation gain control
0
−
1
number of steps
−
63
−
input current
−100
−
+100
nA
3.7
3.9
4.1
V
−100
−120
−150
µA
II
RCONV input (pin 8)
VO
output voltage
I8
current range
I8 = −120 µA
PROT input (pin 3)
VI
input voltage
0
−
VCC
V
V3
voltage detection level
3.7
3.9
4.1
V
II
input current
−10
−
+10
µA
0
−
VCC
V
0.5
0.75
1.0
V
FLASH detection input (pin 9)
VI
input voltage
V9
voltage detection level
H
detection level hysteresis
0.3
0.5
0.8
V
I9
detection pull-up current
−4
−8
−16
µA
July 1994
falling edge
27
Philips Semiconductors
Preliminary specification
Programmable deflection controller
TDA9151B
Notes to the characteristics
1. For all other frequencies the expected supply current will be as shown in Table 6 (fclk is the internal clock frequency,
fLLC is the internal clock frequency applied to pin 14).
2. When the prescaler is on, one in two LLC HIGH periods is omitted.
3. For 16 kHz operation the minimum value of the control range is 5.7 µs. With 1⁄2tFB = 5.7 µs the minimum storage time
is 0 and the maximum is 18 µs.
For 32 kHz operation the minimum value of the control range is 0 µs. With 1⁄2tFB = 2.85 µs the minimum storage time
is 0 and the maximum is 9 µs.
4. The k factor is defined as the amount of correction of a phase step. Thus with k = 0.5 a 50% correction of the error
takes place each line. The resulting step response now becomes kn, with n the line number after the step.
5. The sigma value (σ) of the jitter with respect to LLC (HA) at fH = 32 kHz and a storage time of 5 µs.
Measurement of σ is carried out during 200 lines in the active scan, the resulting peak-to-peak value is approximately
6σ. The visible jitter on the screen will be higher than the peak-to-peak jitter, depending on the deflection stage.
6. DAC values: vertical amplitude = 31; EHT = 0; SHIFT = 3; SCOR = 0.
7. Value is a percentage of I10 − I11.
8. The linearity error is measured without S-correction and based on the same measurement principle as used for the
screen. Measuring method: divide the output signal I10 − I11 into 22 equal parts, ranging from 1 to 22 inclusive.
Measure the value of two succeeding parts called one block starting with part 2 and 3 (block 1) and ending with part
20 and 21 (block 10). Thus part 1 and 22 are unused.
ak – a ( k + 1)
Linearity error for adjacent blocks = -----------------------------a avg
a max – a min
Linearity error for non-adjacent blocks = -----------------------------a avg
Where a = amplitude, ak = amplitude block k and aavg = average amplitude.
9. Minimum available range.
10. Selection of test mode.
When the EW output is pulled above VCC − 0.5 V a special test mode is entered in which the prescaler and the clock
detector are disabled.
11. DAC values: vertical amplitude = 31; EHT = 0.
12. The value of −40% (typically 46%) corresponds with data 3F (hexadecimal) and implies maximum 4th order
compensation.
Table 6 Supply current with prescaler on/off.
LLC (MHz)
ON (mA)
OFF (mA)
6.75
note 1
27
13.5
27
38
27
42
note 1
Note
1. Combination not allowed.
July 1994
28
Philips Semiconductors
Preliminary specification
Programmable deflection controller
TDA9151B
TEST AND APPLICATION INFORMATION
I11 − I10.
Fig.16 Control range amplitude.
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Fig.17 Control range S-correction.
July 1994
29
Philips Semiconductors
Preliminary specification
Programmable deflection controller
TDA9151B
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Fig.18 Control range EW parabola/width ratio.
Fig.19 Control range EW corner/EW parabola ratio.
July 1994
30
Philips Semiconductors
Preliminary specification
Programmable deflection controller
TDA9151B
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BBBBBBBBBBBBBBBBBBBBBBB
BBBBBBBBBBBBBBBBBBBBBBB
Fig.20 Control range EW width.
Fig.21 The BULT makes the EW waveform continuous.
July 1994
31
Philips Semiconductors
Preliminary specification
Programmable deflection controller
TDA9151B
PACKAGE OUTLINE
seating plane
26.92
26.54
8.25
7.80
3.2
max
3.60
3.05
4.2
max
0.51
min
2.0
max
0.53
max
2.54
(9x)
0.254 M
0.38 max
7.62
1.73 max
10.0
8.3
MSA258
20
11
6.40
6.22
1
10
Dimensions in mm.
Fig.22 Plastic dual in-line package; 20 leads (300 mil); DIP20, SOT146-1.
specified storage maximum. If the printed-circuit board has
been pre-heated, forced cooling may be necessary
immediately after soldering to keep the temperature within
the permissible limit.
SOLDERING
Plastic dual in-line packages
BY DIP OR WAVE
The maximum permissible temperature of the solder is
260 °C; this temperature must not be in contact with the
joint for more than 5 s. The total contact time of successive
solder waves must not exceed 5 s.
REPAIRING SOLDERED JOINTS
Apply a low voltage soldering iron below the seating plane
(or not more than 2 mm above it). If its temperature is
below 300 °C, it must not be in contact for more than 10 s;
if between 300 and 400 °C, for not more than 5 s.
The device may be mounted up to the seating plane, but
the temperature of the plastic body must not exceed the
July 1994
32
Philips Semiconductors
Preliminary specification
Programmable deflection controller
TDA9151B
DEFINITIONS
Data sheet status
Objective specification
This data sheet contains target or goal specifications for product development.
Preliminary specification
This data sheet contains preliminary data; supplementary data may be published later.
Product specification
This data sheet contains final product specifications.
Limiting values
Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or
more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation
of the device at these or at any other conditions above those given in the Characteristics sections of the specification
is not implied. Exposure to limiting values for extended periods may affect device reliability.
Application information
Where application information is given, it is advisory and does not form part of the specification.
LIFE SUPPORT APPLICATIONS
These products are not designed for use in life support appliances, devices, or systems where malfunction of these
products can reasonably be expected to result in personal injury. Philips customers using or selling these products for
use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such
improper use or sale.
PURCHASE OF PHILIPS I2C COMPONENTS
Purchase of Philips I2C components conveys a license under the Philips’ I2C patent to use the
components in the I2C system provided the system conforms to the I2C specification defined by
Philips. This specification can be ordered using the code 9398 393 40011.
July 1994
33
Philips Semiconductors
Preliminary specification
Programmable deflection controller
TDA9151B
NOTES
July 1994
34
Philips Semiconductors
Preliminary specification
Programmable deflection controller
TDA9151B
NOTES
July 1994
35
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SCD33
© Philips Electronics N.V. 1994
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Printed in The Netherlands
533061/1500/02/pp36
Document order number:
Date of release: July 1994
9397 737 90011