TDA7278 HIGH-EFFICIENCY CD ACTUATOR DRIVER WIDE OPERATIVE SUPPLY RANGE (1.6 to 5V) LOW VOLTAGE OPERATION CAPABILITY 4 LOAD DRIVING VOLTAGES PWM REGULATED (STEP DOWN FROM BATTERY) LOW ON RESISTANCE H BRIDGES (2 x 1.6Ω MAX + 2 x 2.5Ω MAX) FOR: – FOCUS AND TRACKING ACTUATORS – SLEDGE AND SPINDLE MOTORS SYNCHRONIZABLE SAWTOOTH OSCILLATOR CONFIGURABLE DC/DC CONVERTER FOR ADJUSTABLE MAIN POWER SUPPLY, WITH LOW ON RESISTANCE (0.4Ω MAX) SWITCH GENERAL ENABLE INPUT ADJUSTABLE WATCH DOG AND DELAYED POWER ON RESET FUNCTIONS PQFP44 ADJUSTABLE COMPARATORS FOR BATTERY LOW AND BATTERY EMPTY DETECTION March 1997 H OUT 2B ERROR 1 ERROR 2 BEMP BLOW VCON VREF(2) VREF(1) ERROR 4 ERROR 3 H OUT 4B PIN CONNECTION 44 43 42 41 40 39 38 37 36 35 34 FLIN 4 VBAT 4 30 VBAT FLIN 1 5 29 FLIN 3 GND 6 28 GND H OUT 1A 7 27 H OUT 3A H IN 1 8 26 H IN 3 H OUT 1B 9 25 H OUT 3B OUT 10 24 ENABLE VHIGH 11 23 SYNC 12 13 14 15 16 17 18 19 20 21 22 STCAP 31 WDINP 3 CRES FLIN 2 RESET H OUT 4A VBG 32 OUT2 2 OUT1 H OUT 2A VCPU H IN 4 IRC 33 INP 1 SSCAP H IN 2 D94AU112A 1/15 TDA7278 ABSOLUTE MAXIMUM RATINGS (25°C) Pin Name Min Max Unit HIN 1, HIN 2, HIN 3, HIN 4 -0.4 8 V HOUT 1A, HOUT 2A, HOUT 3A, HOUT 4A, HOUT 1B, HOUT 2B, HOUT 3B, HOUT 4B -0.4 8 V FLIN 1, FLIN 2, FLIN 3, FLIN 4 -0.4 10 V ERROR 1, ERROR 2, ERROR 3, ERROR 4, -0.4 7 V VBAT -0.4 8 V VREF 1, V REF 2 -0.4 7 V BLOW, BEMP, VCON -0.4 7 V OUT, VHIGH -0.4 16 V OUT 2 -0.4 8 V OUT 1 -0.4 16 V SSCAP, IRC, INP -0.4 7 V VCPU -0.4 7 V VBG, RESET, CRES, WDINP, STCAP, SYNC -0.4 7 V EN -0.4 8 V * Pin 1, 8, 12, 14, 20, 26 and 33 are ESD sensitive (max. voltage ±1KV) THERMAL DATA Symbol Top Tj T j-amb 2/15 Parameter Value Unit –25 to 70 °C Max. Junction Temperature 100 °C Thermal Resistance Junction to Ambient 70 °C/W Operating Temperature range TDA7278 PIN FUNCTIONS No Name 21 WDINP Watch dog input - AC coupled to WD µcontroller output (Disabled when connected to GND) 20 CRES Start up reset control for µC & watch dog time constant Function 19 RESET Reset output command to µC (open collector) 41 BEMP Battery empty comparator input 40 BLOW Battery low comparator input 39 VCON Battery level control output VCON = Z VBEMP > VBCON > VBG VCON = 1 VBEMP > VBG > VBLOW VCON = 0 VBG > VBEMP > VBLOW 24 ENABLE 18 VBG 12 SSCAP Soft start capacitor 16 OUT 1 Switching transistor terminal high 17 OUT 2 Switching transistor terminal low 15 VCPU Regulated voltage 14 IRC Error amplifier output 13 INP Error amplifier inverting input 11 VHIGH 10 OUT 22 STCAP Sawtooth toth 23 SYNC Oscillator synchronizing input 4, 30 VBAT Power supply voltage 6, 28 GND Power ground 38 VREF 2 37 VREF 1 Reference input voltage 5 FLIN 1 Switching Output 7 HOUT 1A General Enable Input (active Low) Regulated Voltage Switching transistor output H bridge positive output HIN 1 HOUT 1B H bridge negative output 43 ERROR 1 Error input FLIN 3 HOUT 3A Regulated voltage H bridge supply HIN 3 25 HOUT 3B H bridge negative output 35 ERROR 3 Error input 3 FLIN 2 HOUT2A VCPU DC-DC converter Vhigh Boost DC-DC Converter Oscillator Focus actuator step down converter & H bridge Switching Output H bridge positive output 26 2 Band Gap Reference Buffered reference output voltage 9 27 Battery control circuit Reference voltage capacitor 8 29 Watch dog & reset circuit Regulated voltage H bridge supply Tracking actuator step down converter & H bridge Switching output H bridge positive output 1 HIN 2 44 HOUT 2B H bridge negative output Regulated voltage H bridge supply 42 ERROR 2 Error input Spindle motor step down converter & H bridge 3/15 TDA7278 ELECTRICAL CHARACTERISTICS (Tamb = 25°C, VBAT = 1.6V unless otherwise specified) Symbol VBAT Parameter Power Supply (Tamb = 25 to 70°C) Power Supply (Tamb = 25 to 60°C) VHIGH VCPU (adj) VBG AV K ZIN Current Consumption from VCPU (1) Current Consumption from VBAT (3) Leakage Current in standby condition Output Voltages RON ofDC/DC Converter Switch Max Output Current from VCPU Voltage Ripple on VCPU Oscillator - free freq. - sync. freq - ∆ free freq. H_bridge - Ron, actuators (CH 1,3) - Ron, motors (CH 2,4) PWM Circuit - Ron, actuators - Ron, motors Reference Voltage Load Regulation Line Regulation Bridge gain Reset Time Coefficient Error Impedance Inputs VREF2 Load Regulation VREF1 Impedance WINDIP Impedance BEMP & BLOW intervention threshold RESET Voltage Saturation VCON Voltage Saturation Test Condition Config. in fig. 3a: VCPU <4V Config. in fig. 3a: VCPU >4V Config. in fig. 3b Config. in fig. 3c Stand-by condition Config. in fig 3a Config. in fig. 3a Config. in fig. 3b Config. in fig. 3c Stand-by condition Config. in fig 3a VCPU = 5V Min. 1.6 1.6 VCPU +0.3 1.6 Typ. Max. VCPU 4 4 4 Unit V V V V 4 VCPU 5 5 V V V V 5.5 5 V mA 1.5 mA 1.6 VCPU +0.3 1.6 VBAT = 5V VBAT +4 2.4 I = 1A VCPU < 4.5V Config. fig 3a STCAP = 470pF . VBAT = 1.6 to 5V I = 100mA VBAT +7 0.25 µA VBAT +12 5 0.4 V V Ω mA 150 180 20 KHz KHz KHz 1.0 1.6 1.6 2.5 Ω Ω 0.5 0.8 1.28 0.8 1.25 1.34 30 30 4.5 17.2 Ω Ω V mV mV 200 80 I = 100mA ILOAD =-10 to+10µA; VBAT = 1.6 to 5V From Error to HIN note 2 ILOAD =-1 to+1mA 1.22 -30 2.8 7.4 26 –30 0.55 ILOAD =-100µA ILOAD =-100µA ILOAD =100µA 3.6 11 40 30 750 30 0.65 0.75 200 200 VCPU-200 (1): all the 4 PWM outputs switched off. (2) TRESET = width of the Reset pulse on pin 19 = K ⋅ C, where C is the capacitance on pin 20 (CRES). To avoid reset, the frequency of watch dog pulses must be greater than (3 ⋅ TRESET)-1 (3) All the 4 PWM output switched OFF, auxiliary and main DC/DC converters polarized but not switching 4/15 20 msec/µF kΩ mV kΩ kΩ V mV mV mV TDA7278 VBAT 4 30 ST CAP VREF (2) 22 37 ERROR 1 VBAT 23 VREF (1) SYNC ERROR 3 Figure 1: Block Diagram. 35 43 DRIV OSCILL 5 38 ER S - R + VHIGH 8 VHIGH VHIGH DRIV - 10 FL IN 1 Q 11 + OUT VBAT VHIGH H IN 1 DRIV 7 9 H OUT 1A H OUT 1B V bg INP IRC 13 14 DRIV 29 ER VCPU OUT1 SSCAP S - R + 15 VHIGH + + VHIGH VHIGH DRIV - Vbg 27 25 17 VBAT 3 REFERENCE and THERMAL 24 Vbg ER S - R + + DRIV H IN 2 DRIV 2 20 44 H OUT 2A H OUT 2B 19 CONTROL WD INP VHIGH VHIGH - FL IN 2 Q 1 RESET H OUT 3B DRIV 18 Vbg/2 CRES H OUT 3A 12 VHIGH ENABLE H IN 3 DRIV VBAT VBG FL IN 3 Q 26 16 DRIV OUT2 VBAT VHIGH Vbg 21 VBAT VHIGH DRIV 31 ER 40 + VCON 39 S - R + VCPU 33 - + + - Vbg/2 VHIGH VHIGH DRIV 32 34 6 28 GND 42 H IN 4 DRIV - GND FL IN 4 Q Vbg/2 H OUT 4A H OUT 4B 36 ERROR 4 BLOW 41 ERROR 2 BEMP D94AU078B 5/15 TDA7278 SYNC 23 22 VREF (2) 38 4 37 30 ERROR 1 VREF (1) VBAT ST CAP ERROR 3 Figure 2: Test Circuit 35 43 VBAT VHIGH OSCILL DRIV 5 470pF ER 10µF S - R + VHIGH Q 100µH 11 8 VBAT + 47µH 10 DRIV 10µF DRIV OUT 10µF AUXIL. STEP UP FEEDBAKC & COMPENSATION NETWORK (see fig.4) 13 H OUT 1A 9 H OUT 1B IRC 14 DRIV 29 S - R + OUT1 FOCUS ACTUATOR VBAT VHIGH ER STEP LP or STEP DOWN STRUCTURE (see fig.3) 7 V bg INP VCPU H IN 1 VHIGH VHIGH - FL IN 1 100µH Q 26 15 16 VHIGH + DRIV - OUT2 H IN 3 VHIGH VHIGH DRIV - FL IN 3 10µF DRIV Vbg 27 H OUT 3A 25 H OUT 3B TRACKING ACTUATOR + 17 SSCAP 12 2µF VBAT VHIGH VBG 18 DRIV VBAT 3 100nF ENABLE REFERENCE and THERMAL 24 ER Vbg S - R + 100µH Q 1 + CRES 20 DRIV 10µF DRIV 1µF RESET VBAT BEMP BLOW H OUT 2B 31 FL IN 4 M SPINDLE MOTOR VBAT VHIGH 21 DRIV 41 ER 40 39 S - R + + 100µH Q 33 Vbg/2 + - + - Vbg/2 H IN 4 VHIGH VHIGH DRIV 10µF DRIV - 32 H OUT 4A 34 H OUT 4B M 42 36 ERROR 4 GND 28 ERROR 2 6 6/15 H OUT 2A Vbg VCPU VCON 2 44 19 CONTROL WD INP H IN 2 VHIGH VHIGH - FL IN 2 D94AU111A SLEDGE MOTOR TDA7278 Figure 3: DC – DC Converter Configuration. VCPU 15 VBAT VHIGH L 16 OUT 1 DRIV C OUT 2 17 D94AU081B a) step-up VCPU 15 VBAT VHIGH 16 OUT 1 DRIV L OUT 2 17 C D94AU082B b) step-down VCPU 15 VBAT VHIGH C 16 OUT 1 DRIV OUT 2 17 D94AU083B c) with transformer 7/15 TDA7278 Figure 4: DC – DC Converter: Feedback and Compensation Networks. VCPU SETTING RESISTOR INP R4 13 Cf R 14 IRC Vbg VCPU 15 D94AU113A a) Dominant Pole Compensation INP R4 R3 C2 13 Cf Rf R2 14 IRC - VCPU + 15 Vbg D94AU114A b) Extended Bandwidth 2 zero, 2 pole compensation INP R4 R3 Cf C2 Rf R2 14 - IRC VCPU C1 13 15 + Vbg R1 D94AU115A c) Extended Bandwidth 2 zero, 3 pole compensation 8/15 TDA7278 SUGGESTED VALUES FOR OUTPUT FILTER AND COMPENSATION NETWORK DC- DC COVERTER CONFIGURATIONS OUTPUT FILTER (see fig. 3) COMPENSATION (see fig. 4) a) DOMINANT POLE R = 50KΩ Cf = 47nF R4 = 35KΩ b) 2 ZERO, 2 POLE L = 47µH C = 47µF STEP-DOWN R2 = 11.18KΩ R3 = 100 KΩ C2 = 936pF Rf = 16.65KΩ Cf = 5.6nF R4 = 70KΩ a) DOMINANT POLE R = 100KΩ Cf = 220nF R4 = 70KΩ c) 2 ZERO, 3 POLE L = 47µH C = 47µF R1 = 500Ω C1 = 18nF R2 = 20.8KΩ R3 = 250KΩ C2 = 636pF Rf = 21.4KΩ Cf = 7.44nF R4 = 200KΩ STEP-UP AND TRANSFORMER c) 2 ZERO, 3 POLE R1 = 500Ω C1 = 18nF R2 = 10.4KΩ R3 = 250KΩ C2 = 318pF Rf = 21.4KΩ Cf = 3.7nF R4 = 200KΩ L = 11µH C = 47µF PINS: 1, 2, 44 PINS: 8, 7,9 12V 1 12V VHIGH 8 + 2 VHIGH + 7 44 VHIGH 9 D96AU447A VHIGH D96AU448A 9/15 TDA7278 PINS: 25, 26, 27 PINS: 32, 33, 34 12V 12V VHIGH 26 VHIGH 33 + 27 + 32 VHIGH 25 VHIGH 34 D96AU449A PIN: 3 D96AU450A PINS: 5 12V 12V VBAT VBAT VHIGH 4 VHIGH 4 5 3 VHIGH VHIGH D96AU451 PIN: 29 D96AU452 PINS: 31 12V 12V VBAT 30 VBAT VHIGH 30 29 31 VHIGH VHIGH D96AU453 10/15 VHIGH D96AU454 TDA7278 PINS: 35 PIN: 36 VCPU 35 VCPU 36 + 7V + 7V 38 38 D96AU465 D96AU466 PIN: 43 PIN: 42 VCPU - VCPU 42 43 + 7V + 7V 38 38 D96AU467 PIN: 18 D96AU468 PINS: 19 VBAT VBAT 19 18 + - 7V REFERENCE 7V D96AU459 D96AU458 11/15 TDA7278 PINS: 21 PINS: 20 VCPU VCPU 1.8 + 20 7V VCPU VCPU 0.7 - VCPU VCPU + - + 21 - 7V - VCPU 0.6 VCPU + + - D96AU460A D96AU461A PIN: 22 PIN: 23 VBAT VBAT 1.3 + VCPU 22 VBAT 7V 0.6 + - 23 7V D96AU463 VBAT 0.2 + - D96AU462 PINS: 10, 11 PIN: 24 17V VBAT VBAT VBAT 11 + 24 10 12V D96AU464A D96AU474 12/15 TDA7278 PINS: 12, 13, 14 PINS: 16, 17 VBAT VBAT VBAT 16 13 + VBG 12 17 17V 14 D96AU476 7V D96AU475 PINS: 37, 38 PIN: 39 VCPU VCPU 37 + VCPU - 39 38 7V 7V D96AU469 D96AU470A PINS: 40, 41 VBG VCPU + 40 5V VCPU + 7V 41 5V D96AU471 13/15 TDA7278 PQFP44 (10x10) PACKAGE MECHANICAL DATA mm DIM. MIN. inch TYP. MAX. A MIN. TYP. MAX. 2.45 A1 0.25 A2 1.95 B 0.096 0.010 2.00 2.10 0.077 0.079 0.30 0.45 0.012 0.018 c 0.13 0.23 0.005 0.009 D 12.95 13.20 13.45 0.51 0.52 0.53 D1 9.90 10.00 10.10 0.390 0.394 0.398 D3 8.00 0.315 e 0.80 0.031 0.083 E 12.95 13.20 13.45 0.510 0.520 0.530 E1 9.90 10.00 10.10 0.390 0.394 0.398 E3 8.00 L 0.65 0.315 0.80 L1 0.95 0.026 0.031 1.60 0.037 0.063 K 0°(min.), 7°(max.) D D1 A D3 A2 A1 23 33 22 34 0.10mm .004 B E E1 B E3 Seating Plane 12 44 11 1 C L L1 e K PQFP44 14/15 TDA7278 Information furnished is believed to be accurate and reliable. However, SGS-THOMSON Microelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of SGS-THOMSON Microelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. SGS-THOMSON Microelectronics products are not authorized for use as criticalcomponents in life support devices or systems without express written approval of SGS-THOMSON Microelectronics. 1997 SGS-THOMSON Microelectronics All Rights Reserved SGS-THOMSON Microelectronics GROUP OF COMPANIES Australia - Brazil - France - Germany - Hong Kong - Italy - Japan - Korea - Malaysia - Malta - Morocco - The Netherlands - Singapore Spain - Sweden - Switzerland - Taiwan - Thaliand - United Kingdom - U.S.A. 15/15