TDA7580 FM/AM digital IF sampling processor Features ■ FM/AM IF sampling DSP ■ ON-CHIP analogue to digital converter for 10.7MHz IF signal conversion ■ FM channel equalization ■ FM adjacent channel suppression ■ Reception enhancement in multipath condition ■ Stereo decoder and weak signal processing ■ 2 Channel serial audio interface (SAI) with sample rate converter ■ I2C and buffer SPI control interfaces ■ RDS filter, demodulator & decoder ■ Inter processor transport interface for antenna and tuner diversity ■ Front-end AGC feedback Description The TDA7580 is an integrated circuit implementing an advanced mixed analogue and digital solution, to perform the signal processing Table 1. LQFP64 of an AM/FM channel. The HW & SW architecture has been devised to perform a digital equalization of the FM/AM channel, and a real rejection of adjacent channels and any other signals, interfering with the listening of the desired station. In severe multiple path conditions, the reception is improved to get high quality audio. Device summary Part number Package Packing TDA7580 LQFP64 Tube TDA758013TR LQFP64 Tape and reel March 2007 Rev 5 1/39 www.st.com 1 Contents TDA7580 Contents 1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 2 Block diagram and electrical specifications . . . . . . . . . . . . . . . . . . . . . . 7 2.1 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2.2 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 3 SAI Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 4 RDS SPI interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 5 BSPI interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 6 Inter processor transport interface for antenna diversity . . . . . . . . . . 26 7 I2C timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 8 Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 9 2/39 8.1 24 bit DSP core . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 8.2 DSP peripherals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 8.3 Clock generation unit (CGU) and oscillator . . . . . . . . . . . . . . . . . . . . . . . 29 8.4 Stereo decoder (HWSTER) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 8.5 Serial audio interface (SAI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 8.6 I2C interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 8.7 Serial peripheral interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 8.8 High speed serial synchronous interface (HS3I) . . . . . . . . . . . . . . . . . . . 31 8.9 Tuner AGC keying DAC (KEYDAC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 8.10 Asynchronous sample rate converter (ASRC) . . . . . . . . . . . . . . . . . . . . . 31 8.11 IF band pass Σ Δ analogue to digital converter (IFADC) . . . . . . . . . . . . . 31 8.12 Digital down converter (DDC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 8.13 RDS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 8.14 AM/FM Detector (CORDIC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Application diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 TDA7580 Contents 9.1 Electrical application scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 10 Package marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 11 Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 12 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 3/39 List of tables TDA7580 List of tables Table 1. Table 2. Table 3. Table 4. Table 5. Table 6. Table 7. Table 8. Table 9. Table 11. Table 12. Table 13. Table 14. Table 15. Table 16. Table 17. Table 18. Table 19. Table 20. Table 21. Table 22. 4/39 Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Recommended DC operating conditions (Tj = -40°C to 125°C) . . . . . . . . . . . . . . . . . . . . . . 8 Thermal data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 General interface electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Low voltage interface CMOS DC electrical characteristics. . . . . . . . . . . . . . . . . . . . . . . . . 15 High voltage CMOS interface DC electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . 15 Current consumption (Tj =-40°C to 125°C). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Crystal characteristics for 1 and 2 chip load . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 External clock signal on XTI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 DSP core (Tj =-40°C to 125°C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 FM stereo decoder characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Sample rate converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 SPI and I2C timing table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 SAI Timing table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 RDS SPI timing table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 BSPI timing table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 HS3I timing table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 I2C BUS timing table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 TDA7580 List of figures List of figures Figure 1. Figure 2. Figure 3. Figure 4. Figure 5. Figure 6. Figure 7. Figure 8. Figure 9. Figure 10. Figure 11. Figure 12. Figure 13. Figure 14. Figure 15. Figure 16. Figure 17. Figure 18. Figure 19. Figure 20. Figure 21. Figure 22. Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 PIN connection (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Power on and boot sequence using I2C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Power on and boot sequence using SPI. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 SAI Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 SAI protocol (when: RLRS=0; RREL=0; RCKP=1; RDIR=0) . . . . . . . . . . . . . . . . . . . . . . . 20 SAI protocol (when: RLRS=1; RREL=0; RCKP=1; RDIR=1) . . . . . . . . . . . . . . . . . . . . . . . 21 SAI protocol (when: RLRS=0; RREL=0; RCKP=0; RDIR=0) . . . . . . . . . . . . . . . . . . . . . . . 21 SAI protocol (when: RLRS=0; RREL=1; RCKP=1; RDIR=0) . . . . . . . . . . . . . . . . . . . . . . . 21 RDS SPI timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 RDS SPI clocking scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 BSPI timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 BSPI clocking scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 High speed synchronous serial interface - HS3I . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 HS3I clocking scheme. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 DSP and RDS I2C BUS timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Radio mode with external slave audio DAC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Radio mode with external master audio device . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Audio mode with external slave audio device . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Application diagram example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 Package marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 Mechanical, data and package dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 5/39 Overview 1 TDA7580 Overview The algorithm is self-adaptive, thus it requires no “on-the-field” adjustments after the parameters optimization. The chip embeds a Band Pass Sigma Delta Analogue to Digital Converter for 10.7MHz IF conversion from a “tuner device” (the TDA7515 is highly recommended). The 24bit DSP allows flexibility in the algorithms implementation, thus giving some freedom for customer required features. The total processing power offers a significant headroom for customer’s software requirement, even when the channel equalization and the decoding software is running. the program and data memory space can be loaded from an external non volatile memory via I2C or SPI. The oscillator module works with an external 74.1MHz quartz crystal. It has very low electro magnetic interference, as it introduces very low distortion, and in any case harmonics fall outside the radio bandwidth. The companion tuner device receives the reference clock through a differential ended interface, which works off the oscillator module by properly dividing down the master clock frequency. That allows the overall system saving an additional crystal for the tuner. After the IF conversion, the digitized baseband signal passes through the base band processing section, either FM or AM, depending on the listener selection. The FM base band processing comprises of stereo decoder, spike detection and noise blanking. The AM noise blanking is fully software implemented. The internal RDS filter, demodulator and decoder features complete functions to have the output data available through either I2C or SPI interface. No DSP support is needed but at start-up, so that RDS can work in background and in parallel with other DSP processing. This mode (RDS only) allows current consumption saving for low power application modes. An I2C/SPI interface is available for any control and communication with the main micro, as well as RDS data interface. The DSP SPI block embeds a 10 words FIFO for both transmit and receive channels, to lighten the DSP task and frequently respond to the interrupt from the control interface. Serial audio interface (SAI) is the ideal solution for the audio data transfer, both transmit and receive: either master or slave. The flexibility of this module gives a wide choice of different protocols, including I2S. Two fully independent bidirectional data channels, with separate clocks allows the use of TDA7580 as general purpose digital audio processor. A fully asynchronous sample rate converter (ASRC) is available as a peripheral prior to sending audio data out via the SAI, so that internal audio sampling rate (~36kHz and FM/AM mode) can be adapted by upconversion to any external rate. An inter processor transport interface (HS3I, high speed synchronous serial interface) is also available for a modular system which implements Dual Tuner Diversity, thus enhancing the overall system performance. It is about a synchronous serial interface which exchanges data up to the MPX rate. It has been designed to reduce the electro magnetic interference toward the sensitive analogue signal from the tuner. General purpose I/O registers are connected to and controlled by the DSP, by means of memory map. A debug and test interface is available for on chip software debug as well as for internal registers read/write operation. 6/39 TDA7580 2 Block diagram and electrical specifications Block diagram and electrical specifications Figure 1. Block diagram RDS A/D I2C/SPI I2C/SPI HS3I IF digital SAI1 Signal processor DAC SAI0 CGU SRC Oscillator Table 2. Absolute maximum ratings Symbol VDD VDD3 Parameter Power supplies (1) Nom. 1.8V Nom. 3.3V Analog input or output voltage belonging to 3.3V IO ring (VDDSD, VDDOSC) Tj Tstg Value Unit -0.5 to 2.5 -0.5 to 4.0 V V -0.5 to 4.0 V Digital input or output voltage, 5V tolerant Normal(2) Failsafe(3) -0.5 to 6.50 -0.5 to 3.80 V V All remaining digital input or output voltage Nom. 1.8V Nom. 3.3V -0.5 to (VDD+0.5) -0.5 to (VDD3+0.5) V Operating junction temperature range -40 to 125 °C Storage temperature -55 to 150 °C 1. VDD3 refers to all of the nominal 3.3V power supplies (VDDH, VOSC, VDDSD). VDD refers to all of the nominal 1.8V power supplies (VDD, VMTR). 2. During Normal Mode operation VDD3 is always available as specified. 3. During Fail-safe Mode operation VDD3 may be not available. Warning: Operation at or beyond these limits may result in permanent damage to the device. Normal operation is not guaranteed at these extremes. 7/39 Block diagram and electrical specifications Table 3. Symbol TDA7580 Recommended DC operating conditions (Tj = -40°C to 125°C) Parameter Comment Min. Typ. Max. Unit VDD 1.8V Power supply voltage Core power supply 1.7 1.80 1.9 V VDDH 3.3V Power supply voltage (1) IO Rings power supply (with GNDH) 3.15 3.30 3.45 V VOSC 3.3V Power supply voltage (1) Oscillator power supply (GNDOSC) 3.15 3.30 3.45 V VDDSD 3.3V Power supply voltage (1) IF ADC power supply (with GNDSD) 3.15 3.30 3.45 V VMTR 1.8V Power supply voltage DAC keying and tuner clock power supply (with GNDMTR) 1.7 1.80 1.9 V 1. VDDH, VOSC, VDDSD are also indicated in this document as VDD3. All others as VDD. Table 4. Symbol Rth j-amb 8/39 Thermal data Parameter Thermal resistance junction to ambient Value Unit 68 °C/W TDA7580 Pin description GND VDD DBOUT1 DBRQ1 DBIN1 DBCK1 VDDH GNDH DBOUT0 DBRQ0 DBIN0 DBCK0 59 58 57 56 55 54 53 52 51 50 49 VDD 46 TST3_LRCKR 45 TST2_SCKR 44 LRCK_LRCKT 6 43 SCLK_SCKT GNDSD 7 42 SDO0 GNDOSC 8 41 VDDH XTI 9 40 GNDH XTO 10 39 TST1_SDI1 VDDOSC 11 38 TST4_SDI0 VDDMTR 12 37 GPIO_SDO1 CKREFP 13 36 TESTN CKREFN 14 35 GND AGCKEY 15 34 VDD GNDMTR 16 33 RESETN DEBUG0 DEBUG1 SAI VCMOP VDDISO 5 60 GND 47 I INN GNDH 4 61 INP VDDH 3 62 48 19 I 2C P/ /S RD 20 P S VLO VDDSD 2 63 1 IFADC VHI VCM 64 PIN connection (top view) OSC. Figure 2. Tuner 2.1 Block diagram and electrical specifications 21 22 23 24 25 26 27 28 29 30 31 32 VDD IQSYNC IQCH1 IQCH2 IQCH3 VDDH GNDH RDS_INT RDS_CS INT ADDR_SD RDS GND SCL_SCK 18 SDA_MOSI MISO 17 PROTSEL_SS D S HS3I IFADC Modulator Power Supply pins pair Oscillator Power Supply pins pair Tuner Clock Out and AGC Keying DAC Power Supply pins pair Core Logic 1.8V Power Supply pins pair I/O Ring 3.3V Power Supply pins pair Table 5. N° Pin description Name Type Description Notes 1 VHI A It needs external Internally generated IFADC Opamps 2.65V (@VDD=3.3V) reference voltage pin minimum 4.7μF ceramic for external filtering capacitor 2 VCM A Internally generated common mode 1.65V It needs external (@VDD=3.3V) reference voltage pin for minimum 10μF ceramic external filtering capacitor 3 VLO A Internally generated IFADC opamps It needs external 0.65V (@VDD=3.3V) reference voltage pin minimum 4.7μF ceramic for external filtering capacitor 4 INP A Positive IF signal input from tuner 2.0Vpp @VDD=3.3V 5 INN A Negative IF signal input from tuner 2.0Vpp @VDD=3.3V 6 VCMOP - Not connected. After Reset 9/39 Block diagram and electrical specifications Table 5. N° TDA7580 Pin description (continued) Name Type Description Notes After Reset 7 GNDSD G IFADC modulator analogue ground Clean ground, to be star connected to voltage regulator ground 8 GNDOSC G Oscillator ground Clean ground, to be star connected to voltage regulator ground 9 XTI I High impedance oscillator input (quartz connection) or clock input when in Antenna Diversity slave mode Maximum voltage swing is VDD=3.3V 10 XTO O Low impedance oscillator output (quartz connection) 11 VDDOSC P Oscillator power supply 3.3V 12 VDDMTR P Tuner reference clock and AGC keying DAC power supply 1.8V Tuner reference clock positive output. FM 100kHz AMEU 18kHz With internal pull-up, on at reset [PP] Output Output 13 CKREFP B 14 CKREFN B Tuner reference clock negative output. FM 100kHz AMEU 18kHz With internal pull-up, on at reset [PP] 15 AGCKEY A DAC output for Tuner AGC keying 1.5kohm ±30% output impedance. 1Vpp ±1% output dynamic range 16 GNDMTR G Ground of the tuner reference clock buffer and the AGC keying DAC B DSP0 GPIO for control serial interface (low: SPI or high: I2C) selection at device Bootstrap. In SPI protocol mode, after boot procedure, SPI slave select, otherwise DSP0 GPIO0 DSP0 GPIO0 5V tolerant With internal pull-up, on at reset [PP] Input B Control serial interface and RDS IO: - SPI mode: slave data in or master data out for main SPI & RDS SPI data in - I2C mode: data for main I2C or RDS I2C 5V tolerant With internal pull-up, on at reset [PP] Input DSP0 GPIO1 5V tolerant. With internal pull-up, on at reset [PP] Input 5V tolerant. With internal pull-up, on at reset [PP] Input 17 18 PROTSEL_SS SDA_MOSI 19 MISO B SPI slave data out or master data in for main SPI and RDS SPI data out 20 SCL_SCK B Bit clock for Control Serial Interface and RDS 10/39 TDA7580 Block diagram and electrical specifications Table 5. N° Pin description (continued) Name Type Description Notes After Reset 21 GND G Digital core power ground 22 VDD P Digital core power supply 1.8V B High speed synchronous serial interface (HS3I) clock if HS3I master mode, else DSP1 GPIO or DSP1 debug port clock (DBOUT1) DSP1 GPIO0 5V tolerant. With internal pull-up, on at reset Input B High speed synchronous serial interface (HS3I) channel 1 data if HS3I master mode, else DSP1 GPIO or DSP1 debug port request (DBRQ1) DSP1 GPIO1 5V tolerant. With internal pull-up, on at reset [PP] Input B High speed synchronous serial interface (HS3I) channel 2 data if HS3I master mode, else DSP1 GPIO or DSP1 debug port data In (DBIN1) DSP1 GPIO2 5V tolerant. With internal pull-down, on at reset [PP] Input DSP1 GPIO3 5V tolerant With internal pull-down, on at reset [PP] Input DSP1 GPIO4. 5V tolerant, open drain With internal pull-up, on at reset [OD] Input Input 23 24 25 IQSYNC IQCH1 IQCH2 26 IQCH3 B High speed synchronous serial interface (HS3I) channel 3 data if HS3I master mode, else DSP1 GPIO or DSP1 debug port data out (DBCK1) 27 VDDH P 3.3V IO ring power supply (HS3I, I2C/SPI, RDS, INT) 28 GNDH G 3.3V IO ring power ground (HS3I, I2C/SPI, RDS, INT) 29 RDS_INT B RDS interrupt to external main microprocessor in case of traffic information 30 RDS_CS B RDS chip select. When RESETN rising, If DSP1 GPIO5. 5V RDS_CS 0, the RDS’s SPI is selected; tolerant. With internal else RDS’s I2C pull-up, on at reset [PP] 31 INT I DSP0 external interrupt 5V tolerant. With internal pull-up, on at reset DSP0 GPIO2 5V tolerant With internal pull-down, on at reset [PP] 32 ADDR_SD B IFS chip master (Low) or slave (High) mode selection, latched in upon RESETN release. It selects the LSB of the I2C addresses. Station detector output 33 RESETN I Chip hardware reset, active low 5V tolerant With internal pull-up 34 VDD P Digital power supply 1.8V 35 GND G Digital power ground 36 TESTN I Test enable pin, active low Input With internal pull-up 11/39 Block diagram and electrical specifications Table 5. TDA7580 Pin description (continued) Notes After Reset 5V tolerant. DSP0 GPIO3. With internal pull-up, on at reset [PP] Input B 5V tolerant. DSP0 Audio SAI0 data input or test selection pin GPIO5. With internal in test mode pull-up, on at reset [PP] Input TST1_SDI1 B DSP0 GPIO for boot selection or audio SAI1 input. Test selection pin in test mode. 5V tolerant. DSP0 GPIO4. With internal pull-up, on at reset [PP] Input 40 GNDH G 3.3V IO ring power ground (audio SAI, ResetN, test pins) 41 VDDH P 3.3V IO ring power supply (audio SAI, ResetN, test pins) 42 SDO0 B Radio or audio SAI0 data output 5V tolerant. With internal pull up, @0V at reset [PP] Output 43 SCLK_SCKT B SAI0 receive and transmit bit clock (master or slave with ASRC); SAI1 transmit bit clock 5V tolerant With internal pull up, on at reset [PP] Input 44 LRCK_LRCKT B SAI0 receive and transmit left/right clock (master or slave with ASRC); SAI1 transmit left/right clock 5V tolerant With internal pull up, on at reset [PP] Input 45 TST2_SCKR B SAI0 Transmit bit clock; SAI1 receive and transmit bit clock. Or test selection pin in test mode 5V tolerant. DSP0 GPIO6. With internal pull up, on at reset [PP] Input 46 TST3_LRCKR B SAI0 Transmit LeftRight clock; SAI1 Receive and Transmit bit clock. Or Test selection pin in Test Mode DSP0 GPIO7. 5V tolerant. With internal pull up, on at reset [PP] Input 47 VDD P Digital core power supply 1.8V 48 GND G Digital core power ground N° Name 37 GPIO_SDO1 B DSP0 GPIO for boot selection or audio SAI0 output. 38 TST4_SDI0 39 49 DBCK0 Type B Description Debug port clock of DSP0 (DBCK0) DSP0 GPIO. 9. 5V tolerant. With internal pull down, on at reset [PP] Input Input 50 DBIN0 B Debug port data input of DSP0 (DBIN0) DSP0 GPIO. 11. 5V tolerant. With internal pull down, on at reset [PP] 51 DBRQ0 B Debug port request of DSP0 (DBRQ0) DSP0 GPIO. 5V tolerant With internal pull up, on at reset [PP] Input 52 DBOUT0 B Debug port data output of DSP0 (DBOUT0) DSP0 GPIO10. 5V tolerant. With internal pull up, on at reset [PP] Input 12/39 TDA7580 Table 5. N° Block diagram and electrical specifications Pin description (continued) Name Type Description Notes After Reset 53 GNDH G 3.3V IO ring power ground (debug interface, GPIO) 54 VDDH P 3.3V IO ring power supply (Debug interface, GPIO) B DSP1 debug port clock (DBCK1) if HS3I master mode, else high speed synchronous serial interface (HS3I) channel3 data DSP1 GPIO9. 5V tolerant. With internal pull down, on at reset [PP] Input B DSP1 GPIO or DSP1 debug port data in (DBIN1) if HS3I master mode, else high speed synchronous serial interface (HS3I) channel2 data i DSP1 GPIO11 5V tolerant With internal pull down, on at reset [PP] Input B DSP1 GPIO or DSP1 debug port request 5V tolerant. With (DBRQ1) if HS3I master mode, else high internal pull up, on at speed synchronous serial interface (HS3I) reset [PP] channel1 data DSP1 GPIO10 5V tolerant With internal pull up, on at reset [PP] 1.8V 55 56 57 DBCK1 DBIN1 DBRQ1 58 DBOUT1 B DSP1 GPIO or DSP1 debug port data out (DBOUT1) if HS3I master mode, else high speed synchronous serial interface (HS3I) clock 59 VDD P Digital core power supply 60 GND G Digital core power ground 61 VDDISO P 3.3V N-isolation biasing supply 62 GNDH G 3.3V IO ring power ground (modulator digital section) 63 VDDH P 3.3V IO ring power supply (modulator digital section) 64 VDDSD P 3.3V IFADC modulator analogue power supply Input Input Clean 3.3V supply to be star connected to voltage regulator Clean power supply, to be star connected to 3.3V voltage regulator I/O Type I/O Definition and status P: Power supply from voltage regulator G: Power ground from voltage regulator A: Analogue I/O I: Digital input O: Digital output B: Bidirectional I/O Z: high impedance (input) O: logic low output X: undefined output 1: logic high output Output PP: Push pull / OD: Open drain 13/39 Block diagram and electrical specifications TDA7580 2.2 Electrical characteristics Table 6. General interface electrical characteristics (Tj =-40°C to 125°C; VDD=1.8V, VDD3= 3.3V) Symbol Parameter Test condition Min. Typ. Max. Unit lilh Low level input current I/Os@VDD3 (absolute value) Vi = 0V (1) (2) without pull-up-down device 1 μA lihh High level input current I/Os@VDD3 (absolute value) Vi = VDD3 (1) (2) without pull-up-down device 1 μA lil Low level input current I/Os@VDD (absolute value) Vi = 0V (1) (3) (4) without pull-up-down device 1 μA lih High level input current I/Os@VDD (absolute value) Vi = VDD (1) (3) (4) without pull-up device 1 μA Iipdh Pull-down current I/Os @ VDD3 Vi = VDD3 (5) with pull-down device Iopuh Pull-up current I/Os @ VDD3 Vi = 0V (6) with pull-up device Iopul Pull-up current I/Os @ VDD Iaihop Analogue pin sunk / drawn current Vi = VDD3 on pin1 Vi = 0V Iacm Analogue pin sunk / drawn current Vi = VDD3 on pin 2 Vi = 0V Iail Analogue pin sunk / drawn current Vi = VDD3 on pin 3 Vi = 0V Iain Analogue pin sunk / drawn current Vi = VDD3 on pin 4 and pin 5 Vi = 0V Iaih6 Analogue pin current on pin 6 Iaik Analogue pin sunk / drawn current Vi = VDD on pin 15 Vi = 0V (spec absolute value) Ioz Tri-state output leakage IozFT Ilatchup Vesd 5V tolerant tri-state output leakage Vi = 0V (3) with pull-up device 35 60 85 μA -100 -70 -40 μA -40 -30 -20 μA 0.95 1.25 1.55 mA -6.25 -5.0 -3.75 mA 6.0 8.0 10.0 mA -10.0 -8.0 -6.0 mA 3.75 5.0 6.25 mA -1.55 -1.25 -0.95 mA 24 32 40 μA -40 -32 -24 μA 5 μA 1.6 mA 1 μA Vo = 0V or VDD3 without pull up / down device (1) 1 μA Vo = 0V or VDD (1) 1 μA Vo = 5V 80 μA Vo = 0V or VDD3 0.8 1.2 I/O latch up current V < 0V, V > VDD 200 mA Electrostatic protection Leakage, 1μA 2000 V 1. The leakage currents are generally very small, <1nA. The value given here, 1mA, is the maximum that can occur after an electrostatic stress on the pin. 2. On pins: 17 to 20, 23 to 26, 29 to 33, 36 to 39, 42 to 46, 49 to 52, 55 to 58. 3. On pins: 13 and 14. 4. Same check on the analogue pin 15 (physically without pull-up-down) 5. On pins: 25, 26, 32, 49, 50, 55, 56 6. On pins: 17 to 20, 23 to 24, 29 to 31, 33, 36 to 39, 42 to 46, 51, 52, 57, 58 14/39 TDA7580 Table 7. Symbol Block diagram and electrical specifications Low voltage interface CMOS DC electrical characteristics (Tj =-40°C to 125°C; VDD3= 3.3V) Parameter Test condition Vil Low level input voltage 1.70V<=VDD<=1.90V Vih High level input voltage 1.70V<=VDD<=1.90V Min. Typ. Max. Unit 0.2*VDD V 0.8*VDD V (1) Vol Low level output voltage Iol = 4mA Voh High level output voltage Iol = -4mA (1) 0.15 VDD-0,15 V V 1. It is the source/sink current under worst case conditions and reflects the name of the I/O cell according to the drive capability. Table 8. Symbol High voltage CMOS interface DC electrical characteristics (Tj =-40°C to 125°C; VDD=1.8V) Parameter Test condition Vil Low level input voltage 3.15V<=VDD3<=3.45V Vih High level input voltage 3.15V<=VDD3<=3.45V Vol Voh Low level output voltage High level output voltage Iol = XmA Min. Typ. Iol = -XmA Unit 0.8 V 2.0 V (1) (2) (1) (2) Max. 0.15 VDD3-0.15 V V 1. It is the source/sink current under worst case conditions & reflects the name of the I/O cell according to the drive capability 2. X=4mA for pins 17 to 20, 29, 30, 32, 37 to 39, 42 to 46; X=8mA for pins 23 to 26, 49 to 52, 55 to 58. Table 9. Symbol Current consumption (Tj =-40°C to 125°C) Parameter Test condition Min. Typ. Max. Unit 120 150 mA 13 16 mA 50 mA IDD Current through VDD power supply VDD=1.8V,VDD3=3.3V All digital blocks working IDDHdc Static current through VDDH power supply VDD=1.8V,VDD3=3.3V IDDHac Current through VDDH power supply VDD=1.8V,VDD3=3.3V I/Os working with 5pF load ISD Current through VSD power supply VDD=1.8V,VDD3=3.3V 25 35 45 mA IOSCdc Current through VOSC power supply VDD=1.8V,VDD3=3.3V without quartz 5.5 8 10.5 mA IOSCac Current through VOSC power supply VDD=1.8V,VDD3=3.3V with quartz 6.5 9 11.5 mA IMTR Current through VMTR power supply VDD=1.8V,VDD3=3.3V 0.5 1.3 2.0 mA Note: 10 74.1MHz internal DSP clock, at Tamb = 25°C. Current due to external loads not included. 15/39 Block diagram and electrical specifications Table 10. Symbol Oscillator characteristics (Tj =-40°C to 125°C; VDD =1.7V to 1.9V, VDD3 = 3.15V to 3.45V) Parameter FOSCFM Note: TDA7580 Test condition Min. Oscillator frequency (XTI/XTO) Typ. Max. Unit 74.1 MHz The accuracy depends on the quartz frequency precision: high stability oscillator Table 11. Crystal characteristics for 1 and 2 chip load Parameter value Parameter name 1 chip load 2 chips load Temperature range -55°C÷125°C -55°C÷125°C Adjustment tolerance (@ 25°C ± 3°C) ± 30 ppm ± 30 ppm Frequency stability (-20°C÷+70°C) ± 50 ppm ± 50 ppm Aging @ 25°C 5 ppm/year 5 ppm/year Shunt (static) capacitance [Co] <5pF <5pF Motional capacitance 1fF ± 30% 1fF ± 30% Mode of oscillation AT-3rd AT-3rd Resonance resistance < 75 ohm < 45 ohm Capacitive load for oscillation frequency = 74.1MHz 10pF 12pF Table 12. External clock signal on XTI (In case the device is driven by an external clock through the XTI pin, the characteristics reported in this table have to be met) Parameter value Parameter name Min Clock frequency Max 74.10 Frequency stability (-20°C÷+70°C) MHz ppm Clock jitter 10 ps rms Start up time 5 ms 220 640 mV rms 0.50 1.80 V p-p 45 55 % 500 ps Clock level (square wave) (1) Clock duty cycle (square wave) Clock rise / fall time (square wave) 1. specified @ XTI pin of TDA7580 (1) -50 Unit 50 Clock level (sine wave) (1) 16/39 Typ TDA7580 Table 13. Block diagram and electrical specifications DSP core (Tj =-40°C to 125°C) Symbol FdspMax Table 14. Parameter Maximum DSP clock frequency Test condition VDD=1.7V, VDD3= 3.3V Min. Typ. Max. 81.5 Unit MHz FM stereo decoder characteristics (Tj =-40°C to 125°C; VDD =1.7V to 1.9V, VDD3 = 3.15V to 3.45V; BW for measurements 20Hz to 15KHz) Symbol Parameter Test condition Max. Unit 0 dB 0.02 0.04 % 78 80 82 dB Min. Typ. Max. Unit 20Hz to 20kHz, full scale, 16 bit inp. -95 -92 dB 20Hz to 20kHz, full scale, 20 bit inp. -98 -95 dB 1 kHz full scale, 16 bit inp. -98 -95 dB 2 kHz full scale, 16 bit inp. -98 -95 dB 5 kHz full scale, 16 bit inp. -98 -95 dB 10 kHz full scale, 16 bit inp -98 -95 dB 15 kHz full scale, 16 bit inp -98 -95 dB 1 kHz full scale, 20 bit inp. -119 -116 dB 2 kHz full scale, 20 bit inp. -116 -113 dB 5 kHz full scale, 20 bit inp. -112 -109 dB 10 kHz full scale, 20 bit inp -108 -105 dB 15 kHz full scale, 20 bit inp -105 -102 dB a_ch Channel separation (Adjustble by SW from 0 to -45dB) THD Total harmonic distortion 1KHz; mono; Δf=75KHz; (S+N)/N Signal plus noise to noise ratio 1KHz; mono; Δf=40KHz; Min. Typ. -45 MCK = 18.525MHz, Fsin/Fsout = 0.820445366 Table 15. Symbol THD+N Sample rate converter (Tj =-40°C to 125°C; VDD =1.7V to 1.9V, VDD3 = 3.15V to 3.45V); BW for measurements 20Hz to 20KHz Parameter Test condition Total harmonic distortion + noise Dynamic Range 1 kHz -60 dB - 16 bit inp. A-weighted 97 100 dB fratio = 0.82 1 kHz -60 dB - 24 bit inp. A-weighted 141 145 dB Pass band ripple from 20Hz to 15kHz Sampling frequency in/out ratio Fsout = 44.1 kHz DR Rp Fratio 0.4 0.7 0.5 dB 1.13 17/39 Block diagram and electrical specifications Figure 3. TDA7580 Power on and boot sequence using I2C VDD3 VDD INT RESETN ADDR_SD IFS SLAVE=1 IFS MASTER=0 PROTSEL_SS RDS_CS GPIO_SDO1 I2C/SPI SLAVE=1 I2C/SPI MASTER=0 TST1_SDI1 Boot SDA_MOSI tint trhd tvdd3 SW download Data Tuner data tdat tsw trsu tvdd Figure 4. RDS init tseq treson ttun Power on and boot sequence using SPI VDD3 VDD INT RESETN IFS SLAVE=1 IFS MASTER=0 ADDR_SD PROTSEL_SS RDS_CS GPIO_SDO1 I2C/SPI SLAVE=1 I2C/SPI MASTER=0 TST1_SDI1 Boot SDA_MOSI tint trhd tvdd3 tvdd 18/39 RDS init SW download tdat tsw trsu treson tseq Data Tuner data ttun TDA7580 Block diagram and electrical specifications Table 16. SPI and I2C timing table (Tj =-40°C to 125°C; VDD =1.7V to 1.9V, VDD3 = 3.15V to 3.45V) Timing Description Min Typ Max Unit tvdd3 Rise time of 3.3V supply 1 13 25 ms tvdd Rise time of 1.8V supply 1 6 10 ms tint Maximux delay for INT signal - - 1 ms Minimum RESETN hold time at 0 after the start-up 40 - - ms trsu Minimum data set-up time 250 μs trhd Minimum data hold time 250 μs tseq Minimum wait time including boot 4 ms tsw Minimum wait time before downloading the program software 30 μs ttun Minimum wait time before downloading the software to the FE 1 μs tdat Minimum wait time before using interface protocols 1 μs treson 19/39 SAI Interface 3 TDA7580 SAI Interface Figure 5. SAI Timings SDI0-1 Valid Valid LRCKR SCKR (RCKP=0) tlrs tdt tsdis tlrh tsdih tsckpl tsckph tsckr Table 17. SAI Timing table (Tj =-40°C to 125°C; VDD =1.7V to 1.9V, VDD3 = 3.15V to 3.45V) Cload The values on the table are consistent with a capacitance load on SAI lines of 160pF Timing Min Typ Max Unit Clock Cycle 302 976 ns tdt SCKR active edge to data out valid 48 65 ns tlrs LRCK setup time 25 ns tlrh LRCK hold time 25 ns tsdis SDI setup time 65 ns tsdih SDI hold time 65 ns tsckph SCK high time 146 ns tsckpl SCK low time 146 ns tsckr Note: Description TDSP = DSP master clock cycle time = 1/FDSP Figure 6. LRCKR SAI protocol (when: RLRS=0; RREL=0; RCKP=1; RDIR=0) LEFT RIGHT SCKR SDI0-1 20/39 LSB(n-1) MSB(n) MSB-1(n) MSB-2(n) TDA7580 SAI Interface Figure 7. SAI protocol (when: RLRS=1; RREL=0; RCKP=1; RDIR=1) LEFT LRCKR RIGHT SCKR SDI0-1 Figure 8. MSB(n-1) LSB(n) LSB+1(n) LSB+2(n) SAI protocol (when: RLRS=0; RREL=0; RCKP=0; RDIR=0) LEFT LRCKR RIGHT SCKR SDI0-1 Figure 9. LRCKR LSB(n-1) MSB(n) MSB-1(n) MSB-2(n) SAI protocol (when: RLRS=0; RREL=1; RCKP=1; RDIR=0) LEFT RIGHT SCKR SDI0-1 LSB(n-1) MSB(n) MSB-1(n) MSB-2(n) 21/39 RDS SPI interface 4 TDA7580 RDS SPI interface Figure 10. RDS SPI timings SS Valid MISO MOSI SCL (CPOL=0,CPHA=0) tdtr tsetup tsshold tssw thold tsssetup tsclkl tsclkh tsclk Table 18. RDS SPI timing table (Tj =-40°C to 125°C; VDD =1.7V to 1.9V, VDD3 = 3.15V to 3.45V) Cload The values on the table are consistent with a capacitance load on RDS SPI lines of 80pF Symbol Description Min Typ Max Unit Slave configured tsclk Clock cycle 1240 tdtr Sclk edge to MISO valid 239 tsetup MOSI setup time 255 ns thold MOSI hold time 365 ns tsclkh SCK high time width 620 ns tsclkl SCK low time width 620 ns tsssetup SS setup time 620 ns tsshold SS hold time 620 ns SS pulse width 1240 ns tssw 22/39 ns 365 ns TDA7580 RDS SPI interface Figure 11. RDS SPI clocking scheme SS(#17) SCK(#20) (CPOL=0,CPHA=0) SCK(#20) (CPOL=0,CPHA=1) SCK(#20) (CPOL=1,CPHA=0) SCK(#20) (CPOL=1,CPHA=1) MISO(#19) MOSI(#18) MSB 6 5 4 3 2 1 0 23/39 BSPI interface 5 TDA7580 BSPI interface (Tj =-40°C to 125°C; VDD =1.7V to 1.9V, VDD3 = 3.15V to 3.45V) Cload The values on the table are consistent with a capacitance load on BSPI lines of 160pF) Figure 12. BSPI timings SS Valid MISO MOSI SCL (CPOL=0,CPHA=0) tdtr tsetup tsshold thold tssw tsssetup tsclkl tsclkh tsclk Table 19. BSPI timing table Symbol Description Min Typ Max Unit Master configured tsclk Clock cycle 184 tdtr Sclk edge to MOSI valid 61 tsetup MISO setup time 52 ns thold MISO hold time 52 ns tsclkh SCK high time 92 ns tsclkl SCK low time 92 ns tsssetup SS setup time 92 ns tsshold SS hold time 92 ns SS pulse width 184 ns ns tssw ns 92 ns Slave configured tsclk Clock cycle 238 tdtr Sclk edge to MISO valid 88 tsetup MOSI setup time 65 ns thold MOSI hold time 65 ns tsclkh SCK high time 119 ns tsclkl SCK high low 119 ns tsssetup SS setup time 119 ns tsshold SS hold time 119 ns SS pulse width 238 ns tssw 24/39 119 ns TDA7580 BSPI interface Figure 13. BSPI clocking scheme SS(#17) SCK(#20) (CPOL=0,CPHA=0) SCK(#20) (CPOL=0,CPHA=1) SCK(#20) (CPOL=1,CPHA=0) SCK(#20) (CPOL=1,CPHA=1) MISO(#19) MOSI(#18) MSB 6 5 4 3 2 1 0 25/39 Inter processor transport interface for antenna diversity 6 TDA7580 Inter processor transport interface for antenna diversity (Tj =-40°C to 125°C; VDD =1.7V to 1.9V, VDD3 = 3.15V to 3.45V) Cload. The values on the table are consistent with a capacitance load on HS3I lines of 20pF Figure 14. High speed synchronous serial interface - HS3I Master Bit Clock Master Data Out M2 M3 256 cycles of 74.1MHz Master Synch Slave Data Out S0 S1 S2 S3 Figure 15. HS3I clocking scheme tmbco tsdos tmbcs Master Bit Clock tmbcc Master Data Out Master Synch Slave Data Out Table 20. HS3I timing table Timing Note: 26/39 Description Min Max Unit 107.97 ns tsclk MBC clock cycle tdtr MBC active edge to master data out valid 4 ns tsetup MBC active edge to master synch valid 4 ns thold Slave data out setup time 6 ns TDSP = DSP master clock cycle time = 1/FDSP 107.95 Typ I2C timing TDA7580 I2C timing 7 Figure 16. DSP and RDS I2C BUS timings Table 21. Symbol I2C BUS timing table (Tj =-40°C to 125°C; VDD =1.7V to 1.9V, VDD3 = 3.15V to 3.45V) Parameter Test condition Standard mode I2C BUS Fast mode I2C BUS Unit Min. Max. Min. Max. 0 100 0 400 kHz FSCL SCLl clock frequency tBUF Bus free between a stop and start condition 4800 – 1300 – ns Hold time (repeated) START condition. After this period, the first clock pulse is generated 4800 – 600 – ns tLOW LOW period of the SCL clock 4800 – 1300 – ns tHIGH HIGH period of the SCL clock 4800 – 600 – ns tSU:STA Set-up time for a repeated start condition 4800 – 600 – ns tHD:DAT DATA hold time 0 - 0 900 ns tHD:STA tR Rise time of both SDA and SCL signals Cb in pF – 300 12+0.1Cb 300 ns tF Fall time of both SDA and SCL signals Cb in pF – 300 12+0.1Cb 300 ns tSU;STO Set-up time for STOP condition 4800 – 600 – ns tSU:DAT Data set-up time 250 – 250 – ns Capacitive load for each bus line 10 400 10 400 pF Cb 27/39 Functional description 8 TDA7580 Functional description The TDA7580 IC offers a solution for high performance FM/AM car radio receivers. The high processing power allows audio processing of both internal and external audio source. The processing engine is based on a 24bit programmable DSP, with separate banks of program and data RAMs. A number of hardware modules (peripherals) help in the algorithm implementation of channel equalization and FM/AM baseband post processing. The HW architecture allows to perform dual tuner diversity. In this case two TDA7580 are needed: one device must be configurated as master, generates the clock and controls the main data interfaces. The second device becomes the slave and converts the second IF path, as well as helps the first chip as co-processor. 8.1 24 bit DSP core Some capabilities of the DSP are listed below: 28/39 ● Single cycle multiply and accumulate with convergent rounding and condition code generation ● 24 x 24 to 56-bit MAC Unit ● Double precision multiply ● Scaling and saturation arithmetic ● 48-bit or 2 x 24-bit parallel moves ● 64 interrupt vector locations ● Fast or long interrupts possible ● Programmable interrupt priorities and masking ● Repeat instruction and zero overhead DO loops ● Hardware stack capable of nesting combinations of 7 DO loops or 15 interrupts / subroutines ● Bit manipulation instructions possible on all registers and memory locations, also jump on bit test ● 4 pin serial debug interface ● Debug access to all internal registers, buses and memory locations ● 5 word deep program address history FIFO ● Hardware and software breakpoints for both program and data memory accesses ● Debug single stepping, instruction injection and disassembly of program memory TDA7580 8.2 Functional description DSP peripherals ● Clock generation unit (CGU) ● Stereo decoder (HWSTER) ● Serial audio interface (SAI) ● Tuner AGC keying DAC (KEYDAC) ● Programmable I/O interface (I2C/BSPI) ● Asynchronous sample rate converter (ASRC) ● IF band pass sigma delta modulator (IFADC) ● Digital down converter (DDC) ● Discriminator (CORDIC) ● RDS ● Tuner diversity HS3I The peripherals are mapped in the X memory space. Most of them can be handled by interrupt, with software programmable priority. Peripherals running at very high rate have direct access to X and Y data bus for very fast movement from or to the core, by mean of single cycle instruction. 8.3 Clock generation unit (CGU) and oscillator This unit is responsible for supplying all necessary clocks and synchronization signals to the whole chip. The control status register of this unit contains information about the current working mode (oscillator [master mode] or clock buffer [slave mode]), the tuner clock frequency setting, the general setup of the oscillator. This last function is performed inside the CGU, that establishes using a self trimming algorithm, which is the current values that can bias the oscillator: this feature lets the oscillator be independent from process parameters variation. The values of bias current are stored in the control status register of the CGU: 4 bits for the coarse current steps and 6 bits for the fine current steps. In slave mode the oscillator behaves as a buffer: the chip can be then driven using an external clock. The clock divider, placed in this unit, generates the tuner the reference clock and can be programmed for frequencies down to 9KHz with selectable duty cycle and from 4.4Hz to 9KHz with duty cycle 50%. An external clock can drive the XTI pin (please see Table 12 for reference). 8.4 Stereo decoder (HWSTER) The fully digital hardware stereo decoder does all the signal processing necessary to demodulate an FM MPX signal which is prepared by the channel equalization algorithm in the digital IF sampling device, providing pilot tone dependent mono/stereo switching, as well as stereo-blend and highcut functionality. Selectable de-emphasis time constant allow the use of this module for different FM radio receiver standards. 29/39 Functional description TDA7580 There are built in filters for field strength processing. In order to obtain the maximum flexibility the field strength processing and noise cancellation, however, are implemented as software inside the programming DSP, which has to provide control signals for the stages softmute, stereoblend, and highcut. 8.5 Serial audio interface (SAI) The two SAI modules have been embedded in such a way great flexibility is available in their use. The two modules are fully separate and they each have a receive and a transmit channel, as well as they can be selected as either master or slave. The bit clocks and left & right clocks are routed through the pins, so the audio interface can be chosen to be adapted to a large variety of application. One SAI transmit channel can have the asynchronous sample rate converter in front, thus separate different audio rate domains. Additional feature are: 8.6 ● support of 16/24/32 bit word length ● programmable left/right clock polarity ● programmable rising/falling edge of the bit clock for data valid ● programmable data shift direction, MSB or LSB received / transmitted first I2C interfaces The inter integrated circuit bus is a single bidirectional two wire bus used for efficient inter IC control. All I2C bus compatible devices incorporate an on-chip interface which allows them communicate directly with each other via the I2C bus. Every component hooked up to the I2C bus has its own unique address whether it is a CPU, memory or some other complex function chip. Each of these chips can act as a receiver and /or transmitter on its functionality. Two pins are used to interface both I2C of the DSP and RDS, which have different internal I2C address, thus reducing the on board pin interconnections. 8.7 Serial peripheral interfaces The DSP and RDS can have this serial interface, alternative to the I2C one. DSP and RDS SPI modules have separate pin for chip select. The DSP SPI has a ten 24 bit words deep FIFO for both receive and transmit sections, which reduces DSP processing overhead even at high data rate. The serial interface is needed to exchange commands and data over the LAN. During an SPI transfer, data is transmitted and received simultaneously. A serial clock line synchronizes shifting and sampling of the information on the two serial data lines. A slave select line allows individual selection of a slave SPI device. When an SPI transfer occurs an 8-bit word is shifted out one data pin while another 8-bit character is simultaneously shifted in a second data pin. The central element in the SPI 30/39 TDA7580 Functional description system is the shift register and the read data buffer. The system is single buffered in the transfer direction and double buffered in the receive direction. 8.8 High speed serial synchronous interface (HS3I) The high speed serial synchronous interface is a module to send and receive data at high rate (up to 9.25Mbit/s per channel) in order to exchange data between 2 separate TDA7580 chip. The exchanged data are related to signals that are used to increase reception quality in car radio systems, which make use of antenna diversity based upon two separate antenna and tuner sections. The channel synchronization clock has a programmable duty cycle, so to reduce in band harmonics noise. 8.9 Tuner AGC keying DAC (KEYDAC) This DAC provides the front-end tuner with an analogue signal to be used to control the automatic gain controlled stage, thus giving all time the best voltage dynamic range at the IFADC input. 8.10 Asynchronous sample rate converter (ASRC) This hardware module provides a very flexible way to adapt the internal audio rate, to the one of an external source. It does not require further work off the DSP. There is no need to explicitly configure the input and the output sample rates, as the ASRC solves this problem with an automatic digital ratio locked loop. Main features are: 8.11 ● Automatic tracking of sample frequency ● Fully digital ratio locked loop ● Sampling clock jitter rejection ● Up conversion up to 1:2 Ratio ● Linear phase IF band pass Σ Δ analogue to digital converter (IFADC) The IFADC is a band pass Sigma Delta A to D converter with sampling rate of 37.05MHz (nominal) and notch frequency of 10.7MHz. The structure is a second order switched capacitor multi bit modulator with self calibration algorithm to adjust the notch frequency. The differential ended input allows 4.0Vpp voltage dynamic range, and reduces the inferred noise back to the previous stage (tuner), and in turn gives high rejection to common mode noises. The high linearity (very high IMD) is needed to fulfill good response of the channel equalization algorithm. Low thermal and 1/f noise assures high dynamic range. 31/39 Functional description 8.12 TDA7580 Digital down converter (DDC) The DDC module allows to evaluate the in-phase and quadrature components of the incoming digital IF signal. The I and Q computation is performed by the DDC block, which at the same time shifts down to 0-IF frequency the incoming digital signal. After the down conversion the rate is still very high (at the 37.05MHz rate); a SincK filter samples data down by a factor of 32, decreasing it to 1.1578MHz. An additional decimation is performed by the subsequent FIR filters, thus lowering the data rate at the final 289.45kHz, being the MPX data rate. 8.13 RDS The RDS block is an hardware cell able to process RDS/RBDS signal, intended for recovering the inaudible RDS/RBDS information which are transmitted by most of FM radio broadcasting stations. It comprises of the following: ● Demodulation of the european radio data system (RDS) ● Demodulation of the US radio broadcast data system (RDBS) ● Automatic group and block synchronisation with flywheel mechanism ● Error detection and correction ● RAM buffer with a storage capacity of 24 RDS blocks and related status information ● I2C and SPI interface, with pins shared with the DSP I2C/SPI After filtering the oversampled MPX signal, the RDS/RDBS demodulator extracts the RDS data clock, RDS data signal and the quality information. The following RDS/RBDS decoder synchronizes the bitwise RDS stream to a group and block wise information. This processing also includes error detection and error correction algorithms. In addition, an automatic flywheel control avoids exhausting the data exchange between RDS/RDBS processor and the host. 8.14 AM/FM Detector (CORDIC) The AM/FM detector is a fully programmable peripheral used to detect the phase, amplitude and frequency information of an input complex signal (in-phase and quadrature signals). It can be used to demodulate PM, AM and FM modulated signals. The detection is performed using a high accuracy CORDIC algorithm, working essentially as a cartesian to polar transformer. Four CORDICs are available to allow concurrent software calls. 32/39 TDA7580 Application diagrams 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 1 64 Figure 17. Radio mode with external slave audio DAC 48 2 47 TST3_LRCKR TST2_SCKR LRCK_LRCKT SCLK_SCKT SDO0 3 4 5 6 7 8 46 45 44 43 42 41 TDA7580 9 40 35 15 34 16 33 28 27 26 25 24 23 22 21 20 19 18 17 Fs=36kHz 1 8 2 7 3 6 4 5 TDA7535 Dual DAC 32 36 14 31 GPIO_SDO1 37 13 30 12 29 11 TST1_SDI1 39 TST4_SDI0 38 10 In this mode an external slave stereo DAC, like the ST TDA7535, can be easily connected and the TDA7580 outputs the audio from radio station at 36kHz rate. 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 1 64 Figure 18. Radio mode with external master audio device 48 2 47 3 TST3_LRCKR 46 4 TST2_SCKR LRCK_LRCKT SCLK_SCKT SDO0 5 6 7 8 9 45 44 1 43 2 42 41 TDA7580 4 External Audio Receiver with its owned audio rate Fs 32 31 30 29 28 27 33 26 34 16 25 15 24 35 23 36 14 22 GPIO_SDO1 37 13 21 12 20 TST1_SDI1 39 TST4_SDI0 38 19 11 18 3 Fs 40 10 17 9 Application diagrams An external digital audio device is connected externally as a digital audio master, and the internal TDA7580 sample rate converter is responsible for the conversion from internal 36kHz to the external audio rate. 33/39 Application diagrams TDA7580 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 1 64 Figure 19. Audio mode with external slave audio device 48 2 47 3 TST3_LRCKR 46 4 TST2_SCKR LRCK_LRCKT SCLK_SCKT SDO0 5 6 7 8 TDA7580 9 45 44 43 42 1 8 41 2 7 3 6 4 5 1 8 40 10 CD Player Fs=44.1kHz Fs=44.1kHz 7 3 6 15 34 4 5 16 33 TDA7535 Analog In 32 27 26 25 24 23 22 21 20 19 18 17 31 2 35 30 36 14 29 13 11 28 12 TST1_SDI1 39 TST4_SDI0 38 GPIO_SDO1 37 ADC The 2 stereo channel serial audio interface of the TDA7580 chip allows a very flexible application in which external audio source/sinks can be connected. The example shows an external CD player digital output giving the main Fs audio rate of the whole system. This rate is also the one of the external DACs and an ADC, being configured as slave. 34/39 4.7 mF Note: 22 23 28 25 26 30 31 4.7 mF 15pF (*) SCL SDA VDDA 22pF 22pF 220pF DAGC Frel- Frel+ IFOUT2 IFOUT1 VDDH (**) 10pF 470nF SCL 10µF VDD 470 I2C BUS 470 XTI XTO 29 12 10 9 8 11 30 21 22 20 18 16 15 14 13 5 4 7 6 3 2 1 MASTER/SLAVE SELECTION (STATION DETECTOR AFTER RESET) DSP_INTERRUPT RDS_INTERRUPT {put pull-up on board} RDS_INT VDDMTR 180R 5.6pF GNDOSC VDDOSC RDS_CS GND VDD SCL_SCK SDA_MOSI GNDMTR AGCKEY 470 CKREFP INM INP GNDSD CKREFN SDA VLO VCMOP 470 470 10nF 10nF 4.7 mF VDA RANGE 5.6pF TO 10pF 470nF DEPENDING ON BOARD PARASITICS (**) VDA and VDD = 1.8V VDDA and VDDH = 3.3V (*) OPTIONAL TDA7515 10 mF VHI INT 31 ADDR_SD 32 GNDH 100nF VDDH VDDH 27 28 TQFP64 63 GNDH 100nF VDDH VDDH TDA7580 62 VDDH VDDSD 64 61 GND VDD TESTN RO VDDH VDD 10µF VDD VDDH 100nF 10µF 100nF VDDH 470nF VDDA VDD RO RO RO 10K(*) 10K(*) 10µF GPIO_SDO1 GNDH VDDH GND VDD GNDH VDDH RESETN GND VDD SDOUT_SDO0 SCLK0_SCKT LRCK0_LRCKT DBRQ0 DBRQ1 TST3_LRCKR VDDISO 35 34 36 37 40 41 48 47 53 54 33 60 59 42 43 44 51 57 46 VDDA GNDA GNDD SDATA SCK FSYNC VDDH VDDH 10 6 5 2 3 13 14 SO14 7 8 TDA7535 9 12 ADDITIONAL GPIO 10mF 220nF 220nF RSTN R_Audio OUTSR L_Radio OUTSL VCM VDDD RO = 0±1KW To prevent Electromagnetic injection 9.1 VCM TDA7580 Application diagrams Electrical application scheme The following application diagram is only an example. For real application setup, it is necessary to refer to the application notes. Figure 20. Application diagram example VCMOP capacitor (4.7uF) is only needed for CA silicon. This is needed to be consistent with "pin description " in Table 6 35/39 Package marking 10 Package marking Figure 21. Package marking 36/39 TDA7580 TDA7580 Package information In order to meet environmental requirements, ST offers these devices in ECOPACK® packages. These packages have a lead-free second level interconnect. The category of second level interconnect is marked on the package and on the inner box label, in compliance with JEDEC standard JESD97. The maximum ratings related to soldering conditions are also marked on the inner box label. ECOPACK is an ST trademark. ECOPACK specifications are available at: www.st.com. Figure 22. Mechanical, data and package dimensions mm inch DIM. MIN. TYP. MAX. A MIN. TYP. 1.60 0.063 A1 0.05 0.15 0.002 A2 1.35 1.40 1.45 0.053 B 0.17 0.22 0.27 0.0066 0.0086 0.0106 0.006 0.055 0.057 C 0.09 0.20 0.0035 D 11.80 12.00 12.20 0.464 0.472 0.480 D1 9.80 10.00 10.20 0.386 0.394 0.401 0.0079 D3 7.50 0.295 e 0.50 0.0197 E 11.80 12.00 12.20 0.464 E1 9.80 10.00 10.20 0.386 E3 7.50 L 0.45 OUTLINE AND MECHANICAL DATA MAX. 0.472 0.480 0.394 0.401 0.295 0.60 0.75 0.0177 0.0236 0.0295 L1 1.00 K 0˚ (min.), 3.5˚ (min.), 7˚(max.) 0.0393 ccc 0.080 LQFP64 (10 x 10 x 1.4mm) 0.0031 D D1 A D3 A2 A1 48 33 49 32 0.08mm ccc B Seating Plane E E1 E3 B 17 64 1 16 C e L L1 11 Package information K TQFP64 0051434 F 37/39 Revision history 12 TDA7580 Revision history Table 22. 38/39 Document revision history Date Revision Changes 24-Jan-06 1 Initial release. 01-Jun-04 2 Changed the style look following the “Corporate technical publications design guide. Changed the maturity from product preview to final. 01-Dec-04 3 Included legend for I/O definition. Included separated specification for the 2 SPI (BSPI and RDS-SPI). Upgraded all tables with temperature range and electrical / timing parameters. Changed description of PIN 6 in PIN description table. Added new sub section titled AM/FM Detector (CORDIC). 01-Jan-06 4 Updated all tables. 09-Mar-07 5 Package changed, layout and text modifications TDA7580 Please Read Carefully: Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at any time, without notice. All ST products are sold pursuant to ST’s terms and conditions of sale. Purchasers are solely responsible for the choice, selection and use of the ST products and services described herein, and ST assumes no liability whatsoever relating to the choice, selection or use of the ST products and services described herein. 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