TI THS4281DBVR

THS4281
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SLOS432 – APRIL 2004
VERY LOW-POWER, HIGH-SPEED, RAIL-TO-RAIL INPUT AND OUTPUT
VOLTAGE-FEEDBACK OPERATIONAL AMPLIFIER
FEATURES
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DESCRIPTION
Very Low Quiescent Current: 750 µA (at 5 V)
Rail-to-Rail Input and Output:
– Common-Mode Input Voltage Extends
400 mV Beyond the Rails
– Output Swings Within 150 mV From the
Rails
Wide -3 dB Bandwidth at 5 V:
– 90-MHz @ Gain = +1, 40 MHz @ Gain = +2
High Slew Rate: 35 V/µs
Fast Settling Time (2-V Step):
– 78 ns to 0.1%
– 150 ns to 0.01%
Low Distortion @ Gain = +2, VO = 2-Vpp, 5 V:
– -91 dBc at 100 kHz, -67 dBc at 1 MHz
Input Offset Voltage: 2.5 mV (Max at 25°C)
Output Current >30 mA (10-Ω Load, 5 V)
Low Voltage Noise of 12.5 nV/√Hz
Supply Voltages: +2.7 V, 3 V, +5 V, ±5 V, +15 V
Packages: SOT-23, MSOP, and SOIC
Fabricated using the BiCom-II process, the THS4281
is a low-power, rail-to-rail input and output voltage-feedback operational amplifier designed to
operate over a wide power supply range of 2.7-V to
15-V single supply, and ±1.35-V to ±7.5-V dual
supply. Consuming only 750 µA with a unity gain
bandwidth of 90 MHz and a high 35-V/µs slew rate,
the THS4281 allows portable or other power-sensitive
applications to realize high performance with minimal
power. To ensure long battery life in portable applications, the quiescent current is trimmed to be less
than 900 µA at 25°C, and 1 mA from –40°C to 85°C.
The THS4281 is a true single-supply amplifier with a
specified common-mode input range of 400 mV
beyond the rails. This allows for high-side current
sensing applications without phase reversal concerns. Its output swings to within 40 mV from the rails
with 10-kΩ loads, and 150 mV from the rails with
1-kΩ loads.
The THS4281 has a good 0.1% settling time of 78 ns,
and 0.01% settling time of 150 ns. The low THD of
-87 dBc at 100 kHz, coupled with a maximum offset
voltage of less than 2.5 mV, makes the THS4281 a
good match for high-resolution ADCs sampling less
than 2 MSPS.
APPLICATIONS
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Portable/Battery-Powered Applications
High Channel Count Systems
ADC Buffer
Active Filters
Current Sensing
The THS4281 is offered in a space-saving SOT-23-5
package, a small MSOP-8 package, and the industry
standard SOIC-8 package.
470 pF
V BAT
500 I
2.5 k
RSENSE
V OUT = I RSENSE
VBAT
VBAT
0.2 −
500 +
Load
100 470 pF
THS4281
+IN
ADS8320
−IN
10 nF
2.5 k
VBAT/2
High-Side, Low Power Current-Sensing System
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
FilterPro is a trademark of Texas Instruments.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2004, Texas Instruments Incorporated
THS4281
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SLOS432 – APRIL 2004
These devices have limited built-in ESD protection. The leads should be shorted together or the device
placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates.
ABSOLUTE MAXIMUM RATINGS (1)
over operating free-air temperature range (unless otherwise noted)
UNIT
Supply voltage, VS- to VS+
16.5 V
±VS± 0.5 V
Input voltage, VI
±2 V
Differential input voltage, VID
±100 mA
Output current, IO
Continuous power dissipation
See Dissipation Rating Table
Maximum junction temperature, any condition,
(2)
TJ
Maximum junction temperature, continuous operation, long term
150°C
reliability (2)
TJ
125°C
Storage temperature range, Tstg
-65°C to 150°C
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds
ESD ratings
(1)
(2)
300°C
HBM
3500 V
CDM
1500 V
MM
100 V
The absolute maximum ratings under any condition is limited by the constraints of the silicon process. Stresses above these ratings may
cause permanent damage. Exposure to absolute maximum conditions for extended periods may degrade device reliability. These are
stress ratings only, and functional operation of the device at these or any other conditions beyond those specified is not implied.
The maximum junction temperature for continuous operation is limited by package constraints. Operation above this temperature may
result in reduced reliability and/or lifetime of the device. recommended operating conditions.
RECOMMENDED OPERATING CONDITIONS
Supply voltage, (VS+ and VS -)
Dual supply
Single supply
MIN
MAX
±1.35
±8.25
2.7
16.5
UNIT
V
DISSIPATION RATINGS TABLE PER PACKAGE
θJC
(°C/W)
θJA (1)
(°C/W)
DBV (5)
55
D (8)
38.3
DGK (8)
71.5
PACKAGE
(1)
(2)
2
POWER RATING (2)
TA < 25°C
TA = 85°C
255.4
391 mW
156 mW
97.5
1.02 W
410 mW
180.8
553 mW
221 mW
This data was taken using the JEDEC standard High-K test PCB.
Power rating is determined with a junction temperature of 125°C. This is the point where distortion starts to substantially increase.
Thermal management of the final PCB should strive to keep the junction temperature at or below 125°C for best performance and long
term reliability.
THS4281
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SLOS432 – APRIL 2004
PACKAGING/ORDERING INFORMATION
PACKAGED DEVICES
DEVICE MARKING
PACKAGE TYPE
AON
SOT-23 - 5
--
SOIC - 8
AOO
MSOP - 8
THS4281DBVT
THS4281DBVR
THS4281D
THS4281DR
THS4281DGK
THS4281DGKR
TRANSPORT MEDIA, QUANTITY
Tape and Reel, 250
Tape and Reel, 3000
Rails, 75
Tape and Reel, 2500
Rails, 75
Tape and Reel, 2500
PIN CONFIGURATION
TOP VIEW
DBV
TOP VIEW
D and DGK
THS4281
VOUT
1
VS−
2
IN+
3
5
4
THS4281
VS+
NC
1
8
NC
IN−
2
7
VS+
IN+
3
6
VOUT
VS−
4
5
NC
IN−
NOTE: NC indicates there is no internal connection to these pins.
3
THS4281
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SLOS432 – APRIL 2004
ELECTRICAL CHARACTERISTICS, VS = 3 V (VS+ = 3 V, VS- = GND)
G = +2, RF = 2.49 kΩ, RL = 1 kΩ to 1.5 V, unless otherwise noted
TYP
PARAMETER
CONDITIONS
OVER TEMPERATURE
UNITS
MIN/
MAX
83
MHz
Typ
G = +2, VO = 100 mVpp,
RF = 1.65 kΩ
40
MHz
Typ
G = +5, VO = 100 mVpp,
RF = 1.65 kΩ
8
MHz
Typ
G = +10, VO = 100 mVpp,
RF = 1.65 kΩ
3.8
MHz
Typ
20
MHz
Typ
25°C
25°C
0°C to
70°C
-40°C
to 85°C
AC PERFORMANCE
G = +1, VO = 100 mVpp,
RF = 34 Ω
Small-Signal Bandwidth
0.1 dB Flat Bandwidth
G = +2, VO = 100 mVpp,
RF = 1.65 kΩ
Full-Power Bandwidth
G = +2, VO = 2 Vpp
8
MHz
Typ
G = +1, VO = 2-V Step
26
V/µs
Typ
G = -1, VO = 2-V Step
27
V/µs
Typ
Slew Rate
Settling time to 0.1%
G = -1, VO = 1-V Step
80
ns
Typ
Settling time to 0.01%
G = -1, VO = 1-V Step
155
ns
Typ
Rise/Fall Times
G = +1, VO = 2-V Step
55
ns
Typ
Harmonic Distortion
G = +2, VO = 2 Vpp
-52
dBc
Typ
-52
dBc
Typ
-69
dBc
Typ
-71
dBc
Typ
VO = 1 Vpp, f = 10 kHz
0.003
%
Typ
VO = 2 Vpp, f = 10 kHz
0.03
%
Typ
0.05/0.08
%
Typ
0.25/0.35
°
Typ
Second Harmonic Distortion
Third Harmonic Distortion
Second Harmonic Distortion
Third Harmonic Distortion
THD + N
Differential Gain (NTSC/PAL)
Differential Phase (NTSC/PAL)
f = 1 MHz, RL = 1 kΩ
f = 100 kHz, RL = 1 kΩ
G = +2, RL = 150 Ω
Input Voltage Noise
f = 100 kHz
12.5
nA/√Hz
Typ
Input Current Noise
f = 100 kHz
1.5
pA/√Hz
Typ
Open-Loop Voltage Gain (AOL)
95
dB
Typ
Input Offset Voltage
0.5
Max
DC PERFORMANCE
2.5
Average Offset Voltage Drift
Input Bias Current
Average Bias Current Drift
VCM = 1.5 V
Input Offset Current
0.5
0.1
0.8
0.4
Average Offset Current Drift
3.5
3.5
mV
±7
±7
µV/°C
Typ
1
1
µA
Max
±2
±2
nA/°C
Typ
0.5
0.5
µA
Max
±2
±2
nA/°C
Typ
Min
INPUT CHARACTERISTICS
Common-Mode Input Range
-0.4/3.4
-0.3/3.3
-0.1/3.1
-0.1/3.1
V
Common-Mode Rejection Ratio
VCM = 0 V to 3 V
92
75
70
70
dB
Min
Input Resistance
Common-mode
100
MΩ
Typ
Input Capacitance
Common-mode/Differential
0.8/1.2
pF
Typ
4
THS4281
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SLOS432 – APRIL 2004
ELECTRICAL CHARACTERISTICS, VS = 3 V (VS+ = 3 V, VS- = GND) (continued)
G = +2, RF = 2.49 kΩ, RL = 1 kΩ to 1.5 V, unless otherwise noted
TYP
PARAMETER
CONDITIONS
25°C
OVER TEMPERATURE
25°C
0°C to
70°C
-40°C
to 85°C
UNITS
MIN/
MAX
V
Typ
OUTPUT CHARACTERISTICS
Output Voltage Swing
RL = 10 kΩ
0.04/2.96
RL = 1 kΩ
0.1/2.9
0.14/2.86
0.2/2.8
0.2/2.8
V
Min
Output Current (Sourcing)
RL = 10 Ω
23
18
15
15
mA
Min
Output Current (Sinking)
RL = 10 Ω
29
22
19
19
mA
Min
Output Impedance
f = 1 MHz
1
Ω
Typ
POWER SUPPLY
Maximum Operating Voltage
3
16.5
16.5
16.5
V
Max
Minimum Operating Voltage
3
2.7
2.7
2.7
V
Min
Maximum Quiescent Current
0.75
0.9
0.98
1.0
mA
Max
Minimum Quiescent Current
0.75
0.6
0.57
0.55
mA
Min
Power Supply Rejection (+PSRR)
VS+ = 3.25 V to 2.75 V,
VS- = 0 V
90
70
65
65
dB
Min
Power Supply Rejection (-PSRR)
VS+ = 3 V, VS- = 0 V to 0.65 V
90
70
65
65
dB
Min
5
THS4281
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SLOS432 – APRIL 2004
ELECTRICAL CHARACTERISTICS, VS = 5 V (VS+ = 5 V, VS- = GND)
G = +2, RF = 2.49 kΩ, RL = 1 kΩ to 2.5 V, unless otherwise noted
TYP
PARAMETER
CONDITIONS
25°C
OVER TEMPERATURE
25°C
0°C to
70°C
-40°C to
85°C
UNITS
MIN/
MAX
AC PERFORMANCE
G = +1, VO = 100 mVpp,
RF = 34 Ω
90
MHz
Typ
G = +2, VO = 100 mVpp,
RF = 2 kΩ
40
MHz
Typ
G = +5, VO = 100 mVpp,
RF = 2 kΩ
8
MHz
Typ
G = +10, VO = 100 mVpp,
RF = 2 kΩ
3.8
MHz
Typ
0.1-dB Flat Bandwidth
G = +2, VO = 100 mVpp,
RF = 2 kΩ
20
MHz
Typ
Full-Power Bandwidth
G = +2, VO = 2 Vpp
9
MHz
Typ
G = +1, VO = 2-V Step
31
V/µs
Typ
G = -1, VO = 2-V Step
34
V/µs
Typ
Small-Signal Bandwidth
Slew Rate
Settling Time to 0.1%
G = -1, VO = 2-V Step
78
ns
Typ
Settling Time to 0.01%
G = -1, VO = 2-V Step
150
ns
Typ
Rise/Fall Times
G = +1, VO = 2-V Step
48
ns
Typ
Harmonic Distortion
G = +2, VO = 2 Vpp
-67
dBc
Typ
-76
dBc
Typ
Second Harmonic Distortion
Third Harmonic Distortion
Second Harmonic Distortion
Third Harmonic Distortion
THD + N
Differential Gain (NTSC/PAL)
Differential Phase (NTSC/PAL)
f = 1 MHz, RL = 1 kΩ
-92
dBc
Typ
-106
dBc
Typ
VO = 2 Vpp, f = 10 kHz
0.0009
%
Typ
VO = 4 Vpp, f = 10 kHz
0.0005
%
Typ
0.11/0.17
%
Typ
0.11/0.14
°
Typ
f = 100 kHz, RL = 1 kΩ
G = +2, RL = 150 Ω
Input Voltage Noise
f = 100 kHz
12.5
nV/√Hz
Typ
Input Current Noise
f = 100 kHz
1.5
pA/√Hz
Typ
dB
Min
Max
DC PERFORMANCE
Open-Loop Voltage Gain (AOL)
105
85
80
80
Input Offset Voltage
0.5
2.5
3.5
3.5
mV
±7
±7
µV/°C
Typ
1
1
µA
Max
±2
±2
nA/°C
Typ
0.5
0.5
µA
Max
±2
±2
nA/°C
Typ
Average Offset Voltage Drift
Input Bias Current
Average Bias Current Drift
Input Offset Current
Average Offset Current Drift
6
VCM = 2.5 V
0.5
0.1
0.8
0.4
THS4281
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SLOS432 – APRIL 2004
ELECTRICAL CHARACTERISTICS, VS = 5 V (VS+ = 5 V, VS- = GND) (continued)
G = +2, RF = 2.49 kΩ, RL = 1 kΩ to 2.5 V, unless otherwise noted
TYP
PARAMETER
CONDITIONS
OVER TEMPERATURE
25°C
25°C
0°C to
70°C
-40°C to
85°C
UNITS
MIN/
MAX
-0.4/5.4
-0.3/5.3
-0.1/5.1
-0.1/5.1
V
Min
85
80
80
INPUT CHARACTERISTICS
Common-Mode Input Range
Common-Mode Rejection Ratio
VCM = 0 V to 5 V
100
dB
Min
Input Resistance
Common-mode
100
MΩ
Typ
Input Capacitance
Common-mode/Differential
0.8/1.2
pF
Typ
V
Typ
V
Min
Min
OUTPUT CHARACTERISTICS
RL = 10 kΩ
0.04/4.96
RL = 1 kΩ
0.15/4.85
0.2/4.8
Output Current (Sourcing)
RL = 10 Ω
33
24
20
20
mA
Output Current (Sinking)
RL = 10 Ω
44
30
25
25
mA
Min
Output Impedance
f = 1 MHz
1
Ω
Typ
Max
Output Voltage Swing
0.25/4.75 0.25/4.75
POWER SUPPLY
Maximum Operating Voltage
5
16.5
16.5
16.5
V
Minimum Operating Voltage
5
2.7
2.7
2.7
V
Min
Maximum Quiescent Current
0.75
0.9
0.98
1.0
mA
Max
Minimum Quiescent Current
0.75
0.6
0.57
0.55
mA
Min
Power Supply Rejection (+PSRR)
VS+ = 5.5 V to 4.5 V,
VS- = 0 V
100
80
75
75
dB
Min
Power Supply Rejection (-PSRR)
VS+ = 5 V, VS- = 0 V to 1.0 V
100
80
75
75
dB
Min
7
THS4281
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SLOS432 – APRIL 2004
ELECTRICAL CHARACTERISTICS, VS = ±5 V
G = +2, RF = 2.49 kΩ, RL = 1 kΩ, unless otherwise noted
TYP
PARAMETER
CONDITIONS
25°C
OVER TEMPERATURE
25°C
0°C to
70°C
-40°C to
85°C
UNITS
MIN/
MAX
AC PERFORMANCE
G = +1, VO = 100 mVpp, RF = 34 Ω
95
MHz
Typ
G = +2, VO = 100 mVpp
40
MHz
Typ
G = +5, VO = 100 mVpp
8
MHz
Typ
G = +10, VO = 100 mVpp
3.8
MHz
Typ
0.1-dB Flat Bandwidth
G = +2, VO = 100 mVpp
20
MHz
Typ
Full-Power Bandwidth
G = +1, VO = 2 Vpp
9.5
MHz
Typ
G = +1, VO = 2-V Step
35
V/µs
Typ
G = -1, VO = 2-V Step
35
V/µs
Typ
Small-Signal Bandwidth
Slew Rate
Settling Time to 0.1%
G = -1, VO = 2-V Step
78
ns
Typ
Settling Time to 0.01%
G = -1, VO = 2-V Step
140
ns
Typ
Rise/Fall Times
G = +1, VO = 2-V Step
45
ns
Typ
Harmonic Distortion
G = +2, VO = 2 Vpp
-69
dBc
Typ
-76
dBc
Typ
-93
dBc
Typ
Second Harmonic Distortion
Third Harmonic Distortion
Second Harmonic Distortion
Third Harmonic Distortion
THD + N
Differential Gain (NTSC/PAL)
Differential Phase (NTSC/PAL)
f = 1 MHz, RL = 1 kΩ
f = 100 kHz, RL = 1 kΩ
-107
dBc
Typ
VO = 2 Vpp, f = 10 kHz
0.0009
%
Typ
VO = 8 Vpp, f = 10 kHz
0.0003
%
Typ
0.03/0.03
%
Typ
0.08/0.1
°
Typ
G = +2, RL = 150 Ω
Input Voltage Noise
f = 100 kHz
12.5
nV/√Hz
Typ
Input Current Noise
f = 100 kHz
1.5
pA/√Hz
Typ
DC PERFORMANCE
Open-Loop Voltage Gain (AOL)
108
90
85
85
dB
Min
Input Offset Voltage
0.5
2.5
3.5
3.5
mV
Max
±7
±7
µV/°C
Typ
0.5
0.8
1
1
µA
Max
±2
±2
nA/°C
Typ
0.5
0.5
µA
Max
±2
±2
nA/°C
Typ
V
Min
Average Offset Voltage Drift
Input Bias Current
Average Bias Current Drift
VCM = 0 V
Input Offset Current
0.1
0.4
Average Offset Current Drift
INPUT CHARACTERISTICS
Common-Mode Input Range
±5.4
±5.3
±5.1
±5.1
90
85
85
Common-Mode Rejection Ratio
VCM = -5 V to +5 V
107
dB
Min
Input Resistance
Common-mode
100
MΩ
Typ
Input Capacitance
Common-mode / Differential
0.8/1.2
pF
Typ
RL = 10 kΩ
±4.93
V
Typ
RL = 1 kΩ
±4.8
±4.6
±4.5
±4.5
V
Min
Output Current (Sourcing)
RL = 10 Ω
48
35
30
30
mA
Min
Output Current (Sinking)
RL = 10 Ω
60
45
40
40
mA
Min
Output Impedance
f = 1 MHz
1
Ω
Typ
OUTPUT CHARACTERISTICS
Output Voltage Swing
8
THS4281
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SLOS432 – APRIL 2004
ELECTRICAL CHARACTERISTICS, VS = ±5 V (continued)
G = +2, RF = 2.49 kΩ, RL = 1 kΩ, unless otherwise noted
TYP
PARAMETER
CONDITIONS
OVER TEMPERATURE
25°C
25°C
0°C to
70°C
-40°C to
85°C
UNITS
MIN/
MAX
±5
±8.25
±8.25
±8.25
V
Max
Minimum Operating Voltage
±5
±1.35
±1.35
±1.35
V
Min
Maximum Quiescent Current
0.8
0.93
1.0
1.05
mA
Max
POWER SUPPLY
Maximum Operating Voltage
Minimum Quiescent Current
0.8
0.67
0.62
0.6
mA
Min
Power Supply Rejection (+PSRR)
VS+ = 5.5 V to 4.5 V, VS- = 5.0 V
100
80
75
75
dB
Min
Power Supply Rejection (-PSRR)
VS+ = 5 V, VS- = -5.5 V to -4.5 V
100
80
75
75
dB
Min
9
THS4281
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SLOS432 – APRIL 2004
TYPICAL CHARACTERISTICS
1000
900
TA = 25°C
800
TA = −40°C
700
600
500
3
4
5
6
7
8
0.5
0
−0.5
−1
VS = 5 V
−1.5
VS = 3 V
−2
−2.5
9 10 11 12 13 14 15
−0.5
−1
−1.5
−2
1
2
3
4
5
6
VICR − Common-Mode Input Voltage − V
Figure 2.
Figure 3.
(VS = 15 V)
INPUT OFFSET VOLTAGE
vs
COMMON-MODE INPUT VOLTAGE
POSITIVE VOLTAGE HEADROOM
vs
SOURCE CURRENT
NEGATIVE VOLTAGE HEADROOM
vs
SINK CURRENT
4
4
Load Tied to VS/2
0
−0.5
−1
−1.5
−2
Load Tied to VS/2
±5 V
3.5
3
− Voltage Headroom − (Vout − Vs−)
+ Voltage Headroom − (Vs+ − Vout)
VS = 15 V
0.5
15 V
2.5
2
5V
1.5
1
0.5
0
−1 0
2
4
6
8
10 12 14 16
VICR − Common-Mode Input Voltage − V
20
30
40
50
2
5V
1.5
1
0.5
60
0
10
20
30
40
50
Figure 4.
Figure 5.
Figure 6.
(VS = 5 V)
OUTPUT VOLTAGE
vs
LOAD RESISTANCE
(VS = ±5 V)
OUTPUT VOLTAGE
vs
LOAD RESISTANCE
(VS = 15 V)
OUTPUT VOLTAGE
vs
LOAD RESISTANCE
4
VS = ±5 V
Load Tied to GND
3
VS = 5 V
Load Tied to VS/2
3
2.5
2
1.5
1
VO − Output Voltage − V
5
2
1
0
−1
−2
−3
−4
0.5
−5
0
10
15 V
2.5
−Iout − Sink Current − mA
5
3.5
10
±5 V
3
+Iout − Source Current − mA
4.5
4
3.5
0
0
VO − Output Voltage − V
V OS − Input Offset Voltage − mV
0
Figure 1.
1
VO − Output Voltage − V
VS = ±5 V
0.5
−2.5
−6 −5 −4 −3 −2 −1 0
−1
0
1
2
3
4
5
6
VICR − Common-Mode Input Voltage − V
VCC − Supply Voltage − V
100
1k
RL − Load Resistance − Ω
Figure 7.
10
V OS − Input Offset Voltage − mV
V OS − Input Offset Voltage − mV
I Q − Quiescent Current −µ A
1
1
TA = 85°C
−2.5
(VS = ±5 V)
INPUT OFFSET VOLTAGE
vs
COMMON-MODE INPUT VOLTAGE
(VS = 3 V, VS = 5 V)
INPUT OFFSET VOLTAGE
vs
COMMON-MODE INPUT VOLTAGE
QUIESCENT CURRENT
vs
SUPPLY VOLTAGE
10 k
10
100
1k
RL − Load Resistance − Ω
Figure 8.
10 k
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
60
VS = 15 V
Load Tied to VS/2
10
100
1k
RL − Load Resistance − Ω
Figure 9.
10 k
THS4281
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SLOS432 – APRIL 2004
TYPICAL CHARACTERISTICS (continued)
(VS = 2.7 V)
FREQUENCY RESPONSE
FREQUENCY RESPONSE
9
6
RF = 4 kΩ
6
3
VS = 5 V
2
RF = 4 kΩ
VS = 2.7 V
VS = ±5 V
1
0
6
Signal Gain − dB
4
9
VS = 15 V
Signal Gain − dB
Gain = 1,
RF = 34 Ω,
RL = 1 kΩ,
VO = 100 mVPP
5
Signal Gain − dB
(VS = 3 V)
FREQUENCY RESPONSE
RF = 1.65 kΩ
RF = 1 kΩ
3
RF = 1.65 kΩ
RF = 1 kΩ
3
−1
0
VS = 2.7 V
Gain = 2,
RL = 1 kΩ,
VO = 0.1 VPP
−2
−3
−4
0
−3
1
10
0.1
100
1
10
f − Frequency − MHz
f − Frequency − MHz
VS = 3 V
Gain = 2,
RL = 1 kΩ,
VO = 0.1 VPP
−3
0.1
100
1
10
Figure 10.
Figure 11.
Figure 12.
(VS = 5 V)
FREQUENCY RESPONSE
(VS = ±5 V)
FREQUENCY RESPONSE
(VS = 2.7 V, VS = 3 V)
0.1-dB FREQUENCY RESPONSE
9
9
6.2
RF = 2 kΩ
RF = 4 kΩ
RF = 4 kΩ
RF = 1 kΩ
3
−3
0.1
3
VS = ± 5 V,
Gain = 2,
RL = 1 kΩ,
VO = 0.1 VPP
0.1
100
5.8
5.7
5.6
5.5
1
10
f − Frequency − MHz
VS = 3 V
Gain = 2,
RF = 1.65 kΩ,
RL = 1 kΩ,
VO = 0.1 VPP
5.4
0.1
100
1
10
Figure 15.
(VS = 5 V, ±5 V, 15 V)
0.1-dB FREQUENCY RESPONSE
(VS = 2.7 V)
FREQUENCY RESPONSE
(VS = 3 V)
FREQUENCY RESPONSE
24
20
VS = 5 V
5.8
5.7
1
10
f − Frequency − MHz
Figure 16.
G=5
12
8
G=2
4
Gain = 2,
RF = 2 kΩ (VS = 5 V),
RF = 2.49 kΩ (VS = ±5 V, 15 V),
RL = 1 kΩ,
VO = 0.1 VPP
5.4
0.1
16
16
G=5
12
8
G=2
4
G = −1
G = −1
0
0
−4
100
VS = 3V,
RF = 1.65 kΩ,
RL = 1 kΩ,
VO = 0.1 VPP
G = 10
20
Signal Gain − dB
Signal Gain − dB
VS = ± 5 V
5.9
24
VS = 2.7 V,
RF = 1.65 kΩ,
RL = 1 kΩ,
VO = 0.1 VPP
G = 10
VS = 15 V
100
f − Frequency − MHz
Figure 14.
6
Signal Gain − dB
RF = 1 kΩ
5.9
Figure 13.
6.1
5.5
6
RF = 2.49 kΩ
−3
1
10
f − Frequency − MHz
6.2
5.6
6
0
VS = 5 V
Gain = 2,
RL = 1 kΩ,
VO = 0.1 VPP
VS = 2.7 V
6.1
Signal Gain − dB
Signal Gain − dB
Signal Gain − dB
6
0
100
f − Frequency − MHz
0.1
1
10
f − Frequency − MHz
Figure 17.
100
−4
0.1
1
10
100
f − Frequency − MHz
Figure 18.
11
THS4281
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SLOS432 – APRIL 2004
TYPICAL CHARACTERISTICS (continued)
(VS = ±5 V)
FREQUENCY RESPONSE
(VS = 5 V)
FREQUENCY RESPONSE
24
Signal Gain − dB
Signal Gain − dB
20
G=5
12
G=2
8
4
16
12
G=2
8
12
G=2
8
4
G = −1
0
1
10
0
−4
0.1
100
−4
1
10
f − Frequency − MHz
f − Frequency − MHz
100
0.1
Figure 21.
(VS = 2.7 V)
LARGE-SIGNAL
FREQUENCY RESPONSE
(VS = 5 V)
LARGE-SIGNAL
FREQUENCY RESPONSE
(VS = ±5 V)
LARGE-SIGNAL
FREQUENCY RESPONSE
1
1
1
0.5
0.5
VO = 500 mVPP
VO = 500 mVPP
−1
VO = 1 VPP
−2
VO = 2 VPP
−4
−1.5
−2
VO = 2 VPP
Gain = 1,
RF = 34 Ω,
RL = 1 kΩ,
VS = 5 V
−3.5
VO = 2 VPP
−3
Gain = 1,
RF = 34 Ω,
RL = 1 kΩ,
VS = ± 5 V
−3.5
−4
1
10
1
100
10
f − Frequency − MHz
100
f − Frequency − MHz
Figure 24.
OPEN-LOOP GAIN
vs
FREQUENCY
OUTPUT IMPEDANCE
vs
FREQUENCY
REJECTION RATIO
vs
FREQUENCY
50
Gain
80
0
−25
70
−50
60
−75
Phase
−100
40
−125
30
−150
20
−175
10
−200
0
−10
−225
1k
−250
10k 100k 1 M 10 M 100 M
f − Frequency − Hz
Z o − Output Impedance − Ω
90
110
1000
25
Phase − °
RL = 1 kΩ,
VS = ±5 V
100
−2
Figure 23.
110
10
VO = 1 VPP
−1.5
Figure 22.
100
1
−1
−4
100
f − Frequency − MHz
50
−0.5
−2.5
−3
10
1
VO = 1 VPP
−1
100
Gain = 1
RF = 2.5 kΩ
VS = 5 V, ± 5 V, 15 V
90
10
1
0.1
CMRR
80
PSRR+
70
60
50
PSRR−
40
30
20
10
0.01
100 k
0
1M
10 M
100 M
f − Frequency − Hz
Figure 25.
VS = 15 V and 5 V
100
Rejection Ratios − dB
−3.5
−0.5
−2.5
Gain = 1,
RF = 34 Ω,
RL = 1 kΩ,
VS = 2.7 V
−3
Signal Gain − dB
Signal Gain − dB
−0.5
VO = 500 mVPP
0
0
−2.5
100
Figure 20.
0.5
−1.5
1
10
f − Frequency − MHz
Figure 19.
0
Signal Gain − dB
G=5
G = −1
−4
0.1
Open-Loop Gain − dB
16
4
0
VS = 15 V,
RF = 2.49 kΩ,
RL = 1 kΩ,
VO = 0.1 VPP
G = 10
20
G=5
G = −1
12
24
VS = ±5 V,
RF = 2.49 kΩ,
RL = 1 kΩ,
VO = 0.1 VPP
G = 10
Signal Gain − dB
20
16
24
VS = 5 V,
RF = 2 kΩ,
RL = 1 kΩ,
VO = 0.1 VPP
G = 10
(VS = 15 V)
FREQUENCY RESPONSE
Figure 26.
1G
1k
10 k
100 k
1M
f − Frequency − Hz
Figure 27.
10 M
100 M
THS4281
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SLOS432 – APRIL 2004
TYPICAL CHARACTERISTICS (continued)
NOISE
vs
FREQUENCY
Vn
12.5 nV/rt(Hz)
In
10
1.5 pA/rt(Hz)
60
Gain = −1,
RF = 3 kΩ,
RL = 1 kΩ,
VS = 2.7 V
40
Gain = −1,
RF = 3 kΩ,
RL = 1 kΩ,
VS = 5 V
50
Fall
SR − Slew Rate − V/ µ s
100
(VS = 5 V)
SLEW RATE
50
VS = 2.7 V to 15 V,
TA = 27°C
SR − Slew Rate − V/ µ s
I n − Current Noise − pA/ Hz
V n − Voltage Noise − nV/ Hz
1000
(VS = 2.7 V)
SLEW RATE
30
Rise
20
10
40
Fall
Rise
30
20
10
1
10
100
1K
10K
100K
0
f − Frequency − Hz
0.5
0.75
1
1.25
1.5
1.75
0
0.5
2
1
VO − Output Voltage − VPP
(VS = ±5 V)
SLEW RATE
(VS = 15 V)
SLEW RATE
(VS = ±1.35 V)
SETTLING TIME
Fall
Rise
30
20
Rise
100
80
Fall
60
40
Gain = −1
RL = 1 kΩ
RF= 3 kΩ
VS = ±1.35 V
1-V Step
0
−0.2
Fall
20
0
1.5
2
2.5
3
3.5
4
4.5
5
−0.6
0
VO − Output Voltage − VPP
1
2
3
4 5 6 7 8 9 10 11 12
VO − Output Voltage − VPP
0
20
40
60
Figure 32.
Figure 33.
(VS = ±1.35 V)
SETTLING TIME
(VS = ±2.5 V)
SETTLING TIME
(VS = ±2.5 V)
SETTLING TIME
0.6
Fall
0.4
Gain = −1
RL = 1 kΩ
RF= 3 kΩ
VS = ±1.35 V
1-V Step
0.2
0
−0.2
−0.4
−0.6
1.5
1
1
0.8
Gain = −1
RL = 1 kΩ
RF = 3 kΩ
VS = ±2.5 V
0.5
0
100
Gain = −1
RL = 1 kΩ
RF = 3 kΩ
VS = ±2.5 V
2-V Step
0.6
% Error
Rise
VO − Output Voltage − V
1
80
t − Time − ns
Figure 31.
0.8
% Error
0.2
−0.4
10
4
Rise
0.4
120
VO − Output Voltage − V
SR − Slew Rate − V/µ s
SR − Slew Rate − V/ µ s
Gain = −1,
RF = 3 kΩ,
RL = 1 kΩ,
VS = 15 V
140
40
3.5
0.6
160
1
3
Figure 30.
Gain = −1,
RF = 3 kΩ,
RL = 1 kΩ,
VS = ±5 V
0.5
2.5
Figure 29.
50
0
2
Figure 28.
70
60
1.5
VO − Output Voltage − VPP
0.4
0.2
Fall
−0.5
0
−1
−0.2
−0.8
Rise
−1
20
40
60
80 100 120 140 160 180
t − Time − ns
Figure 34.
−1.5
0
10 20 30 40 50 60 70 80 90 100
t − Time − ns
Figure 35.
−0.4
40
60
80
100 120 140 160 180 200
t − Time − ns
Figure 36.
13
THS4281
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SLOS432 – APRIL 2004
TYPICAL CHARACTERISTICS (continued)
(VS = ±5 V)
SETTLING TIME
(VS = ±5 V)
SETTLING TIME
−30
1
Gain = −1
RL = 1 kΩ
RF = 3 kΩ
VS = ±5 V
2-V Step
0.8
1
0.6
0
% Error
Gain = −1
RL = 1 kΩ
RF= 3 kΩ
VS = ±5 V
0.5
0.4
0.2
Rise
−0.5
0
−1
−0.2
10
60
80
(Gain = +2)
HARMONIC DISTORTION
vs
FREQUENCY
−90
−30
−80
VS = 3.3 V, 2 VPP, HD2
−85
VS = ±5 V,
15 V HD2
−80
VS = 5 V,±5 V,
15 V HD3
−100
−90
VS = 3 V, 1 VPP, HD2
−100
VS = 3 V, 1 VPP, HD3
−105
−110
VS = 3.3 V, 1 VPP, HD2
−115
−120
VS = 3.3 V, 1 VPP, HD3
1
10
100
f − Frequency − MHz
−90
VS = 2.7 V, HD3
−100
VS = 5 V ±5 V,
15 V HD2
−110
VS = 5 V ±5 V,
15 V HD3
10 k 20 k
1k
10 k
100 k
f − Frequency − Hz
1M
Figure 42.
(Gain = +2)
HARMONIC DISTORTION
vs
FREQUENCY
HARMONIC DISTORTION
vs
LOAD RESISTANCE
(VS = 2.7 V, 5 V)
HARMONIC DISTORTION
vs
OUTPUT VOLTAGE
VS = 2.7 V, 3 V, HD2
VS = 3 V, HD3
VS = 2.7 V, HD3
VS = 5 V ±5 V,
15 V HD2
1k
10 k
100 k
f − Frequency − Hz
Figure 43.
1M
VS = 3 V, 2 VPP, HD3
−90
VS = 3 V, 1 VPP, HD2
−70
−100
VS = 3 V, 1 VPP, HD3
VS = 5V and ±5V, 2VPP, HD3
−120
VS = 5 V ±5 V,
15 V HD3
−120
VS = 3 V, 2 VPP, HD2
−80
−110
10 M
1k
Gain = 2,
RL = 1 kΩ, to VS/2,
f = 10 kHz
VS = 2.7 V, HD2
−80
−90
−100
−110
VS = 2.7 V, HD3
VS = 5 V, HD2
−120
VS = 5 V, and
±5 V, 2 VPP, HD2
−130
100
10 M
−60
Gain = 2
f = 10 khz
Harmonic Distortion − dBc
−70
Harmonic Distortion − dBc
Harmonic Distortion − dBc
−80
Figure 41.
−60
−130
100
VS = 2.7 V, HD2
−130
100
−60
−110
−70
Figure 40.
VO = 2 VPP,
Gain = 2,
RL = 1 kΩ, to VS/2
−100
−60
f − Frequency − Hz
−30
14
1k
−50
−120
Gain = 2,
RL = 1 kΩ, to VS/2
−130
10
VO = 1 VPP,
Gain = 2,
RL = 1 kΩ, to VS/2
−40
VS = 3.3 V, 2 VPP, HD3
−95
−125
−110
0.1
−90
10
(VS = 3 V, 3.3 V)
HARMONIC DISTORTION
vs
FREQUENCY
−70
−80
1
f − Frequency − MHz
(Gain = +1)
HARMONIC DISTORTION
vs
FREQUENCY
VS = 5 V, HD2
−70
0.1
Figure 39.
−60
−50
VS = 5 V,±5 V,
15 V HD3
Figure 38.
VS = 2.7 V, HD3
−40
−90
Figure 37.
Harmonic Distortion − dBc
Harmonic Distortion − dBc
−50
VS = ±5 V,
15 V HD2
−80
t − Time − ns
VO = 2 VPP,
Gain = 1,
RL = 1 kΩ, to VS/2
VS = 2.7 V, HD2
−40
−70
100 120 140 160 180 200
t − Time − ns
−30
VS = 2.7 V, HD3
VS = 5 V, HD2
−60
−110
−0.4
40
20 30 40 50 60 70 80 90 100
Harmonic Distortion − dBc
0
−50
−100
Fall
−1.5
VO = 1 VPP,
Gain = 1,
RL = 1 kΩ, to VS/2
VS = 2.7 V, HD2
−40
Harmonic Distortion − dBc
1.5
VO − Output Voltage − V
(Gain = +1)
HARMONIC DISTORTION
vs
FREQUENCY
VS = 5 V, HD3
10 k
RL − Load Resistance − Figure 44.
100 k
−130
0.1
1
VO − Output Voltage − VPP
Figure 45.
10
THS4281
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SLOS432 – APRIL 2004
TYPICAL CHARACTERISTICS (continued)
(VS = 3 V, ±5 V)
HARMONIC DISTORTION
vs
OUTPUT VOLTAGE
−70
−80
−90
VS = 3 V, HD3
−100
VS = ±5 V, HD2
−110
Gain = 2,
RL = 1 kΩ, to VS/2,
f = 10 kHz
−80
−90
−100
VS = 3.3 V, HD2
−110
VS =15 V, HD2
−120
−120
VS = ±5 V, HD3
VS = 15 V, HD3
−130
−130
0.1
1
VO − Output Voltage − VPP
0.1
10
1
10
20
0.100
VO = 2.5 VPP
VO = 2 VPP
VO = 1 VPP
VO = 0.5 VPP
0.010
VS = 2.7 V,
Bandwidth = 600 kHz,
Gain = 2,
RF = 2 kΩ,
RL = 1 kΩ to VS/2
0.001
10
VO − Output Voltage − VPP
100
1k
10 k
200 k
f − Frequency − Hz
Figure 46.
Figure 47.
Figure 48.
(VS = 3 V)
TOTAL HARMONIC DISTORTION +
NOISE
vs
FREQUENCY
(VS = 5 V)
TOTAL HARMONIC DISTORTION +
NOISE
vs
FREQUENCY
(VS = ±5 V)
TOTAL HARMONIC DISTORTION +
NOISE
vs
FREQUENCY
0.100
VO = 2 VPP
VO = 2.8 VPP
0.010
VO = 1 VPP
VS = 3 V,
Bandwidth = 600 kHz,
Gain = 2,
RF = 2 kΩ,
RL = 1 kΩ to VS/2
0.001
10
100
1k
10 k
f − Frequency − Hz
Figure 49.
200 k
THD+N −Total Harmonic Distortion + Noise − %
THD+N −Total Harmonic Distortion + Noise − %
VS = 3.3 V, HD3
0.1000
VS = 5 V,
Bandwidth = 600 kHz,
Gain = 2,
RF = 2 kΩ,
RL = 1 kΩ to VS/2
VO = 4.8 VPP
0.0100
VO = 4.6 VPP
0.0010
VO = 4 VPP
0.0001
10
100
1k
10 k
f − Frequency − Hz
Figure 50.
200 k
THD+N −Total Harmonic Distortion + Noise − %
Harmonic Distortion − dBc
−70
−60
VS = 3 V, HD2
THD+N −Total Harmonic Distortion + Noise − %
Gain = 2,
RL = 1 kΩ, to VS/2,
f = 10 kHz
Harmonic Distortion − dBc
−60
(VS = 2.7 V)
TOTAL HARMONIC DISTORTION +
NOISE
vs
FREQUENCY
(VS = 3.3 V, 15 V)
HARMONIC DISTORTION
vs
OUTPUT VOLTAGE
0.1000
VS = ±5 V,
Bandwidth = 600 kHz,
Gain = 2,
RF = 2 kΩ,
RL = 1 kΩ
0.0010
VO = 9.6 VPP
VO = 9 VPP
0.0100
VO = 4 VPP
VO = 8 VPP
0.0001
10
100
1k
10 k
200 k
f − Frequency − Hz
Figure 51.
15
THS4281
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SLOS432 – APRIL 2004
TYPICAL CHARACTERISTICS (continued)
VS = 15 V,
Bandwidth = 600 kHz,
Gain = 2,
RF = 2 kΩ,
RL = 1 kΩ , to VS/2
0.0100
VO = 14.5 VPP
VO = 14 VPP
VO = 4 VPP
VO = 8 VPP
0.0010
VO = 12 VPP
0.0001
10
100
1k
10 k
200 k
0.1000
VS = 3.3 V
VS = 3 V
VS = 2.7 V
0.0100
Amplifier Noise
Limit Line
0.0010
f = 1 kHz,
Bandwidth = 22 kHz,
Gain = 2,
RF = 2 kΩ,
RL = 1 kΩ , to VS/2
0.1
1
10
VO − Output Voltage − VPP
20
0.1000
VS = 5 V
VS = ±5 V
VS = 15 V
VS = 3.3 V
VS = 3 V
VS = 2.7 V
0.0100
0.0010
f = 10 kHz,
Bandwidth = 80 kHz,
Gain = 2,
RF = 2 kΩ,
RL = 1 kΩ , to VS/2
Amplifier Noise
Limit Line
0.0001
0.1
1
10
Figure 53.
Figure 54.
(f = 100 kHz)
TOTAL HARMONIC DISTORTION +
NOISE
vs
OUTPUT VOLTAGE
(VS = 5 V)
DIFFERENTIAL GAIN
vs
NUMBER OF LOADS
(VS = 5 V)
DIFFERENTIAL PHASE
vs
NUMBER OF LOADS
0.8
VS = ±5 V
VS = 15 V
VS = 3 V
VS = 2.7 V
0.010
0.001
0.1
PAL
°
0.6
0.5
NTSC
0.4
0.3
Gain = 2
RF= 2.5 kΩ
VS = 5 V
40 IRE − NTSC and Pal
Worst Case ±100 IRE Ramp
0.2
0.1
Amplifier Noise
Limit Line
1
10
VO − Output Voltage − VPP
Figure 55.
PAL
0.7
VS = 5 V
VS = 3.3 V
f = 100 kHz,
Bandwidth = 600 kHz,
Gain = 2,
RF = 2 kΩ,
RL = 1 kΩ , to VS/2
2
1.8
Differential Phase −
0.100
1
2
Number of Loads − 150 Ω
Figure 56.
1.6
NTSC
1.4
1.2
1
0.8
0.6
Gain = 2
Rf = 2.5 kΩ
VS = 5 V
40 IRE − NTSC and Pal
Worst Case ±100 IRE Ramp
0.4
0.2
0
20
20
VO − Output Voltage − VPP
Figure 52.
Differential Gain − %
THD+N −Total Harmonic Distortion + Noise − dBc
VS = 15 V
0.0001
f − Frequency − Hz
16
VS = ±5 V
VS = 5 V
(f = 10 kHz)
TOTAL HARMONIC DISTORTION +
NOISE
vs
OUTPUT VOLTAGE
THD+N −Total Harmonic Distortion + Noise − dBc
0.1000
(f = 1 kHz)
TOTAL HARMONIC DISTORTION +
NOISE
vs
OUTPUT VOLTAGE
THD+N −Total Harmonic Distortion + Noise − dBc
THD+N −Total Harmonic Distortion + Noise − dBc
(VS = 15 V)
TOTAL HARMONIC DISTORTION +
NOISE
vs
FREQUENCY
3
0
1
2
Number of Loads − 150 Ω
Figure 57.
3
THS4281
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SLOS432 – APRIL 2004
TYPICAL CHARACTERISTICS (continued)
(VS = ±5 V)
DIFFERENTIAL PHASE
vs
NUMBER OF LOADS
1.4
PAL
0.8
NTSC
0.6
Gain = 2
RF= 2.5 kΩ
VS = ±5 V
40 IRE − NTSC and Pal
Worst Case ±100 IRE Ramp
0.4
0.2
1
1
NTSC
0.8
0.6
0.2
2
1
VS = 15 V
500
400
VS = ±5 V
VS = 5 V
300
200
VS = 3 V
100
0
2
Number of Loads − 150 Ω
−200
−40−30−20−10 0 10 20 30 40 50 60 70 80 90
3
TC − Case Temperature − °C
Figure 59.
Figure 60.
(VS = 5 V)
INPUT BIAS AND OFFSET
CURRENT
vs
TEMPERATURE
(VS = 15 V)
INPUT BIAS AND
OFFSET CURRENT
vs
TEMPERATURE
SMALL-SIGNAL
TRANSIENT RESPONSE
40
520
500
36
510
490
32
20
460
IIB+
450
16
12
440
8
430
4
IOS
28
IIB−
490
24
480
20
470
16
IIB+
460
12
450
8
440
4
Gain = 2
RL = 1 kΩ
RF = 2.5 kΩ
VS = ± 7.5 V
−20
−30
−50
−60
0
100 200 300 400 500 600 700
Figure 63.
LARGE-SIGNAL
TRANSIENT RESPONSE
(VS = 5 V)
OVERDRIVE RECOVERY TIME
(VS = ±5 V)
OVERDRIVE RECOVERY TIME
0
−0.5
Gain = 2
RL = 1 kΩ
RF = 2.5 kΩ
VS = ± 5 V
−2.5
4
3.75
3.25
2.75
2.25
Output
1
1.75
0
1.25
Input
4
3
2
1
2
1
0
0
−1
−2
−1
Output
−3
−2
−4
−5
−1
100 200 300 400 500 600 700 800
Gain = 2
RL = 1 kΩ
RF = 2.5 kΩ
VS = ± 5 V
5
3
2
3
6
VO − Output Voltage − V
Input
VO − Output Voltage − V
1
4.25
Gain = 2
RL = 1 kΩ
RF = 2.5 kΩ
VS = 5 V
5
2
1.5
0
0
−10
t − Time − ns
6
−2
Input
10
Figure 62.
Output
−1.5
20
Figure 61.
3
−1
30
TC − Case Temperature − °C
TC − Case Temperature − °C
0.5
40
−40
0
430
−40 −30−20 −10 0 10 20 30 40 50 60 70 80 90
0
420
−40 −30−20−10 0 10 20 30 40 50 60 70 80 90
2.5
VO − Output Voltage − mV
24
IIB−
470
500
Output
50
32
I OS − Input Offset Current − n A
28
I IB − Input Bias Current − n A
IOS
480
60
36
VS =15 V
I OS − Input Offset Current − n A
VS = 5 V
VO − Output Voltage − mV
600
Figure 58.
510
−3
VICR = VS/2
−100
0
3
Number of Loads − 150 Ω
I IB − Input Bias Current − n A
Gain = 2
Rf = 2.5 kΩ
VS = ±5 V
40 IRE − NTSC and Pal
Worst Case ±100 IRE Ramp
0.4
VI − Input Voltage − V
0
700
1.2
Differential Phase −
Differential Gain − %
1
800
1.4
PAL
°
1.2
1.6
VOS− Input Offset Voltage − µ V
1.6
INPUT OFFSET VOLTAGE
vs
TEMPERATURE
0
0.5
1
1.5
2
2.5
t − Time − µs
3
3.5
0.75
−6
VI − Input Voltage − V
(VS = ±5 V)
DIFFERENTIAL GAIN
vs
NUMBER OF LOADS
Input
0
0.5
1
1.5
2
2.5
3
−3
3.5
t − Time − µs
t − Time − ns
Figure 64.
Figure 65.
Figure 66.
17
THS4281
www.ti.com
SLOS432 – APRIL 2004
TYPICAL CHARACTERISTICS (continued)
OVERDRIVE RESPONSE
OUTPUT VOLTAGE
vs
TIME
2
V O − Output Voltage − V
6
VS = ±2.5 V
Gain = 2,
RL = 1 kΩ,
RF = 2 kΩ
VO
4
1
2
0
VI
0
−1
−2
−2
−4
−3
0
20
40
60
t − Time − s
Figure 67.
18
80
−6
100
V I − Input Voltage − V
3
THS4281
www.ti.com
SLOS432 – APRIL 2004
APPLICATION INFORMATION
+VS
HIGH-SPEED OPERATIONAL AMPLIFIERS
The THS4281 is a unity gain stable rail-to-rail input
and output voltage feedback operational amplifier
designed to operate from a single 2.7-V to 16.5-V
power supply.
+
VI
VO
_
Rf
2.49 kΩ
To Load
2.49 kΩ
Rg
0.1 µF 6.8 µF
+
and
Figure 68 shows the noninverting gain configuration
of 2 V/V used to demonstrate the typical performance
curves.
Voltage feedback amplifiers can use a wide range of
resistors values to set their gain with minimal impact
on frequency response. Larger-valued resistors decrease loading of the feedback network on the output
of the amplifier, but may cause peaking and instability. For a gain of +2, feedback resistor values
between 1 kΩ and 4 kΩ are recommended for most
applications. However, as the gain increases, the use
of even higher feedback resistors can be used to
conserve power. This is due to the inherent nature of
amplifiers becoming more stable as the gain increases, at the expense of bandwidth. Figure 69 and
Figure 70 show the THS4281 using feedback resistors of 10 kΩ and 100 kΩ. Be cautioned that using
such high values with high-speed amplifiers is not
typically recommended, but under certain conditions,
such as high gain and good high-speed-PCB layout
practices, such resistances can be used.
Figure 68. Wideband, Noninverting Gain
Configuration
24
RF = 100 kΩ
20
Signal Gain − dB
WIDEBAND, NONINVERTING OPERATION
−VS
RF = 1.65 kΩ
and 10 kΩ
16
12
8
VS = 3 V
Gain = 10,
RL = 1 kΩ,
VO = 0.1 VPP
4
0
0.1
1
10
100
f − Frequency − MHz
Figure 69. Signal Gain vs
Frequency, VS = 3 V
24
RF = 100 kΩ
20
Signal Gain − dB
•
•
•
•
•
•
Wideband, Noninverting Operation
Wideband, Inverting Gain Operation
Video Drive Circuits
Single-Supply Operation
Power Supply Decoupling Techniques
Recommendations
Active Filtering With the THS4281
Driving Capacitive Loads
Board Layout
Thermal Analysis
Additional Reference Material
Mechanical Package Drawings
0.1 µF 6.8 µF
50-Ω Source
49.9 Ω
Applications Section Contents
•
•
•
•
•
+
16
RF = 2.5 kΩ
and 10 kΩ
12
8
4
0
0.1
VS = ±5 V
Gain = 10,
RL = 1 kΩ,
VO = 0.1 VPP
1
10
100
f − Frequency − MHz
Figure 70. Signal Gain vs
Frequency, VS = ±5 V
19
THS4281
www.ti.com
SLOS432 – APRIL 2004
WIDEBAND, INVERTING OPERATION
Figure 71 shows a typical inverting configuration
where the input and output impedances and noise
gain from Figure 68 are retained with an inverting
circuit gain of -1 V/V.
+VS
+
0.1 µF
6.8 µF
+
RT
1.24 kΩ
CT
0.1 µF
VO
_
To Load
50-Ω Source
Rg
VI
Rf
2.49 kΩ
RM
51.1 Ω
2.49 kΩ
0.1 µF
6.8 µF
+
−VS
Figure 71. Wideband, Inverting Gain
Configuration
In the inverting configuration, some key design considerations must be noted. One is that the gain
resistor (Rg) becomes part of the signal channel input
impedance. If the input impedance matching is desired (which is beneficial whenever the signal is
coupled through a cable, twisted pair, long PC board
trace, or other transmission line conductors), Rg may
be set equal to the required termination value and Rf
adjusted to give the desired gain. However, care
must be taken when dealing with low inverting gains,
as the resultant feedback resistor value can present a
significant load to the amplifier output. For example,
an inverting gain of 2, setting Rg to 49.9 Ω for input
matching, eliminates the need for RM but requires a
100-Ω feedback resistor. The 100-Ω feedback resistor, in parallel with the external load, causes
excessive loading on the amplifier output. To eliminate this excessive loading, it is preferable to increase
both Rg and Rf values, as shown in Figure 71, and
then achieve the input matching impedance with a
third resistor (RM) to ground. The total input impedance is the parallel combination of Rg and RM.
20
Another consideration in inverting amplifier design is
setting the bias current cancellation resistor (RT) on
the noninverting input. If the resistance is set equal to
the total dc resistance presented to the device at the
inverting terminal, the output dc error (due to the
input bias currents) is reduced to the input offset
current multiplied by RT. In Figure 71, the dc source
impedance presented at the inverting terminal is 2.49
kΩ || (2.49 kΩ + 25.3 Ω) ≅ 1.24 kΩ. To reduce the
additional high-frequency noise introduced by the
resistor at the noninverting input, RT is bypassed with
a 0.1-µF capacitor to ground (CT).
SINGLE-SUPPLY OPERATION
The THS4281 is designed to operate from a single
2.7-V to 16.5-V power supply. When operating from a
single power supply, care must be taken to ensure
the input signal and amplifier are biased appropriately
to allow for the maximum output voltage swing and
not violate VICR. The circuits shown in Figure 72
shows inverting and noninverting amplifiers configured for single-supply operation.
+VS
50-Ω Source
+
VI
49.9 Ω
RT
VO
_
To Load
+VS
Rf
2
Rg
2 kΩ
2 kΩ
Power Supply Bypassing
Not Shown For Simplicity
+VS
2
Rf
VS
2 kΩ
50-Ω Source
Rg
VI
RT
51.1 Ω
_
2 kΩ
RT
+
VO
To Load
+VS
+VS
2
2
CT
Figure 72. DC-Coupled Single Supply Operation
THS4281
www.ti.com
SLOS432 – APRIL 2004
APPLICATION CIRCUITS
Active Filtering With the THS4281
2.05 k
The two most common low-pass filter circuits used
are the Sallen-Key filter and the Multiple Feedback
(MFB)–aka Rauch filter. FilterPro was used to determine a 2-pole Butterworth response filter with a
corner (-3 dB) frequency of 100 kHz which is shown
in Figure 73 and Figure 74. One of the advantages of
the MFB filter, a much better high frequency rejection,
is clearly shown in the response shown in Figure 75.
This is due to the inherent R-C filter to ground being
the first elements in the design of the MFB filter. The
Sallen-Key design also has an R-C filter, but the
capacitor connects directly to the output. At very high
frequencies, where the amplifier's access loop gain is
decreasing, the ability of the amplifier to reject high
frequencies is severely reduced and allows the high
frequency signals to pass through the system. One
other advantage of the MFB filter is the reduced
sensitivity in component variation. This is important
when using real-world components where capacitors
can easily have ±10% variations.
2 k
2 k
5V
_
VI
649 2.61 k
1.5 nF
1 nF
VO
+
−5V
RL
1 k
Figure 73. Second-Order Sallen-Key 100-kHz
Butterworth Filter, Gain = 2 V/V
270 pF
1.02 k
5V
2.1 k
_
VI
VO
+
2.2 nF
RL
1 k
−5V
Figure 74. Second-Order MFB 100-kHz
Butterworth Filter, Gain = 2 V/V
10
Sallen-Key
Response
0
−10
Signal Gain − dB
High performance active filtering with the THS4281 is
achievable due to the amplifier's good slew rate, wide
bandwidth, and voltage feedback architecture. Several options are available for high-pass, low-pass,
bandpass, and bandstop filters of varying orders.
Filters can be quite complex and time consuming to
design. Several books and application reports are
available to help design active filters. But, to help
simplify the process and minimize the chance of
miscalculations, Texas Instruments has developed a
filter design program called FilterPro™. FilterPro is
available for download at no cost from TI's Web site
(www.ti.com).
−20
−30
−40
−50
MFB
Response
−60
VS = 3 V, 5 V, ±5 V, 15 V,
VO = 100 mVPP
−70
−80
1k
10k
100k
1M
10M
100M
f − Frequency − Hz
Figure 75. Second-Order 100-kHz Active Filter
Response
Driving Capacitive Loads
One of the most demanding, and yet common, load
conditions for an op amp is capacitive loading. Often,
the capacitive load is the input of an A/D converter,
including additional external capacitance, which may
be recommended to improve A/D linearity. A
high-speed, high open-loop gain amplifier like the
THS4281 can be susceptible to instability and
peaking when a capacitive load is placed directly on
the output. When the amplifier's open-loop output
resistance is considered, this capacitive load introduces an additional pole in the feedback path that
decreases the phase margin. When the primary
considerations are frequency response flatness,
pulse response fidelity, or distortion, a simple and
effective solution is to isolate the capacitive load from
the feedback loop by inserting a small series isolation
resistor (10 Ω to 25 Ω) between the amplifier output
and the capacitive load.
21
THS4281
www.ti.com
SLOS432 – APRIL 2004
Power Supply Decoupling Techniques and
Recommendations
Power supply decoupling is a critical aspect of any
high-performance amplifier design. Careful decoupling provides higher quality ac performance. The
following guidelines ensure the highest level of performance.
1. Place decoupling capacitors as close to the
power supply inputs as possible, with the goal of
minimizing the inductance.
2. Placement priority should put the smallest valued
capacitors closest to the device.
3. Use of solid power and ground planes is recommended to reduce the inductance along power
supply return current paths (with the exception of
the areas underneath the input and output pins
as noted below).
4. A bulk decoupling capacitor is recommended (6.8
to 22 µF) within 1 inch, and a ceramic (0.1 µF)
within 0.1 inch of the power input pins.
NOTE:
The bulk capacitor may be
shared by other op amps.
BOARD LAYOUT
Achieving optimum performance with a high frequency amplifier like the THS4281 requires careful
attention to board layout parasitics and external
component types. See the EVM layout figures in the
Design Tools Section.
Recommendations that optimize performance include:
1. Minimize parasitic capacitance to any ac
ground for all of the signal I/O pins. Parasitic
capacitance on the output and inverting input pins
can cause instability and on the noninverting
input, it can react with the source impedance to
cause unintentional band limiting. To reduce unwanted capacitance, a window around the signal
I/O pins should be opened in all of the ground
and power planes around those pins. Otherwise,
ground and power planes should be unbroken
elsewhere on the board.
2. Minimize the distance (< 0.1 inch) from the
power supply pins to high frequency 0.1-µF
decoupling capacitors. Avoid narrow power and
ground traces to minimize inductance. The power
supply connections should always be decoupled
as described above.
3. Careful selection and placement of external
components preserves the high frequency
performance of the THS4281. Resistors should
be a low reactance type. Surface-mount resistors
work best and allow a tighter overall layout.
22
Metal-film, axial-lead resistors can also provide
good high frequency performance. Again, keep
their leads and PC board trace length as short as
possible. Never use wire wound type resistors in
a high frequency application. Because the output
pin and inverting input pin are the most sensitive
to parasitic capacitance, always position the
feedback and series output resistor, if any, as
close as possible to the output pin. Other network
components, such as noninverting input termination resistors, should also be placed close to the
package. Excessively high resistor values can
create significant phase lag that can degrade
performance. Keep resistor values as low as
possible, consistent with load-driving considerations. It is suggested that a good starting point
for design is to set the Rf to 2 kΩ for low-gain,
noninverting applications. Doing this automatically keeps the resistor noise terms reasonable
and minimizes the effect of parasitic capacitance.
4. Connections to other wideband devices on
the board should be made with short direct
traces or through onboard transmission lines.
For short connections, consider the trace and the
input to the next device as a lumped capacitive
load. Relatively wide traces (50 mils to 100 mils)
should be used, preferably with ground and
power planes opened up around them. Estimate
the total capacitive load and set RISO from the
plot of recommended RISO vs capacitive load.
Low parasitic capacitive loads (<4 pF) may not
need an R(ISO), because the THS4281 is nominally compensated to operate at unity gain (+1
V/V) with a 2-pF capacitive load. Higher capacitive loads without an R(ISO) are allowed as the
signal gain increases. If a long trace is required,
and the 6-dB signal loss intrinsic to a doubly
terminated transmission line is acceptable, implement a matched impedance transmission line
using microstrip or stripline techniques (consult
an ECL design handbook for microstrip and
stripline layout techniques). A matching series
resistor into the trace from the output of the
THS4281 is used as well as a terminating shunt
resistor at the input of the destination device.
Remember also that the terminating impedance is
the parallel combination of the shunt resistor and
the input impedance of the destination device:
this total effective impedance should be set to
match the trace impedance. If the 6-dB attenuation of a doubly terminated transmission line is
unacceptable,
a
long
trace
can
be
series-terminated at the source end only. Treat
the trace as a capacitive load in this case, and
set the series resistor value as shown in the plot
of R(ISO) vs capacitive load. If the input impedance of the destination device is low, there is
signal attenuation due to the voltage divider
formed by R(ISO) into the terminating impedance.
THS4281
www.ti.com
SLOS432 – APRIL 2004
A 50-Ω environment is normally not necessary
onboard, and in fact a higher impedance environment improves distortion as shown in the distortion versus load plots.
5. Socketing a high speed part like the THS4281
is not recommended. The additional lead length
and pin-to-pin capacitance introduced by the
socket can create a troublesome parasitic network which can make it almost impossible to
achieve a smooth, stable frequency response.
Best results are obtained by soldering the
THS4281 onto the board.
When determining whether or not the device satisfies
the maximum power dissipation requirement, it is
important to consider not only quiescent power dissipation, but also dynamic power dissipation. Often
maximum power dissipation is difficult to quantify
because the signal pattern is inconsistent, but an
estimate of the RMS value can provide a reasonable
analysis.
THERMAL ANALYSIS
Texas Instruments is committed to providing its customers with the highest quality of applications support. To support this goal, an evaluation board has
been developed for the THS4281 operational amplifier. The evaluation board is available and easy to
use allowing for straight-forward evaluation of the
device. These evaluation board can be obtained by
ordering through the Texas Instruments Web site,
www.ti.com, or through your local Texas Instruments
Sales Representative. A schematic for the evaluation
board is shown in Figure 77 with their default
component values. Unpopulated footprints are shown
to provide insight into design flexibility.
The THS4281 does not incorporate automatic thermal
shutoff protection, so the designer must take care to
ensure that the design does not violate the absolute
maximum junction temperature of the device. Failure
may result if the absolute maximum junction temperature of 150° C is exceeded. For long-term dependability, the junction temperature should not exceed
125°C.
The thermal characteristics of the device are dictated
by the package and the PC board. Maximum power
dissipation for a given package can be calculated
using the following formula.
Tmax–T A
P Dmax JA
where:
PDmax is the maximum power dissipation in the amplifier (W).
Tmax is the absolute maximum junction temperature (°C).
TA is the ambient temperature (°C).
θJA = θJC + θCA
θJC is the thermal coefficient from the silicon junctions to the
case (°C/W).
θCA is the thermal coefficient from the case to ambient air
(°C/W).
P D − Maximum Power Dissipation − W
1.8
1.6
8-pin SOIC (D) Package
1.4
8-pin MSOP
(DGK) Package
1.2
1
0.8
DESIGN TOOLS
Evaluation Fixtures
Information
and
Application
Support
Computer simulation of circuit performance using
SPICE is often useful when analyzing the performance of analog circuits and systems. This is particularly true for video and RF amplifier circuits where
parasitic capacitance and inductance can have a
major effect on circuit performance. A SPICE model
for the THS4281 device is available through either
the Texas Instruments Web site (www.ti.com) or as
one model on a disk from the Texas Instruments
Product Information Center (1–800–548–6132). The
PIC is also available for design assistance and
detailed product information at this number. These
models do a good job of predicting small-signal ac
and transient performance under a wide variety of
operating conditions. They are not intended to model
the distortion characteristics of the amplifier, nor do
they attempt to distinguish between the package
types in their small-signal ac performance. Detailed
information about what is and is not modeled is
contained in the model file itself.
0.6
0.4
0.2
0
−40
5-pin SOT23
(DBV) Package
−20
0
20
40
60
80
TA − Free-Air Temperature − °C
100
θJA = 97.5°C/W for 8-Pin SOIC (D)
θJA = 180.8°C/W for 8-Pin MSOP (DGK)
θJA = 255.4°C/W for 5-Pin SOT−23 (DBV)
TJ = 125°C, No Airflow
Figure 76. Maximum Power Dissipation vs
Ambient Temperature
23
THS4281
www.ti.com
J7
J5
–vs
C4
22 µF
R4
2 kΩ
R0603_1%
+
R2
2 kΩ
R0603_1%
J1
+vs
FB2
FB1
C3
0.1 µF
C0805
C2
100 pF
+Vs
–Vs
SLOS432 – APRIL 2004
+vs
U1
4
SIDEMOUNT_SMA
R1
51.1 Ω
R0805_1%
6
3
2
1
+
C5
22 µF
R5
953 Ω
R0603_1%
SIDEMOUNT_SMA
THS4281DBV
R6
R0603_1%
C1
C1206
TP1
J6
R3
49.9 Ω
R0805_1%
J4
GND
J3
PD
SIDEMOUNT_SMA
C7
100 pF
5
–vs
J2
C6
0.1 µF
C0805
Figure 77. THS4281EVM Schematic
TOP
Figure 78. THS4281EVM Layout
(Top Layer and Silkscreen Layer)
24
Layer 2 − GND
Figure 79. THS4281EVM Board Layout
THS4281
www.ti.com
SLOS432 – APRIL 2004
Layer 3 − GND
Figure 80. THS4281EVM Board Layout
BOTTOM
Figure 81. THS4281EVM Board Layout
25
THS4281
www.ti.com
SLOS432 – APRIL 2004
BILL OF MATERIALS
THS4281DBV EVM
ITEM
(1)
DESCRIPTION
SMD
SIZE
REFERENCE
DESIGNATOR
PCB
QTY.
FB1, FB2
2
1
Bead, Ferrite, 3A, 80 Ω
1206
2
OPEN
1206
C1
1
3
Cap, 22 µF, tanatalum, 25 V,
10%
D
C4, C5
4
Cap, 0.1 µF, ceramic, X7R, 50V
0805
5
Cap, 100 pF, ceramic, 5%, 150V
AQ12
6
OPEN
7
MANUFACTURER'S
PART NUMBER (1)
DISTRIBUTOR'S
PART NUMBER
(STEWARD)
HI1206N800R-00
(DIGI-KEY) 240-1010-1-ND
2
(AVX) TAJD226K025R
(GARRETT) TAJD226K025R
C3, C6
2
(AVX) 08055C104KAT2A
(GARRETT) 08055C104KAT2A
C2, C7
2
(AVX) AQ12EM101JAJME
(TTI) AQ12EM101JAJME
0603
R6
1
Resistor, 2 KΩ, 1/10W, 1%
0603
R2, R4
2
(PHYCOMP)
9C06031A2001FKHFT
(GARRETT)
9C06031A2001FKHFT
8
Resistor, 953 Ω, 1/10W, 1%
0603
R5
1
(PHYCOMP)
9C06031A9530FKRFT
(GARRETT)
9C06031A9530FKRFT
9
Resistor, 51.1 Ω, 1/8W, 1%
0805
R1
1
(PHYCOMP)
9C08052A51R1FKHFT
(GARRETT)
9C08052A51R1FKHFT
10
Resistor, 49.9 Ω, 1/8W, 1%
0805
R3
1
(PHYCOMP)
9C08052A49R9FKHFT
(GARRETT)
9C08052A49R9FKHFT
11
Jack, banana receptance, 0.25"
diameter hole
J5, J6, J7
3
(HH SMITH) 101
(NEWARK) 35F865
12
OPEN
J3
1
13
Test point, black
TP1
1
(KEYSTONE) 5001
(DIGI-KEY) 5001K-ND
14
Connector, edge, SMA PCB
JACK
J1, J2, J4
3
(JOHNSON) 142-0701-801
(NEWARK) 90F2624
15
Standoff, 4-40 HEX, 0.625"
length
4
(KEYSTONE) 1804
(NEWARK) 89F1934
16
Screw, PHILLIPS, 4-40, 0.250"
4
SHR-0440-016-SN
17
IC, THS4281
1
(TI) THS4281DBV
18
Board, printed circuit
1
(TI) EDGE # 6448015 Rev.A
U1
The manufacturer's part numbers are used for test purposes only.
ADDITIONAL REFERENCE MATERIALS
•
•
•
•
26
PowerPAD Made Easy, application brief, (SLMA004)
PowerPAD Thermally Enhanced Package, technical brief (SLMA002)
Active Low-Pass Filter Design, application report (SLOA049)
FilterPro MFB and Sallen-Key Low-Pass Filter Design Program, application report (SBFA001)
PACKAGE OPTION ADDENDUM
www.ti.com
19-May-2005
PACKAGING INFORMATION
Orderable Device
Status (1)
Package
Type
Package
Drawing
Pins Package Eco Plan (2)
Qty
THS4281D
ACTIVE
SOIC
D
8
THS4281DBVR
ACTIVE
SOT-23
DBV
THS4281DBVRG4
ACTIVE
SOT-23
THS4281DBVT
ACTIVE
THS4281DBVTG4
75
Lead/Ball Finish
MSL Peak Temp (3)
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
5
3000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
DBV
5
3000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SOT-23
DBV
5
250
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
ACTIVE
SOT-23
DBV
5
250
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
THS4281DGK
ACTIVE
MSOP
DGK
8
100
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
THS4281DGKR
ACTIVE
MSOP
DGK
8
2500 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
THS4281DGKRG4
ACTIVE
MSOP
DGK
8
2500 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
THS4281DR
ACTIVE
SOIC
D
8
2500 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
THS4281DRG4
ACTIVE
SOIC
D
8
2500 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS) or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
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Addendum-Page 1
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