INFINEON TLE7233G

Datasheet, Rev. 1.0, February 2008
TLE7233G
SPIDER - 4 channel low side driver with limp home
Automotive Power
SPI Driver for Enhanced Relay Control
SPIDER - TLE7233G
Table of Contents
Table of Contents
Table of Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
1
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
2
2.1
Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Voltage and current naming definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
3
3.1
3.2
Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Pin Assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Pin Definitions and Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
4
4.1
4.2
4.3
General Product Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Functional Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Thermal Resistance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
5
5.1
Power Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Limp Home Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
6
6.1
6.2
6.3
6.4
Power Stages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Inductive Output Clamp . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Timing Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Electrical Characteristics Power Stages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
13
13
14
15
16
7
7.1
7.2
7.3
7.4
Protection Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Over Load Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Over Temperature Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Reverse Polarity Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Electrical Characteristics Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
18
18
18
18
19
8
8.1
8.2
Diagnostic Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Open Load Diagnosis timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Electrical Characteristics Diagnostic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
9
9.1
9.2
9.3
9.4
9.5
Serial Peripheral Interface (SPI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SPI Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Daisy Chain Capability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SPI Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Timing Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Electrical Characteristics SPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
10
Application Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
11
Package Outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
12
Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Datasheet
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22
23
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Rev. 1.0, 2008-02-28
SPI Driver for Enhanced Relay Control
SPIDER - TLE7233G
1
TLE7233G
Overview
Features
•
•
•
•
•
•
•
•
•
4 channel low side relay driver
8 bit SPI for diagnostics and control
SPI providing Daisy Chain Capability
Limp Home functionality
Very wide range for digital Supply Voltage
Four input pins provide flexible and straightforward PWM operation
Stable behavior at Under Voltage
Green Product (RoHS compliant)
AEC Qualified
Table 1
PG-SSOP-24-5
Product Summary
VDD
VDDA
RDS(ON)
IL (nom,min)
ID (OVL,max)
ID (STB,max)
VDS(AZ)
fSCLK
Digital supply voltage
Analog supply voltage
ON State resistance at Tj = 150°C for each channel
Nominal load current
Overload switch off threshold
Output leakage current per channel at 25 °C
Drain to Source clamping voltage
SPI clock frequency
3.0 V ... 5.5 V
4.5 V ... 5.5 V
2.2 Ω
390 mA
950 mA
1 µA
41 V
5 MHz
Diagnostic Features
•
•
•
•
Latched diagnostic information via SPI
Over temperature monitoring
Over load detection in ON state
Open load detection in OFF state
Type
Package
Marking
TLE7233G
PG-SSOP-24-5
TLE7233G
Datasheet
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Rev. 1.0, 2008-02-28
SPI Driver for Enhanced Relay Control
SPIDER - TLE7233G
Overview
Protection Functions
•
•
•
•
Short circuit
Over load
Over temperature
Electrostatic discharge (ESD)
Application
•
•
All types of resistive, inductive and capacitive loads
Especially designed for driving relays in automotive applications
Description
The TLE7233G is a four channel low-side relay switch (1 Ω per channel) in PG-SSOP-24-5 package providing
embedded protective functions. It is especially designed as a relay driver for automotive applications. The 8 bit
serial peripheral interface (SPI) is provided for control and diagnostics of the device and the loads. The SPI
interface provides daisy-chain capability.
The TLE7233G is equipped with four input pins that can be individually routed to the output control of their
corresponding channel and therefore offer complete flexibility in design and PCB layout. The input multiplexer is
controlled via SPI.
A limp home pin (LHI) provides a simple use of the input pins; this enables a direct connection between the input
pins and their corresponding outputs. The limp home function works under VDDA in order to ensure functionality
even with a missing digital supply.
The device provides many diagnostics of the load enabling both open load and short circuit detection. The SPI
diagnostic bits indicate any eventual latched fault condition.
Each output stage is protected against short circuit. In case of over load, the affected channel switches off.
Temperature sensors are available for each channel in order to protect the device against over temperature.
The power transistors are made of N-channel vertical power MOSFETs. The inputs CMOS compatible referenced
to Ground. The device is monolithically integrated in Smart Power Technology.
Datasheet
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Rev. 1.0, 2008-02-28
SPI Driver for Enhanced Relay Control
SPIDER - TLE7233G
Block Diagram
2
Block Diagram
RST
VDD
VDDA
OUT0
IN0
IN1
IN2
OUT1
temperature
sensor
input logic
IN3
LHI
input register
CS
SCLK
SI
SPI
OUT2
OUT3
short circuit
detection
control,
diagnostic
and
protective
functions
gate
control
open load
detection
SO
diagnostic register
GND
Overview_GS.emf
Figure 1
Datasheet
Block Diagram
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Rev. 1.0, 2008-02-28
SPI Driver for Enhanced Relay Control
SPIDER - TLE7233G
Block Diagram
2.1
Voltage and current naming definition
Following figure shows all the terms used in this datasheet, with associated convention for positive values.
Idda
Idd
VDDA
IRS T
V DD
I IN3
VRS T
I IN2
V IN3
I IN1
VIN2
I IN0
V IN1
I LHI
VIN0
ICS
V LHI
VCS
IS CLK
VS CLK IS I
VSI
VSO
IS O
VDDA
V bat
VDD
RST
IN3
IN2
IN1
IN0
OUT0
LHI
OUT1
CS
OUT2
SCLK
OUT3
I D1
I D2
I D3
VDS 0
VDS 1
VDS 2
VDS 3
SI
SO
I D0
GND
I GND
Terms_GS.emf
Figure 2
Terms
In all tables of electrical characteristics is valid: Channel related symbols without channel number are valid for each
channel separately (e.g. VDS specification is valid for VDS0 … VDS3).
All SPI register bits are marked as follows: PARAMETER (e.g. IN0). In SPI register description, the values in bold
letters (e.g. 0) are default values.
Datasheet
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Rev. 1.0, 2008-02-28
SPI Driver for Enhanced Relay Control
SPIDER - TLE7233G
Pin Configuration
3
Pin Configuration
3.1
Pin Assignment
(top view)
SUB
1
24
n.c.
SUB
2
23
SCLK
OUT3
3
22
SO
OUT2
4
21
SI
VDD
5
20
IN3
GND
6
19
GND
VDDA
7
18
IN2
LHI
8
17
IN1
OUT1
9
16
IN0
OUT0
10
15
CS
SUB
11
14
RST
SUB
12
13
n.c.
PG-SSOP-24 .emf
Figure 3
Pin Configuration
3.2
Pin Definitions and Functions
Pin
Symbol
I/O
1)
Function
Power Supply
5
VDD
-
Digital Supply Voltage; Connected to 5V Voltage with Reverse
protection Diode and Filter against EMC
7
VDDA
-
Analog Supply Voltage;
6,19
GND
-
Ground; common ground for digital, analog and power
1,2,11,
12
SUB
-
Substrate; shorted to die pad,can be left not connected or used for thermal
connection and shorted to ground
Power Stages
10
OUT0
O
Output Channel 0; Drain of power transistor channel 0
9
OUT1
O
Output Channel 1; Drain of power transistor channel 1
4
OUT2
O
Output Channel 2; Drain of power transistor channel 2
3
OUT3
O
Output Channel 3; Drain of power transistor channel 3
16
IN0
I
PD Control Input; Digital input 3.3 V or 5V. In case of not used keep open.
17
IN1
I
PD Control Input; Digital input 3.3 V or 5V. In case of not used keep open.
Inputs
Datasheet
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Rev. 1.0, 2008-02-28
SPI Driver for Enhanced Relay Control
SPIDER - TLE7233G
Pin Configuration
Pin
Symbol
I/O
1)
18
IN2
I
PD Control Input; Digital input 3.3 V or 5V. In case of not used keep open.
20
IN3
I
PD Control Input; Digital input 3.3 V logic. In case of not used keep open.
8
LHI
I
PD Limp Home; Digital input 3.3 V or 5V. In case of not used keep open.
14
RST
I
PD Reset input pin; Digital input 3.3 V or 5V. Low active
15
CS
I
PU SPI chip select; Digital input 3.3 V or 5V.Low active
23
SCLK
I
PD serial clock; Digital input 3.3 V or 5V.
21
SI
I
PD serial data in; Digital input 3.3 V or 5V.
22
SO
O
serial data out; Digital input 3.3 V or 5V.
n.c.
-
not connected; pin not used
Function
SPI
Others
13,24
1) O: Output, I: Input,
PD: pull-down resistor integrated,
PU pull-up resistor integrated
Datasheet
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Rev. 1.0, 2008-02-28
SPI Driver for Enhanced Relay Control
SPIDER - TLE7233G
General Product Characteristics
4
General Product Characteristics
4.1
Absolute Maximum Ratings
Absolute Maximum Ratings 1)
Tj = -40 °C to +150 °C; VDD = 3.0 V to VDDA, VDDA = 4.5V to 5.5V.
All voltages with respect to ground, positive current flowing into pin (unless otherwise specified)
Pos.
Parameter
Symbol
Limit Values
Min.
Max.
Unit
Conditions
Power Supply
4.1.1
Digital supply voltage
VDD
-0.3
5.5
V
–
4.1.2
Analog supply voltage
VDDA
-0.3
5.5
V
–
ID
-0.5
0.5
A
–
–
36
V
–
41
V
active clamped
mJ
2)
Power Stages
4.1.3
Load current
4.1.4
Output voltage for short circuit protection VD
(single pulse)
4.1.5
Voltage at power transistor
4.1.6
Maximum energy dissipation one channel
VDS
EAS
single pulse
–
65
Tj(0) = 85 °C
ID(0) = 0.35 A
single pulse
–
30
Tj(0) = 150 °C
ID(0) = 0.25 A
–
–
18
13
repetitive (1 · 104 cycles)
repetitive (1 · 106 cycles)
Tj(0) = 150 °C
ID(0) = 0.25 A
ID(0) = 0.17 A
EAR
Logic Pins
4.1.7
Voltage at input pins
VIN0..3
-0.3
5.5
V
4.1.8
Voltage at LHI pin
VLHI
-0.3
5.5
V
–
V
3)
V
3)
V
3)
V
3)
V
3)
–
4.1.9
Voltage at reset pin
VRST
-0.3
4.1.10
Voltage at chip select pin
VCS
-0.3
4.1.11
Voltage at serial clock pin
VSCLK
-0.3
4.1.12
Voltage at serial input pin
VSI
-0.3
4.1.13
Voltage at serial output pin
VSO
-0.3
VDD + 0.3
VDD + 0.3
VDD + 0.3
VDD + 0.3
VDD + 0.3
Tj
Tstg
-40
150
°C
–
-55
150
°C
–
kV
HBM4)
Temperatures
4.1.14
Junction Temperature during operation
4.1.15
Storage Temperature
ESD Susceptibility
4.1.16
ESD Resistivity
VESD
Output
-4
4
Input / SPI
-2
2
1) Not subject to production test, specified by design.
2) Pulse shape represents inductive switch off: ID(t) = ID(0) × (1 - t / tpulse); 0 < t < tpulse
3) VDD + 0.3 V < 5.5 V
Datasheet
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Rev. 1.0, 2008-02-28
SPI Driver for Enhanced Relay Control
SPIDER - TLE7233G
General Product Characteristics
4) ESD susceptibility, HBM according to EIA/JESD 22-A114B
Note: Stresses above the ones listed here may cause permanent damage to the device. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
Note: Integrated protection functions are designed to prevent IC destruction under fault conditions described in the
data sheet. Fault conditions are considered as “outside” normal operating range. Protection functions are
not designed for continuous repetitive operation.
4.2
Pos.
Functional Range
Parameter
Symbol
Limit Values
Unit
Conditions
Min.
Max.
VDD
VDDA
3. 0
5.5
V
–
4.5
5.5
V
–
IDD(ON)
–
0.5
mA
–
–
5
mA
–
4.2.1
Digital supply voltage
4.2.2
Analog supply voltage
4.2.3
Digital supply current all channels
ON
4.2.4
Analog supply current all channels IDDA(ON)
ON
Note: Within the functional range the IC operates as described in the circuit description. The electrical
characteristics are specified within the conditions given in the related electrical characteristics table.
4.3
Thermal Resistance
Note: This thermal data was generated in accordance with JEDEC JESD51 standards.
For more information, go to www.jedec.org.
Pos.
4.3.5
Parameter
Junction to Soldering Point
Symbol
RthJSP
RthJA
Limit Values
Min.
Typ.
Max.
–
–
29
Unit
Conditions
K/W
pin 2,6, 11, 191)
1)2)
Junction to Ambient
–
47
–
K/W
1) Specified RthJSP value is simulated at natural convection on a cold plate setup (all pins are fixed to ambient temperature).
Ta = 25 °C. LS0 to LS3 are dissipating 1 W power (0.25 W each).
4.3.6
2) Specified RthJA value is according to Jedec JESD51-2,-7 at natural convection on FR4 2s2p board; The product
(Chip+Package PG-SSOP-24) was simulated on a 76.2 x 114.3 x 1.5 mm board with 2 inner copper layers (2 x 70 µm Cu,
2 x 35 µm Cu). Ta = 25 °C, LS1 to LS3 are dissipating 1 W power (0.25 W each).
Datasheet
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Rev. 1.0, 2008-02-28
SPI Driver for Enhanced Relay Control
SPIDER - TLE7233G
Power Supply
5
Power Supply
The TLE7233G is supplied by two power supply lines VDD and VDDA. The digital power supply line VDD is designed
to be functional at a very wide voltage range. The analog power supply VDDA supports 5 V supply.
Power-on reset functions have been implemented for both supply lines. After start-up of the power supply, all SPI
registers are reset to their default values and the device remains in idle mode. Capacitors at pins VDD - GND and
VDDA - GND are recommended.
A reset pin is available. At low logic level at this pin, all registers are set to their default values and the quiescent
supply currents are minimized.
The VDD supply line is used for the I/O buffer circuits of the SPI pins, therefore the voltage on the SO pin is always
related to this supply voltage. A capacitor between pins VDD and GND is recommended (especially in case of EMI).
To enable the Daisy chain functionality it is necessary to have VDD and VDDA in the specified functional range.
The device provides a sleep mode to minimize current consumption, which also resets the register banks. It is
controlled by a low active reset pin (RST) which disables the device and minimize the current consumption. The
table below gives an overview of the different power modes.
Table 2
Power modes1)
RESET
VDD
(low active)
Power mode State Description
VDDA
SCLK
LHI
SLEEP
Device at minimum current consumption
low
X
X
0 Hz
low
IDLE
Device operational, all channels OFF no
diagnosis activated
high
ON
ON
0 Hz
low
LIMP HOME Device in Limp home mode
ON
X
Device operational with enabled channels and high
diagnostic currents active
X
ON
X
high
ON
ON
5 MHz
(max)
low
1) low: pin input is digital low,
high: pin input is digital high,
X: pin state don’t care,
ON: voltage on this analog supply pin is in the specified functional range
Datasheet
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Rev. 1.0, 2008-02-28
SPI Driver for Enhanced Relay Control
SPIDER - TLE7233G
Power Supply
5.1
Limp Home Mode
The TLE7233G offers the capability of driving dedicated channels during eventual fail-safe operation of the
system. This limp home mode is activated by a high signal at pin LHI. In this mode, the SPI registers are reset and
the input pins are directly routed to their corresponding channels, see Table 3 for details.
Furthermore, the SPI is ignored and all input pin are referred to VDDA in order to ensure a defined operation mode
if the digital supply or the microcontroller fail.
A high signal on LHI overrides a Reset signal on RST. In case of a limp home during sleep the device will therefore
wake up and enter the limp home mode.
During Limp home mode any SPI transmission will receive a TER flag.
After limp home operation all registers are reset and the device enters in sleep mode following low logic RST state,
or returns to ON state (all channels OFF with diagnostic currents active). Next SPI transmission will receive a TER
Flag.
Input
controlled
Output
IN0
OUT0
IN1
OUT1
IN2
OUT2
IN3
OUT3
Table 3
Datasheet
Routing during limp home mode
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SPI Driver for Enhanced Relay Control
SPIDER - TLE7233G
Power Stages
6
Power Stages
The TLE7233G is a four channel low-side relay switch.
The power stages are made of N-channel vertical power MOSFET transistors.
6.1
Input Circuit
The TLE7233G has four input pins, that can be configured to be used for control of the output stages. The INn
parameter of the SPI provide the following operation modes:
•
•
•
•
channel is in off mode without diagnosis
(if all channels are programmed to this mode, the device goes into idle mode)
channel is switched according to signal level at input pin INx
channel is switched on
channel is switched off with active diagnosis
Figure 5 shows the input circuit of TLE7233G.
IN
IIN
InputStage.emf
Figure 4
Datasheet
Input signal conditioning circuit on all input and limp home pins
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Rev. 1.0, 2008-02-28
SPI Driver for Enhanced Relay Control
SPIDER - TLE7233G
Power Stages
OFF
Channel 0
IN0
IN0
&
ON
OFF
INx0
OFF
D0
LHI
Channel 1
IN1
IN1
&
ON
OFF
INx1
OFF
D1
LHI
Channel 2
IN2
IN2
&
ON
OFF
INx2
OFF
D2
LHI
Channel 3
IN3
IN3
&
ON
OFF
INx3
D3
LHI
InputLogic_GS.emf
Figure 5
Input Multiplexer
The current sink to ground ensures that the channels switch off in case of open input pin. The zener diode protects
the input circuit against ESD pulses. After power-on reset, the device enters idle mode.
6.2
Inductive Output Clamp
When switching off inductive loads, the potential at pin OUT rises to VDS(CL) potential, because the inductance
intends to continue driving the current. The voltage clamping is necessary to prevent destruction of the device,
see Figure 6 for details. Nevertheless, the maximum allowed load inductance is limited.
Datasheet
14
Rev. 1.0, 2008-02-28
SPI Driver for Enhanced Relay Control
SPIDER - TLE7233G
Power Stages
V bat
ID
OUT
L,
RL
VDS
VDS(CL)
GND
OutputClamp .emf
Figure 6
Output Clamp Implementation
Maximum Load Inductance
During demagnetization of inductive loads, energy has to be dissipated in the TLE7233G.
This energy can be calculated with following equation:
V bat – V DS(CL) 

RL ⋅ IL
L
- ⋅ ln 1 – ----------------------------------E = V DS(CL) ⋅ -----------------------------------  + I L ⋅ -----RL
RL
V bat – V DS(CL) 

Following equation simplifies under the assumption of RL = 0:

V bat
2 
1
E = --- LI L ⋅ 1 – -----------------------------------
2
V bat – V DS(CL) 

The maximum energy, which is converted into heat, is limited by the thermal design of the component.
6.3
Timing Diagrams
The power transistors are switched on and off with a dedicated slope via the IN bits of the serial peripheral
interface SPI. The switching times tON and tOFF are designed equally.
CS
VDS
SPI: ON
SPI: OFF
tON
tOFF
t
80%
20%
t
Figure 7
SwitchOn.emf
Switching a Resistive Load
In input mode, a high signal at the input pin is equivalent to a SPI ON command and a low signal to SPI OFF
command respectively. Please refer to Section 9.3 for details on operation modes.
The listed switching times are not valid, when switching to or from stand-by mode.
Datasheet
15
Rev. 1.0, 2008-02-28
SPI Driver for Enhanced Relay Control
SPIDER - TLE7233G
Power Stages
6.4
Electrical Characteristics Power Stages
VDD = 3.0 V to VDDA, VDDA = 4.5V to 5.5V, Tj = -40 °C to +150 °C
All voltages with respect to ground, positive current flowing into pin (unless otherwise specified)
typical values: VDD = 5.0 V, VDDA = 5.0 V, Tj = 25 °C
Pos.
Parameter
Symbol
Limit Values
Unit
Conditions
Min.
Typ.
Max.
VDD
IDD(ON)
3. 0
–
5.5
V
–
–
–
0.5
mA
IDD(idle)
–
–
VDD = VDDA = 5 V
VRST = VCS = VDD
VSCLK = 0 V
VIN = 0 V
fSCLK = 0 Hz
VRST = VCS = high
Tj = 25 °C 1)
Tj = 85 °C 1)
Tj = 150 °C
VRST = 0 V
Tj = 25 °C 1)
Tj = 85 °C 1)
Tj = 150 °C
Power Supply
6.4.1
Digital supply voltage
6.4.2
Digital supply current all channels
ON
6.4.3
Digital supply idle current
µA
20
20
40
6.4.4
Digital supply sleep current
IDD(sleep)
–
µA
–
5
5
20
6.4.5
Digital power-on reset threshold
voltage
6.4.6
Analog supply voltage
6.4.7
VDD(PO)
VDDA
Analog supply current all channels IDDA(ON)
–
–
3.0
V
–
4.5
–
5.5
V
–
–
–
5
mA
–
–
–
µA
VCS = VDD
VSI = 0 V
VSCLK = 0 V
Tj = 25 °C 1)
Tj = 85 °C 1)
Tj = 150 °C
VCS = VDD
VRST = 0 V
Tj = 25 °C 1)
Tj = 85 °C 1)
Tj = 150 °C
ON
6.4.8
Analog supply idle current
IDDA(idle)
25
6.4.9
Analog supply sleep current
Idd(sleep)
–
µA
–
5
5
20
6.4.10
Analog power-on reset threshold
voltage
VDDA(PO)
–
RDS(ON)
–
–
4.5
V
–
Ω
IL = 250 mA
Tj = 25 °C 1)
Tj = 150 °C
mA
2)
Output Characteristics
6.4.11
6.4.12
On-State resistance per channel
Nominal load current
Datasheet
ID(nom)
390
16
1.0
2.0
2.2
415
–
Rev. 1.0, 2008-02-28
SPI Driver for Enhanced Relay Control
SPIDER - TLE7233G
Power Stages
VDD = 3.0 V to VDDA, VDDA = 4.5V to 5.5V, Tj = -40 °C to +150 °C
All voltages with respect to ground, positive current flowing into pin (unless otherwise specified)
typical values: VDD = 5.0 V, VDDA = 5.0 V, Tj = 25 °C
Pos.
6.4.13
6.4.14
Parameter
Symbol
Limit Values
Min.
Typ.
–
–
Unit
Conditions
µA
VDS = 13.5 V
Tj = 25 °C 1)
Tj = 85 °C 1)
Tj = 150 °C
Max.
Output leakage current
(per channel)
ID(OFF)
Output clamping voltage
VDS(CL)
41
–
52
V
3)
1
2
5
Input Pin Characteristics
6.4.15
L level of pin
IN & LHI
VIN(L)
0
–
0.9
V
–
6.4.16
H level of pin
IN & LHI
VIN(H)
2.2
–
5.5
V
–
6.4.17
L-input pull-down current through
pin
IIN(L)
3
12
80
µA
6.4.18
H-input pull-down current through
pin
IIN(H)
10
40
80
µA
VDD = 5 V 1)
VIN = 0.6 V
VDD = 5 V
L level of pin RST
VRST(L)
0
VRST(H)
0.4*
6.4.19
6.4.20
H level of pin RST
VIN = 5 V
–
0.2*
–
–
VDD
VDD
–
VDD
VDD = 5 V 1)
VRST = 0.6 V
VDD = 5 V
VRST = 5 V
6.4.21
L-input pull-down current through
pin RST
IRST(L)
3
12
80
µA
6.4.22
H-input pull-down current through
pin RST
IRST(H)
10
40
80
µA
6.4.23
Sleep wake-up time
–
–
200
µs
–
6.4.24
Reset duration
1
–
–
µs
–
6.4.25
Turn-on time
VDS = 20% Vbat
twu(sleep)
tRST(L)
tON
–
–
60
µs
Vbb = 13.5 V
IDS = 250 mA,
resistive load
6.4.26
Turn-off time
VDS = 80% Vbb
tOFF
–
–
60
µs
Vbb = 13.5 V
IDS = 250 mA,
resistive load
Timings
1) Not subject to production test, specified by design
2) calculated value based on following parameters:
all channels on with equal load current, RDS(ON) = RDS(ON,150°C) ,
3) maximum value is increasing in sleep mode
Datasheet
17
Ta = 85 °C, Tj,max = 150 °C, Rth = RthJA(typ)
Rev. 1.0, 2008-02-28
SPI Driver for Enhanced Relay Control
SPIDER - TLE7233G
Protection Functions
7
Protection Functions
Note: The device provides embedded protective functions. Integrated protection functions are designed to prevent
IC destruction under fault conditions described in this datasheet. Fault conditions are considered as
“outside” normal operating range. Protection functions are not designed for continuous repetitive operation.
7.1
Over Load Protection
The TLE7233G is protected against over load or short circuit of the load. After time tOFF(OVL), the over loaded
channel n switches off and therefore the corresponding diagnostics flag Dn is set. The channel can be switched
on after clearing the diagnostics flag. Please refer to Figure 8 for details.
IN
t
tOFF(OVL)
ID0
ID0(OVL)
IN0 = 01 b
D0 = 0 b
D0 = 1b
IN0 = 00 b
D0 = 0 b
IN0 = 01 b
t
OverLoad .emf
Figure 8
Shut Down at Over Load
7.2
Over Temperature Protection
A temperature sensor for each channel causes an overheated channel n to switch off to prevent destruction. Then
the according diagnostics flag Dn is set. The channel can be switched on after clearing the diagnosis flag. Please
refer to Section 8 for information on diagnostics features.
7.3
Reverse Polarity Protection
In case of reverse polarity, the intrinsic body diode of the power transistor causes increased power dissipation. The reverse
current through the intrinsic body diode of the power transistor has to be limited by the connected load. The VDD and VDDA
supply pins must be externally protected against reverse polarity. The over temperature and over load protection are not active
during reverse polarity.
Datasheet
18
Rev. 1.0, 2008-02-28
SPI Driver for Enhanced Relay Control
SPIDER - TLE7233G
Protection Functions
7.4
Electrical Characteristics Protection
VDD = 3.0 V to VDDA, VDDA = 4.5V to 5.5V, Tj = -40 °C to +150 °C
All voltages with respect to ground, positive current flowing into pin (unless otherwise specified)
typical values: VDD = 5.0 V, VDDA = 5.0 V, Tj = 25 °C
Pos.
Parameter
Symbol
Limit Values
Min.
Typ.
Unit
Conditions
Max.
Over Load Protection
7.4.1
Over load detection current
ID(OVL)
0.5
0.95
A
–
7.4.2
Over load shut-down delay time
tOFF(OVL)
5
60
µs
–
150
1701)
°C
–
10
K
1)
Over Temperature Protection
7.4.3
Thermal shut down temperature
Tj(SC)
7.4.4
Thermal hysteresis
∆ Tj
1) Not subject to production test, specified by design
Datasheet
19
Rev. 1.0, 2008-02-28
SPI Driver for Enhanced Relay Control
SPIDER - TLE7233G
Diagnostic Features
8
Diagnostic Features
The SPI of TLE7233G provides diagnosis information about the device and about the load. The diagnosis
information of the protective functions of channel n is latched in the diagnosis flag Dn. The open load diagnosis of
channel n is latched in the diagnosis flag OLn. Both flags are cleared by INn = 00B and the diagnosis current ID(PD),
which is a small pull down current, is disabled.
Following table shows possible failure modes and the according protective and diagnostic action.
j
Failure Mode
Comment
Open Load
Diagnosis, when channel n is switched on:
or short circuit to GND INn = 01B: if input pin is high: none
INn = 10B: none
Diagnosis, when channel n is switched off:
INn = 00B: none, diagnosis flags are cleared and the diagnosis current is switched off
INn = 01B: if input pin is low, according to voltage at the output pin, the flag OLn is set
after time td(OL)
INn = 11B: according to voltage level at the output pin, flags OLn are set after time td(OL)
Over temperature
When over temperature occurs, the affected channel n is switched off. The according
diagnosis flag Dn is set.
The diagnosis flags are latched until they have been cleared by INn = 00B. The over
temperature detection is active in ON-state as well as OFF-state.
Over Load
(Short Circuit)
When over load is detected at channel n, the affected channel is switched off after time
tOFF(OVL) and the dedicated diagnosis flag Dn is set.
The diagnosis flags are latched until they have been cleared by INn = 00B.
8.1
Open Load Diagnosis timing
The TLE7233G offers a open load diagnosis for each channel in OFF mode.
The time td(fault) is applied to filter short time events.
Open Load occures here
Open Load occures here
IN
IN
t
t
VDS
V DS
V DS (OL)
VDS (OL)
t
t d(fault)
td(fault)
OLn = 1b
t
OL n = 1b
OpenLoad.emf
Figure 9
Datasheet
Open Load timing
20
Rev. 1.0, 2008-02-28
SPI Driver for Enhanced Relay Control
SPIDER - TLE7233G
Diagnostic Features
8.2
Electrical Characteristics Diagnostic
VDD = 3.0 V to VDDA, VDDA = 4.5V to 5.5V, Tj = -40 °C to +150 °C
All voltages with respect to ground, positive current flowing into pin (unless otherwise specified)
typical values: VDD = 5.0 V, VDDA = 5.0 V, Tj = 25 °C
Pos.
Parameter
Symbol
Limit Values
Min.
Typ.
Unit
Conditions
2.5
V
–
100
µA
VDS = 13.5 V
Max.
OFF State Diagnosis
8.2.1
Open load detection threshold
voltage
8.2.2
Output pull-down diagnosis current ID(PD)
per channel
8.2.3
Open load diagnosis delay time
VDS(OL)
1.0
td(OL)
30
200
µs
–
ON State Diagnosis
8.2.4
Over load detection current
ID(OVL)
0.5
0.95
Α
–
8.2.5
Over load detection delay time
tOFF(OVL)
5
60
µs
–
Datasheet
21
Rev. 1.0, 2008-02-28
SPI Driver for Enhanced Relay Control
SPIDER - TLE7233G
Serial Peripheral Interface (SPI)
9
Serial Peripheral Interface (SPI)
The diagnosis and control interface is based on a serial peripheral interface (SPI).
The SPI is a full duplex synchronous serial slave interface, which uses four lines: SO, SI, SCLK and CS. Data is
transferred by the lines SI and SO at the data rate given by SCLK. The falling edge of CS indicates the beginning
of a data access. Data is sampled in on line SI at the falling edge of SCLK and shifted out on line SO at the rising
edge of SCLK. Each access must be terminated by a rising edge of CS. A modulo 8 counter ensures that data is
taken only, when a multiple of 8 bit has been transferred. The interface provides daisy chain capability.
SO
CS
SI
MSB
6
5
4
3
2
1
MSB
6
5
4
3
2
1
LSB
LSB
CS
SCLK
time
SPI.emf
Figure 10
Serial Peripheral Interface
The SPI protocol is described in Section 9.3. It is reset to the default values after power-on reset.
9.1
SPI Signal Description
CS - Chip Select:
The system micro controller selects the TLE7233G by means of the CS pin. Whenever the pin is in low state, data
transfer can take place. When CS is in high state, any signals at the SCLK and SI pins are ignored and SO is
forced into a high impedance state.
CS High to Low transition:
•
•
The diagnosis information is transferred into the shift register.
SO changes from high impedance state to high or low state depending on the logic OR combination between
the transmission error flag (TER) and the signal level at pin SI. As a result, even in daisy chain configuration,
a high signal indicates a faulty transmission. The transmission error flag is set after any kind of reset, so a reset
between two SPI commands is indicated. For details, please refer to Figure 11. This information stays
available to the first rising edge of SCLK.
Datasheet
22
Rev. 1.0, 2008-02-28
SPI Driver for Enhanced Relay Control
SPIDER - TLE7233G
Serial Peripheral Interface (SPI)
TER
SI
1
OR
SO
0
SI
SPI
SO
S
CS
SCLK
S
TER.emf
Figure 11
Transmission Error Flag on SO Line
CS Low to High transition:
Data from shift register is transferred into the input matrix register only, when after the falling edge of CS exactly
a multiple (1, 2, 3, …) of eight SCLK signals have been detected.
SCLK - Serial Clock:
This input pin clocks the internal shift register. The serial input (SI) transfers data into the shift register on the falling
edge of SCLK while the serial output (SO) shifts diagnostic information out on the rising edge of the serial clock.
It is essential that the SCLK pin is in low state whenever chip select CS makes any transition.
SI - Serial Input:
Serial input data bits are shifted in at this pin, the most significant bit first. SI information is read on the falling edge
of SCLK. Please refer to Section 9.3 for further information.
SO - Serial Output:
Data is shifted out serially at this pin, the most significant bit first. SO is in high impedance state until the CS pin
goes to low state. New data will appear at the SO pin following the rising edge of SCLK. Please refer to Section 9.3
for further information.
9.2
Daisy Chain Capability
The SPI of TLE7233G provides daisy chain capability. In this configuration several devices are activated by the
same CS signal MCS. The SI line of one device is connected with the SO line of another device (see Figure 12),
which builds a chain. The ends of the chain are connected with the output and input of the master device, MO and
MI respectively. The master device provides the master clock MCLK, which is connected to the SCLK line of each
device in the chain.
Datasheet
23
Rev. 1.0, 2008-02-28
SPI Driver for Enhanced Relay Control
SPIDER - TLE7233G
Serial Peripheral Interface (SPI)
SI
SO
SI
SO
SPI
CS
CS
SPI
SCLK
MI
MCS
MCLK
Figure 12
SO
SPI
device 3
SCLK
SI
CS
MO
device 2
SCLK
device 1
SPI_DasyChain.emf
Daisy Chain Configuration
In the SPI block of each device, there is one shift register where one bit from SI line is shifted in each SCLK. The
bit shifted out can be seen at SO. After 8 SCLK cycles, the data transfer for one device has been finished. In single
chip configuration, the CS line must transit from low to high to make the device accept the transferred data. In
daisy chain configuration the data shifted out at device #1 has been shifted in to device #2. When using three
devices in daisy chain, three times 8 bits have to be shifted through the devices. After that, the MCS line must
transit from low to high (see Figure 13).
MI
SO device 3
SO device 2
SO device 1
MO
SI device 3
SI device 2
SI device 1
MCS
MCLK
time
SPI_DasyChain2.emf
Figure 13
Data Transfer in Daisy Chain Configuration
9.3
SPI Protocol
The SPI protocol of the TLE7233G provides two registers. The input register and the diagnosis register. The
diagnosis register contains four pairs of diagnosis flags, the input register contains the input multiplexer
configuration. After power-on reset, all register bits are cleared to 0.
SI
7
6
IN3
Datasheet
5
4
3
IN2
2
IN1
24
1
0
IN0
Rev. 1.0, 2008-02-28
SPI Driver for Enhanced Relay Control
SPIDER - TLE7233G
Serial Peripheral Interface (SPI)
Field
INn
(n = 3-0)
Datasheet
Bits
Type Description
7:6,
5:4,
3:2,
1:0
W
Input Register Channel n
00B Stand-by Mode:
Fast channel switched off.
Diagnosis flags are cleared.
Diagnosis current is disabled.
01B Input Direct drive mode:
Channel is switched according to signal at corresponding input pin.
Diagnosis current is enabled in OFF-state. See Figure 5 for details.
10B ON Mode:
Channel is switched on.
Diagnosis current is enabled.
11B OFF Mode:
Channel is switched off.
Diagnosis current is enabled.
25
Rev. 1.0, 2008-02-28
SPI Driver for Enhanced Relay Control
SPIDER - TLE7233G
Serial Peripheral Interface (SPI)
SO
Reset Value: 100H
CS1)
7
6
5
4
3
2
1
0
TER
OL3
D3
OL2
D2
OL1
D1
OL0
D0
1) This bit is valid between CS hi -> lo and first SCLK lo -> hi transition.
Field
Bits
Type Description
TER
CS
R
OLn
(n = 3-0)
7, 5, 3, R
1
Open Load Flag of channel n
0
Normal operation.
1
Open load has occurred in OFF state.
Dn
(n = 3-0)
6, 4, 2, R
0
Diagnosis Flag of channel n
0
Normal operation.
1
Over load or over temperature switch off has occurred in ON state.
9.4
Timing Diagrams
Transmission Error
0
Previous transmission was successful (modulo 8 clocks received).
1
Previous transmission failed or first transmission after reset.
tCS (lead)
tCS (lag)
tCS (td)
tS C LK (P )
CS
0.7Vdd
0.2Vdd
tS CLK (H)
tS CLK (L)
0.7Vdd
SCLK
0.2Vdd
t S I(s u)
tS I(h)
0.7Vdd
SI
0.2Vdd
tS O(en)
tS O(v )
tS O(dis )
0.7Vdd
SO
0.2Vdd
SPI Timing.emf
Figure 14
Datasheet
Timing Diagram
26
Rev. 1.0, 2008-02-28
SPI Driver for Enhanced Relay Control
SPIDER - TLE7233G
Serial Peripheral Interface (SPI)
9.5
Electrical Characteristics SPI
VDD = 3.0 V to VDDA, VDDA = 4.5V to 5.5V, Tj = -40 °C to +150 °C
All voltages with respect to ground, positive current flowing into pin (unless otherwise specified)
typical values: VDD = 5.0 V, VDDA = 5.0 V, Tj = 25 °C
Pos.
Parameter
Symbol
Limit Values
Min.
Typ.
Max.
0
–
0.2*
Unit
Conditions
Input Characteristics (CS, SCLK, SI)
9.5.1
9.5.2
9.5.3
9.5.4
L level of pin
CS
SCLK
SI
VCS(L)
VSCLK(L)
VSI(L)
H level of pin
CS
SCLK
SI
VCS(H)
VSCLK(H)
VSI(H)
L-input pull-up current through CS ICS(L)
H-input pull-up current through CS ICS(H)
–
VDD
0.5*VDD
–
VDD
5
17
40
µA
VCS = 0 V
3
15
40
µA
1)
–
VCS = 2 V
9.5.5
9.5.6
L-input pull-down current through
pin
SCLK
SI
H-input pull-down current through
pin
SCLK
SI
3
12
80
µA
ISCLK(L)
ISI(L)
1)
VSCLK = 0.6 V
VSI = 0.6 V
10
40
80
µA
ISCLK(H)
ISI(H)
VSCLK = 5 V
VSI = 5 V
Output Characteristics (SO)
0
–
0.4
H level output voltage
VSO(L)
VSO(H)
VDD-
–
VDD
Output tristate leakage current
ISO(OFF)
-10
–
10
µA
VCS = VDD
9.5.10
Serial clock frequency
0
–
5
MHz
–
9.5.11
Serial clock period
200
–
–
ns
–
9.5.12
Serial clock high time
50
–
–
ns
–
9.5.13
Serial clock low time
50
–
–
ns
–
9.5.14
Enable lead time (falling CS to
rising SCLK)
fSCLK
tSCLK(P)
tSCLK(H)
tSCLK(L)
tCS(lead)
250
–
–
ns
–
9.5.15
Enable lag time (falling SCLK to
rising CS)
tCS(lag)
250
–
–
ns
–
9.5.16
Transfer delay time (rising CS to
falling CS)
tCS(td)
250
–
–
ns
–
9.5.17
Data setup time (required time SI to tSI(su)
falling SCLK)
20
–
–
ns
–
9.5.18
Data hold time (falling SCLK to SI) tSI(h)
20
–
–
ns
–
9.5.7
L level output voltage
9.5.8
9.5.9
V
ISO = -2 mA
ISO = 1.5 mA
0.5 V
Timings
Datasheet
27
Rev. 1.0, 2008-02-28
SPI Driver for Enhanced Relay Control
SPIDER - TLE7233G
Serial Peripheral Interface (SPI)
VDD = 3.0 V to VDDA, VDDA = 4.5V to 5.5V, Tj = -40 °C to +150 °C
All voltages with respect to ground, positive current flowing into pin (unless otherwise specified)
typical values: VDD = 5.0 V, VDDA = 5.0 V, Tj = 25 °C
Pos.
Parameter
Symbol
Limit Values
Min.
Typ.
Max.
Unit
Conditions
9.5.19
Output enable time (falling CS to
SO valid)
tSO(en)
–
–
200
ns
CL = 50 pF 1)
9.5.20
Output disable time (rising CS to
SO tri-state)
tSO(dis)
–
–
200
ns
CL = 50 pF 1)
9.5.21
Output data valid time with
capacitive load
tSO(v)
–
–
100
ns
CL = 50 pF 1)
1) Not subject to production test, specified by design.
Datasheet
28
Rev. 1.0, 2008-02-28
SPI Driver for Enhanced Relay Control
SPIDER - TLE7233G
Application Information
10
Application Information
Note: The following information is given as a hint for the implementation of the device only and shall not be
regarded as a description or warranty of a certain functionality, condition or quality of the device.
Figure 15 shows a simplified application circuit. VDDA and VDD need to be reverse protected. Also the Resistors in
the digital pins are for reverse polarity protection.
Vbb
VDDA
C1
Vdda
VDD
Vdd
C2
Loads
RST
R10 C3
Watch
dog
IN3
R9
IN2
R8
IN1
R7
IN0
R6
TLE 7233G
Discrete
Limp
home
or PWM
signal
circuit
OUT0
LHI
OUT1
CS
OUT2
SCLK
OUT3
R5
R4
SPI uC
R3
SI
R2
SO
R1
GND
Application_GS.emf
Figure 15
Application Diagram
Note: This is a very simplified example of an application circuit. The function must be verified in the real application.
C1,C2,C3 are recommended to be 4.7nF and all Resistors can be 1kOhm.
For further information you may contact http://www.infineon.com/
Datasheet
29
Rev. 1.0, 2008-02-28
SPI Driver for Enhanced Relay Control
SPIDER - TLE7233G
Package Outlines
11
Package Outlines
0˚...8˚
0.25 ±0.05 2)
B
0.1 B
Seating Plane
0˚...8˚
0.64 ±0.25
6 ±0.2
0.17 M C A B 24x
24
0.19 +0.06
8˚ MAX.
0.2
8˚ MAX.
0.65
1.75 MAX.
8˚ MAX.
C
3.9 ±0.11)
(1.47)
0.175 ±0.07
0.35 x 45˚
M
C
13
1
12
8.65 ±0.11)
A
Index Marking
1) Does not include plastic or metal protrusion of 0.15 max. per side
2) Does not include dambar protrusion of 0.13 max.
Figure 16
PG-SSOP-24-5, -6
PG-SSOP-24-5 (Plastic Green Shrink Small Outline Package)
Green Product (RoHS compliant)
To meet the world-wide customer requirements for environmentally friendly products and to be compliant with
government regulations the device is available as a green product. Green products are RoHS-Compliant (i.e
Pb-free finish on leads and suitable for Pb-free soldering according to IPC/JEDEC J-STD-020).
You can find all of our packages, sorts of packing and others in our
Infineon Internet Page “Products”: http://www.infineon.com/products.
Datasheet
30
Dimensions in mm
Rev. 1.0, 2008-02-28
SPI Driver for Enhanced Relay Control
SPIDER - TLE7233G
Revision History
12
Version
Rev. 1.0
Datasheet
Revision History
Date
Changes
2008-02-28
initial released Datasheet
31
Rev. 1.0, 2008-02-28
Edition 2008-02-28
Published by
Infineon Technologies AG
81726 Munich, Germany
© 2008 Infineon Technologies AG
All Rights Reserved.
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characteristics. With respect to any examples or hints given herein, any typical values stated herein and/or any
information regarding the application of the device, Infineon Technologies hereby disclaims any and all warranties
and liabilities of any kind, including without limitation, warranties of non-infringement of intellectual property rights
of any third party.
Information
For further information on technology, delivery terms and conditions and prices, please contact the nearest
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