µ
SLOS351D − MARCH 2001 − REVISED FEBRUARY 2004
D
D
D
D
D
D
D
D
D
D
Rail-To-Rail Output
Wide Bandwidth . . . 3 MHz
High Slew Rate . . . 2 .4 V/µs
Supply Voltage Range . . . 2.7 V to 16 V
Supply Current . . . 550 µA/Channel
Input Noise Voltage . . . 39 nV/√Hz
Input Bias Current . . . 1 pA
Specified Temperature Range
0°C to 70°C . . . Commercial Grade
−40°C to 125°C . . . Industrial Grade
Ultrasmall Packaging
− 5 Pin SOT-23 (TLV271)
− 8 Pin MSOP (TLV272)
Ideal Upgrade for TLC27x Family
Operational Amplifier
+
−
description
The TLV27x takes the minimum operating supply voltage down to 2.7 V over the extended industrial
temperature range while adding the rail-to-rail output swing feature. This makes it an ideal alternative to the
TLC27x family for applications where rail-to-rail output swings are essential. The TLV27x also provides 3-MHz
bandwidth from only 550 µA.
Like the TLC27x, the TLV27x is fully specified for 5-V and ±5-V supplies. The maximum recommended supply
voltage is 16 V, which allows the devices to be operated from a variety of rechargeable cells (±8 V supplies down
to ±1.35 V).
The CMOS inputs enable use in high-impedance sensor interfaces, with the lower voltage operation making
an attractive alternative for the TLC27x in battery-powered applications.
All members are available in PDIP and SOIC with the singles in the small SOT-23 package, duals in the MSOP,
and quads in the TSSOP package.
The 2.7-V operation makes it compatible with Li-Ion powered systems and the operating supply voltage range
of many micropower microcontrollers available today including TI’s MSP430.
SELECTION OF SIGNAL AMPLIFIER PRODUCTS†
VDD (V)
VIO
(µV)
Iq/Ch
(µA)
IIB (pA)
GBW
(MHz)
SR
(V/µs)
SHUTDOWN
RAILTORAIL
SINGLES/DUALS/QUADS
2.7−16
500
550
1
3
2.4
—
O
S/D/Q
TLC27x
3−16
1100
675
1
1.7
3.6
—
—
S/D/Q
TLV237x
2.7−16
500
550
1
3
2.4
Yes
I/O
S/D/Q
TLC227x
4−16
300
1100
1
2.2
3.6
—
O
D/Q
TLV246x
2.7−6
150
550
1300
6.4
1.6
Yes
I/O
S/D/Q
TLV247x
2.7−6
250
600
2
2.8
1.5
Yes
I/O
S/D/Q
TLV244x
2.7−10
300
† Typical values measured at 5 V, 25°C
725
1
1.8
1.4
—
O
D/Q
DEVICE
TLV27x
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright 2001−2004, Texas Instruments Incorporated
!"#$%&'#! ( )*$$+!' &( #" ,*-.)&'#! /&'+0
$#/*)'( )#!"#$% '# (,+)")&'#!( ,+$ '+ '+$%( #" +1&( !('$*%+!'(
('&!/&$/ 2&$$&!'30 $#/*)'#! ,$#)+((!4 /#+( !#' !+)+((&$.3 !).*/+
'+('!4 #" &.. ,&$&%+'+$(0
WWW.TI.COM
1
µ
SLOS351D − MARCH 2001 − REVISED FEBRUARY 2004
FAMILY PACKAGE TABLE
PACKAGE TYPES
NUMBER OF
CHANNELS
PDIP
SOIC
TLV271
1
8
TLV272
2
8
TLV274
4
14
DEVICE
SHUTDOWN
SOT-23
TSSOP
MSOP
8
5
—
—
—
8
—
—
8
—
14
—
14
—
—
UNIVERSAL
EVM BOARD
Refer to the EVM
Selection Guide
(Lit# SLOU060)
TLV271 AVAILABLE OPTIONS
PACKAGED DEVICES
VIOMAX AT
25°C
TA
0°C to 70°C
SOT-23
SMALL OUTLINE
(D)†
TLV271CD
(DBV)‡
TLV271CDBV
SYMBOL
PLASTIC DIP
(P)
VBHC
—
5 mV
−40°C to 125°C
TLV271ID
TLV271IDBV
VBHI
TLV271IP
† This package is available taped and reeled. To order this packaging option, add an R suffix to the part number (e.g., TLV271IDR).
‡ This package is only available taped and reeled. For standard quantities (3,000 pieces per reel), add an R suffix (e.g., TLV270IDBVR). For smaller
quantities (250 pieces per mini-reel), add a T suffix to the part number (e.g., TLV270IDBVT).
TLV272 AVAILABLE OPTIONS
PACKAGED DEVICES
VIOMAX AT
25°C
TA
0°C to 70°C
MSOP
SMALL OUTLINE
(D)§
(DGK)§
SYMBOL
PLASTIC DIP
(P)
TLV272CD
TLV272CDGK
AVF
—
5 mV
−40°C to 125°C
TLV272ID
TLV272IDGK
AVG
TLV272IP
§ This package is available taped and reeled. To order this packaging option, add an R suffix to the part number (e.g., TLV272IDR).
TLV274 AVAILABLE OPTIONS
PACKAGED DEVICES
TA
VIOMAX AT 25°C
SMALL OUTLINE
(D)¶
PLASTIC DIP
(N)
TSSOP
(PW)¶
TLV274CD
—
TLV274CPW
0°C to 70°C
5 mV
−40°C to 125°C
TLV274ID
TLV274IN
TLV274IPW
¶ This package is available taped and reeled. To order this packaging option, add an R suffix to the part number (e.g., TLV274IDR).
2
WWW.TI.COM
µ
SLOS351D − MARCH 2001 − REVISED FEBRUARY 2004
TLV27x PACKAGE PINOUTS(1)
TLV271
D OR P PACKAGE
(TOP VIEW)
TLV271
DBV PACKAGE
(TOP VIEW)
OUT
GND
IN+
1
5
VDD
NC
IN −
IN +
GND
2
3
4
IN −
1
8
2
7
3
6
4
5
VDD
2OUT
2IN −
2IN+
8
2
7
3
6
4
5
NC
VDD
OUT
NC
TLV274
D, N, OR PW PACKAGE
TLV272
D, DGK, OR P PACKAGE
(TOP VIEW)
1OUT
1IN −
1IN +
GND
1
(TOP VIEW)
1OUT
1IN −
1IN+
VDD
2IN+
2IN −
2OUT
1
14
2
13
3
12
4
11
5
10
6
9
7
8
4OUT
4IN −
4IN+
GND
3IN+
3IN −
3OUT
NC − No internal connection
(1) SOT−23 may or may not be indicated
TYPICAL PIN 1 INDICATORS
Pin 1
Printed or
Molded Dot
Pin 1
Stripe
Pin 1
Bevel Edges
WWW.TI.COM
Pin 1
Molded ”U” Shape
3
µ
SLOS351D − MARCH 2001 − REVISED FEBRUARY 2004
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†
Supply voltage, VDD (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16.5 V
Differential input voltage, VID . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± VDD
Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.2 V to VDD + 0.2 V
Input current range, II . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 10 mA
Output current range, IO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 100 mA
Continuous total power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Dissipation Rating Table
Operating free-air temperature range, TA: C suffix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 70°C
I suffix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −40°C to 125°C
Maximum junction temperature, TJ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150°C
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260°C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 1: All voltage values, except differential voltages, are with respect to GND.
DISSIPATION RATING TABLE
PACKAGE
θJC
(°C/W)
θJA
(°C/W)
TA ≤ 25°C
POWER RATING
TA = 25°C
POWER RATING
D (8)
38.3
176
710 mW
396 mW
D (14)
26.9
122.3
1022 mW
531 mW
D (16)
25.7
114.7
1090 mW
567 mW
DBV (5)
55
324.1
385 mW
201 mW
DBV (6)
55
294.3
425 mW
221 mW
DGK (8)
54.23
259.96
481 mW
250 mW
DGS (10)
54.1
257.71
485 mW
252 mW
N (14, 16)
32
78
1600 mW
833 mW
P (8)
41
104
1200 mW
625 mW
PW (14)
29.3
173.6
720 mW
374 mW
PW (16)
28.7
161.4
774 mW
403 mW
recommended operating conditions
Single supply
Supply voltage, VDD
Split supply
Common-mode input voltage range, VICR
C-suffix
Operating free-air temperature, TA
4
I-suffix
WWW.TI.COM
MIN
MAX
2.7
16
±1.35
±8
0
0
VDD−1.35
70
−40
125
UNIT
V
V
°C
µ
SLOS351D − MARCH 2001 − REVISED FEBRUARY 2004
electrical characteristics at specified free-air temperature, VDD = 2.7 V, 5 V, and ±5 V (unless
otherwise noted)
dc performance
PARAMETER
VIO
Input offset voltage
αVIO
Offset voltage drift
TEST CONDITIONS
VIC = VDD/2,
RL = 10 kkΩ,
kΩ,
VO = VDD/2,
RS = 50 Ω
VIC = 0 to VDD−1.35V,
RS = 50 Ω
CMRR
AVD
Common-mode rejection ratio
Large-signal differential voltage
amplification
VDD = 2.7 V
TA†
25°C
MIN
MAX
0.5
5
Full range
7
25°C
58
Full range
55
25°C
65
VDD = 5 V
Full range
62
VIC = −5 to VDD−1.35V,
RS = 50 Ω,
VDD = ±5 V
25°C
69
Full range
66
25°C
97
VDD = 2.7 V
Full range
76
25°C
100
VDD = 5 V
Full range
86
VDD = ±5 V
25°C
100
Full range
90
UNIT
mV
V/°C
µV/°C
2
25°C
VIC = 0 to VDD−1.35V,
RS = 50 Ω,
VO(PP) = VDD/2,
RL = 10 kkΩ
TYP
70
80
dB
85
106
110
dB
115
† Full range is 0°C to 70°C for C suffix and full range is − 40°C to 125°C for I suffix. If not specified, full range is − 40°C to 125°C.
input characteristics
PARAMETER
IIO
TEST CONDITIONS
Input offset current
VDD = 5 V,
VIC = VDD/2,
VO = VDD/2, RS = 50 Ω
IIB
Input bias current
ri(d)
Differential input resistance
CIC
Common-mode input capacitance
f = 21 kHz
WWW.TI.COM
TA
25°C
MIN
TYP
1
MAX
70°C
100
125°C
1000
25°C
1
UNIT
60
pA
60
70°C
100
125°C
1000
pA
25°C
1000
GΩ
25°C
8
pF
5
µ
SLOS351D − MARCH 2001 − REVISED FEBRUARY 2004
electrical characteristics at specified free-air temperature, VDD = 2.7 V, 5 V, and ±5 V (unless
otherwise noted)
output characteristics
PARAMETER
TEST CONDITIONS
VDD = 2.7 V
VIC = VDD/2, IOH = −1 mA
VOH
MIN
TYP
2.55
2.58
Full range
2.48
25°C
4.9
VDD = 5 V
Full range
4.85
VDD = ±5 V
25°C
4.92
Full range
4.9
25°C
1.9
Full range
1.5
25°C
4.6
Full range
4.5
High-level output voltage
VDD = 2.7 V
VIC = VDD/2, IOH = −5 mA
TA†
25°C
VDD = 5 V
VDD = ±5 V
25°C
4.7
Full range
4.65
VDD = 2.7 V
Full range
25°C
25°C
VIC = VDD/2, IOL = 1 mA
VDD = 5 V
VDD = ±5 V
VOL
Low-level output voltage
VDD = 2.7 V
Full range
VDD = 5 V
Full range
25°C
VIC = VDD/2, IOL = 5 mA
VO = 0.5 V from rail, VDD = 2.7 V
IO
Output current
VO = 0.5 V from rail, VDD = 5 V
VO = 0.5 V from rail, VDD = 10 V
4.96
25°C
V
2.1
4.68
4.84
0.1
0.15
0.22
0.05
0.1
−4.95
−4.92
0.15
Full range
25°C
−4.9
0.5
0.7
WWW.TI.COM
V
1.1
0.28
0.4
−4.84
−4.7
0.5
VDD = ±5 V
Full range
Positive rail
25°C
4
Negative rail
25°C
5
Positive rail
25°C
7
Negative rail
25°C
8
Positive rail
25°C
13
−4.65
Negative rail
25°C
12
† Full range is 0°C to 70°C for C suffix and full range is − 40°C to 125°C for I suffix. If not specified, full range is − 40°C to 125°C.
‡ Depending on package dissipation rating
6
UNIT
4.93
Full range
25°C
MAX
mA
µ
SLOS351D − MARCH 2001 − REVISED FEBRUARY 2004
electrical characteristics at specified free-air temperature, VDD = 2.7 V, 5 V, and ±5 V (unless
otherwise noted) (continued)
power supply
PARAMETER
IDD
TEST CONDITIONS
Supply current (per channel)
VDD = 2.7 V
VDD = 5 V
VO = VDD/2
VDD = 10 V
PSRR
Supply voltage rejection ratio
(∆VDD /∆VIO)
VDD = 2.7 V to 16 V,
No load
VIC = VDD /2,
TA†
25°C
MIN
TYP
MAX
470
560
25°C
550
660
25°C
625
800
Full range
UNIT
µA
1000
25°C
70
Full range
65
80
dB
† Full range is 0°C to 70°C for C suffix and full range is − 40°C to 125°C for I suffix. If not specified, full range is − 40°C to 125°C.
dynamic performance
PARAMETER
UGBW
Unity gain bandwidth
TA†
TEST CONDITIONS
RL = 2 kΩ,
kΩ
CL = 10 pF
2.4
VDD = 5 V to 10 V
25°C
3
25°C
φm
ts
Slew rate at unity gain
VO(PP) = VDD/2,
CL = 50 pF, RL = 10 kkΩ,,
TYP
25°C
VDD = 2.7 V
SR
MIN
VDD = 2.7 V
Full range
1.35
MAX
MHz
2.1
V/ s
V/µs
1
25°C
1.45
VDD = 5 V
Full range
1.2
VDD = ±5 V
25°C
1.8
Full range
1.3
UNIT
2.4
V/ s
V/µs
2.6
V/ s
V/µs
Phase margin
RL = 2 kΩ
CL = 10 pF
25°C
65
°
Gain margin
RL = 2 kΩ
CL = 10 pF
25°C
18
dB
Settling time
VDD = 2.7 V,
V(STEP)PP = 1 V,
CL = 10 pF,
VDD = 5 V, ±5 V,
V(STEP)PP = 1 V,
CL = 47 pF,
AV = −1,
RL = 2 kΩ
0.1%
2.9
µss
25°C
AV = −1,
0.1%
2
RL = 2 kΩ
† Full range is 0°C to 70°C for C suffix and full range is − 40°C to 125°C for I suffix. If not specified, full range is − 40°C to 125°C.
noise/distortion performance
PARAMETER
TEST CONDITIONS
VDD = 2.7 V,
VO(PP) = VDD/2 V,
RL = 2 kΩ,
k , f = 10 kHz
THD + N
Total harmonic distortion plus noise
VDD = 5 V, ±5 V,
VO(PP) = VDD/2 V,
RL = 2 kΩ,
k , f = 10K
AV = 1
AV = 10
TA
Equivalent input noise voltage
In
Equivalent input noise current
MAX
UNIT
0.05%
0.18%
0.02%
25°C
25
C
0.09%
0.50%
f = 1 kHz
Vn
TYP
0.02%
25°C
25
C
AV = 100
AV = 1
AV = 10
AV = 100
MIN
39
25°C
f = 10 kHz
f = 1 kHz
25°C
WWW.TI.COM
35
0.6
nV/√Hz
fA /√Hz
7
µ
SLOS351D − MARCH 2001 − REVISED FEBRUARY 2004
TYPICAL CHARACTERISTICS
Table of Graphs
FIGURE
CMRR
Common-mode rejection ratio
vs Frequency
Input bias and offset current
vs Free-air temperature
1
VOL
VOH
Low-level output voltage
vs Low-level output current
3, 5, 7
High-level output voltage
vs High-level output current
4, 6, 8
VO(PP)
IDD
Peak-to-peak output voltage
vs Frequency
9
Supply current
vs Supply voltage
10
PSRR
Power supply rejection ratio
vs Frequency
11
AVD
Differential voltage gain & phase
vs Frequency
12
Gain-bandwidth product
vs Free-air temperature
13
vs Supply voltage
14
2
SR
Slew rate
vs Free-air temperature
15
φm
Vn
Phase margin
vs Capacitive load
16
Equivalent input noise voltage
vs Frequency
17
Voltage-follower large-signal pulse response
18, 19
Voltage-follower small-signal pulse response
20
Inverting large-signal response
21, 22
Inverting small-signal response
23
Crosstalk
8
vs Frequency
WWW.TI.COM
24
µ
SLOS351D − MARCH 2001 − REVISED FEBRUARY 2004
TYPICAL CHARACTERISTICS
100
VDD = 5 V, 10 V
80
60
VDD = 2.7 V
40
20
0
10
100
1k
100 k
10 k
1M
250
VDD = 2.7 V, 5 V and 10 V
VIC = VDD/2
200
150
100
50
0
−40 −25 −10 5
TA =−40°C
TA = 125°C
TA = 70°C
TA = 25°C
0.80
TA = 0°C
0.40
TA = 125 °C
4.00
TA = 70 °C
3.50
3.00
2.50
TA = 25 °C
2.00
1.50
TA = 0 °C
1.00
TA = −40 °C
0.50
1 2 3 4 5 6 7 8 9 10 11 12
IOH − High-Level Output Current − mA
8
TA =70°C
TA =25°C
TA =0°C
TA =−40°C
2
80
100
IOL − Low-Level Output Current − mA
Figure 7
3.00
2.50
TA = 25°C
2.00
1.50
TA = 70°C
1.00
TA = 125°C
0.50
5
10
10
VDD = 10 V
8
TA = −40°C
6
TA = 0°C
4
TA = 25°C
2
120
TA = 70°C
TA = 125°C
0
20
40
60
80
100
IOH − High-Level Output Current − mA
Figure 8
WWW.TI.COM
15
20
25
30
35
40
45
IOH − High-Level Output Current − mA
Figure 6
0
0
60
TA = 0°C
3.50
0
PEAK-TO-PEAK OUTPUT VOLTAGE
vs
FREQUENCY
V O(PP) − Peak-to-Peak Output Voltage − V
TA =125°C
40
TA = −40°C
4.00
0 5 10 15 20 25 30 35 40 45 50 55 60 65 70
IOL − Low-Level Output Current − mA
HIGH-LEVEL OUTPUT VOLTAGE
vs
HIGH-LEVEL OUTPUT CURRENT
V OH − High-Level Output Voltage − V
VOL − Low-Level Output Voltage − V
VDD = 10 V
20
VCC = 5 V
4.50
Figure 5
10
0
2 4 6 8 10 12 14 16 18 20 22 24
IOL − Low-Level Output Current − mA
0.00
Figure 4
LOW-LEVEL OUTPUT VOLTAGE
vs
LOW-LEVEL OUTPUT CURRENT
TA = 0 °C
TA = 40 °C
5.00
VDD = 5 V
4.50
0.00
4
0.40
HIGH-LEVEL OUTPUT VOLTAGE
vs
HIGH-LEVEL OUTPUT CURRENT
V OH − High-Level Output Voltage − V
VOL − Low-Level Output Voltage − V
V OH − High-Level Output Voltage − V
2.40
6
TA = 70 °C
TA = 25 °C
0.80
Figure 3
5.00
VDD = 2.7 V
0
1.20
0
20 35 50 65 80 95 110 125
LOW-LEVEL OUTPUT VOLTAGE
vs
LOW-LEVEL OUTPUT CURRENT
2.80
1.20
1.60
Figure 2
HIGH-LEVEL OUTPUT VOLTAGE
vs
HIGH-LEVEL OUTPUT CURRENT
1.60
2.00
TA − Free-Air Temperature − °C
Figure 1
2.00
VDD = 2.7 V
2.40 T = 125 °C
A
0.00
−50
f − Frequency − Hz
0.00
2.80
300
VOL − Low-Level Output Voltage − V
120
LOW-LEVEL OUTPUT VOLTAGE
vs
LOW-LEVEL OUTPUT CURRENT
INPUT BIAS AND OFFSET CURRENT
vs
FREE-AIR TEMPERATURE
I IB I IO − Input Bias and Offset Current − pA
CMRR − Common-Mode Rejection Ratio − dB
COMMON-MODE REJECTION RATIO
vs
FREQUENCY
120
11
VDD = 10 V
10
9
8
7
6
AV = −10
RL = 2 kΩ
CL = 10 pF
TA = 25°C
THD = 5%
5
VDD = 5 V
4
3
2
VDD = 2.7 V
1
0
10
100
1k
10 k
100 k
1M
10 M
f − Frequency − Hz
Figure 9
9
µ
SLOS351D − MARCH 2001 − REVISED FEBRUARY 2004
TYPICAL CHARACTERISTICS
POWER SUPPLY REJECTION RATIO
vs
FREQUENCY
SUPPLY CURRENT
vs
SUPPLY VOLTAGE
AV = 1
VIC = VDD / 2
I DD − Supply Current − mA/ch
0.9
PSRR − Power Supply Rejection Ratio − dB
1.0
TA = 125°C
0.8
TA = 70°C
0.7
0.6
0.5
0.4
TA = 25°C
0.3
TA = 0°C
0.2
TA = −40°C
0.1
0.0
120
TA = 25°C
100
VDD = 5 V, 10 V
80
VDD = 2.7 V
60
40
20
0
10
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
VDD − Supply Voltage − V
100
1k
DIFFERENTIAL VOLTAGE GAIN AND PHASE
vs
FREQUENCY
90
45
60
0
Gain
−45
20
−90
VDD=5 V
RL=2 kΩ
CL=10 pF
TA=25°C
−20
−40
10
100
−135
1k
10 k
100 k 1 M
−180
10 M
GBWP −Gain Bandwidth Product − MHz
Phase
Phase − °
AVD − Differential Voltage Gain − dB
4.0
135
100
0
3.5
VDD = 10 V
3.0
2.5
2.0
VDD = 5 V
VDD = 2.7 V
1.5
1.0
0.5
0.0
−40 −25 −10 5
Figure 13
Figure 12
SLEW RATE
vs
FREE-AIR TEMPERATURE
3.5
3.0
SR+
1.0
AV = 1
RL = 10 kΩ
CL = 50 pF
TA = 25°C
0.5
2.5
4.5
6.5
8.5
10.5
12.5
VCC − Supply Voltage −V
Figure 14
10
14.5
80
SR−
2.5
2.0
SR+
1.5
VDD = 5 V
AV = 1
RL = 10 kΩ
CL = 50 pF
VI = 3 V
1.0
0.5
0.0
VDD = 5 V
RL= 2 kΩ
TA = 25°C
AV = Open Loop
90
0.0
−40 −25 −10 5
20 35 50 65 80 95 110 125
TA − Free-Air Temperature − °C
Figure 15
WWW.TI.COM
Phase Margin − °
2.0
PHASE MARGIN
vs
CAPACITIVE LOAD
100
3.0
2.5
SR − Slew Rate − V/ µ s
SR − Slew Rate − V/ µ s
SR−
1.5
20 35 50 65 80 95 110 125
TA − Free-Air Temperature − °C
f − Frequency − Hz
SLEW RATE
vs
SUPPLY VOLTAGE
1M
GAIN BANDWIDTH PRODUCT
vs
FREE-AIR TEMPERATURE
180
120
40
100 k
Figure 11
Figure 10
80
10 k
f − Frequency − Hz
70
Rnull = 100
60
50
40
Rnull = 0
30
Rnull = 50
20
10
0
10
100
CL − Capacitive Load − pF
Figure 16
1000
µ
SLOS351D − MARCH 2001 − REVISED FEBRUARY 2004
TYPICAL CHARACTERISTICS
VOLTAGE-FOLLOWER LARGE-SIGNAL
PULSE RESPONSE
VDD = 2.7, 5, 10 V
TA = 25°C
90
4
80
70
60
50
3
2
1
VDD = 5 V
AV = 1
RL = 2 kΩ
CL = 10 pF
VI = 3 VPP
TA = 25°C
VI
0
40
3
30
2
20
1
VO
10
0
0
100
1k
10 k
f − Frequency − Hz
0
100 k
2
6
4
2
VO
0
0
2
4
6
8
0.12
0.08
VDD = 5 V
AV = 1
RL = 2 kΩ
CL = 10 pF
VI = 100 mVPP
TA = 25°C
0.04
VI
0.00
0.04
VO
0.00
0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8
10 12 14 16 18
t − Time − µs
Figure 20
Figure 19
INVERTING LARGE-SIGNAL RESPONSE
INVERTING LARGE-SIGNAL RESPONSE
V I − Input Voltage − V
4
VDD = 5 V
AV = 1
RL = 2 kΩ
CL = 10 pF
VI = 3 VPP
TA = 25°C
1
0
3
2
1
0
VO
0
2
4
6
8
10
12
14
V − Output Voltage − V
O
VI
2
0.12
0.08
t − Time − µs
3
10 12 14 16 18
V − Output Voltage − mV
O
0
V − Output Voltage − V
O
VDD = 10 V
AV = 1
RL = 2 kΩ
CL = 10 pF
VI = 6 VPP
TA = 25°C
V − Input Voltage − mV
I
V − Input Voltage − V
I
6
VI
8
VOLTAGE-FOLLOWER SMALL-SIGNAL
PULSE RESPONSE
8
2
6
Figure 18
VOLTAGE-FOLLOWER LARGE-SIGNAL
PULSE RESPONSE
4
4
t − Time − µs
8
6
VDD = 10 V
AV = VI = −1
RL = 2 kΩ
CL = 10 pF
TA = 25°C
4
2
0
VI
6
VO
4
2
0
16
0
t − Time − µs
2
4
6
8
10
t − Time − µs
12
14
V O − Output Voltage − V
10
Figure 17
V − Input Voltage − V
I
V − Output Voltage − V
O
100
V − Input Voltage − V
I
V n − Equivalent Input Noise Voltage − nV/
Hz
EQUIVALENT INPUT NOISE VOLTAGE
vs
FREQUENCY
16
Figure 22
Figure 21
WWW.TI.COM
11
µ
SLOS351D − MARCH 2001 − REVISED FEBRUARY 2004
TYPICAL CHARACTERISTICS
CROSSTALK
vs
FREQUENCY
0
0.00
VDD = 5 V
AV = VI = −1
RL = 2 kΩ
CL = 10 pF
VI = 100 mVpp
TA = 25°C
−40
VI
0.10
VO
0.05
0.00
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5
Crosstalk − dB
0.05
VDD = 2.7, 5, & 15 V
VI = 1 VDD/2
AV = 1
RL = 2 kΩ
TA = 25°C
−20
0.10
V O − Output Voltage − V
V I − Input Voltage − V
INVERTING SMALL-SIGNAL RESPONSE
−60
−80
−100
Crosstalk
−120
−140
10
100
1k
10 k
f − Frequency − Hz
t − Time − µs
100 k
Figure 24
Figure 23
APPLICATION INFORMATION
driving a capacitive load
When the amplifier is configured in this manner, capacitive loading directly on the output decreases the device’s
phase margin leading to high frequency ringing or oscillations. Therefore, for capacitive loads of greater than
10 pF, it is recommended that a resistor be placed in series (RNULL) with the output of the amplifier, as shown
in Figure 25. A minimum value of 20 Ω should work well for most applications.
RF
RG
−
Input
RNULL
Output
+
CLOAD
VDD/2
Figure 25. Driving a Capacitive Load
12
WWW.TI.COM
µ
SLOS351D − MARCH 2001 − REVISED FEBRUARY 2004
APPLICATION INFORMATION
offset voltage
The output offset voltage, (VOO) is the sum of the input offset voltage (VIO) and both input bias currents (IIB) times
the corresponding gains. The following schematic and formula can be used to calculate the output offset
voltage:
RF
RG
IIB−
+
−
VI
RS
V
VO
+
OO
+V
IO
ǒ ǒ ǓǓ
R
1)
R
F
"I
G
IB)
R
S
ǒ ǒ ǓǓ
1)
R
R
F
G
"I
IB–
R
F
IIB+
Figure 26. Output Offset Voltage Model
general configurations
When receiving low-level signals, limiting the bandwidth of the incoming signals into the system is often
required. The simplest way to accomplish this is to place an RC filter at the noninverting terminal of the amplifier
(see Figure 27).
RG
RF
O +
V
I
VDD/2
VI
V
ǒ
1)
R
R
F
G
Ǔǒ
Ǔ
1
1 ) sR1C1
−
VO
+
R1
f
–3dB
+
1
2pR1C1
C1
Figure 27. Single-Pole Low-Pass Filter
If even more attenuation is needed, a multiple pole filter is required. The Sallen-Key filter can be used for this
task. For best results, the amplifier should have a bandwidth that is 8 to 10 times the filter frequency bandwidth.
Failure to do this can result in phase shift of the amplifier.
C1
+
_
VI
R1
R1 = R2 = R
C1 = C2 = C
Q = Peaking Factor
(Butterworth Q = 0.707)
R2
f
C2
RG
RF
–3dB
RG =
+
(
1
2pRC
RF
1
2−
Q
)
VDD/2
Figure 28. 2-Pole Low-Pass Sallen-Key Filter
WWW.TI.COM
13
µ
SLOS351D − MARCH 2001 − REVISED FEBRUARY 2004
APPLICATION INFORMATION
circuit layout considerations
To achieve the levels of high performance of the TLV27x, follow proper printed-circuit board design techniques.
A general set of guidelines is given in the following.
D Ground planes—It is highly recommended that a ground plane be used on the board to provide all
components with a low inductive ground connection. However, in the areas of the amplifier inputs and
output, the ground plane can be removed to minimize the stray capacitance.
D Proper power supply decoupling—Use a 6.8-µF tantalum capacitor in parallel with a 0.1-µF ceramic
capacitor on each supply terminal. It may be possible to share the tantalum among several amplifiers
depending on the application, but a 0.1-µF ceramic capacitor should always be used on the supply terminal
of every amplifier. In addition, the 0.1-µF capacitor should be placed as close as possible to the supply
terminal. As this distance increases, the inductance in the connecting trace makes the capacitor less
effective. The designer should strive for distances of less than 0.1 inches between the device power
terminals and the ceramic capacitors.
D Sockets—Sockets can be used but are not recommended. The additional lead inductance in the socket pins
will often lead to stability problems. Surface-mount packages soldered directly to the printed-circuit board
is the best implementation.
D Short trace runs/compact part placements—Optimum high performance is achieved when stray series
inductance has been minimized. To realize this, the circuit layout should be made as compact as possible,
thereby minimizing the length of all trace runs. Particular attention should be paid to the inverting input of
the amplifier. Its length should be kept as short as possible. This helps to minimize stray capacitance at the
input of the amplifier.
D Surface-mount passive components—Using surface-mount passive components is recommended for high
performance amplifier circuits for several reasons. First, because of the extremely low lead inductance of
surface-mount components, the problem with stray series inductance is greatly reduced. Second, the small
size of surface-mount components naturally leads to a more compact layout thereby minimizing both stray
inductance and capacitance. If leaded components are used, it is recommended that the lead lengths be
kept as short as possible.
14
WWW.TI.COM
µ
SLOS351D − MARCH 2001 − REVISED FEBRUARY 2004
APPLICATION INFORMATION
general power dissipation considerations
For a given θJA, the maximum power dissipation is shown in Figure 29 and is calculated by the following formula:
P
D
+
Where:
ǒ
T
Ǔ
–T
MAX A
q
JA
PD = Maximum power dissipation of TLV27x IC (watts)
TMAX = Absolute maximum junction temperature (150°C)
TA
= Free-ambient air temperature (°C)
θJA = θJC + θCA
θJC = Thermal coefficient from junction to case
θCA = Thermal coefficient from case to ambient air (°C/W)
MAXIMUM POWER DISSIPATION
vs
FREE-AIR TEMPERATURE
2
Maximum Power Dissipation − W
1.75
1.5
1.25
TJ = 150°C
PDIP Package
Low-K Test PCB
θJA = 104°C/W
SOIC Package
Low-K Test PCB
θJA = 176°C/W
MSOP Package
Low-K Test PCB
θJA = 260°C/W
1
0.75
0.5
0.25
SOT-23 Package
Low-K Test PCB
θJA = 324°C/W
0
−55 −40 −25 −10 5
20 35 50 65 80 95 110 125
TA − Free-Air Temperature − °C
NOTE A: Results are with no air flow and using JEDEC Standard Low-K test PCB.
Figure 29. Maximum Power Dissipation vs Free-Air Temperature
WWW.TI.COM
15
µ
SLOS351D − MARCH 2001 − REVISED FEBRUARY 2004
APPLICATION INFORMATION
macromodel information
Macromodel information provided was derived using Microsim Parts Release 9.1, the model generation
software used with Microsim PSpice . The Boyle macromodel (see Note 4) and subcircuit in Figure 30 are
generated using TLV27x typical electrical and operating characteristics at TA = 25°C. Using this information,
output simulations of the following key parameters can be generated to a tolerance of 20% (in most cases):
D Maximum positive output voltage swing
D Unity-gain frequency
D Maximum negative output voltage swing
D Common-mode rejection ratio
D Slew rate
D Phase margin
D Quiescent power dissipation
D DC output resistance
D Input bias current
D AC output resistance
D Open-loop voltage amplification
D Short-circuit output current limit
NOTE 2: G. R. Boyle, B. M. Cohn, D. O. Pederson, and J. E. Solomon, “Macromodeling of Integrated Circuit Operational Amplifiers,” IEEE Journal
of Solid-State Circuits, SC-9, 353 (1974).
3
99
VDD
+
egnd
rd1
rd2
rss
ro2
css
fb
rp
−
c1
7
11
12
+
c2
vlim
1
r2
+
9
6
IN+
−
vc
D
D
8
+
−
vb
ga
2
G
G
−
IN−
ro1
gcm
ioff
53
S
S
OUT
dp
91
10
iss
GND
4
+
dc
−
dlp
ve
+ 54
vlp
−
+
hlim
−
5
92
−
vln
+
de
*DEVICE=amp_tlv27x_highVdd,OP AMP,NJF,INT
* amp_tlv_27x_highVdd operational amplifier ”macromodel”
* subcircuit updated using Model Editor release 9.1 on 05/15/00
* at 14:40 Model Editor is an OrCAD product.
*
* connections:
non-inverting input
*
| inverting input
*
| | positive power supply
*
| | | negative power supply
*
| | | | output
*
| | | | |
.subckt amp_tlv27x_highVdd 1 2 3 4 5
*
c1
11
12 457.48E−15
c2
6
7
5.0000E−12
css
10
99 1.1431E−12
dc
5
53 dy
de
54
5
dy
dlp
90
91 dx
dln
92
90 dx
dp
4
3
dx
egnd
99
0
poly(2) (3,0) (4,0) 0 .5 .5
fb
7
99 poly(5) vb vc ve vlp vln 0
176.02E6 −1E3 1E3 180E6
−180E6
ga
gcm
iss
hlim
j1
J2
r2
rd1
rd2
ro1
ro2
rp
rss
vb
vc
ve
vlim
vlp
vln
.model
.model
.model
.model
.ends
6
0
10
90
11
12
6
3
3
8
7
3
10
9
3
54
7
91
0
dx
dy
jx1
jx2
0
11 12 16.272E−6
6
10 99 6.8698E−9
4
dc 1.3371E−6
0
vlim 1K
2
10 jx1
1
10 jx2
9
100.00E3
11
61.456E3
12
61.456E3
5
10
99
10
4
150.51E3
99
149.58E6
0
dc 0
53
dc .78905
4
dc .78905
8
dc 0
0
dc 14.200
92
dc 14.200
D(Is=800.00E−18)
D(Is=800.00E−18 Rs=1m Cjo=10p)
NJF(Is=500.00E−15 Beta=198.03E−6 Vto=−1)
NJF(Is=500.00E−15 Beta=198.03E−6 Vto=−1)
Figure 30. Boyle Macromodel and Subcircuit
PSpice and Parts are trademarks of MicroSim Corporation.
16
90
dln
WWW.TI.COM
IMPORTANT NOTICE
Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications,
enhancements, improvements, and other changes to its products and services at any time and to discontinue
any product or service without notice. Customers should obtain the latest relevant information before placing
orders and should verify that such information is current and complete. All products are sold subject to TI’s terms
and conditions of sale supplied at the time of order acknowledgment.
TI warrants performance of its hardware products to the specifications applicable at the time of sale in
accordance with TI’s standard warranty. Testing and other quality control techniques are used to the extent TI
deems necessary to support this warranty. Except where mandated by government requirements, testing of all
parameters of each product is not necessarily performed.
TI assumes no liability for applications assistance or customer product design. Customers are responsible for
their products and applications using TI components. To minimize the risks associated with customer products
and applications, customers should provide adequate design and operating safeguards.
TI does not warrant or represent that any license, either express or implied, is granted under any TI patent right,
copyright, mask work right, or other TI intellectual property right relating to any combination, machine, or process
in which TI products or services are used. Information published by TI regarding third-party products or services
does not constitute a license from TI to use such products or services or a warranty or endorsement thereof.
Use of such information may require a license from a third party under the patents or other intellectual property
of the third party, or a license from TI under the patents or other intellectual property of TI.
Reproduction of information in TI data books or data sheets is permissible only if reproduction is without
alteration and is accompanied by all associated warranties, conditions, limitations, and notices. Reproduction
of this information with alteration is an unfair and deceptive business practice. TI is not responsible or liable for
such altered documentation.
Resale of TI products or services with statements different from or beyond the parameters stated by TI for that
product or service voids all express and any implied warranties for the associated TI product or service and
is an unfair and deceptive business practice. TI is not responsible or liable for any such statements.
Following are URLs where you can obtain information on other Texas Instruments products and application
solutions:
Products
Applications
Amplifiers
amplifier.ti.com
Audio
www.ti.com/audio
Data Converters
dataconverter.ti.com
Automotive
www.ti.com/automotive
DSP
dsp.ti.com
Broadband
www.ti.com/broadband
Interface
interface.ti.com
Digital Control
www.ti.com/digitalcontrol
Logic
logic.ti.com
Military
www.ti.com/military
Power Mgmt
power.ti.com
Optical Networking
www.ti.com/opticalnetwork
Microcontrollers
microcontroller.ti.com
Security
www.ti.com/security
Telephony
www.ti.com/telephony
Video & Imaging
www.ti.com/video
Wireless
www.ti.com/wireless
Mailing Address:
Texas Instruments
Post Office Box 655303 Dallas, Texas 75265
Copyright 2004, Texas Instruments Incorporated