TI TLV2402-Q1

TLV2401-Q1 , TLV2402-Q1, TLV2404-Q1
SLOS716 – APRIL 2011
www.ti.com
FAMILY OF 880-nA/Ch RAIL-TO-RAIL INPUT/OUTPUT OPERATIONAL AMPLIFIERS WITH
REVERSE BATTERY PROTECTION
Check for Samples: TLV2401-Q1 , TLV2402-Q1, TLV2404-Q1
FEATURES
1
•
•
•
•
•
•
•
•
•
•
Qualified for Automotive Applications
Micro-Power Operation . . . <1 µA/Channel
Input Common-Mode Range Exceeds the
Rails . . . –0.1 V to VCC + 5 V
Reverse Battery Protection Up To 18 V
Rail-to-Rail Input/Output
Gain Bandwidth Product . . . 5.5 kHz
Supply Voltage Range . . . 2.5 V to 16 V
Specified Temperature Range: –40°C to 125°C
Ultrasmall Packaging
– 5-Pin SOT-23 (TLV2401-Q1)
– 8-Pin MSOP (TLV2402-Q1)
Universal OpAmp EVM (Refer to the EVM
Selection Guide SLOU060)
Operational Amplifier
DESCRIPTION/ORDERING INFORMATION
The TLV240x family of single-supply operational
amplifiers has the lowest supply current available
today at only 880 nA per channel. Reverse battery
protection guards the amplifier from an overcurrent
condition due to improper battery installation. For
harsh environments, the inputs can be taken 5 V
above the positive supply rail without damage to the
device.
The low supply current is coupled with extremely low
input bias currents enabling them to be used with
mega-W resistors making them ideal for portable,
long active life, applications. DC accuracy is ensured
with a low typical offset voltage as low as 390 µV,
CMRR of 120 dB and minimum open loop gain of 130
V/mV at 2.7 V.
The maximum recommended supply voltage is as
high as 16 V and ensured operation down to 2.5 V,
with electrical characteristics specified at 2.7 V, 5 V
and 15 V. The 2.5-V operation makes it compatible
with Li-Ion battery-powered systems and many
micro-power
microcontrollers
available
today
including TI’s MSP430.
All members are available in PDIP and SOIC with the
singles in the small SOT-23 package, duals in the
MSOP, and quads in TSSOP.
SUPPLY CURRENT
vs
SUPPLY VOLTAGE
1.4
AV = 1
VIN = VCC / 2
TA = 25 °C
Supply Current, ICC (mA/Ch)
1.2
1.0
0.8
0.6
0.4
0.2
0
0
2
4
6
8
10 12
Supply Voltage, VCC (V)
14
16
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2011, Texas Instruments Incorporated
TLV2401-Q1 , TLV2402-Q1, TLV2404-Q1
SLOS716 – APRIL 2011
www.ti.com
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
SELECTION OF SINGLE SUPPLY OPERATIONAL AMPLIFIER PRODUCTS (1) (2)
DEVICE
VCC
(V)
VIO
(mV)
BW
(MHz)
SLEW
RATE
(V/µs)
ICC/ch
(µA)
RAIL-TO-RAIL
TLV240x-Q1 (2)
2.5–16
0.390
0.005
0.002
0.880
I/O
(1)
(2)
All specifications are typical values measured at 5 V.
This device also offers 18-V reverse battery protection and 5-V over-the-rail operation on the inputs.
DEVICE INFORMATION
TLV2401-Q1
DBV PACKAGE
(TOP VIEW)
1
OUT
GND
TLV2401-Q1
D PACKAGE
(TOP VIEW)
VCC
5
2
3
IN+
4
NC
IN–
IN+
GND
1
8
2
7
3
6
4
5
8
2
7
3
6
4
5
NC
VCC
OUT
NC
IN–
TLV2402-Q1
D OR DGK PACKAGE
(TOP VIEW)
1OUT
1IN–
1IN+
GND
1
TLV2404-Q1
D OR PW PACKAGE
(TOP VIEW)
VCC
2OUT
2IN–
2IN+
1OUT
1IN–
1IN+
VCC
2IN+
2IN–
2OUT
1
14
2
13
3
12
4
11
5
10
6
9
7
8
4OUT
4IN–
4IN+
GND
3IN+
3IN–
3OUT
NC – No internal connection
ORDERING INFORMATION (1)
PACKAGE (2)
TA
MSOP – DGK
Reel of 2500
SOIC – D
Reel of 2500
ORDERABLE PART NUMBER
TLV2402QDGKRQ1
TOP-SIDE MARKING
QWX
TLV2401QDRQ1
–40°C to 125°C
(1)
(2)
2
TLV2402QDRQ1
Product Preview
TLV2404QDRQ1
SOT – DBV
Reel of 3000
TLV2401QDBVRQ1
Product Preview
TSSOP – PW
Reel of 2000
TLV2404QPWRQ1
Product Preview
For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
web site at www.ti.com.
Package drawings, thermal data, and symbolization are available at www.ti.com/packaging.
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Copyright © 2011, Texas Instruments Incorporated
Product Folder Link(s): TLV2401-Q1 TLV2402-Q1 TLV2404-Q1
TLV2401-Q1 , TLV2402-Q1, TLV2404-Q1
SLOS716 – APRIL 2011
www.ti.com
ABSOLUTE MAXIMUM RATINGS (1)
over operating free-air temperature range (unless otherwise noted)
MIN
(2)
MAX
17
UNIT
VCC
Supply voltage
VID
Differential input voltage range
±20
V
II
Input current range (any input)
±10
mA
IO
Output current range
±10
mA
See Dissipation Ratings
Table
Continuous total power dissipation
TA
Operating free-air temperature range
TJ
Operating virtual junction temperature
Tstg
Storage temperature range
ESD
–40
–60
Electrostatic discharge (3)
°C
150
°C
125
°C
500
Machine Model (MM)
200
Field_Induced_Charged Device Model (CDM)
(2)
(3)
125
Human-Body Model (HBM)
V
1000
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds
(1)
V
260
°C
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
All voltage values, except differential voltages, are with respect to GND.
Tested in accordance with AEC-Q100.
DISSIPATION RATINGS
PACKAGE
QJC
(°C/W)
QJA
(°C/W)
TA ≤ 25°C
POWER RATING
TA = 125°C
POWER RATING
D (8)
38.3
176
710 mW
142 mW
D (14)
26.9
122.6
1022 mW
204.4 mW
DBV (5)
55
324.1
385 mW
77.1 mW
DGK (8)
54.2
259.9
481 mW
96.2 mW
PW (14)
29.3
173.6
720 mW
144 mW
RECOMMENDED OPERATING CONDITIONS
Single supply
MIN
MAX
2.5
16
±1.25
±8
UNIT
VCC
Supply voltage
VICR
Common-mode input voltage range
–0.1
VCC+5
V
TA
Operating free-air temperature
–40
125
°C
Split supply
Copyright © 2011, Texas Instruments Incorporated
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V
3
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SLOS716 – APRIL 2011
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ELECTRICAL CHARACTERISTICS
DC Performance
VCC = 2.7 V, 5 V, and 15 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
TA
MIN
TYP
MAX
390
1900
UNIT
DC Performance
25°C
VIO
Input offset voltage
αVIO
Offset voltage draft
VO = VCC/2 V, VIC = VCC/2 V, RS = 50 Ω
Common mode rejection ratio
VIC = 0 to VCC,
RS = 50 Ω
VCC = 5 V
VCC = 15 V
VCC = 2.7 V, VO(pp) = 1 V, RL = 500 kΩ
AVD
2800
25°C
VCC = 2.7 V
CMRR
Full
range
Large-signal differential
voltage amplification
VCC = 5 V, VO(pp) = 3 V, RL = 500 kΩ
VCC = 15 V, VO(pp) = 6 V, RL = 500 kΩ
µV/°C
3
25°C
60
Full
range
56
25°C
65
Full
range
58
25°C
73
Full
range
73
25°C
130
Full
range
12
25°C
300
Full
range
37
25°C
1000
Full
range
66
µV
120
120
dB
120
400
1000
V/mV
1800
Input Characteristics
25°C
IIO
Input offset current
VO = VCC/2 V, VIC = VCC/2 V, RS = 50 Ω
IIB
Input bias current
ri(d)
Differential input resistance
Ci(c)
Common-mode input
capacitance
4
25
Full
range
25°C
400
100
Full
range
25°C
f = 100 kHz
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25°C
250
pA
300
900
pA
300
MΩ
3
pF
Copyright © 2011, Texas Instruments Incorporated
Product Folder Link(s): TLV2401-Q1 TLV2402-Q1 TLV2404-Q1
TLV2401-Q1 , TLV2402-Q1, TLV2404-Q1
SLOS716 – APRIL 2011
www.ti.com
ELECTRICAL CHARACTERISTICS
DC Performance (continued)
VCC = 2.7 V, 5 V, and 15 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
TA
MIN
TYP
25°C
2.65
2.68
Full
range
2.63
25°C
4.95
Full
range
4.93
25°C
14.95
Full
range
14.93
25°C
2.62
Full
range
2.6
25°C
4.92
Full
range
4.9
25°C
14.92
Full
range
14.9
MAX
UNIT
Output Characteristics
VCC =2.7 V
VIC = VCC/2,
IOH = –2 µA
VCC = 5 V
VCC = 15 V
VOH
High-level output voltage
VCC = 2.7 V
VIC = VCC/2,
IOH = –50 µA
VCC = 5 V
VCC = 15 V
25°C
VIC = VCC/2, IOL = 2 µA
VOL
IO
14.98
V
2.65
4.95
14.95
90
Full
range
Low-level output voltage
150
180
25°C
Output current
4.98
180
VIC = VCC/2, IOL = 50 µA
Full
range
VO = 0.5 V from rail
25°C
±200
25°C
880
230
mV
260
µA
Power Supply
VCC =2.7 V or 5 V
ICC
Supply current (per channel)
VO = VCC/2
VCC = 2.7 V or 5 V, VIC = VCC/2, No load
PSRR
900
Full
range
VCC = –18 V, VIN = 0 V, VO = Open circuit
Power supply rejection ratio
(ΔVCC/ΔVIO)
990
1300
25°C
VCC = 15 V
Reverse supply current
Full
range
1050
nA
1400
25°C
50
25°C
100
Full
range
83
nA
120
dB
25°C
100
VCC = 5 to 15 V, VIC = VCC/2, No load
Full
range
97
120
RL = 500 kΩ, CL = 100 pF
25°C
5.5
kHz
25°C
2.5
V/ms
dB
Dynamic Performance
UGBW
Unity gain bandwidth
SR
Slew rate at unity gain
φM
Phase margin
Gain margin
tS
Settling time
RL = 500 kΩ, CL = 100 pF
VCC = 2.7 V or 5 V,
V(STEP)PP = 1 V,
AV = –1,
CL = 100 pF
RL = 100 kΩ
VCC = 15 V,
V(STEP)PP = 1 V,
AV = –1,
CL = 100 pF
RL = 100 kΩ
Copyright © 2011, Texas Instruments Incorporated
25°C
60°
15
dB
1.84
0.1%
0.1%
25°C
6.1
ms
32
0.01%
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SLOS716 – APRIL 2011
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ELECTRICAL CHARACTERISTICS
DC Performance (continued)
VCC = 2.7 V, 5 V, and 15 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
TA
MIN
TYP
MAX
UNIT
Noise/Distortion Performance
Vn
Equivalent input noise voltage
In
Equivalent input noise current
6
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f = 10 Hz
f = 100 Hz
800
25°C
f = 100 Hz
500
8
nV/√Hz
fA/√Hz
Copyright © 2011, Texas Instruments Incorporated
Product Folder Link(s): TLV2401-Q1 TLV2402-Q1 TLV2404-Q1
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SLOS716 – APRIL 2011
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TYPICAL CHARACTERISTICS
Table of Graphs
FIGURE
VIO
IIB
IIO
Input Offset Voltage
Input Bias Current
Input Offset Current
vs Common-mode input voltage
Figure 1, Figure 2, Figure 3
vs Free-air temperature
Figure 4, Figure 6, Figure 8
vs Common-mode input voltage
Figure 5, Figure 7, Figure 9
vs Free-air temperature
Figure 4, Figure 6, Figure 8
vs Common-mode input voltage
Figure 5, Figure 7, Figure 9
CMRR
Common-mode rejection ratio
vs Frequency
Figure 10
VOH
High-level output voltage
vs High-level output current
Figure 11, Figure 13, Figure 15
VOL
Low-level output voltage
vs Low-level output current
Figure 12, Figure 14, Figure 16
VO(PP)
Output voltage peak-to-peak
vs Frequency
Figure 17
Zo
Output impedance
vs Frequency
Figure 18
ICC
Supply current
vs Supply voltage
Figure 19
PSRR
Power supply rejection ratio
vs Frequency
Figure 20
AVD
Differential voltage gain
vs Frequency
Figure 21
Phase
vs Frequency
Figure 21
Gain-bandwidth product
vs Supply voltage
Figure 22
SR Slew rate
vs Free-air temperature
Figure 23
Phase margin
vs Capacitive load
Figure 24
Gain margin
vs Capacitive load
Figure 25
Supply current
vs Reverse voltage
Figure 26
φm
Voltage noise over a 10 Second Period
Figure 27
Large signal follower pulse response
Figure 28, Figure 29, Figure 30
Small signal follower pulse response
Figure 31
Large signal inverting pulse response
Figure 32, Figure 33, Figure 34
Small signal inverting pulse response
Figure 35
Crosstalk
vs Frequency
Copyright © 2011, Texas Instruments Incorporated
Figure 36
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INPUT OFFSET VOLTAGE
vs
COMMON-MODE INPUT VOLTAGE
INPUT OFFSET VOLTAGE
vs
COMMON-MODE INPUT VOLTAGE
100
1400
VCC = 2.7 V
TA = 25°C
400
800
600
400
200
0
Input Offset Voltage, VIO (mV)
1000
–100
–200
–300
0
–400
–0.1 0.4 1.0 1.6 2.2 2.8 3.4 4.0 4.6 5.2
Common-Mode Input Voltage, VICR (V)
0
–100
–200
–400
–0.1
2.0
4.2 6.4 8.6 10.8 13.0 15.2
Common-Mode Input Voltage, VICR (V)
Figure 2.
Figure 3.
INPUT BIAS / OFFSET CURRENT
vs
FREE-AIR TEMPERATURE
INPUT BIAS / OFFSET CURRENT
vs
COMMON MODE INPUT VOLTAGE
INPUT BIAS / OFFSET CURRENT
vs
FREE-AIR TEMPERATURE
400
400
300
200
100
IIO
0
IIB
–100
–200
–40 –25 –10 5 20 35 50 65 80 95 110 125
Free-Air Temperature, TA (°C)
600
350
VCC = 2.7 V
TA = 25 °C
300
250
200
150
100
50
IIO
0
–50
IIB
–100
–150
–0.1
Input Bias/Offset Current, IIB/IIO (pA)
VCC = 2.7 V
VIC = 1.35 V
I IB /I IO – Input Bias / Offset Current – pA
500
VCC = 5 V
VIC = 2.5 V
400
300
200
100
IIO
0
IIB
–100
–200
–40 –25 –10 5 20 35 50 65 80 95 110 125
Free-Air Temperature, TA (°C)
0.2 0.6 1.0 1.4 1.8 2.2 2.6 2.9
Common-Mode Input Voltage, VICR (V)
Figure 4.
Figure 5.
Figure 6.
INPUT BIAS / OFFSET CURRENT
vs
COMMON-MODE INPUT VOLTAGE
INPUT BIAS / OFFSET CURRENT
vs
FREE-AIR TEMPERATURE
INPUT BIAS / OFFSET CURRENT
vs
COMMON-MODE INPUT VOLTAGE
700
200
Input Bias/Offset Current, IIB/IIO (pA)
150
VCC = 5 V
TA = 25 °C
100
50
IIO
0
–50
IIB
–100
–150
–0.1 0.4 1.0 1.6 2.2 2.8 3.4 4.0 4.6 5.2
Common-Mode Input Voltage, VICR (V)
Figure 7.
600
250
VCC = 15 V
VIC = 7.5 V
500
400
300
200
100
IIO
0
–100
IIB
–200
–40 –25 –10 5 20 35 50 65 80 95 110 125
Free-Air Temperature, TA (°C)
I IB /I IO – Input Bias / Offset Current – pA
Input Bias/Offset Current, IIB/IIO (pA)
100
Figure 1.
600
Input Bias/Offset Current, IIB/IIO (pA)
200
–300
VCC = 5 V
TA = 25 °C
–200
–0.1 0.20 0.60 1.00 1.40 1.80 2.20 2.60 2.9
Common-Mode Input Voltage, VICR (V)
500
VCC = 15 V
TA = 25 °C
300
Input Offset Voltage, VIO (mV)
Input Offset Voltage, VIO (mV)
1200
8
INPUT OFFSET VOLTAGE
vs
COMMON-MODE INPUT VOLTAGE
200
150
100
50
IIO
0
–50
IIB
–100
–150
–0.1
Figure 8.
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VCC = 15 V
TA = 25 °C
2.0
6.4
8.6 10.8 13.0 15.2
4.2
Common-Mode Input Voltage, VICR (V)
Figure 9.
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SLOS716 – APRIL 2011
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COMMON-MODE REJECTION RATIO
vs
FREQUENCY
HIGH-LEVEL OUTPUT VOLTAGE
vs
HIGH-LEVEL OUTPUT CURRENT
VCC = 2.7 V
RF=100 kΩ
RI=1 kΩ
80
60
40
20
VCC = 2.7 V
2.4
Low-Level Output Voltage, VOL (V)
100
TA = –40°C
2.1
TA = –0°C
TA = 25 °C
TA = 70 °C
TA = 125 °C
1.8
1.5
10
100
1k
Frequency, f (Hz)
0
10k
1.25
TA = 25 °C
TA = 0 °C
TA = –40°C
1.00
0.75
TA = 70 °C
TA = 125 °C
0.50
0.25
0
1.2
0
1
100
50
150
200
0
High-Level Output Current, IOH (mA)
100
150
50
Low-Level Output Current, IOL (mA)
200
Figure 10.
Figure 11.
Figure 12.
HIGH-LEVEL OUTPUT VOLTAGE
vs
HIGH-LEVEL OUTPUT CURRENT
LOW-LEVEL OUTPUT VOLTAGE
vs
LOW-LEVEL OUTPUT CURRENT
HIGH-LEVEL OUTPUT VOLTAGE
vs
HIGH-LEVEL OUTPUT CURRENT
15.0
1.50
TA = –40°C
4.5
TA = –0°C
TA = 25 °C
TA = 70 °C
TA = 125 °C
4.0
3.5
VCC = 5 V
High-Level Output Voltage, VOH (V)
VCC = 5 V
Low-Level Output Voltage, VOL (V)
5.0
High-Level Output Voltage, VOH (V)
1.50
2.7
VCC=2.7, 5, 15 V
High-Level Output Voltage, VOH (V)
Common-Mode Rejection Ratio, CMRR (dB)
120
LOW-LEVEL OUTPUT VOLTAGE
vs
LOW-LEVEL OUTPUT CURRENT
1.25
TA = 0 °C
TA = –40°C
1.00
0.75
TA = 25 °C
TA = 70 °C
TA = 125 °C
0.50
0.25
14.5
TA = –0°C
TA = 25 °C
TA = 70 °C
TA = 125 °C
14.0
13.5
TA = –40°C
VCC = 15 V
0
3.0
0
100
150
50
High-Level Output Current, IOH (mA)
0
200
100
150
50
Low-Level Output Current, IOL (mA)
0
200
50
100
150
Figure 14.
Figure 15.
LOW-LEVEL OUTPUT VOLTAGE
vs
LOW-LEVEL OUTPUT CURRENT
OUTPUT VOLTAGE PEAK-TO-PEAK
vs
FREQUENCY
OUTPUT IMPEDANCE
vs
FREQUENCY
10k
1.25
TA = –40°C
1.00
TA = –0°C
TA = 25 °C
TA = 70 °C
TA = 125 °C
0.75
0.50
0.25
14
VCC = 15 V
12
Output Impedance, ZO (W)
Output Voltage Peak-to-Peak, VO(PP) (V)
16
VCC = 15 V
10
8
6
4
RL = 100 kΩ
CL = 100 pF
TA = 25°C
VCC = 5 V
2
VCC = 2.7 V
0
100
150
50
Low-Level Output Current, IOL (mA)
200
Figure 16.
AV = 10
1k
AV = 1
100
VCC = 2.7, 5, & 15 V
TA = 25°C
0
–2
0
100
1k
Frequency, f (Hz)
10k
10
100
Figure 17.
Copyright © 2011, Texas Instruments Incorporated
200
High-Level Output Current, IOH (mA)
Figure 13.
1.50
Low-Level Output Voltage, VOL (V)
13
1k
Frequency, f (Hz)
10k
Figure 18.
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SUPPLY CURRENT
vs
SUPPLY VOLTAGE
POWER SUPPLY REJECTION RATIO
vs
FREQUENCY
1.4
Power Supply Rejection Ratio, PSRR (dB)
120
Supply Current, ICC (mA/Ch)
1.2
1.0
0.8
0.6
TA = 125°C
TA = 70 °C
TA = 25 °C
TA = 0 °C
TA = –40°C
0.4
0.2
AV = 1
VIN = VCC / 2
0
2.5 4.0 5.5 7.0 8.5 10.0 11.5 13.0 14.5 16.0
Supply Voltage, VCC (V)
100
90
80
70
60
50
40
10
1
100
1k
Frequency, f (Hz)
Figure 20.
DIFFERENTIAL VOLTAGE GAIN AND PHASE
vs
FREQUENCY
GAIN BANDWIDTH PRODUCT
vs
SUPPLY VOLTAGE
7
30
45
20
10
0
0
VCC = 2.7, 5, & 15 V
RL = 500 kΩ
CL = 100 pF
TA = 25°C
–10
10
100
1k
Frequency, f (Hz)
Phase ( °)
90
40
Gain Bandwidth Product, GBWP (kHz)
135
50
–20
–45
10k
3
2
1
Supply Voltage, VCC (V)
SLEW RATE
vs
FREE-AIR TEMPERATURE
PHASE MARGIN
vs
CAPACITIVE LOAD
80
70
SR+
VCC = 5, 15 V
60
2.0
1.5
SR–
VCC = 2.7, 5, & 15 V
Phase Margin ( °)
Slew Rate, SR (V/ms)
4
Figure 22.
VCC = 2.7 V
1.0
5
Figure 21.
3.0
2.5
TA = 25°C
RL = 100 kΩ
CL = 100 pF
f = 1 kHz
6
0
2.5 4.0 5.5 7.0 8.5 10.0 11.5 13.0 14.5 16.0
3.5
50
40
30
VCC = 2.7, 5, & 15 V
RL = 500 kΩ
TA = 25°C
20
0.5
10
0
–40 –25 –10 5 20 35 50 65 80 95 110 125
Free-Air Temperature, TA (°C)
0
10
100
1k
Capacitive Load, CL (pF)
Figure 23.
10
10k
Figure 19.
60
Differential Voltage Gain, AVD (dB)
VCC = 2.7, 5, & 15 V
TA = 25°C
110
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10k
Figure 24.
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GAIN MARGIN
vs
CAPACITIVE LOAD
SUPPLY CURRENT
vs
REVERSE VOLTAGE
60
25
55
RL= 500 kΩ
TA = 25°C
VCC = 15 V
15
45
Supply Current, ICC (nA)
Gain Margin (dB)
TA = 25°C
50
20
10
VCC = 2.7 & 5 V
40
35
30
25
20
15
5
10
5
0
–18 –16 –14 –12 –10 –8
0
10k
1k
0
–2
Figure 26.
VOLTAGE NOISE
OVER A 10 SECOND PERIOD
LARGE SIGNAL FOLLOWER
PULSE RESPONSE
2
5
VCC = 5 V
f = 0.1 Hz to 10 Hz
TA = 25°C
3
4
Output Voltage, VO (V)
2
1
0
–1
–2
1
VIN
3
0
VCC = 2.7 V
AV = 1
RL = 100 kΩ
CL = 100 pF
TA = 25°C
2
1
VO
–1
0
–3
–4
0
1
2
3
5
4
6
7
8
9
–1
10
0
1
2
Time, t (s)
3
5
4
6
Time, t (ms)
Figure 27.
Figure 28.
LARGE SIGNAL FOLLOWER
PULSE RESPONSE
LARGE SIGNAL FOLLOWER
PULSE RESPONSE
30
4
8
VCC = 5 V
AV = 1
RL = 100 kΩ
CL = 100 pF
TA = 25°C
5
3
2
1
0
4
3
–1
2
VO
25
VIN
Output Voltage, VO (V)
VIN
6
Input Voltage, VIN (V)
7
15
VCC = 15 V
AV = 1
RL = 100 kΩ
CL = 100 pF
TA = 25°C
20
10
5
15
0
10
–5
VO
5
Input Voltage, VIN (V)
Input Referred Voltage Noise (mV)
–4
Figure 25.
4
Output Voltage, VO (V)
–6
Reverse Voltage, VCC (V)
Capacitive Load, CL (pF)
Input Voltage, VIN (V)
100
10
1
0
0
–5
–1
0
1
2
3
4
Time, t (ms)
5
6
0
2
4
Figure 29.
Copyright © 2011, Texas Instruments Incorporated
6
8
10
12
14
16
Time, t (ms)
Figure 30.
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LARGE SIGNAL INVERTING
PULSE RESPONSE
Input Voltage, VIN (V)
Output Voltage, VO (V)
Input Voltage, VIN (mV)
SMALL SIGNAL FOLLOWER
PULSE RESPONSE
Time, t (ms)
Time, t (ms)
LARGE SIGNAL INVERTING
PULSE RESPONSE
LARGE SIGNAL INVERTING
PULSE RESPONSE
Output Voltage, VO (V)
Input Voltage, VIN (V)
Input Voltage, VIN (V)
Figure 32.
Output Voltage, VO (V)
Figure 31.
Time, t (ms)
Time, t (ms)
SMALL SIGNAL INVERTING
PULSE RESPONSE
CROSSTALK
vs
FREQUENCY
Output Voltage, VO (V)
Crosstalk (dB)
Figure 34.
Input Voltage, VIN (V)
Figure 33.
Time, t (ms)
Frequency, f (Hz)
Figure 35.
12
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Figure 36.
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Product Folder Link(s): TLV2401-Q1 TLV2402-Q1 TLV2404-Q1
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SLOS716 – APRIL 2011
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APPLICATION INFORMATION
Reverse Battery Protection
The TLV240x-Q1 are protected against reverse battery voltage up to 18 V. When subjected to reverse battery
condition the supply current is typically less than 100 nA at 25°C (inputs grounded and outputs open). This
current is determined by the leakage of 6 Schottky diodes and will therefore increase as the ambient temperature
increases.
When subjected to reverse battery conditions and negative voltages applied to the inputs or outputs, the input
ESD structure will turn on—this current should be limited to less than 10 mA. If the inputs or outputs are referred
to ground, rather than midrail, no extra precautions need be taken.
Common-Mode Input Range
The TLV240x-Q1 has rail-to-rail input and outputs. For common-mode inputs from –0.1 V to VCC – 0.8 V a PNP
differential pair will provide the gain.
For inputs between VCC – 0.8 V and VCC, two NPN emitter followers buffering a second PNP differential pair
provide the gain. This special combination of NPN/PNP differential pair enables the inputs to be taken 5 V above
the rails, because as the inputs go above VCC, the NPNs switch from functioning as transistors to functioning as
diodes. This will lead to an increase in input bias current. The second PNP differential pair continues to function
normally as the inputs exceed VCC.
The TLV240x-Q1 has a negative common-input range that exceeds ground by 100 mV. If the inputs are taken
much below this, reduced open loop gain will be observed with the ultimate possibility of phase inversion.
Offset Voltage
The output offset voltage, (VOO) is the sum of the input offset voltage (VIO) and both input bias currents (IIB) times
the corresponding gains. The following schematic and formula can be used to calculate the output offset voltage:
RF
IIB–
RG
+
–
VI
VO
+
RS
IIB+
R
V
V
OO
IO
1
R
F
G
R
I
IB
R
S
1
R
F
I
G
IB–
R
F
Figure 37. Output Offset Voltage Model
Copyright © 2011, Texas Instruments Incorporated
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www.ti.com
General Configurations
When receiving low-level signals, limiting the bandwidth of the incoming signals into the system is often required.
The simplest way to accomplish this is to place an RC filter at the noninverting terminal of the amplifier (see
Figure 38).
RG
RF
–
VO
+
VI
R1
C1
f
V
R
O
V
I
1
R
F
1
G
–3dB
1
2 R1C1
1
sR1C1
Figure 38. Single-Pole Low-Pass Filter
If even more attenuation is needed, a multiple pole filter is required. The Sallen-Key filter can be used for this
task. For best results, the amplifier should have a bandwidth that is 8 to 10 times the filter frequency bandwidth.
Failure to do this can result in phase shift of the amplifier.
C1
+
_
VI
R1
R1 = R2 = R
C1 = C2 = C
Q = Peaking Factor
(Butterworth Q = 0.707)
R2
f
C2
RG
RF
1
2 RC
–3dB
RG =
(
RF
1
2–
Q
)
Figure 39. 2-Pole Low-Pass Sallen-Key Filter
14
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SLOS716 – APRIL 2011
www.ti.com
Circuit Layout Considerations
To achieve the levels of high performance of the TLV240x-Q1, follow proper printed-circuit board design
techniques. A general set of guidelines is given in the following.
• Ground planes – It is highly recommended that a ground plane be used on the board to provide all
components with a low inductive ground connection. However, in the areas of the amplifier inputs and output,
the ground plane can be removed to minimize the stray capacitance.
• Proper power supply decoupling – Use a 6.8-mF tantalum capacitor in parallel with a 0.1-mF ceramic
capacitor on each supply terminal. It may be possible to share the tantalum among several amplifiers
depending on the application, but a 0.1-mF ceramic capacitor should always be used on the supply terminal
of every amplifier. In addition, the 0.1-mF capacitor should be placed as close as possible to the supply
terminal. As this distance increases, the inductance in the connecting trace makes the capacitor less
effective. The designer should strive for distances of less than 0.1 inches between the device power terminals
and the ceramic capacitors.
• Sockets – Sockets can be used but are not recommended. The additional lead inductance in the socket pins
will often lead to stability problems. Surface-mount packages soldered directly to the printed-circuit board is
the best implementation.
• Short trace runs/compact part placements – Optimum high performance is achieved when stray series
inductance has been minimized. To realize this, the circuit layout should be made as compact as possible,
thereby minimizing the length of all trace runs. Particular attention should be paid to the inverting input of the
amplifier. Its length should be kept as short as possible. This will help to minimize stray capacitance at the
input of the amplifier.
• Surface-mount passive components – Using surface-mount passive components is recommended for high
performance amplifier circuits for several reasons. First, because of the extremely low lead inductance of
surface-mount components, the problem with stray series inductance is greatly reduced. Second, the small
size of surface-mount components naturally leads to a more compact layout thereby minimizing both stray
inductance and capacitance. If leaded components are used, it is recommended that the lead lengths be kept
as short as possible.
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15
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SLOS716 – APRIL 2011
www.ti.com
General Power Dissipation Considerations
For a given θJA, the maximum power dissipation is shown in Figure 40 and is calculated by the following formula:
T
P
D
–T
MAX A
JA
Where:
PD = Maximum power dissipation of THS240x IC (watts)
TMAX= Absolute maximum junction temperature (150°C)
TA = Free-ambient air temperature (°C)
θJA = θJC + θCA
θJC = Thermal coefficient from junction to case
θCA = Thermal coefficient from case to ambient air (°C/W)
MAXIMUM POWER DISSIPATION
vs
FREE-AIR TEMPERATURE
2
Maximum Power Dissipation – W
1.75
1.5
1.25
TJ = 150°C
PDIP Package
Low-K Test PCB
θJA = 104°C/W
SOIC Package
Low-K Test PCB
θJA = 176°C/W
MSOP Package
Low-K Test PCB
θJA = 260°C/W
1
0.75
0.5
0.25
SOT-23 Package
Low-K Test PCB
θJA = 324°C/W
0
–55 –40 –25 –10 5 20 35 50 65 80 95 110 125
TA – Free-Air Temperature – °C
(1)
Results are with no air flow and using JEDEC Standard Low-K test PCB.
Figure 40. Maximum Power Dissipation vs Free-Air Temperature
16
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SLOS716 – APRIL 2011
www.ti.com
Macromodel Information
Macromodel information provided was derived using Microsim PartsE Release 8, the model generation software
used with Microsim PSpiceE. The Boyle macromodel (1) and subcircuit in Figure 41 are generated using the
TLV240x-Q1 typical electrical and operating characteristics at TA = 25°C. Using this information, output
simulations of the following key parameters can be generated to a tolerance of 20% (in most cases):
• Maximum positive output voltage swing
• Maximum negative output voltage swing
• Slew rate
• Quiescent power dissipation
• Input bias current
• Open-loop voltage amplification
• Unity-gain frequency
• Common-mode rejection ratio
• Phase margin
• DC output resistance
• AC output resistance
• Short-circuit output current limit
99
3
VCC+
+
ree
rc2
rc1
rp
egnd
cee
c1
IN+
11
1
12
+
c2
r2
96
7
+
vlim
–
8
vc
2
q1
IN–
dp
q2
+
–
13
14
re1
re2
vb
53
dc
–
gcm
dlp
91
iee
4
ga
–
+ 54
dln
90
+
+
vlp
5
92
–
hlim
–
ve
ro1
ioff
VOUT
10
VCC–
ro2
fb
–
–
vln
+
de
.subckt 240X_5V–X 1 2 3 4 5
*
c1
11
12
9.8944E–12
c2
6
7
30.000E–12
cee
10
99
8.8738E–12
dc
5
53
dy
de
54
5
dy
dlp
90
91
dx
dln
92
90
dx
dp
4
3
dx
egnd
99
0
poly(2) (3,0) (4,0) 0 .5 .5
fb
7
99
poly(5) vb vc ve vlp vln 0 61.404E6 –1E3 1E3 61E6 –61E6
ga
6
0
11 12 1.0216E–6
gcm
0
6
10 99 10.216E–12
iee
10
4
dc 54.540E–9
ioff
0
6
dc 5e–12
hlim
90
0
vlim 1K
q1
11
2
13 qx1
q2
12
1
14 qx2
r2
6
9
1.00E+05
rc1
rc2
re1
re2
ree
ro1
ro2
rp
vb
vc
ve
vlim
vlp
vln
.model
.model
.model
.model
.ends
3
3
13
14
10
8
7
3
9
3
54
7
91
0
dx
dy
qx1
qx2
11
9.79E+05
9.79E+05
12
10
3.04E+04
3.04E+04
10
99
3.67E+09
5
10
99
10
1.42E+06
4
0
dc 0
53
dc 0.88315
4
dc 0.88315
8
dc 0
0
dc 540
92
dc 540
D(Is=800.00E–18)
D(Is=800.00E–18 Rs=1m Cjo=10p)
NPN(Is=800.00E–18 Bf=27.270E21)
NPN(Is=800.0000E–18 Bf=27.270E21)
Figure 41. Boyle Macromodels and Subcircuit
(1)
G. R. Boyle, B. M. Cohn, D. O. Pederson, and J. E. Solomon, “Macromodeling of Integrated Circuit Operational Amplifiers”, IEEE
Journal of Solid-State Circuits, SC-9, 353 (1974).
Copyright © 2011, Texas Instruments Incorporated
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17
PACKAGE OPTION ADDENDUM
www.ti.com
16-Aug-2012
PACKAGING INFORMATION
Orderable Device
TLV2402QDGKRQ1
Status
(1)
Package Type Package
Drawing
ACTIVE
VSSOP
DGK
Pins
Package Qty
8
2500
Eco Plan
(2)
Green (RoHS
& no Sb/Br)
Lead/
Ball Finish
MSL Peak Temp
(3)
Samples
(Requires Login)
CU NIPDAU Level-2-260C-1 YEAR
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF TLV2402-Q1 :
• Catalog: TLV2402
NOTE: Qualified Version Definitions:
• Catalog - TI's standard catalog product
Addendum-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
16-Aug-2012
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
TLV2402QDGKRQ1
Package Package Pins
Type Drawing
VSSOP
DGK
8
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
2500
330.0
12.4
Pack Materials-Page 1
5.3
B0
(mm)
K0
(mm)
P1
(mm)
3.4
1.4
8.0
W
Pin1
(mm) Quadrant
12.0
Q1
PACKAGE MATERIALS INFORMATION
www.ti.com
16-Aug-2012
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
TLV2402QDGKRQ1
VSSOP
DGK
8
2500
358.0
335.0
35.0
Pack Materials-Page 2
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