TI TLV2381IDBVT

TLV2381
TLV2382
SLOS377A – SEPTEMBER 2001– REVISED JULY 2003
FAMILY OF MICROPOWER RAIL-TO-RAIL INPUT AND OUTPUT
OPERATIONAL AMPLIFIERS
FEATURES
DESCRIPTION
D
D
D
D
D
D
D
D
The TLV238x single supply operational amplifiers
provide rail-to-rail input and output capability. The
TLV238x takes the minimum operating supply voltage
down to 2.7 V over the extended industrial temperature
range, while adding the rail-to-rail output swing feature.
The TLV238x also provides 160-kHz bandwidth from
only 7 µA. The maximum recommended supply voltage
is 16 V, which allows the devices to be operated from
(±8 V supplies down to ±1.35 V) two rechargeable cells.
D
BiMOS Rail-to-Rail Input/Output
Input Bias Current . . . 1 pA
High Wide Bandwidth . . . 160 kHz
High Slew Rate . . . 0.1 V/µs
Supply Current . . . 7 µA (per channel)
Input Noise Voltage . . . 90 nV/√Hz
Supply Voltage Range . . . 2.7 V to 16 V
Specified Temperature Range
– –40°C to 125°C . . . Industrial Grade
Ultra-Small Packaging
– 5 Pin SOT-23 (TLV2381)
The combination of rail-to-rail inputs and outputs make
them good upgrades for the TLC27Lx family—offering
more bandwidth at a lower quiescent current. The offset
voltage is lower than the TLC27LxA variant.
APPLICATIONS
D
D
D
D
To maintain cost effectiveness the TLV2381/2 are only
available in the extended industrial temperature range.
This means that one device can be used in a wide range
of applications that include PDAs as well as automotive
sensor interface.
Portable Medical
Power Monitoring
Low Power Security Detection Systems
Smoke Detectors
All members are available in SOIC, with the singles in
the small SOT-23 package, duals in the MSOP.
SELECTION GUIDE
DEVICE
VS
[V]
IQ/ch
[µA]
VICR
[V]
VIO
[mV]
IIB
[pA]
GBW
[MHz]
SLEW RATE
[V/µs]
Vn, 1 kHz
[nV/√Hz]
TLV238x
2.7 to 16
10
–0.2 to VS + 0.2
4.5
60
0.16
0.06
100
TLV27Lx
2.7 to 16
11
–0.2 to VS – 1.2
5
60
0.16
0.06
100
TLC27Lx
4 to 16
17
–0.2 to VS – 1.5
10/5/2
60
0.085
0.03
68
OPAx349
1.8 to 5.5
2
–0.2 to VS + 0.2
10
10
0.070
0.02
300
OPAx347
2.3 to 5.5
34
–0.2 to VS + 0.2
6
10
0.35
0.01
60
60
0.200
0.02
19
TLC225x
2.7 to 16
62.5
0 to VS – 1.5
1.5/0.85
NOTE: All dc specs are maximums while ac specs are typicals.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright  2001–2003 Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
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1
TLV2381
TLV2382
SLOS377A – SEPTEMBER 2001– REVISED JULY 2003
PACKAGE/ORDERING INFORMATION
PRODUCT
PACKAGE
PACKAGE
CODE
SYMBOL
TLV2381ID
SOIC-8
D
2381I
TLV2381IDBV
SOT-23
DBV
VBKI
TLV2382ID
SOIC-8
D
2382I
SPECIFIED
TEMPERATURE
RANGE
–40 C to 125
C
–40°C
125°C
ORDER NUMBER
TRANSPORT MEDIA
TLV2381ID
Tube
TLV2381IDR
Tape and Reel
TLV2381IDBVR
TLV2381IDBVT
Tape and Reel
TLV2382ID
Tube
TLV2382IDR
Tape and Reel
absolute maximum ratings over operating free-air temperature (unless otherwise noted)†
Supply voltage, VS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16.5 V
Input voltage, VI (see Notes 1 and 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VS + 0.2 V
Output current, IO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 mA
Differential input voltage, VID . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VS
Continuous total power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Dissipation Rating Table
Maximum junction temperature, TJ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150°C
Operating free-air temperature range, TA: I suffix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –40°C to 125°C
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 125°C
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 300°C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. Relative to GND pin.
2. Maximum is 16.5 V or VS+0.2 V whichever is the lesser value.
DISSIPATION RATING TABLE
2
PACKAGE
θJC
(°C/W)
θJA
(°C/W)
TA ≤ 25°C
POWER RATING
TA = 85°C
POWER RATING
D (8)
38.3
176
710 mW
370 mW
DBV (5)
55
324.1
385 mW
201 mW
DBV (6)
55
294.3
425 mW
221 mW
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TLV2381
TLV2382
SLOS377A – SEPTEMBER 2001– REVISED JULY 2003
recommended operating conditions
Supply voltage, (VS)
Dual supply
Single supply
Input common-mode voltage range
Operating free air temperature, TA
I-suffix
MIN
MAX
±1.35
±8
2.7
16
–0.2
VS+0.2
125
–40
UNIT
V
V
°C
electrical characteristics at recommended operating conditions, VS = 2.7 V, 5 V, and 15 V (unless
otherwise noted)
dc performance
PARAMETER
VIO
Input offset voltage
αVIO
Offset voltage drift
TEST CONDITIONS
VIC = VS/2,
RL = 100 kΩ
VO = VS/2
RS = 50 Ω
VIC = 0 V to VS,
RS = 50 Ω
VIC = 0 V to VS–1.3 V,
RS = 50 Ω
CMRR
Common-mode rejection ratio
VIC = 0 V to VS,
RS = 50 Ω
VIC = 0 V to VS–1.3 V,
RS = 50 Ω
VIC = 0 V to VS,
RS = 50 Ω
VIC = 0 V to VS–1.3 V,
RS = 50 Ω
VS = 2.7 V
VS = 5 V
VS = 15 V
VS = 2.7 V
AVD
Large-signal differential voltage
amplification
VO(PP)=VS/2,
RL = 100 kΩ
VS = 5 V
VS = 15 V
TA†
25°C
MIN
TYP
MAX
0.5
4.5
Full range
6.5
25°C
54
Full range
53
25°C
71
Full range
70
25°C
58
Full range
57
25°C
72
Full range
70
25°C
65
Full range
64
25°C
72
Full range
70
25°C
80
Full range
77
25°C
80
Full range
77
25°C
77
Full range
74
mV
µV/°C
1.1
25°C
UNIT
69
dB
86
74
dB
88
80
dB
90
100
100
dB
83
† Full range is –40°C to 125°C.
input characteristics
PARAMETER
IIO
TEST CONDITIONS
VIC = VS/2,
RL = 100 kΩ ,
Input bias current
ri(d)
Differential input resistance
CIC
Common-mode input capacitance
MIN
TYP
MAX
1
60
≤70°C
Input offset current
IIB
TA
≤25°C
VO = VS/2,
RS = 50 Ω
100
≤125°C
≤25°C
60
200
≤125°C
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pA
1000
1
≤70°C
f = 1 kHz
UNIT
pA
1000
25°C
1000
GΩ
25°C
8
pF
3
TLV2381
TLV2382
SLOS377A – SEPTEMBER 2001– REVISED JULY 2003
electrical characteristics at recommended operating conditions, VS = 2.7 V, 5 V, and 15 V (unless
otherwise noted) (continued)
power supply
PARAMETER
TA†
25°C
TEST CONDITIONS
IDD
Supply current (per channel)
VO = VS/2
PSRR
Power supply rejection ratio (∆VS/∆VIO)
VS = 2.7 V to 16V,
VIC = VS/2 V
MIN
TYP
MAX
7
10
Full range
No load,
15
25°C
74
Full range
70
82
UNIT
µA
dB
† Full range is –40°C to 125°C for I suffix.
output characteristics
PARAMETER
TEST CONDITIONS
VS = 2.7 V
VIC = VS/2,
IO = 100 µA
VO
VS = 5 V
Output voltage swing from rail
VS = 15 V
VS = 5 V
VIC = VS/2,
IO = 500 µA
IO
Output current
† Full range is –40°C to 125°C for I suffix.
VS = 15 V
VO = 0.5 V from rail
VS = 2.7 V
TA†
25°C
MIN
TYP
200
160
Full range
220
25°C
120
Full range
200
25°C
120
Full range
150
25°C
800
Full range
900
25°C
400
Full range
500
25°C
MAX
85
UNIT
mV
50
420
mV
200
µA
400
dynamic performance
PARAMETER
TEST CONDITIONS
GBP
Gain bandwidth product
RL = 100 kΩ , CL = 10 pF,
SR
Slew rate at unity gain
VO(pp) = 2 V,
CL = 10 pF
RL = 100 kΩ,
kΩ
RL = 100 kΩ,
CL = 50 pF
φM
Phase margin
Gain margin
ts
Settling time (0.1%)
f = 1 kHz
V(STEP)pp = 1 V, AV = –1,
CL = 10 pF,
RL = 100 kΩ
Rise
Fall
TA
25°C
MIN
TYP
MAX
160
25°C
0.06
–40°C
0.05
125°C
0.08
UNIT
kHz
V/ s
V/µs
25°C
62
°
25°C
6.7
dB
31
25°C
µs
61
noise/distortion performance
PARAMETER
Vn
4
Equivalent input noise voltage
TEST CONDITIONS
f = 1 kHz
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TA
25°C
MIN
TYP
90
MAX
UNIT
nV/√Hz
TLV2381
TLV2382
SLOS377A – SEPTEMBER 2001– REVISED JULY 2003
TYPICAL CHARACTERISTICS
Table of Graphs
FIGURE
VIO
IIB/IIO
Input offset voltage
vs Common-mode input voltage
Input bias and offset current
vs Free-air temperature
VOH
VOL
High-level output voltage
vs High-level output current
5, 7, 9
Low-level output voltage
vs Low-level output current
6, 8, 10
IQ
Quiescent current
1, 2, 3
4
vs Supply voltage
11
vs Free-air temperature
12
Supply voltage and supply current ramp up
13
AVD
GBP
Differential voltage gain and phase shift
vs Frequency
14
Gain-bandwidth product
vs Free-air temperature
15
φm
CMRR
Phase margin
vs Load capacitance
16
Common-mode rejection ratio
vs Frequency
17
PSRR
Power supply rejection ratio
vs Frequency
18
Input referred noise voltage
vs Frequency
19
SR
Slew rate
vs Free-air temperature
20
VO(PP)
Peak-to-peak output voltage
vs Frequency
21
Inverting small-signal response
22
Inverting large-signal response
23
Crosstalk
vs Frequency
INPUT OFFSET VOLTAGE
vs
COMMON-MODE INPUT VOLTAGE
INPUT OFFSET VOLTAGE
vs
COMMON-MODE INPUT VOLTAGE
500
0
–500
–1000
–1500
1500
V IO – Input Offset Voltage – µ A
1000
2000
VS = 5 V
TA = 25°C
1500
V IO – Input Offset Voltage – µ A
V IO – Input Offset Voltage – µ A
1500
1000
500
0
–500
–1000
–1500
–2000
–2000
0
0.3 0.6 0.9 1.2 1.5 1.8 2.1 2.4 2.7
VIC – Common-Mode Input Voltage – V
Figure 1
INPUT OFFSET VOLTAGE
vs
COMMON-MODE INPUT VOLTAGE
2000
2000
VS = 2.7 V
TA = 25°C
24
0
0.5
1
1.5
2 2.5
3 3.5
4
4.5
VIC – Common-Mode Input Voltage – V
Figure 2
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5
VS = 15 V
TA = 25°C
1000
500
0
–500
–1000
–1500
–2000
–0.2
7.5
15.2
VIC – Common-Mode Input Voltage – V
Figure 3
5
TLV2381
TLV2382
SLOS377A – SEPTEMBER 2001– REVISED JULY 2003
TYPICAL CHARACTERISTICS
INPUT BIAS AND INPUT
OFFSET CURRENT
vs
FREE-AIR TEMPERATURE
15
VIC = 0
80
VO = 0
70
RS = 50 Ω
60
50
40
30
IIB
IIO
20
10
–40°C
12.5
0°C
25°C
10
70°C
7.5
5
125°C
2.5
0
0
25
45
65
85
105
TA – Free-Air Temperature – °C
0
125
2
4
6
25°C
3
70°C
2.5
2
1.5
125°C
0.5
0
2 2.5
125°C
4
70°C
3.5
3
25°C
2.5
0°C
2
1.5
1
–40°C
0.5
3 3.5
4
4.5
25°C
0°C
0.9
0.6
–40°C
0.6
0.8
1
1.2
IOL – Low-Level Output Current – mA
Figure 10
70°C
1.2
0.9
125°C
0.6
0.3
0.2
7
1.4
0.4
0.6
0.8
1
1.2
1.4
8
16 V
7
70°C
6
5
–40°C
25°C
4
0°C
3
2
5V
6
5
2.7 V
4
3
2
1
0
0.4
1.5
QUIESCENT CURRENT
vs
FREE-AIR TEMPERATURE
1
0
0.2
25°C
Figure 9
I (Q) – Quiescent Currenr – µ A
1.8
0
0°C
1.8
IOH – High-Level Output Current – mA
QUIESCENT CURRENT
vs
SUPPLY VOLTAGE
8
I (Q) – Quiescent Currenr – µ A
V OL– Low-Level Output Voltage – V
70°C
0.3
VS = 2.7 V
0
125°C
125°C
16 18 20
0
VS = 2.7 V
2.1
10 12 14
–40°C
Figure 8
2.7
8
2.1
IOL – Low-Level Output Current – mA
LOW-LEVEL OUTPUT VOLTAGE
vs
LOW-LEVEL OUTPUT CURRENT
1.2
6
2.4
0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 5.5 6
5
Figure 7
1.5
4
2.7
IOH – High-Level Output Current – mA
2.4
2
HIGH-LEVEL OUTPUT VOLTAGE
vs
HIGH-LEVEL OUTPUT CURRENT
0
1.5
–40°C
Figure 6
VOH – High-Level Output Voltage – V
V OL– Low-Level Output Voltage – V
VOH – High-Level Output Voltage – V
0°C
3.5
1
0°C
VS = 5 V
4.5
–40°C
0.5
70°C
25°C
IOL – Low-Level Output Current – mA
5
VS = 5 V
0
125°C
0
8 10 12 14 16 18 20 22 24
LOW-LEVEL OUTPUT VOLTAGE
vs
LOW-LEVEL OUTPUT CURRENT
5
4.5
1
VS = 15 V
Figure 5
HIGH-LEVEL OUTPUT VOLTAGE
vs
HIGH-LEVEL OUTPUT CURRENT
4
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
IOH – High-Level Output Current – mA
Figure 4
6
VS = 15 V
V OL– Low-Level Output Voltage – V
VDD± = ± 2.5 V
VOH – High-Level Output Voltage – V
I IB and I IO – Input Bias and Input
Offset Currents – pA
100
90
LOW-LEVEL OUTPUT VOLTAGE
vs
LOW-LEVEL OUTPUT CURRENT
HIGH-LEVEL OUTPUT VOLTAGE
vs
HIGH-LEVEL OUTPUT CURRENT
0
2
4
6
8
10
12
VS – Supply Voltage – V
Figure 11
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14
16
0
–40 –25–10 5 20 35 50 65 80 95 110 125
TA – Free-Air Temperature – °C
Figure 12
TLV2381
TLV2382
SLOS377A – SEPTEMBER 2001– REVISED JULY 2003
TYPICAL CHARACTERISTICS
DIFFERENTIAL VOLTAGE GAIN
AND PHASE SHIFT
vs
FREQUENCY
40
120
10
5
A VD – Differential Voltage Gain – dB
VS
VO
0
VS = 0 to 15 V,
RL = 100 Ω,
CL = 10 pF,
TA = 25°C
15
IQ
10
5
0
5
10
15
20
25
0
30
VS = 5 V
RL = 100 kΩ
CL = 10 pF
TA = 25°C
100
80
60°
40
90°
20
120°
0
150°
–20
0.1
1
10
160
70
VS = 2.7 V
VS = 15 V
130
120
110
VS = 5 V
RL = 100 kΩ
TA = 25°C
60
50
40
30
20
10
0
20 35 50 65 80 95 110 125
10
TA – Free-Air Temperature – °C
100
80
70
60
50
40
30
20
10
0
10
100
80
70
60
50
40
30
20
10
0
10 k
f – Frequency – Hz
Figure 18
100 k
1M
Hz
1k
10 k
100 k
1M
f – Frequency – Hz
Figure 17
SLEW RATE
vs
FREE-AIR TEMPERATURE
0.09
250
VS = 5 V,
G = 2,
RF = 100 kΩ
200
0.08
SR – Slew Rate – V/ µ s
VS =±2.5 V
TA = 25°C
1k
VS = 5 V
TA = 25°C
90
INPUT REFERRED NOISE VOLTAGE
vs
FREQUENCY
Vn– Input Referred Noise Voltage – nV/
PSRR – Power Supply Rejection Ratio – dB
100
100
110
100
Figure 16
POWER SUPPLY REJECTION RATIO
vs
FREQUENCY
10
1000
120
CL – Load Capacitance – pF
Figure 15
90
180°
10 k 100 k 1 M
COMMON-MODE REJECTION RATIO
vs
FREQUENCY
CMRR – Common-Mode Rejection Ratio – dB
80
Phase Margin – Degrees
GBP – Gain-Bandwidth Product – kHz
PHASE MARGIN
vs
LOAD CAPACITANCE
170
100
–40 –25 –10 5
1k
Figure 14
GAIN-BANDWIDTH PRODUCT
vs
FREE-AIR TEMPERATURE
140
100
f – Frequency – Hz
t – Time – ms
VS = 5 V
30°
60
Figure 13
150
0°
Phase Shift
15
I CC – Supply Current – µ A
VS – Supply Voltage – V/dc
SUPPLY VOLTAGE AND
SUPPLY CURRENT RAMP UP
150
100
SR+
0.07
0.06
SR–
0.05
0.04
0.03
0.02
50
0.01
0
1
10
100
1k
f – Frequency – Hz
Figure 19
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10 k
100 k
0
–40 –25 –10 5
VS = 5 V
Gain = 1
VO = 1
RL = 100 kΩ
CL = 50 pF
20 35 50 65 80 95 110 125
TA – Free-air Temperature – °C
Figure 20
7
TLV2381
TLV2382
SLOS377A – SEPTEMBER 2001– REVISED JULY 2003
TYPICAL CHARACTERISTICS
PEAK-TO-PEAK OUTPUT VOLTAGE
vs
FREQUENCY
INVERTING SMALL-SIGNAL
RESPONSE
V OPP – Output Voltage Peak-to-Peak – V
16
2
VI = 3 VPP
VS = 15 V
14
1.5
1
Amplitude – VPP
12
RL = 100 kΩ,
CL = 10 pF,
THD+N <= 5%
10
8
6
2
–1.5
VS = 2.7 V
VO = 3 VPP
–2
–100
0
10
100
0
–0.5
–1
VS = 5 V
4
Gain = –1,
RL = 100 kΩ,
CL = 10 pF,
VS = 5 V,
VO = 3 VPP,
f = 1 kHz
0.5
1000
1k
10 k
0
100 200 300 400 500 600 700
t – Time – µs
f – Frequency – Hz
Figure 22
Figure 21
CROSSTALK
vs
FREQUENCY
INVERTING LARGE-SIGNAL
RESPONSE
0
0.06
VI = 100 mVPP
Gain = –1,
RL = 100 kΩ,
CL = 10 pF,
VS = 5 V,
VO = 100 mVPP,
f = 1 kHz
0.02
0
–40
Crosstalk – dB
Amplitude – VPP
0.04
–0.02
–80
–120
VO = 100 mVPP
–140
0
10
100 200 300 400 500 600 700
100
1k
f – Frequency – Hz
t – Time – µs
Figure 23
8
–60
–100
–0.04
–0.06
–100
VS = 5 V
RL = 2 kΩ
CL = 10 pF
TA = 25°C
Channel 1 to 2
–20
Figure 24
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10 k
100 k
TLV2381
TLV2382
SLOS377A – SEPTEMBER 2001– REVISED JULY 2003
APPLICATION INFORMATION
offset voltage
The output offset voltage (VOO) is the sum of the input offset voltage (VIO) and both input bias currents (IIB) times the
corresponding gains. The following schematic and formula can be used to calculate the output offset voltage:
RF
RG
ǒ ǒ ǓǓ ǒ ǒ ǓǓ
IIB–
+
–
VI
+
RS
V
VO
OO
+ VIO 1 )
R
R
F
G
" IIB) RS
1
)
R
R
F
G
" IIB– RF
IIB+
Figure 25. Output Offset Voltage Model
general configurations
When receiving low-level signals, limiting the bandwidth of the incoming signals into the system is often required. The
simplest way to accomplish this is to place an RC filter at the noninverting terminal of the amplifier (see Figure 26).
RG
RF
O
V
I
VDD/2
VI
V
–
VO
+
R1
f
–3dB
+
ǒ Ǔǒ
1
) RRF
G
Ǔ
) sR1C1
1
1
1
+ 2pR1C1
C1
Figure 26. Single-Pole Low-Pass Filter
If even more attenuation is needed, a multiple pole filter is required. The Sallen-Key filter can be used for this task.
For best results, the amplifier should have a bandwidth that is 8 to 10 times the filter frequency bandwidth. Failure
to do this can result in phase shift of the amplifier.
C1
+
_
VI
R1
R1 = R2 = R
C1 = C2 = C
Q = Peaking Factor
(Butterworth Q = 0.707)
R2
f
C2
RG
RF
–3dB
RG =
+ 2p1RC
(
RF
1
2–
Q
)
VDD/2
Figure 27. 2-Pole Low-Pass Sallen-Key Filter
www.ti.com
9
TLV2381
TLV2382
SLOS377A – SEPTEMBER 2001– REVISED JULY 2003
APPLICATION INFORMATION
circuit layout considerations
To achieve the levels of high performance of the TLV238x, follow proper printed-circuit board design techniques. A
general set of guidelines is given in the following.
D
D
D
D
D
10
Ground planes—It is highly recommended that a ground plane be used on the board to provide all
components with a low inductive ground connection. However, in the areas of the amplifier inputs and
output, the ground plane can be removed to minimize the stray capacitance.
Proper power supply decoupling—Use a 6.8-µF tantalum capacitor in parallel with a 0.1-µF ceramic
capacitor on each supply terminal. It may be possible to share the tantalum among several amplifiers
depending on the application, but a 0.1-µF ceramic capacitor should always be used on the supply terminal
of every amplifier. In addition, the 0.1-µF capacitor should be placed as close as possible to the supply
terminal. As this distance increases, the inductance in the connecting trace makes the capacitor less
effective. The designer should strive for distances of less than 0.1 inches between the device power
terminals and the ceramic capacitors.
Sockets—Sockets can be used but are not recommended. The additional lead inductance in the socket pins
will often lead to stability problems. Surface-mount packages soldered directly to the printed-circuit board
is the best implementation.
Short trace runs/compact part placements—Optimum high performance is achieved when stray series
inductance has been minimized. To realize this, the circuit layout should be made as compact as possible,
thereby minimizing the length of all trace runs. Particular attention should be paid to the inverting input of
the amplifier. Its length should be kept as short as possible. This will help to minimize stray capacitance at
the input of the amplifier.
Surface-mount passive components—Using surface-mount passive components is recommended for high
performance amplifier circuits for several reasons. First, because of the extremely low lead inductance of
surface-mount components, the problem with stray series inductance is greatly reduced. Second, the small
size of surface-mount components naturally leads to a more compact layout thereby minimizing both stray
inductance and capacitance. If leaded components are used, it is recommended that the lead lengths be
kept as short as possible.
www.ti.com
TLV2381
TLV2382
SLOS377A – SEPTEMBER 2001– REVISED JULY 2003
APPLICATION INFORMATION
general power dissipation considerations
ǒ Ǔ
For a given θJA, the maximum power dissipation is shown in Figure 28 and is calculated by the following formula:
P
+
D
T
–T
MAX A
q JA
Where:
PD = Maximum power dissipation of TLV238x IC (watts)
TMAX = Absolute maximum junction temperature (150°C)
TA
= Free-ambient air temperature (°C)
θJA = θJC + θCA
θJC = Thermal coefficient from junction to case
θCA = Thermal coefficient from case to ambient air (°C/W)
MAXIMUM POWER DISSIPATION
vs
FREE-AIR TEMPERATURE
2
Maximum Power Dissipation – W
1.75
TJ = 150°C
PDIP Package
Low-K Test PCB
θJA = 104°C/W
1.5
1.25
MSOP Package
Low-K Test PCB
θJA = 260°C/W
SOIC Package
Low-K Test PCB
θJA = 176°C/W
1
0.75
0.5
0.25
SOT-23 Package
Low-K Test PCB
θJA = 324°C/W
0
–55 –40 –25 –10 5 20 35 50 65 80 95 110 125
TA – Free-Air Temperature – °C
NOTE A: Results are with no air flow and using JEDEC Standard Low-K test PCB.
Figure 28. Maximum Power Dissipation vs Free-Air Temperature
TLV2381
D PACKAGE
(TOP VIEW)
TLV2381
DBV PACKAGE
(TOP VIEW)
OUT
GND
IN+
1
5
VDD
2
3
4
NC
IN –
IN +
GND
1
8
2
7
3
6
4
5
TLV2382
D PACKAGE
(TOP VIEW)
NC
VDD
OUT
NC
1OUT
1IN –
1IN +
GND
1
8
2
7
3
6
4
5
VDD
2OUT
2IN –
2IN+
IN –
NC – No internal connection
www.ti.com
11
PACKAGE OPTION ADDENDUM
www.ti.com
11-Dec-2006
PACKAGING INFORMATION
Orderable Device
Status (1)
Package
Type
Package
Drawing
Pins Package Eco Plan (2)
Qty
TLV2381ID
ACTIVE
SOIC
D
8
TLV2381IDBVR
ACTIVE
SOT-23
DBV
TLV2381IDBVRG4
ACTIVE
SOT-23
TLV2381IDBVT
ACTIVE
TLV2381IDBVTG4
75
Lead/Ball Finish
MSL Peak Temp (3)
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
5
3000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
DBV
5
3000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SOT-23
DBV
5
250
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
ACTIVE
SOT-23
DBV
5
250
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
TLV2381IDG4
ACTIVE
SOIC
D
8
75
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
TLV2381IDR
ACTIVE
SOIC
D
8
2500 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
TLV2381IDRG4
ACTIVE
SOIC
D
8
2500 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
TLV2381IP
PREVIEW
PDIP
P
8
TBD
Call TI
TLV2382ID
ACTIVE
SOIC
D
8
75
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
TLV2382IDG4
ACTIVE
SOIC
D
8
75
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
TLV2382IDR
ACTIVE
SOIC
D
8
2500 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
TLV2382IDRG4
ACTIVE
SOIC
D
8
2500 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
TLV2382IP
OBSOLETE
PDIP
P
8
TBD
Call TI
Call TI
Call TI
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
11-Dec-2006
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
19-Mar-2008
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
Diameter Width
(mm) W1 (mm)
A0 (mm)
B0 (mm)
K0 (mm)
P1
(mm)
TLV2381IDBVR
SOT-23
DBV
5
3000
180.0
9.0
3.15
3.2
1.4
4.0
TLV2381IDBVT
SOT-23
DBV
5
250
TLV2381IDR
SOIC
D
8
2500
180.0
9.0
3.15
3.2
1.4
330.0
12.4
6.4
5.2
2.1
TLV2382IDR
SOIC
D
8
2500
330.0
12.4
6.4
5.2
2.1
Pack Materials-Page 1
W
Pin1
(mm) Quadrant
8.0
Q3
4.0
8.0
Q3
8.0
12.0
Q1
8.0
12.0
Q1
PACKAGE MATERIALS INFORMATION
www.ti.com
19-Mar-2008
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
TLV2381IDBVR
SOT-23
DBV
5
3000
182.0
182.0
20.0
TLV2381IDBVT
SOT-23
DBV
5
250
182.0
182.0
20.0
TLV2381IDR
SOIC
D
8
2500
340.5
338.1
20.6
TLV2382IDR
SOIC
D
8
2500
340.5
338.1
20.6
Pack Materials-Page 2
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