TLV5613 2.7 V TO 5.5 V 12-BIT PARALLEL DIGITAL-TO-ANALOG CONVERTER WITH POWER DOWN SLAS174A – DECEMBER 1997 – REVISED JULY 1998 D D D D D D D D D D 12-Bit Voltage Output DAC Single Supply 2.7-V to 5.5-V Operation Separate Analog and Digital Supplies ±0.4 LSB Differential Nonlinearity (DNL), ±1.5 LSB Integral Nonlinearity (INL) Programmable Settling Time vs Power Consumption: 1 µs/4.2 mW in Fast Mode, 3.5 µs/1.2 mW in Slow Mode 8-Bit µController Compatible Interface (8+4 Bit) Power-Down Mode (50 nW) Rail-to-Rail Output Buffer Synchronous or Asynchronous Update Monotonic Over Temperature applications D D D D D D D Digital Servo Control Loops Battery Powered Test Instruments Digital Offset and Gain Adjustment Industrial Process Control Speech Synthesis Machine and Motion Control Devices Mass Storage Devices DW OR PW PACKAGE (TOP VIEW) D2 D3 D4 D5 D6 D7 A1 A0 SPD DVDD description The TLV5613 is a 12-bit voltage output digital-to-analog converter (DAC) with a 8-bit microcontroller compatible parallel interface. The 8 LSBs, the 4 MSBs and 3 control bits are written using three different addresses. Developed for a wide range of supply voltages, the TLV5613 can be operated from 2.7 V to 5.5 V. 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 D1 D0 CS WE LDAC PWD GND OUT REF AVDD The resistor string output voltage is buffered by a x2 gain rail-to-rail output buffer. The buffer features a Class A (slow mode: AB) output stage to improve stability and reduce settling time. The programmable settling time of the DAC allows the designer to optimize speed versus power dissipation. The settling time can be chosen by the control bits within the 16-bit data word. Implemented with a CMOS process, the device is designed for single supply operation from 2.7 V to 5.5 V. It is available in 20 pin SOIC in standard commercial and industrial temperature ranges. AVAILABLE OPTIONS PACKAGE SMALL OUTLINE (DW) TA TSSOP (PW) 0°C to 70°C TLV5613CDW TLV5613CPW – 40°C to 85°C TLV5613IDW TLV5613IPW Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Copyright 1998, Texas Instruments Incorporated PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1 TLV5613 2.7 V TO 5.5 V 12-BIT PARALLEL DIGITAL-TO-ANALOG CONVERTER WITH POWER DOWN SLAS174A – DECEMBER 1997 – REVISED JULY 1998 functional block diagram REF SPD PWD Powerdown and Speed Control Power-On Reset 3 2 A(0–1) Interface Control CS WE x2 2 3-Bit Control Latch 4 4-Bit DAC MSW Holding Latch 4 8 8-Bit DAC LSW Holding Latch 8 12 12-Bit DAC Latch 12 8 D(0–7) LDAC Terminal Functions TERMINAL NAME AVDD A0 I/O 11 DESCRIPTION Analog positive power supply 8 I Address input A1 7 I Address input CS 18 I Chip select. Digital input active low, used to enable/disable inputs DVDD 10 D0 (LSB) – D7 (MSB) 2 NO. Digital positive power supply 1–6, 19, 20 I Data input LDAC 16 I Load DAC. Digital input active low, used to load DAC output OUT 13 O DAC analog voltage output PWD 15 I Power down. Digital input active low REF 12 I Analog reference voltage input SPD 9 I Speed select. Digital input GND 14 WE 17 Ground I Write enable. Digital input active low, used to latch data POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 OUT TLV5613 2.7 V TO 5.5 V 12-BIT PARALLEL DIGITAL-TO-ANALOG CONVERTER WITH POWER DOWN SLAS174A – DECEMBER 1997 – REVISED JULY 1998 absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage (DVDD, AVDD to GND) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V Supply voltage difference, AVDD to DVDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 2.8 V to 2.8 V Reference input voltage range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.3 V to AVDD + 0.3 V Digital input voltage range to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.3 V to DVDD + 0.3 V Operating free-air temperature range, TA: TLV5613C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 70°C TLV5613I . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 40°C to 85°C Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 65°C to 150°C Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260°C † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. recommended operating conditions Supply voltage voltage, VDD MIN NOM 5-V Supply 4.5 5 5.5 3-V Supply 2.7 3 3.3 –2.8 0 2.8 V 2 V Supply voltage difference, ∆VDD = AVDD – DVDD Power on reset, POR High-level digital input voltage, VIH Low-level digital input voltage, VIL Reference voltage, voltage Vreff to REFIN terminal 0.55 DVDD = 2.7 V to 5.5 V DVDD = 2.7 V to 5.5 V 2 5-V Supply (see Note 1) GND 3-V Supply (see Note 1) GND 2.048 AVDD – 1.5 1.024 AVDD – 1.5 2 Load capacitance, CL TLV5613C TLV5613I UNIT V V 0.8 Load resistance, RL Operating free-air free air temperature, temperature TA MAX V V kΩ 100 pF 0 70 °C – 40 85 °C NOTE 1: Due to the x2 output buffer, a reference input voltage ≥ (VDD – 0.4)/2 causes clipping of the transfer function. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 3 TLV5613 2.7 V TO 5.5 V 12-BIT PARALLEL DIGITAL-TO-ANALOG CONVERTER WITH POWER DOWN SLAS174A – DECEMBER 1997 – REVISED JULY 1998 electrical characteristics over recommended operating free-air temperature range, supply voltages, and reference voltages (unless otherwise noted) power supply PARAMETER IDD TEST CONDITIONS No load, All inputs = GND or DVDD, DAC latch = 0x800 Power supply current Power down supply current PSRR MIN VDD = 5 V VDD = 3 V TYP UNIT Fast 1.6 3 mA Slow 0.5 1.3 mA Fast 1.4 2.7 mA 0.4 1.1 mA 0.01 10 µA Slow See Figure 14 Power supply rejection ratio MAX Zero scale, See Note 2 –65 Full scale, See Note 3 –65 dB NOTES: 2. Power supply rejection ratio at zero scale is measured by varying AVDD and is given by: PSRR = 20 log [(EZS(AVDDmax) – EZS(AVDDmin))/AVDDmax] 3. Power supply rejection ratio at full scale is measured by varying AVDD and is given by: PSRR = 20 log [(EG(AVDDmax) – EG(AVDDmin))/AVDDmax] static DAC specifications PARAMETER TEST CONDITIONS Resolution TYP MAX 12 UNIT bits See Note 4 ± 1.5 ±4 LSB See Note 5 ± 0.4 ±1 LSB Zero-scale error (offset error at zero scale) See Note 6 ±3 ± 20 Zero-scale-error temperature coefficient Vref(REFIN) = 2.048 V, 1.024 V, See Note 7 3 Gain error Vref(REFIN) = 2.048 V, 1.024 V, See Note 8 ± 0.25 Differential nonlinearity (DNL) EG MIN Vref(REFIN) = 2.048 V, 1.024 V, Vref(REFIN) = 2.048 V, 1.024 V, Integral nonlinearity (INL), end point adjusted EZS Vref(REFIN) = 2.048 V, 1.024 V Vref(REFIN) = 2.048 V, 1.024 V, mV ppm/°C ± 0.5 % of FS voltage Gain error temperature coefficient NOTES: 4. 5. 6. 7. 8. 9. Vref(REFIN) = 2.048 V, 1.024 V, See Note 9 1 ppm/°C The relative accuracy or integral nonlinearity (INL) sometimes referred to as linearity error, is the maximum deviation of the output from the line between zero and full scale excluding the effects of zero code and full-scale errors. The differential nonlinearity (DNL) sometimes referred to as differential error, is the difference between the measured and ideal 1 LSB amplitude change of any two adjacent codes. Monotonic means the output voltage changes in the same direction (or remains constant) as a change in the digital input code. Zero-scale error is the deviation from zero voltage output when the digital input code is zero. Zero-scale-error temperature coefficient is given by: EZS TC = [EZS (Tmax) – EZS (Tmin)]/Vref × 106/(Tmax – Tmin). Gain error is the deviation from the ideal output (Vref – 1 LSB) with an output load of 10 kΩ excluding the effects of the zero-error. Gain temperature coefficient is given by: EG TC = [EG(Tmax) – EG (Tmin)]/Vref × 106/(Tmax – Tmin). output specifications PARAMETER VO TEST CONDITIONS Output voltage RL = 10 kΩ VO(OUT) = 4.096 V, IOSC(source) Output Out ut short circuit source current VO(OUT) = 0 V V, input in ut all 1s IOSC(sink) Output Out ut short circuit sink current RL = 100 Ω Ω, input in ut all 1s POST OFFICE BOX 655303 TYP 0 Output load regulation accuracy 4 MIN RL = 2 kΩ, 0.1 AVDD = 5 V –100 AVDD = 3 V –25 AVDD = 5 V –10 AVDD = 3 V –10 • DALLAS, TEXAS 75265 MAX AVDD–0.4 0.29 UNIT V % of FS voltage mA mA TLV5613 2.7 V TO 5.5 V 12-BIT PARALLEL DIGITAL-TO-ANALOG CONVERTER WITH POWER DOWN SLAS174A – DECEMBER 1997 – REVISED JULY 1998 electrical characteristics over recommended operating free-air temperature range, supply voltages, and reference voltages (unless otherwise noted) reference input (REFIN) PARAMETER Vref Ri Input voltage reference Ci Input capacitance TEST CONDITIONS MIN See Note 10 TYP 0 Reference feed through 0 2 Vpp + 1.024 1 024 V dc REF = 0.2 UNIT AVDD– 1.5 Input resistance input Reference in ut bandwidth MAX V 10 MΩ 5 pF Fast mode 1.6 MHz Slow mode 1 MHz REF = 1 Vpp at 1 kHz + 1.024 V dc, See Note 10 –60 dB NOTES: 10. Reference feedthrough is measured at the DAC output with an input code = 0x000. digital inputs PARAMETER IIH IIL High-level digital input current Ci Input capacitance Low-level digital input current TEST CONDITIONS MIN VI = DVDD VI = 0 V TYP MAX 1 UNIT µA µA –1 8 pF operating characteristics over recommended operating free-air temperature range, supply voltages, and reference voltages (unless otherwise noted) analog output dynamic performance PARAMETER TEST CONDITIONS ts(FS) (FS) Output settling time, time full scale RL = 10 kΩ,, CL = 100 pF, See Note 11 ts(CC) (CC) Output settling time time, code code-to-code to code RL = 10 kΩ,, CL = 100 pF, See Note 12 SR Slew rate RL = 10 kΩ,, CL = 100 pF, See Note 13 Glitch energy Code-to-code transition S/N Signal-to-noise S/(N+D) Signal-to-noise + distortion THD Total harmonic distortion TYP MAX Fast MIN 1 3 Slow 3.5 7 Fast 0.5 1.5 Slow 1 2 Fast 8 Slow 1.5 Spurious free dynamic range 58 µs nV–s 78 69 –68 60 µs V/µs 1 65 fs = 480 KSPS,, fout = 1 kHz,, RL = 10 k, CL = 100 pF UNIT –60 dB 72 NOTES: 11. Settling time is the time for the output signal to remain within ± 0.5 LSB of the final measured value for a digital input code change of 0x020 to 0x3FF or 0x3FF to 0x020. 12. Settling time is the time for the output signal to remain within ± 0.5 LSB of the final measured value for a digital input code change of one count. The max time applies to code changes near zero scale or full scale. 13. Slew rate determines the time it takes for a change of the DAC output from 10% to 90% full-scale voltage. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 5 TLV5613 2.7 V TO 5.5 V 12-BIT PARALLEL DIGITAL-TO-ANALOG CONVERTER WITH POWER DOWN SLAS174A – DECEMBER 1997 – REVISED JULY 1998 timing requirements digital inputs MIN tsu(D) tsu(CS-WE) Setup time, data ready before positive WE edge NOM MAX UNIT 9 ns Setup time, CS low before positive WE edge 13 ns tsu(A) th(D) Setup time, address bits A0, A1 17 ns 0 ns tsu(WE-LD) tw(WE) Setup time, positive WE edge before LDAC low 0 ns Pulse duration, WE high 10 ns tw(LD) Pulse duration, LDAC low 10 µs Hold time, data held after positive WE edge PARAMETER MEASUREMENT INFORMATION D(0–7) X A(0–1) X Data X Address X tsu(D) tsu(A) CS th(D) tw(WE) tsu(CS-WE) WE tsu(WE-LD) LDAC Figure 1. Timing Diagram 6 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 tw(LD) TLV5613 2.7 V TO 5.5 V 12-BIT PARALLEL DIGITAL-TO-ANALOG CONVERTER WITH POWER DOWN SLAS174A – DECEMBER 1997 – REVISED JULY 1998 PARAMETER MEASUREMENT INFORMATION D(0–7) X MSW A(0–1) X 0 X X LSW X 1 X CS WE LDAC Figure 2. Example of a Complete Write Cycle Using LDAC to Update the DAC D(0–7) X MSW A(0–1) X 0 X X LSW 1 X X Control X 3 X CS WE LDAC Figure 3. Example of a Complete Write Cycle Using the Control Word to Update the DAC POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 7 TLV5613 2.7 V TO 5.5 V 12-BIT PARALLEL DIGITAL-TO-ANALOG CONVERTER WITH POWER DOWN SLAS174A – DECEMBER 1997 – REVISED JULY 1998 TYPICAL CHARACTERISTICS MAXIMUM OUTPUT VOLTAGE vs LOAD MAXIMUM OUTPUT VOLTAGE vs LOAD 3 4.5 AVDD = 3 V, Vref = 1.2 V, Input Code = 4095 AVDD = 5 V, Vref = 2 V, Input Code = 4095 2.5 VO – Output Voltage – V VO – Output Voltage – V 4 3.5 3 2.5 2 1.5 1 2 1.5 100 K 100 10 K 1K RL – Output Load – Ω 0.5 100 K 10 TOTAL HARMONIC DISTORTION vs LOAD TOTAL HARMONIC DISTORTION vs LOAD 0 0 AVDD = 5 V, Vref = 2 V, Tone @ 1 kHz THD – Total Harmonic Distortion – dB THD – Total Harmonic Distortion – dB 10 Figure 5 Figure 4 –20 –40 –60 –80 –100 100 K 10 K 1K 100 RL – Output Load – Ω 10 AVDD = 3 V, Vref = 1.2 V, Tone @ 1 kHz –20 –40 –60 –80 –100 100 K 10 K 1K 100 RL – Output Load – Ω Figure 7 Figure 6 8 100 10 K 1K RL – Output Load – Ω POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 10 TLV5613 2.7 V TO 5.5 V 12-BIT PARALLEL DIGITAL-TO-ANALOG CONVERTER WITH POWER DOWN SLAS174A – DECEMBER 1997 – REVISED JULY 1998 TYPICAL CHARACTERISTICS TOTAL HARMONIC DISTORTION vs FREQUENCY TOTAL HARMONIC DISTORTION vs FREQUENCY 0 0 AVDD = 3 V THD – Total Harmonic Distortion – dB THD – Total Harmonic Distortion – dB AVDD = 5 V –10 –20 –30 –40 –50 –60 –70 –80 –10 –20 –30 –40 –50 –60 –70 0 5 10 15 20 25 30 35 0 5 10 20 25 30 35 Figure 9 Figure 8 SIGNAL-TO-NOISE + DISTORTION vs FREQUENCY SIGNAL-TO-NOISE + DISTORTION vs FREQUENCY 80 AVDD = 5 V 70 60 50 40 30 20 10 0 SNRD – Signal-To-Noise Ratio + Distortion – dB SNRD – Signal-To-Noise Ratio + Distortion – dB 15 f – Frequency – kHz f – Frequency – kHz 70 AVDD = 3 V 60 50 40 30 20 10 0 0 5 10 15 20 25 30 35 0 5 f – Frequency – kHz 10 15 20 25 30 35 f – Frequency – kHz Figure 11 Figure 10 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 9 TLV5613 2.7 V TO 5.5 V 12-BIT PARALLEL DIGITAL-TO-ANALOG CONVERTER WITH POWER DOWN SLAS174A – DECEMBER 1997 – REVISED JULY 1998 DNL – Differential Nonlinearity – LSB TYPICAL CHARACTERISTICS 1 0.8 0.6 0.4 0.2 0 –0.2 –0.4 –0.6 –0.8 –1 0 500 1000 1500 2000 2500 3000 3500 4000 Code INL – Integral Nonlinearity – LSB Figure 12. Differential Nonlinearity 4 2 1.5 1 0.5 0 –0.5 –1 –1.5 –2 –4 0 500 1000 1500 2000 2500 Code Figure 13. Integral Nonlinearity 10 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 3000 3500 4000 TLV5613 2.7 V TO 5.5 V 12-BIT PARALLEL DIGITAL-TO-ANALOG CONVERTER WITH POWER DOWN SLAS174A – DECEMBER 1997 – REVISED JULY 1998 TYPICAL CHARACTERISTICS POWER DOWN SUPPLY CURRENT vs TIME 1 I DD – Supply Current – mA 0.1 0.01 0.001 0.0001 0.00001 0.000001 0 100 200 300 400 500 600 t – Time – ms Figure 14 APPLICATION INFORMATION general function The TLV5613 is a 12-bit, single supply DAC, based on a resistor string architecture. It consists of a parallel interface, speed and power down control logic, a resistor string and a rail-to-rail output buffer. The output voltage (full scale determined by reference) is given by: 2 REF CODE [V] 0x1000 Where REF is the reference voltage and CODE is the digital input value, range 0x000 to 0xFFF. A power on reset initially puts the internal latches to a defined state (all bits zero). parallel interface The device latches data on the positive edge of WE. It must be enabled with CS low. Whether the data is written to one of the DAC holding latches (MSW, LSW) or the control register, depends on the address bits A1 and A0. LDAC low updates the DAC with the value in the holding latch. LDAC is an asynchronous input and can be held low, if a separate update is not necessary. Two more asynchronous inputs, SPD and PWD control the settling times and the power down mode: SPD: PWD: Speed control Power control 1 → fast mode 1 → normal operation POST OFFICE BOX 655303 0 → slow mode 0 → power down • DALLAS, TEXAS 75265 11 TLV5613 2.7 V TO 5.5 V 12-BIT PARALLEL DIGITAL-TO-ANALOG CONVERTER WITH POWER DOWN SLAS174A – DECEMBER 1997 – REVISED JULY 1998 APPLICATION INFORMATION It is also possible to program the different modes (fast, slow, power down) and the DAC update latch using the control register. The following tables list the possible combination of the control signals and control bits. PIN BIT SPD SPD 0 0 Slow 0 1 Fast 1 0 Fast 1 1 Fast PIN BIT PWD PWD 0 0 0 1 Down 1 0 Normal 1 1 Down MODE POWER Down PIN BIT LDAC RLDAC 0 0 Transparent 0 1 Transparent 1 0 Hold 1 1 Transparent LATCH data format The TLV5613 writes data either to one of the DAC holding latches or to the control register depending on the address bits A1 and A0. ADDRESS BITS A0 0 0 DAC LSW holding 0 1 DAC MSW holding 1 0 Reserved 1 1 Control REGISTER D7 D6 D5 D4 D3 D2 D1 D0 X X X X X RLDAC PWD SPD X: Don’t care SPD: Speed control bit PWD: Power control bit RLDAC: Load DAC latch 12 A1 1 → fast mode 1 → power down 1 → latch transparent 0 → slow mode 0 → normal operation 0 → DAC latch controlled by LDAC pin POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 TLV5613 2.7 V TO 5.5 V 12-BIT PARALLEL DIGITAL-TO-ANALOG CONVERTER WITH POWER DOWN SLAS174A – DECEMBER 1997 – REVISED JULY 1998 APPLICATION INFORMATION layout considerations To achieve the best performance, it is recommended to have separate power planes for GND, AVDD, and DVDD. Figure 15 shows how to lay out the power planes for the TLV5613. As a general rule, digital and analog signals should be separated as wide as possible. To avoid crosstalk, analog and digital traces must not be routed in parallel. The two positive power planes ( AVDD and DVDD) should be connected together at one point with a ferrite bead. A 100-nF ceramic low series inductance capacitor between DVDD and GND and a 1-µF tantalum capacitor between AVDD and GND as close as possible to the supply pins are recommended for optimal performance. DVDD AVDD Figure 15. TLV5613 Board Layout linearity, offset, and gain error using single end supplies When an amplifier is operated from a single supply, the voltage offset can still be either positive or negative. With a positive offset, the output voltage changes on the first code change. With a negative offset the output voltage may not change with the first code depending on the magnitude of the offset voltage. The output amplifier attempts to drive the output to a negative voltage. However, because the most negative supply rail is ground, the output cannot drive below ground and clamps the output at 0 V. The output voltage remains at zero until the input code value produces a sufficient positive output voltage to overcome the negative offset voltage, resulting in the transfer function shown in Figure 16. Output Voltage 0V DAC Code Negative Offset Figure 16. Effect of Negative Offset (Single Supply) POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 13 TLV5613 2.7 V TO 5.5 V 12-BIT PARALLEL DIGITAL-TO-ANALOG CONVERTER WITH POWER DOWN SLAS174A – DECEMBER 1997 – REVISED JULY 1998 APPLICATION INFORMATION This offset error, not the linearity error, produces this breakpoint. The transfer function would have followed the dotted line if the output buffer could drive below the ground rail. For a DAC, linearity is measured between zero input code (all inputs 0) and full scale code (all inputs 1) after offset and full scale are adjusted out or accounted for in some way. However, single supply operation does not allow for adjustment when the offset is negative due to the breakpoint in the transfer function. So the linearity is measured between full scale code and the lowest code that produces a positive output voltage. TLV5613 interfaced to an Intel MCS251 controller The circuit in Figure 17 shows how to interface the TLV5613 to an Intel MCS251 microcontroller. The address bus and the data bus of the controller are multiplexed on port 0 (non page mode) to save port pins. To separate the address bits and the data bits, the controller provides a dedicated signal, address latch enable (ALE), which is connected to a latch at port 0. An address decoder is required to generate the chip select signal for the TLV5613. In this example, a simple 3-to-8 decoder (74AC138) is used for the interface as shown in Figure 17. The DAC is memory mapped at addresses 0x8000/1/2/3 within the data memory address space and mirrored every 32 address locations (0x8020/1/2/3, 0x8040/1/2/3, etc.). In a typical microcontroller system, programmable logic should be used to generate the chip select signals for the entire system. The data pins and the WE pin of the TLV5613 can be connected directly to the multiplexed address and data bus and the WR signal of the controller. LDAC is held high so that the output voltage is updated using the RLDAC bit in the control register. Hardware power down mode is deactivated permanently by pulling PWD to DVDD. 8xC251 8 P2 A(15–8) 16 8 8 P0 AD(7–0) AD(7–0) 74AC138 74AC373 8 D(7–0) Q(7–0) A2 A3 8 Y(7–0) A CS(7–0) B A4 C DVDD TLV5613 ALE LE A(15–0) OE A15 DVDD G1 G2A G2B 2 A1–0)G2A SPD D(7–0) PWD CS OUT WE WR DVDD REF191 REF Figure 17. TLV5613 Interfaced to an Intel MCS251 Controller MCS is a registered trademark of Intel Corporation. 14 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 LDAC RL TLV5613 2.7 V TO 5.5 V 12-BIT PARALLEL DIGITAL-TO-ANALOG CONVERTER WITH POWER DOWN SLAS174A – DECEMBER 1997 – REVISED JULY 1998 APPLICATION INFORMATION software In the following example, the code generates a waveform at 500 KSPS with 500 samples stored in a table within the program memory space of the microcontroller. The period of the waveform is 1 ms. The waveform data is located in the program memory space from address 01000h to address 013E8h (2 × 500 = 1000 = 03E8h) beginning with the MSW of the first 16-bit word (the 4 MSBs are ignored), followed by the LSW. Two bytes are required for each DAC word (the table is not shown in the code example). The program consists of two parts: D D A main routine, which is executed after reset and which initializes the timer and the interrupt system of the microcontroller. An interrupt service routine, which reads a new value from the waveform table and writes it to the DAC. This example uses timer 0 in mode 3 (8-bit timer with auto reload). The clock of the timer is derived from the system clock and has a frequency of fosc/12. The timer overrun frequency ftim is given by the following equation: f f OSC + tim 12(256–Reload) and the reload value is given by Reload + 256– 12fOSC f tim To get a timer overrun frequency of 500 kHz at a system clock of 24 MHz, the reload value is: Reload + 256 – 12 240.5 + 256–4 + 252 + 0FCh With this value, the timer generates an interrupt every 2 µs. The corresponding service routine T0_isr reads a sample from program memory and writes it to the DAC. First, it disables the update of the DAC output by clearing the RLDAC bit in the control register. Then it reads the MSW and the LSW from the waveform table and stores it in the MSW and LSW register of the TLV5613. The write cycle is completed by setting the RLDAC bit, which updates the DAC output. At the end of the interrupt service routine, the pointer to the waveform samples is increased and is checked to determine if it has reached the end of the table. If the pointer has reached the end of the table, the pointer is set to the start address of the table. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 15 TLV5613 2.7 V TO 5.5 V 12-BIT PARALLEL DIGITAL-TO-ANALOG CONVERTER WITH POWER DOWN SLAS174A – DECEMBER 1997 – REVISED JULY 1998 APPLICATION INFORMATION ;************************************************************************ ;* Title : Waveform generation with TLV5613 * ;* Version: 1.0 ;* MCU * : Intel MCS251, MCS51 * ;* 1998 Texas Instruments Inc. * ;************************************************************************ TABLE_START EQU 01000h ;start address of waveform data TABLE_END_H EQU 013h ;high byte – end address of waveform data TABLE_END_L EQU 0E8h ;low byte RELOAD EQU 0FCh ;timer reload value ORG 00000h ;entry point JMP main ;jump to main program ORG 0000bh ;timer0 (T0) interrupt vector JMP T0_isr ;jump to T0 interrupt service routine – end address of waveform data ;–––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––– ;main: setup timer and interrupt, loop forever ;–––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––– main: CLR A MOV A, IE0 ;disable all interrupts CLR TCON.4 ;stop T0 MOV A, #002h MOV TMOD, A ;set T0 to auto reload mode MOV A, #RELOAD MOV TH0, A ;set T0 reload value MOV TL0, A ;set T0 start value MOV P2, #080h ;set A15 of address bus to select DAC MOV DPTR, #TABLE_START ;set data pointer to start of wave form data idle_loop: 16 SETB IE0.1 ;enable T0 interrupt SETB IE0.7 ;enable interrupts SETB TCON.4 ;start T0 SJMP idle_loop ;loop forever POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 TLV5613 2.7 V TO 5.5 V 12-BIT PARALLEL DIGITAL-TO-ANALOG CONVERTER WITH POWER DOWN SLAS174A – DECEMBER 1997 – REVISED JULY 1998 APPLICATION INFORMATION ;–––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––– ;T0_isr: will be called on every timer interrupt. ;fetches a new 16–bit value from program memory space and writes it ;to the DAC. If end of table is reached, sets DPTR to table start addr. ;–––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––– T0_isr: MOV R0, #003h ;select DAC control register MOV A, #001h ;RLDAC=0, PWD=0, SPD=1 ;no DAC update, normal operation, fast mode MOVX @R0, A ;write Accu to DAC control register MOV R0, #001h ;select DAC MSW register CLR A MOVC A, @A+DPTR ;get MSW from code memory MOVX @R0, A ;write Accu to DAC MSW register INC DPTR ;set DPTR to LSW data MOV R0, #000h ;select DAC LSW register CLR A MOVC A, @A+DPTR ;get LSW from code memory MOVX @R0, A ;write Accu to DAC LSW register MOV R0, #003h ;select DAC control register (to update DAC) MOV A, #005h ;DAC update, normal operation, fast mode MOVX @R0, A ;write Accu to DAC control register INC DPTR ;set DPTR to next MSW ;test end of table MOV A, DPL CJNE A, #TABLE_END_L, T0_isr_end MOV A, DPH CJNE A, #TABLE_END_H, T0_isr_end MOV DPTR, #TABLE_START ;end of table reached –> start again T0_isr_end: RETI END POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 17 TLV5613 2.7 V TO 5.5 V 12-BIT PARALLEL DIGITAL-TO-ANALOG CONVERTER WITH POWER DOWN SLAS174A – DECEMBER 1997 – REVISED JULY 1998 APPLICATION INFORMATION definitions of specifications and terminology integral nonlinearity (INL) The relative accuracy or integral nonlinearity (INL), sometimes referred to as linearity error, is the maximum deviation of the output from the line between zero and full scale excluding the effects of zero code and full-scale errors. differential nonlinearity (DNL) The differential nonlinearity (DNL), sometimes referred to as differential error, is the difference between the measured and ideal 1 LSB amplitude change of any two adjacent codes. Monotonic means the output voltage changes in the same direction (or remains constant) as a change in the digital input code. zero-scale error (EZS) Zero-scale error is defined as the deviation of the output from 0 V at a digital input value of 0. gain error (EG) Gain error is the error in slope of the DAC transfer function. signal-to-noise ratio + distortion (SINAD) Signal-to-noise ratio + distortion is the ratio of the rms value of the output signal to the rms sum of all other spectral components below the Nyquist frequency, including harmonics but excluding dc. The value for SINAD is expressed in decibels. spurious free dynamic range (SFDR) Spurious free dynamic range is the difference between the rms value of the output signal and the rms value of the spurious signal within a specified bandwidth. The value for SFDR is expressed in decibels. total harmonic distortion (THD) Total harmonic distortion is the ratio of the rms sum of the first six harmonic components to the rms value of the fundamental signal and is expressed in decibels. 18 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 TLV5613 2.7 V TO 5.5 V 12-BIT PARALLEL DIGITAL-TO-ANALOG CONVERTER WITH POWER DOWN SLAS174A – DECEMBER 1997 – REVISED JULY 1998 MECHANICAL DATA DW (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE 16 PIN SHOWN 0.050 (1,27) 0.020 (0,51) 0.014 (0,35) 16 0.010 (0,25) M 9 0.419 (10,65) 0.400 (10,15) 0.010 (0,25) NOM 0.299 (7,59) 0.293 (7,45) Gage Plane 0.010 (0,25) 1 8 0°– 8° A 0.050 (1,27) 0.016 (0,40) Seating Plane 0.104 (2,65) MAX 0.012 (0,30) 0.004 (0,10) 0.004 (0,10) PINS ** 16 20 24 A MAX 0.410 (10,41) 0.510 (12,95) 0.610 (15,49) A MIN 0.400 (10,16) 0.500 (12,70) 0.600 (15,24) DIM 4040000 / D 02/98 NOTES: A. B. C. D. All linear dimensions are in inches (millimeters). This drawing is subject to change without notice. Body dimensions do not include mold flash or protrusion not to exceed 0.006 (0,15). Falls within JEDEC MS-013 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 19 TLV5613 2.7 V TO 5.5 V 12-BIT PARALLEL DIGITAL-TO-ANALOG CONVERTER WITH POWER DOWN SLAS174A – DECEMBER 1997 – REVISED JULY 1998 PW (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE 14 PIN SHOWN 0,30 0,19 0,65 14 0,10 M 8 0,15 NOM 4,50 4,30 6,60 6,20 Gage Plane 0,25 1 7 0°– 8° 0,75 0,50 A Seating Plane 1,20 MAX 0,10 0,05 MIN PINS ** 8 14 16 20 24 28 A MAX 3,10 5,10 5,10 6,60 7,90 9,80 A MIN 2,90 4,90 4,90 6,40 7,70 9,60 DIM 4040064 / E 08/96 NOTES: A. B. C. D. 20 All linear dimensions are in millimeters. This drawing is subject to change without notice. Body dimensions do not include mold flash or protrusion not to exceed 0,15. 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