TLV5638 2.7 V TO 5.5 V LOW POWER DUAL 12-BIT DIGITAL-TO-ANALOG CONVERTER WITH INTERNAL REFERENCE AND POWER DOWN SLAS225A – JUNE 1999 – REVISED JANUARY 2000 features 8 2 7 3 6 4 5 VDD OUTB REF AGND 2 1 20 19 NC V DD 3 NC 4 18 NC SCLK 5 17 OUTB NC 6 16 NC CS 7 15 REF NC 8 14 NC NC NC description 10 11 12 13 AGND 9 NC Digital Servo Control Loops Digital Offset and Gain Adjustment Industrial Process Control Machine and Motion Control Devices Mass Storage Devices NC FK PACKAGE (TOP VIEW) applications D D D D D 1 DIN D D DIN SCLK CS OUTA OUTA D Dual 12-Bit Voltage Output DAC Programmable Internal Reference Programmable Settling Time: 1 µs in Fast Mode, 3.5 µs in Slow Mode Compatible With TMS320 and SPI Serial Ports Differential Nonlinearity <0.5 LSB Typ Monotonic Over Temperature NC D D D D, JG PACKAGE (TOP VIEW) The TLV5638 is a dual 12-bit voltage output DAC with a flexible 3-wire serial interface. The serial interface allows glueless interface to TMS320 and SPI, QSPI, and Microwire serial ports. It is programmed with a 16-bit serial string containing 4 control and 12 data bits. The resistor string output voltage is buffered by a x2 gain rail-to-rail output buffer. The buffer features a Class AB output stage to improve stability and reduce settling time. The programmable settling time of the DAC allows the designer to optimize speed vs power dissipation. With its on-chip programmable precision voltage reference, the TLV5638 simplifies overall system design. Because of its ability to source up to 1 mA, the reference can also be used as a system reference. Implemented with a CMOS process, the device is designed for single supply operation from 2.7 V to 5.5 V. It is available in an 8-pin SOIC package to reduce board space in standard commercial, industrial, and automotive temperature ranges. It is also available in JG and FK packages in the military temperature range. AVAILABLE OPTIONS PACKAGE TA SOIC (D) CERAMIC DIP (JG) 20 PAD LCCC (FK) 0°C to 70°C TLV5638CD — — –40°C to 85°C TLV5638ID — — –40°C to 125°C TLV5638QD TLV5638QDR — — –55°C to 125°C — TLV5638MJG TLV5638MFK Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. SPI and QSPI are trademarks of Motorola, Inc. Microwire is a trademark of National Semiconductor Corporation. Copyright 2000, Texas Instruments Incorporated PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. On products compliant to MIL-PRF-38535, all parameters are tested unless otherwise noted. On all other products, production processing does not necessarily include testing of all parameters. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1 TLV5638 2.7 V TO 5.5 V LOW POWER DUAL 12-BIT DIGITAL-TO-ANALOG CONVERTER WITH INTERNAL REFERENCE AND POWER DOWN SLAS225A – JUNE 1999 – REVISED JANUARY 2000 functional block diagram REF AGND VDD PGA With Output Enable Voltage Bandgap Power-On Reset Power and Speed Control 2 2 2-Bit Control Latch x2 OUTA x2 OUTB DIN 12-Bit DAC A Latch 12 SCLK Serial Interface and Control CS 12 12 Buffer 12 12-Bit DAC B Latch 12 Terminal Functions TERMINAL NAME NO. I/O/P DESCRIPTION AGND 5 P Ground CS 3 I Chip select. Digital input active low, used to enable/disable inputs DIN 1 I Digital serial data input OUT A 4 O DAC A analog voltage output OUT B 7 O DAC B analog voltage output REF 6 I/O Analog reference voltage input/output SCLK 2 I Digital serial clock input VDD 8 P Positive power supply 2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 TLV5638 2.7 V TO 5.5 V LOW POWER DUAL 12-BIT DIGITAL-TO-ANALOG CONVERTER WITH INTERNAL REFERENCE AND POWER DOWN SLAS225A – JUNE 1999 – REVISED JANUARY 2000 absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage (VDD to AGND) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V Reference input voltage range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to VDD + 0.3 V Digital input voltage range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to VDD + 0.3 V Operating free-air temperature range, TA: TLV5638C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 70°C TLV5638I . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –40°C to 85°C TLV5638Q . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –40°C to 125°C TLV5638M . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –55°C to 125°C Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260°C † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. DISSIPATION RATING TABLE PACKAGE TA ≤ 25°C POWER RATING DERATING FACTOR ABOVE TA = 25°C‡ TA = 70°C POWER RATING TA = 85°C POWER RATING TA = 125°C POWER RATING D 635 mW 5.08 mW/°C 407 mW 330 mW 127 mW FK 1375 mW 11.00 mW/°C 880 mW 715 mW 275 mW JG 1050 mW 8.40 mW/°C 672 mW 546 mW 210 mW ‡ This is the inverse of the traditional Junction-to-Ambient thermal Resistance (RΘJA). Thermal Resistances are not production tested and are for informational purposes only. recommended operating conditions Supply voltage voltage, VDD VDD = 5 V VDD = 3 V Power on reset, POR High-level digital input voltage, VIH Low-level digital input voltage, VIL Reference voltage, Vref to REF terminal Reference voltage, Vref to REF terminal MIN NOM MAX 4.5 5 5.5 V 2.7 3 3.3 V *2 V *0.55 VDD = 2.7 V to 5.5 V VDD = 2.7 V to 5.5 V 2 VDD = 5 V (see Note 1) VDD = 3 V (see Note 1) Load resistance, RL 2.048 AGND 1.024 0.8 V VDD –1.5 VDD – 1.5 V 2 Clock frequency, fCLK TLV5638C free air temperature, temperature TA Operating free-air V AGND Load capacitance, CL UNIT V kΩ 100 pF 20 MHz 0 70 TLV5638I –40 85 TLV5638Q –40 125 TLV5638M –55 125 °C *This parameter is not tested for Q and M suffix devices. NOTE 1: Due to the x2 output buffer, a reference input voltage ≥ (VDD–0.4 V)/2 causes clipping of the transfer function. The output buffer of the internal reference must be disabled, if an external reference is used. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 3 TLV5638 2.7 V TO 5.5 V LOW POWER DUAL 12-BIT DIGITAL-TO-ANALOG CONVERTER WITH INTERNAL REFERENCE AND POWER DOWN SLAS225A – JUNE 1999 – REVISED JANUARY 2000 electrical characteristics over recommended operating conditions, Vref = 2.048 V, Vref = 1.024 V (unless otherwise noted) power supply PARAMETER TLV5638C, TLV5638I TEST CONDITIONS MIN IDD Power supply current No load load, All inputs = AGND or VDD, DAC latch = 0x800 Power supply rejection ratio TYP MAX MIN UNIT TYP MAX VDD = 5 V, Int. ref. Fast 4.3 5.2 4.3 5.4 Slow 2.2 2.7 2.2 2.7 VDD = 3 V, Int. ref. Fast 3.8 4.7 3.8 4.9 Slow 1.8 2.3 1.8 2.3 VDD = 5 V, Ext. ref. Fast 3.9 4.8 3.9 5.0 Slow 1.8 2.2 1.8 2.2 VDD = 3 V, Ext. ref. Fast 3.5 4.3 3.5 4.5 Slow 1.5 1.9 1.5 1.9 0.01 10 0.01 10 Power-down supply current PSRR TLV5638Q, TLV5638M Zero scale, See Note 2 –65 –65 Full scale, –65 –65 See Note 3 mA mA mA mA µA dB NOTES: 2. Power supply rejection ratio at zero scale is measured by varying VDD and is given by: PSRR = 20 log [(EZS(VDDmax) – EZS(VDDmin))/VDDmax] 3. Power supply rejection ratio at full scale is measured by varying VDD and is given by: PSRR = 20 log [(EG(VDDmax) – EG(VDDmin))/VDDmax] static DAC specifications PARAMETER TEST CONDITIONS TYP MAX UNIT C and I suffixes ±1.7 ±4 LSB Q and M suffixes ±1.7 ±6 LSB ±0.4 ±1 LSB ±24 mV Resolution MIN 12 INL Integral nonlinearity, nonlinearity end point adjusted See Note 4 DNL Differential nonlinearity See Note 5 EZS EZS TC Zero-scale error (offset error at zero scale) See Note 6 Zero-scale-error temperature coefficient See Note 7 EG Gain error See Note 8 bits 10 ppm/°C ±0.6 % full scale V EG TC Gain error temperature coefficient See Note 9 10 ppm/°C NOTES: 4. The relative accuracy or integral nonlinearity (INL) sometimes referred to as linearity error, is the maximum deviation of the output from the line between zero and full scale excluding the effects of zero code and full-scale errors. Tested from code 32 to 4095. 5. The differential nonlinearity (DNL) sometimes referred to as differential error, is the difference between the measured and ideal 1 LSB amplitude change of any two adjacent codes. Monotonic means the output voltage changes in the same direction (or remains constant) as a change in the digital input code. 6. Zero-scale error is the deviation from zero voltage output when the digital input code is zero. 7. Zero-scale-error temperature coefficient is given by: EZS TC = [EZS (Tmax) – EZS (Tmin)]/Vref × 106/(Tmax – Tmin). 8. Gain error is the deviation from the ideal output (2Vref – 1 LSB) with an output load of 10 kΩ excluding the effects of the zero-error. 9. Gain temperature coefficient is given by: EG TC = [EG(Tmax) – EG (Tmin)]/Vref × 106/(Tmax – Tmin). 4 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 TLV5638 2.7 V TO 5.5 V LOW POWER DUAL 12-BIT DIGITAL-TO-ANALOG CONVERTER WITH INTERNAL REFERENCE AND POWER DOWN SLAS225A – JUNE 1999 – REVISED JANUARY 2000 electrical characteristics over recommended operating conditions, Vref = 2.048 V, Vref = 1.024 V (unless otherwise noted) (continued) output specifications PARAMETER VO TEST CONDITIONS Output voltage MIN RL = 10 kΩ Output load regulation accuracy TYP 0 VO = 4.096 V, 2.048 V, MAX VDD–0.4 RL = 2 kΩ UNIT V ± 0.25 % full scale V reference pin configured as output (REF) PARAMETER Vref(OUTL) Vref(OUTH) Low reference voltage Iref(source) Iref(sink) Output source current TEST CONDITIONS High reference voltage VDD > 4.75 V MIN TYP MAX UNIT 1.003 1.024 1.045 V 2.027 2.048 2.069 V 1 Output sink current –1 mA Load capacitance PSRR 100 Power supply rejection ratio mA –65 pF dB reference pin configured as input (REF) PARAMETER VI RI Input voltage CI Input capacitance TEST CONDITIONS MIN TYP 0 Input resistance Reference input bandwidth REF = 0 0.2 2 Vpp + 1.024 1 024 V dc Reference feedthrough REF = 1 Vpp at 1 kHz + 1.024 V dc (see Note 10) MAX VDD–1.5 UNIT V 10 MΩ 5 pF Fast 1.3 MHz Slow 525 kHz – 80 dB NOTE 10: Reference feedthrough is measured at the DAC output with an input code = 0x000. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 5 TLV5638 2.7 V TO 5.5 V LOW POWER DUAL 12-BIT DIGITAL-TO-ANALOG CONVERTER WITH INTERNAL REFERENCE AND POWER DOWN SLAS225A – JUNE 1999 – REVISED JANUARY 2000 electrical characteristics over recommended operating conditions (unless otherwise noted) (Continued) digital inputs PARAMETER IIH IIL High-level digital input current Ci Input capacitance TEST CONDITIONS VI = VDD VI = 0 V Low-level digital input current MIN TYP MAX 1 UNIT µA µA –1 8 pF analog output dynamic performance PARAMETER TEST CONDITIONS CL = 100 pF,, TYP MAX Fast MIN 1 3 Slow 3.5 7 Fast 0.5 1.5 Slow 1 2 Fast 12 Slow 1.8 ts(FS) (FS) Output settling time, time full scale RL = 10 kΩ,, See Note 11 ts(CC) (CC) time code to code Output settling time, RL = 10 kΩ,, See Note 12 CL = 100 pF,, SR Slew rate RL = 10 kΩ,, See Note 13 CL = 100 pF,, Glitch energy DIN = 0 to 1, CS = VDD FCLK = 100 kHz, Signal-to-noise ratio 69 74 S/(N+D) Signal-to-noise + distortion 58 67 THD Total harmonic distortion fs = 480 kSPS,, fout = 1 kHz,, RL = 10 kΩ, CL = 100 pF Spurious free dynamic range –69 57 µs µs V/µs 5 SNR UNIT nV–s –57 dB 72 NOTES: 11. Settling time is the time for the output signal to remain within ± 0.5 LSB of the final measured value for a digital input code change of 0x020 to 0xFDF and 0xFDF to 0x020 respectively. Not tested, assured by design. 12. Settling time is the time for the output signal to remain within ± 0.5 LSB of the final measured value for a digital input code change of one count. Not tested, assured by design. 13. Slew rate determines the time it takes for a change of the DAC output from 10% to 90% full-scale voltage. digital input timing requirements MIN NOM MAX UNIT tsu(CS–CK) tsu(C16-CS) Setup time, CS low before first negative SCLK edge Setup time, 16th negative SCLK edge (when D0 is sampled) before CS rising edge 10 ns 10 ns twH twL SCLK pulse width high 25 ns SCLK pulse width low 25 ns tsu(D) th(D) Setup time, data ready before SCLK falling edge 10 ns Hold time, data held valid after SCLK falling edge 5 ns 6 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 TLV5638 2.7 V TO 5.5 V LOW POWER DUAL 12-BIT DIGITAL-TO-ANALOG CONVERTER WITH INTERNAL REFERENCE AND POWER DOWN SLAS225A – JUNE 1999 – REVISED JANUARY 2000 PARAMETER MEASUREMENT INFORMATION twL SCLK X 1 2 tsu(D) DIN X twH 3 4 5 15 X 16 th(D) D15 D14 D13 D12 D1 D0 X tsu(C16-CS) tsu(CS-CK) CS Figure 1. Timing Diagram TYPICAL CHARACTERISTICS SUPPLY CURRENT vs FREE-AIR TEMPERATURE POWER DOWN SUPPLY CURRENT vs TIME 4.5 2.4 4 2.2 I DD – Supply Current – mA I DD – Power Down Supply Current – mA 2.6 2 1.8 1.6 1.4 1.2 1 0.8 Fast Mode 3.5 3 2.5 2 Slow Mode 1.5 0.6 0.4 1 0.2 0 0 10 20 50 30 40 t – Time – µs 60 70 80 VDD = 5 V Vref = Int. 2 V Input Code = Full Scale (Both DACs) 0.5 –40 –30 –20 –10 0 10 20 30 40 50 60 70 80 90 TA – Free-Air Temperature – °C Figure 2 Figure 3 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 7 TLV5638 2.7 V TO 5.5 V LOW POWER DUAL 12-BIT DIGITAL-TO-ANALOG CONVERTER WITH INTERNAL REFERENCE AND POWER DOWN SLAS225A – JUNE 1999 – REVISED JANUARY 2000 TYPICAL CHARACTERISTICS OUTPUT VOLTAGE vs LOAD CURRENT SUPPLY CURRENT vs FREE-AIR TEMPERATURE 2.064 4.5 2.062 3.5 Fast Mode 3 2.5 2 Slow Mode 1.5 2.06 Slow Mode 2.058 2.056 2.054 2.052 1 2.05 0.5 –40 –30 –20 –10 0 10 20 30 40 50 60 70 80 90 TA – Free-Air Temperature – °C 0 0.5 1 1.5 2 2.5 3 3.5 4 3.5 4 Source Current – mA Figure 4 Figure 5 OUTPUT VOLTAGE vs LOAD CURRENT OUTPUT VOLTAGE vs LOAD CURRENT 3 4.128 VDD = 5 V Vref = Int. 2 V Input Code = 4095 Fast Mode VDD = 3 V Vref = Int. 1 V Input Code = 0 2.5 VO – Output Voltage – V 4.126 VO – Output Voltage – V VDD = 3 V Vref = Int. 1 V Input Code = 4095 Fast Mode VO – Output Voltage – V I DD – Supply Current – mA 4 VDD = 3 V Vref = Int. 1 V Input Code = Full Scale (Both DACs) 4.124 Slow Mode 4.122 4.12 4.118 Fast Mode 2 1.5 1 0.5 4.116 Slow Mode 0 4.114 0 0.5 1 1.5 2 2.5 3 3.5 4 0 0.5 1.5 2 2.5 Sink Current – mA Source Current – mA Figure 6 8 1 Figure 7 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 3 TLV5638 2.7 V TO 5.5 V LOW POWER DUAL 12-BIT DIGITAL-TO-ANALOG CONVERTER WITH INTERNAL REFERENCE AND POWER DOWN SLAS225A – JUNE 1999 – REVISED JANUARY 2000 TYPICAL CHARACTERISTICS OUTPUT VOLTAGE vs LOAD CURRENT TOTAL HARMONIC DISTORTION AND NOISE vs FREQUENCY THD+N – Total Harmonic Distortion and Noise – dB 5 VDD = 5 V Vref = Int. 2 V Input Code = 0 4.5 3.5 Fast Mode 3 2.5 2 1.5 1 0.5 Slow Mode 0 0 0.5 1 1.5 2 2.5 Sink Current – mA 3 3.5 4 VDD = 5 V Vref = 1 V dc + 1 V p/p Sinewave Output Full Scale –10 –20 –30 –40 –50 –60 Slow Mode –70 Fast Mode –80 –90 –100 100 1000 10000 100000 f – Frequency – Hz Figure 8 Figure 9 TOTAL HARMONIC DISTORTION vs FREQUENCY 0 THD – Total Harmonic Distortion – dB VO – Output Voltage – V 4 0 –10 VDD = 5 V Vref = 1 V dc + 1 V p/p Sinewave Output Full Scale –20 –30 –40 –50 –60 –70 Slow Mode –80 Fast Mode –90 –100 100 10000 1000 100000 f – Frequency – Hz Figure 10 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 9 TLV5638 2.7 V TO 5.5 V LOW POWER DUAL 12-BIT DIGITAL-TO-ANALOG CONVERTER WITH INTERNAL REFERENCE AND POWER DOWN SLAS225A – JUNE 1999 – REVISED JANUARY 2000 INL – Integral Nonlinearity Error – LSB TYPICAL CHARACTERISTICS INTEGRAL NONLINEARITY ERROR 4 3 2 1 0 –1 –2 –3 –4 0 1024 2048 3072 4096 Digital Code DNL – Differential Nonlinearily Error – LSB Figure 11 DIFFERENTIAL NONLINEARITY ERROR 1 0.8 0.6 0.4 0.2 0 –0.2 –0.4 –0.6 –0.8 –1 0 1024 2048 Digital Code 3072 4096 Figure 12 APPLICATION INFORMATION general function The TLV5638 is a dual 12-bit, single supply DAC, based on a resistor string architecture. It consists of a serial interface, a speed and power-down control logic, a programmable internal reference, a resistor string, and a rail-to-rail output buffer. The output voltage (full scale determined by reference) is given by: 2 REF CODE [V] 0x1000 Where REF is the reference voltage and CODE is the digital input value in the range 0x000 to 0xFFF. A power on reset initially puts the internal latches to a defined state (all bits zero). 10 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 TLV5638 2.7 V TO 5.5 V LOW POWER DUAL 12-BIT DIGITAL-TO-ANALOG CONVERTER WITH INTERNAL REFERENCE AND POWER DOWN SLAS225A – JUNE 1999 – REVISED JANUARY 2000 APPLICATION INFORMATION serial interface A falling edge of CS starts shifting the data bit-per-bit (starting with the MSB) to the internal register on the falling edges of SCLK. After 16 bits have been transferred or CS rises, the content of the shift register is moved to the target latches (DAC A, DAC B, BUFFER, CONTROL), depending on the control bits within the data word. Figure 13 shows examples of how to connect the TLV5638 to TMS320, SPI, and Microwire. TMS320 DSP FSX DX CLKX TLV5638 CS DIN SCLK SPI I/O MOSI SCK TLV5638 CS DIN SCLK Microwire I/O SO SK TLV5638 CS DIN SCLK Figure 13. Three-Wire Interface Notes on SPI and Microwire: Before the controller starts the data transfer, the software has to generate a falling edge on the pin connected to FS. If the word width is 8 bits (SPI and Microwire), two write operations must be performed to program the TLV5638. After the write operation(s), the holding registers or the control register are updated automatically on the 16th positive clock edge. serial clock frequency and update rate The maximum serial clock frequency is given by: f sclkmax +t )t 1 whmin wlmin + 20 MHz The maximum update rate is: f updatemax + 16 ǒt 1 whmin )t Ǔ+ 1.25 MHz wlmin Note, that the maximum update rate is just a theoretical value for the serial interface, as the settling time of the TLV5638 has to be considered, too. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 11 TLV5638 2.7 V TO 5.5 V LOW POWER DUAL 12-BIT DIGITAL-TO-ANALOG CONVERTER WITH INTERNAL REFERENCE AND POWER DOWN SLAS225A – JUNE 1999 – REVISED JANUARY 2000 APPLICATION INFORMATION data format The 16-bit data word for the TLV5638 consists of two parts: D D Program bits (D15..D12) New data (D11..D0) D15 D14 D13 D12 R1 SPD PWR R0 SPD: Speed control bit PWR: Power control bit D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 12 Data bits 1 → fast mode 1 → power down 0 → slow mode 0 → normal operation The following table lists the possible combination of the register select bits: register select bits R1 R0 REGISTER 0 0 Write data to DAC B and BUFFER 0 1 Write data to BUFFER 1 0 Write data to DAC A and update DAC B with BUFFER content 1 1 Write data to control register The meaning of the 12 data bits depends on the register. If one of the DAC registers or the BUFFER is selected, then the 12 data bits determine the new DAC value: data bits: DAC A, DAC B and BUFFER D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 New DAC Value If control is selected, then D1, D0 of the 12 data bits are used to program the reference voltage: data bits: CONTROL D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 X X X X X X X X X X REF1 REF0 X: don’t care REF1 and REF0 determine the reference source and, if internal reference is selected, the reference voltage. reference bits REF1 REF0 REFERENCE 0 0 External 0 1 1.024 V 1 0 2.048 V 1 1 External CAUTION: If external reference voltage is applied to the REF pin, external reference MUST be selected. 12 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 TLV5638 2.7 V TO 5.5 V LOW POWER DUAL 12-BIT DIGITAL-TO-ANALOG CONVERTER WITH INTERNAL REFERENCE AND POWER DOWN SLAS225A – JUNE 1999 – REVISED JANUARY 2000 APPLICATION INFORMATION Examples of operation: D Set DAC A output, select fast mode, select internal reference at 2.048 V: 1. Set reference voltage to 2.048 V (CONTROL register): D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 1 1 0 1 0 0 0 0 0 0 0 0 0 0 1 0 D6 D5 D4 D3 D2 D1 D0 2. Write new DAC A value and update DAC A output: D15 D14 D13 D12 1 1 0 0 D11 D10 D9 D8 D7 New DAC A output value The DAC A output is updated on the rising clock edge after D0 is sampled. To output data consecutively using the same DAC configuration, it is not necessary to program the CONTROL register again. D Set DAC B output, select fast mode, select external reference: 3. Select external reference (CONTROL register): D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 1 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 D4 D3 D2 D1 D0 4. Write new DAC B value to BUFFER and update DAC B output: D15 D14 D13 D12 0 1 0 0 D11 D10 D9 D8 D7 D6 D5 New BUFFER content and DAC B output value The DAC A output is updated on the rising clock edge after D0 is sampled. To output data consecutively using the same DAC configuration, it is not necessary to program the CONTROL register again. D Set DAC A value, set DAC B value, update both simultaneously, select slow mode, select internal reference at 1.024 V: 1. Set reference voltage to 1.024 V (CONTROL register): D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 1 D8 D7 D6 D5 D4 D3 D2 D1 D0 D4 D3 D2 D1 D0 2. Write data for DAC B to BUFFER: D15 D14 D13 D12 0 0 0 1 D11 D10 D9 New DAC B value 3. Write new DAC A value and update DAC A and B simultaneously: D15 D14 D13 D12 1 0 0 0 D11 D10 D9 D8 D7 D6 D5 New DAC A value POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 13 TLV5638 2.7 V TO 5.5 V LOW POWER DUAL 12-BIT DIGITAL-TO-ANALOG CONVERTER WITH INTERNAL REFERENCE AND POWER DOWN SLAS225A – JUNE 1999 – REVISED JANUARY 2000 APPLICATION INFORMATION Examples of operation: (continued) Both outputs are updated on the rising clock edge after D0 from the DAC A data word is sampled. To output data consecutively using the same DAC configuration, it is not necessary to program the CONTROL register again. D Set power-down mode: D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 X X 1 X X X X X X X X X X X X X X = Don’t care linearity, offset, and gain error using single ended supplies When an amplifier is operated from a single supply, the voltage offset can still be either positive or negative. With a positive offset, the output voltage changes on the first code change. With a negative offset, the output voltage may not change with the first code, depending on the magnitude of the offset voltage. The output amplifier attempts to drive the output to a negative voltage. However, because the most negative supply rail is ground, the output cannot drive below ground and clamps the output at 0 V. The output voltage then remains at zero until the input code value produces a sufficient positive output voltage to overcome the negative offset voltage, resulting in the transfer function shown in Figure 14. Output Voltage 0V DAC Code Negative Offset Figure 14. Effect of Negative Offset (Single Supply) This offset error, not the linearity error, produces this breakpoint. The transfer function would have followed the dotted line if the output buffer could drive below the ground rail. For a DAC, linearity is measured between zero-input code (all inputs 0) and full-scale code (all inputs 1) after offset and full scale are adjusted out or accounted for in some way. However, single supply operation does not allow for adjustment when the offset is negative due to the breakpoint in the transfer function. So the linearity is measured between full-scale code and the lowest code that produces a positive output voltage. 14 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 TLV5638 2.7 V TO 5.5 V LOW POWER DUAL 12-BIT DIGITAL-TO-ANALOG CONVERTER WITH INTERNAL REFERENCE AND POWER DOWN SLAS225A – JUNE 1999 – REVISED JANUARY 2000 APPLICATION INFORMATION definitions of specifications and terminology integral nonlinearity (INL) The relative accuracy or integral nonlinearity (INL), sometimes referred to as linearity error, is the maximum deviation of the output from the line between zero and full scale excluding the effects of zero code and full-scale errors. differential nonlinearity (DNL) The differential nonlinearity (DNL), sometimes referred to as differential error, is the difference between the measured and ideal 1 LSB amplitude change of any two adjacent codes. Monotonic means the output voltage changes in the same direction (or remains constant) as a change in the digital input code. zero-scale error (EZS) Zero-scale error is defined as the deviation of the output from 0 V at a digital input value of 0. gain error (EG) Gain error is the error in slope of the DAC transfer function. total harmonic distortion (THD) THD is the ratio of the rms value of the first six harmonic components to the value of the fundamental signal. The value for THD is expressed in decibels. signal-to-noise ratio + distortion (S/N+D) S/N+D is the ratio of the rms value of the output signal to the rms sum of all other spectral components below the Nyquist frequency, including harmonics but excluding dc. The value for S/N+D is expressed in decibels. spurious free dynamic range (SFDR) Spurious free dynamic range is the difference between the rms value of the output signal and the rms value of the largest spurious signal within a specified bandwidth. The value for SFDR is expressed in decibels. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 15 TLV5638 2.7 V TO 5.5 V LOW POWER DUAL 12-BIT DIGITAL-TO-ANALOG CONVERTER WITH INTERNAL REFERENCE AND POWER DOWN SLAS225A – JUNE 1999 – REVISED JANUARY 2000 MECHANICAL DATA D (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE 14 PINS SHOWN 0.050 (1,27) 0.020 (0,51) 0.014 (0,35) 14 0.010 (0,25) M 8 0.008 (0,20) NOM 0.244 (6,20) 0.228 (5,80) 0.157 (4,00) 0.150 (3,81) Gage Plane 0.010 (0,25) 1 7 0°– 8° A 0.044 (1,12) 0.016 (0,40) Seating Plane 0.069 (1,75) MAX 0.010 (0,25) 0.004 (0,10) PINS ** 0.004 (0,10) 8 14 16 A MAX 0.197 (5,00) 0.344 (8,75) 0.394 (10,00) A MIN 0.189 (4,80) 0.337 (8,55) 0.386 (9,80) DIM 4040047 / D 10/96 NOTES: A. B. C. D. 16 All linear dimensions are in inches (millimeters). This drawing is subject to change without notice. Body dimensions do not include mold flash or protrusion, not to exceed 0.006 (0,15). Falls within JEDEC MS-012 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 TLV5638 2.7 V TO 5.5 V LOW POWER DUAL 12-BIT DIGITAL-TO-ANALOG CONVERTER WITH INTERNAL REFERENCE AND POWER DOWN SLAS225A – JUNE 1999 – REVISED JANUARY 2000 MECHANICAL INFORMATION FK (S-CQCC-N**) LEADLESS CERAMIC CHIP CARRIER 28 TERMINAL SHOWN 18 17 16 15 14 13 NO. OF TERMINALS ** 12 19 11 20 10 A B MIN MAX MIN MAX 20 0.342 (8,69) 0.358 (9,09) 0.307 (7,80) 0.358 (9,09) 28 0.442 (11,23) 0.458 (11,63) 0.406 (10,31) 0.458 (11,63) 21 9 22 8 44 0.640 (16,26) 0.660 (16,76) 0.495 (12,58) 0.560 (14,22) 23 7 52 0.739 (18,78) 0.761 (19,32) 0.495 (12,58) 0.560 (14,22) 24 6 68 25 5 0.938 (23,83) 0.962 (24,43) 0.850 (21,6) 0.858 (21,8) 84 1.141 (28,99) 1.165 (29,59) 1.047 (26,6) 1.063 (27,0) B SQ A SQ 26 27 28 1 2 3 4 0.080 (2,03) 0.064 (1,63) 0.020 (0,51) 0.010 (0,25) 0.020 (0,51) 0.010 (0,25) 0.055 (1,40) 0.045 (1,14) 0.045 (1,14) 0.035 (0,89) 0.045 (1,14) 0.035 (0,89) 0.028 (0,71) 0.022 (0,54) 0.050 (1,27) 4040140 / D 10/96 NOTES: A. B. C. D. E. All linear dimensions are in inches (millimeters). This drawing is subject to change without notice. This package can be hermetically sealed with a metal lid. The terminals are gold plated. Falls within JEDEC MS-004 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 17 TLV5638 2.7 V TO 5.5 V LOW POWER DUAL 12-BIT DIGITAL-TO-ANALOG CONVERTER WITH INTERNAL REFERENCE AND POWER DOWN SLAS225A – JUNE 1999 – REVISED JANUARY 2000 MECHANICAL INFORMATION JG (R-GDIP-T8) CERAMIC DUAL-IN-LINE PACKAGE 0.400 (10,20) 0.355 (9,00) 8 5 0.280 (7,11) 0.245 (6,22) 1 4 0.065 (1,65) 0.045 (1,14) 0.310 (7,87) 0.290 (7,37) 0.020 (0,51) MIN 0.200 (5,08) MAX Seating Plane 0.130 (3,30) MIN 0.063 (1,60) 0.015 (0,38) 0.100 (2,54) 0°–15° 0.023 (0,58) 0.015 (0,38) 0.014 (0,36) 0.008 (0,20) 4040107/C 08/96 NOTES: A. B. C. D. E. 18 All linear dimensions are in inches (millimeters). This drawing is subject to change without notice. This package can be hermetically sealed with a ceramic lid using glass frit. Index point is provided on cap for terminal identification only on press ceramic glass frit seal only. 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