RICHTEK TMK316BJ106ML

RT8278
2A, 24V, 3MHz Step-Down Converter
General Description
Features
Wide Operating Input Range : 4.5V to 24V
The RT8278 is a high voltage buck converter that can
support an input voltage range from 4.5V to 24V with output
current up to 2A. Current mode operation provides fast
transient response and eases loop stabilization.
Adjustable Output Voltage Range : 0.8V to 15V
Output Current up to 2A
25μ
μA Low Shutdown Current
High Efficiency up to 90% at 2.2MHz
Programmable Frequency : 220kHz to 3MHz
Internal Soft-Start
Stable with Low ESR Output Ceramic Capacitors
Thermal Shutdown Protection
Cycle-By-Cycle Over Current Protection
RoHS Compliant and Halogen Free
The chip provides protection functions such as cycle-bycycle current limiting and thermal shutdown protection.
In shutdown mode, the regulator only draws 25μA of
supply current. The RT8278 is available in a SOP-8
(Exposed Pad) package.
Ordering Information
RT8278
Applications
Package Type
SP : SOP-8 (Exposed Pad-Option 1)
DSL Modem for ADSL2+ Standard
Distributed Power Systems
Pre-Regulator for Linear Regulators
Lead Plating System
G : Green (Halogen Free and Pb Free)
Note :
Richtek products are :
`
Pin Configurations
RoHS compliant and compatible with the current require-
(TOP VIEW)
ments of IPC/JEDEC J-STD-020.
`
Suitable for use in SnPb or Pb-free soldering processes.
BOOT
Marking Information
RT8278
GSPYMDNN
RT8278GSP : Product Number
VIN
2
SW
GND
3
YMDNN : Date Code
GND
9
4
8
RT
7
EN
6
COMP
5
FB
SOP8 (Exposed Pad)
Typical Application Circuit
2
VIN
4.5V to 24V
CIN
10µF
Chip Enable
VIN
BOOT
RT8278
7 EN
1
SW 3
D
B220A
8 RT
RRT
24K
4,
9 (Exposed Pad)
CBOOT
L
10nF 2.2µH
FB 5
GND
COMP
6
CC
1nF
RC
36k
VOUT
3.3V/2A
R1
31.6k
COUT
22µF
R2
10k
NC
CP
DS8278-02 March 2011
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1
RT8278
VOUT (V)
10
8
5
3.3
2.5
1.8
1.5
1.2
Table 1. Recommended Component Selection for fSW = 2.2MHz
R1 (kΩ)
R2 (kΩ)
RC (kΩ)
CC (nF)
L (μH)
115
10
82
0.56
8.2
91
10
68
0.56
6.8
52.3
10
56
1.8
4.7
31.6
10
36
1
2.2
21.5
10
27
1.2
2
12.4
10
20
1.8
1.5
8.87
10
16
3.3
1.5
4.99
10
24
1
1
COUT (μF)
22
22
22
22
22
22
22
22
Functional Pin Description
Pin No.
Pin Name
1
BOOT
2
VIN
3
SW
4,
9 (Exposed Pad)
GND
5
FB
6
COMP
7
EN
8
RT
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2
Pin Function
Bootstrap Power Pin. BOOT supplies the drive for the high side N-MOSFET
switch. Connect a 10nF or greater capacitor from SW to BOOT to power the high
side switch.
Supply Input. VIN supplies the power to the IC, as well as the step-down
converter switches. Drive VIN with a 4.5V to 24V power source. Bypass VIN to
GND with a suitably large capacitor to eliminate noise on the input to the IC.
Switch Node. SW is the switching node that supplies power to the output.
Connect the output LC filter from SW to the output load. Note that a capacitor is
required from SW to BOOT to power the high side switch.
Ground. The exposed pad must be soldered to a large PCB and connected to
GND for maximum power dissipation.
Feedback Input. FB senses the output voltage to regulate. Drive FB with a
resistive voltage divider from the output voltage.
Compensation Node. COMP is used to compensate the regulation control loop.
Connect a series RC network from COMP to GND to compensate the regulation
control loop. In some cases, an additional capacitor from COMP to GND is
required.
Enable Input. EN is a digital input that turns the regulator on or off. Drive EN
higher than 1.4V to turn on the regulator, lower than 0.4V to turn off. For
automatic startup, leave EN unconnected.
Oscillator Resistor Input. Connecting a resistor to ground from this pin sets the
switching frequency.
DS8278-02 March 2011
RT8278
Function Block Diagram
VIN
1µA
Internal
Regulator
Oscillator
VA VCC
EN
10k
3V
Current Sense
Slope Comp Amplifier
+
-
Foldback
Control
BOOT
S
0.4V
+
UV
Comparator
+
1V
Shutdown
Comparator
0.8V
+
EA
-
VA
Q
+
R
Current
Comparator
+
SW
Q
GND
0.8V
-
FB
DS8278-02 March 2011
COMP RT
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3
RT8278
Absolute Maximum Ratings
(Note 1)
VIN ---------------------------------------------------------------------------------------------------------------- −0.3V to 26V
SW --------------------------------------------------------------------------------------------------------------- −0.3V to (VIN + 0.3V)
BOOT ----------------------------------------------------------------------------------------------------------- (VSW − 0.3V) to (VSW + 6V)
All Other Pins ------------------------------------------------------------------------------------------------- −0.3V to 6V
Power Dissipation, PD @ TA = 25°C
SOP-8 (Exposed Pad) -------------------------------------------------------------------------------------Package Thermal Resistance (Note 2)
SOP-8 (Exposed Pad), θJA --------------------------------------------------------------------------------SOP-8 (Exposed Pad), θJC -------------------------------------------------------------------------------Lead Temperature (Soldering, 10 sec.) -----------------------------------------------------------------Junction Temperature ---------------------------------------------------------------------------------------Storage Temperature Range ------------------------------------------------------------------------------ESD Susceptibility (Note 3)
HBM (Human Body Mode) --------------------------------------------------------------------------------MM (Machine Mode) -----------------------------------------------------------------------------------------
Recommended Operating Conditions
1.333W
75°C/W
28°C/W
260°C
150°C
−65°C to 150°C
2kV
200V
(Note 4)
Supply Input Voltage, VIN ----------------------------------------------------------------------------------- 4.5V to 24V
Junction Temperature Range ------------------------------------------------------------------------------- −40°C to 125°C
Ambient Temperature Range ------------------------------------------------------------------------------- −40°C to 85°C
Electrical Characteristics
(VIN = 12V, TA = 25°C, unless otherwise specified)
Parameter
Sym bol
Test Conditions
4.5V ≤ VIN ≤ 24V
Min
Typ
Max
Unit
0.784
0.8
0.816
V
Feedback Reference Voltage
VFB
Upper Switch On Resistance
RDS(ON)1
--
0.18
--
Ω
Lower Switch On Resistance
RDS(ON)2
--
10
--
Ω
Upper Switch Leakage
ILEAK
--
0
10
μA
Current Limit
ILIM
--
3
--
A
--
1.8
--
A/V
Current Sense
Transconductance
Output Current to Comp Pin
Voltage
Error Amplifier
Transconductance
Oscillator Frequency
gCS
gEA
ΔIC = ±10μA
--
920
--
μA/V
fSW
RRT = 24kΩ
--
2.2
--
MHz
VFB = 0V, RRT = 24kΩ
--
550
--
kHz
VUVLO
--
4.2
--
V
ΔV UV LO
--
430
--
mV
--
65
--
%
--
70
--
ns
Short Circuit Frequency
Under Voltage Lockout
Threshold Rising
Under Voltage Lockout
Threshold Hysteresis
VEN = 0V, VSW = 0V
Duty = 90%,
VBOO T − VSW = 4.8V
Maximum Duty Cycle
DMAX
Minimum On Time
tON
VFB = 0.7V, RRT = 24kΩ
To be continued
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DS8278-02 March 2011
RT8278
Parameter
EN T hreshold
Voltage
Symbol
Test Conditions
Min
Typ
Max
Unit
Logic-High
V IH
1.4
--
--
Logic-Low
V IL
--
--
0.4
--
1
--
μA
Enable Pull Up Current
V
Quiescent Current
IQ
VEN = 2V, V FB = 1V
--
0.8
1
mA
Shutdown Current
I SHDN
VEN = 0V
--
25
--
μA
--
150
--
°C
Thermal Shutdown
Note 1. Stresses listed as the above "Absolute Maximum Ratings" may cause permanent damage to the device. These are for
stress ratings. Functional operation of the device at these or any other conditions beyond those indicated in the
operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended
periods may remain possibility to affect device reliability.
Note 2. θJA is measured in natural convection at TA = 25°C on a high effective thermal conductivity four-layer test board of
JEDEC 51-7 thermal measurement standard. The measurement case position of θJC is on the exposed pad of the
package.
Note 3. Devices are ESD sensitive. Handling precaution is recommended.
Note 4. The device is not guaranteed to function outside its operating conditions.
DS8278-02 March 2011
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RT8278
Typical Operating Characteristics
Efficiency vs. Output Current
100
Efficiency vs. Output Current
100
VIN = 12V
90
90
VIN = 19V
70
80
Efficiency (%)
Efficiency (%)
80
60
50
40
30
20
70
60
50
40
30
20
10
10
VOUT = 5V, fSW = 2.2MHz
0
0.0
0.4
0.8
1.2
1.6
VIN = 12V, VOUT = 3.3V, fSW = 2.2MHz
0
2.0
0.0
0.4
0.8
Output Voltage vs. Output Current
2.0
Output Voltage vs. Input Voltage
3.365
5.09
3.360
5.06
5.03
VIN = 19V
5.00
VIN = 12V
4.97
4.94
Output Voltage (V)
Output Voltage (V)
1.6
3.370
5.12
4.91
3.355
3.350
3.345
3.340
3.335
3.330
3.325
3.320
4.88
3.315
4.85
3.310
0.0
0.4
0.8
1.2
1.6
IOUT = 0A
0
2.0
5
10
15
20
25
Input Voltage (V)
Output Current (A)
Reference Voltage vs. Temperature
Quiescent Current vs. Temperature
0.90
0.88
0.84
Reference Voltage (V)
Quiescent Current (mA)
1.2
Output Current (A)
Output Current (A)
0.80
0.76
0.72
0.68
0.86
0.82
0.78
0.74
0.64
VIN = 12V, RRT = Open
0.60
-50
-25
0
25
50
75
Temperature (°C)
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100
125
VIN = 12V, IOUT = 0A
0.70
-50
-25
0
25
50
75
100
125
Temperature (°C)
DS8278-02 March 2011
RT8278
Current Limit vs. Duty Cycle
Current Limit vs. Temperature
4.3
4.5
fSW = 2.2MHz
3.5
4.0
Peak Current (A)
Current Limit (A)
3.9
fSW = 400kHz
3.1
2.7
2.3
3.5
3.0
2.5
1.9
2.0
1.5
1.5
0
20
40
60
80
100
VIN = 12V, VOUT = 3.3V, fSW = 2.2MHz
-50
-25
0
25
50
75
Duty Cycle (%)
Temperature (°C)
Switching Frequency vs. Temperature
Output Ripple Voltage
100
125
Switching Frequency (MHz)1
2.4
VOUT
(10mV/Div)
2.3
2.2
VSW
(10V/Div)
2.1
2.0
1.9
VIN = 12V, VOUT = 3.3V,
lOUT = 0.3A, RRT = 24kΩ
1.8
-50
-25
0
25
50
75
100
IL
(1A/Div)
VIN = 12V, VOUT = 3.3V
IOUT = 2A, fSW = 2.2MHz
Time (200ns/Div)
125
Temperature (°C)
Load Transient Response
VIN = 12V, VOUT = 3.3V
lOUT = 0 to 2A, fSW = 2.2MHz
V OUT
(100mV/Div)
Load Transient Response
V OUT
(100mV/Div)
IOUT
(1A/Div)
IOUT
(1A/Div)
VIN12V,
= 12V,
= 3.3V
VIN =
VOUTVOUT
= 3.3V
1 2A,
to 2A,
2.2MHz
IOUTI=
1A=to
fSWfS==2.2MHz
OUT
Time (100μs/Div)
DS8278-02 March 2011
Time (100μs/Div)
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RT8278
Power On from EN
Power Off from EN
V EN
(2V/Div)
V EN
(2V/Div)
VIN = 12V, VOUT = 3.3V,
IOUT = 2A, fS = 2.2MHz
VIN = 12V, VOUT = 3.3V,
IOUT = 2A, fSW = 2.2MHz
V OUT
(1V/Div)
V OUT
(1V/Div)
IL
(2A/Div)
VIN = 12V, VOUT = 3.3V,
V = 12V, VOUT = 3.3V,
IOUT =IN 2A, fS = 2.2MHz
IOUT = 2A, fSW = 2.2MHz
Time (400μs/Div)
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IL
(2A/Div)
Time (40μs/Div)
DS8278-02 March 2011
RT8278
Application Information
The RT8278 is an asynchronous high voltage buck
converter that supports an input voltage range from 4.5V
to 24V with output current up to 2A.
Output Voltage Setting
The resistive voltage divider allows the FB pin to sense
the output voltage as shown in Figure 1.
VOUT
R1
FB
RT8278
R2
GND
Figure 1. Output Voltage Setting
The output voltage is set by an external resistive voltage
divider according to the following equation :
VOUT = VFB ⎛⎜ 1+ R1 ⎞⎟
⎝ R2 ⎠
where VFB is the feedback reference voltage (0.8V typ.).
External Bootstrap Diode
Connect a 10nF low ESR ceramic capacitor between the
BOOT pin and SW pin. This capacitor provides the gate
driver voltage for the high side MOSFET.
It is recommended to add an external bootstrap diode
between an external 5V voltage source and the BOOT
pin for efficiency improvement when input voltage is lower
than 5.5V or duty cycle is higher than 65% .The bootstrap
diode can be a low cost one such as IN4148 or BAT54.
The external voltage source must be fixed at 5V and can
be provided from the system or the output of the RT8278.
5V
BOOT
RT8278
10nF
SW
Operating Frequency
Selection of the operating frequency is a trade off between
efficiency and component size. High frequency operation
allows the use of smaller inductor and capacitor values.
Operation at lower frequency improves efficiency by
reducing internal gate charge and switching losses, but
requires larger inductance and/or capacitance to maintain
low output ripple voltage. The operating frequency of the
RT8278 is determined by an external resistor that is
connected between the RT pin and ground. The value of
the resistor sets the ramp current that is used to charge
and discharge an internal timing capacitor within the
oscillator. Selection of the RT resistor value can be
determined by examining the curve below in Figure3.
Although frequencies as high as 3MHz are available, the
minimum on-time of the RT8278 imposes a limit on the
operating duty cycle. Figure 4 shows the examples of
minimum on-time constraint for output voltages 3.3V and
1.8V. It is recommended to operate the RT8278 in the
region under the corresponding Vout curve.
Except the minimum on-time constraint, the limit of
maximum duty also needs to be considered. In ideal case,
the duty cycle of the RT8278 can be calculated by below
equation, But in practical case it will be higher than the
calculation result since all the components in a converter
circuit are not ideal. Figure 5 shows an example for the
limit of maximum duty. With 5V input voltage, the 3.3V
output voltage of the RT8278 becomes out of regulation
when the output current is increased. However, when the
input voltage is changed to 12V, the 3.3V output voltage
of the RT8278 remains in regulation even with 2A output
current. According to equation below, the duty cycle is
0.67 for the RT8278 operated with 5V input voltage and
3.3V output voltage in 2.2MHz switching frequency. The
ideal case duty cycle calculation is already over the limit
of maximum duty(65%). Thus, it is obvious that the
RT8278 can't support 2A output current in such
conditions :
Duty Cycle = 1 − 0.15 x fSW
(MHz)
Figure 2. External Bootstrap Diode
DS8278-02 March 2011
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RT8278
Switching Frequency (kHz)1
Chip Enable Operation
Switching Frequency vs. RRT
3000
2750
2500
2250
2000
1750
1500
1250
1000
750
500
250
0
0
200
400
600
800
1000
RRRT
(kΩ)
RT (kΩ)
Figure 3. Switching Frequency vs. RRT
Minimum On-Time Constraint
30.0
The EN pin is the enable input. Pull the EN pin low (<0.4V)
to shutdown the device. During shutdown mode, the
RT8278 quiescent current drops to lower than 25μA. Drive
the EN pin high (>1.4V, < 5.5V), to turn on the device. If
the EN pin is open, it will be pulled high by the internal
circuit. For external timing control (e.g.RC), the EN pin
can also be externally pulled high by adding a 100kΩ or
greater resistor from the VIN pin (see Figure 6). In some
cases, the output voltage of the RT8278 may still be under
UVP threshold when soft-start finishes. Then the RT8278
will restart again and the output voltage of the RT8278 will
rise to the regulation voltage. This phenomenon often
happens in high frequency operation and with slow rising
input voltage. It can easily be solved by adding a voltage
divider on the EN pin. The RT8278 will be enabled when
the input voltage rises close to the nominal input voltage.
27.5
Input Voltage (V)
25.0
Inductor Selection
22.5
The inductor value and operating frequency determine the
ripple current according to a specific input and output
voltage. The ripple current ΔIL increases with higher VIN
and decreases with higher inductance :
20.0
VOUT = 3.3V
17.5
15.0
12.5
VOUT = 1.8V
10.0
V
V
ΔIL = ⎡⎢ OUT ⎤⎥ x ⎡⎢1− OUT ⎤⎥
VIN ⎦
⎣ fSW x L ⎦ ⎣
7.5
5.0
2.5
0.0
1000
1400
1800
2200
2600
3000
Switching Frequency (kHz)
Figure 4. Minimum On-Time Constraint to Input Voltage
Output Voltage (V)
Output Voltage vs. Load Current
3.50
3.45
3.40
3.35
3.30
3.25
3.20
3.15
3.10
3.05
3.00
2.95
2.90
2.85
2.80
VIN = 12V
⎡
⎤ ⎡
VOUT
VOUT ⎤
L =⎢
⎥ x ⎢1 − VIN(MAX) ⎥
f
x
I
Δ
SW
L(MAX)
⎣
⎦ ⎣
⎦
VIN = 5V
fSW = 2.2MHz
0.0
0.4
0.8
1.2
1.6
Load Current (A)
Having a lower ripple current reduces not only the ESR
losses in the output capacitors but also the output voltage
ripple. Higher frequency combined with smaller ripple
current is necessary to achieve high efficiency operation.
However, it requires a large inductor to achieve this goal.
For the ripple current selection, setting the maximum value
of the ripple current ΔIL = 0.24(IMAX) is a reasonable starting
point. The largest ripple current occurs at the highest VIN.
To guarantee that the ripple current stays below the
specified maximum, the inductor value should be chosen
according to the following equation :
2.0
The inductor's current rating (defined by that which causes
a temperature rise from 25°C ambient to 40°C) should be
greater than the maximum load current and its saturation
current should be greater than the short circuit peak current
limit. Refer to Table 2 for the suggested inductor selection.
Figure 5. Limit of Maximum Duty
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DS8278-02 March 2011
RT8278
Table2. Suggested Inductors for Typical Application
Circuit
Component
Dimensions
Series
Supplier
(mm)
TDK
VLC6045
6 x 6 x 4.5
TDK
SLF12565
12.5 x 12.5 x
6.5
TAIYO
YUDEN
NR8040
8x 8 x4
Diode Selection
When the power switch turns off, the path for the current
is through the diode connected between the switch output
and ground. This forward biased diode must have a minimal
voltage drop and recovery time. Schottky diodes are
recommended and should be able to handle those current.
The reverse voltage rating of the diode should be greater
than the maximum input voltage, and the current rating
should be greater than the maximum load current. For
details, please refer to Table 3.
Table 3. Suggested Diode
Component
Series VRRM (V) I OUT (A)
Supplier
Package
DIODES
B330A
30
3
SMA
DIODES
B220A
20
2
SMA
PANJIT
SK22
20
2
DO-214AA
PANJIT
SK23
30
2
DO-214AA
CIN and COUT Selection
The input capacitance, C IN, is needed to filter the
trapezoidal current at the source of the high side MOSFET.
To prevent large ripple current, a low ESR input capacitor
sized for the maximum RMS current should be used. The
RMS current is given by :
V
IRMS = IOUT(MAX) OUT
VIN
VIN
−1
VOUT
This formula has a maximum at VIN = 2VOUT, where
IRMS = I OUT / 2. This simple worst-case condition is
commonly used for design.
Choose a capacitor rated at a higher temperature than
required. Several capacitors may also be paralleled to
meet size or height requirements in the design.
DS8278-02 March 2011
For the input capacitor, one 10μF low ESR ceramic
capacitors is recommended. For the recommended
capacitor, please refer to Table 4 below for more details.
The selection of COUT is determined by the required ESR
to minimize voltage ripple.
Moreover, the amount of bulk capacitance is also a key
for COUT selection to ensure that the control loop is stable.
Loop stability can be checked by viewing the load transient
response as described in a later section.
The output ripple, ΔVOUT , is determined by :
1
⎤
ΔVOUT ≤ ΔIL ⎡⎢ESR +
8fC
OUT ⎥⎦
⎣
The output ripple will be highest at the maximum input
voltage since ΔIL increases with input voltage. Multiple
capacitors placed in parallel may be needed to meet the
ESR and RMS current handling requirement. Dry tantalum,
special polymer, aluminum electrolytic and ceramic
capacitors are all available in surface mount packages.
Special polymer capacitors offer very low ESR value.
However, it provides lower capacitance density than other
types. Although Tantalum capacitors have the highest
capacitance density, it is important to only use types that
pass the surge test for use in switching power supplies.
Aluminum electrolytic capacitors have significantly higher
ESR. However, it can be used in cost sensitive applications
for ripple current rating and long term reliability
considerations. Ceramic capacitors have excellent low
ESR characteristics but can have a high voltage coefficient
and audible piezoelectric effects. The high Q of ceramic
capacitors with trace inductance can also lead to significant
ringing.
Nevertheless, high value low cost ceramic capacitors are
now becoming available in smaller case sizes. Their high
ripple current, high voltage rating and low ESR make them
ideal for switching regulator applications. However, care
must be taken when these capacitors are used at the
input and output. When a ceramic capacitor is used at
the input and the power is supplied by a wall adapter through
long wires, a load step at the output can induce ringing at
the input, VIN. At best, this ringing can couple to the output
and be mistaken as loop instability. At worst, a sudden
inrush of current through the long wires can potentially
cause a voltage spike at VIN large enough to damage the
part.
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RT8278
Choose a capacitor that is greater than the above
calculation result. The frequency of the zero, which
consists of RC and CC, should be lower than one fourth of
fC to get a sufficient phase margin. If the zero moves close
to fC, the phase margin decreases.
Checking Transient Response
The regulator loop response can be checked by looking
at the load transient response. Switching regulators take
several cycles to respond to a step in load current. When
a load step occurs, VOUT immediately shifts by an amount
equal to ΔILOAD (ESR) and COUT also begins to be charged
or discharged generating a feedback error signal for the
regulator to return VOUT to its steady state value. During
this recovery time, VOUT can be monitored for overshoot
or ringing to indicate any stability problem.
In some applications, the output capacitor will be an
electrolytic capacitor, not a ceramic capacitor. A zero will
be produced by the electrolytic capacitor and its ESR. CP
can be used to produce a pole with RC to cancel the zero.
To calculate CP, follow the equation below :
CP =
Compensation Parameters
The switching frequency of RT8278 can be programmed
from free running frequency to 3MHz. Table 1 only lists
the recommended compensation parameters for 2.2MHz
switching frequency. Optimized compensation parameters
for other switching frequency can also be determined
through below procedures. The first step is to decide the
crossover frequency, fc. In general, the crossover
frequency is one tenth of the switching frequency. Then,
Rc can be obtained through the following equation :
CC =
EMI Consideration
Since parasitic inductance and capacitance effects in PCB
circuitry would cause a spike voltage on the SW pin when
the high side MOSFET is turned-on/off, this spike voltage
on SW may impact EMI performance in the system. In
order to enhance EMI performance, there are two methods
to suppress the spike voltage. One is to place an R-C
snubber between SW and GND and place them as close
as possible to the SW pin (see Figure 6). Another method
is to add a resistor in series with the bootstrap
capacitor, CBOOT. But this method will decrease the driving
capability to the high side MOSFET. It is strongly
recommended to reserve the R-C snubber during PCB
layout for EMI improvement. Moreover, reducing the SW
trace area and keeping the main power in a small loop will
be helpful for EMI performance. For detailed PCB layout
guide, please refer to the section on Layout Consideration.
1
f
2π × RC × C
4
where
gCS is Current SenseTransconductance = 1.8 (A/V)
gEA is Error Amplifier Tansconductance = 920 (μA/V)
Once the value of Rc has been determined, the value of
Cc can be obtained by the following equation :
RC =
2π × COUT × fC × VOUT
gCS × gEA × VFB
2
VIN
4.5V to 24V
CIN
10µF
REN*
Chip Enable
VIN
BOOT
RT8278
7 EN
COUT × ESR
RC
SW
1 RBOOT*
CBOOT
L
10nF 2.2µH
3
RS *
CEN*
D
B220A
CS *
8 RT
RRT
24K
* : Optional
4,
9 (Exposed Pad)
GND
FB 5
COMP
6
CC
1nF
RC
36k
VOUT
3.3V/2A
R1
31.6k
COUT
22µF
R2
10k
NC
CP
Figure 6. Reference Circuit with Snubber and Enable Timing Control
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12
DS8278-02 March 2011
RT8278
Thermal Considerations
resistance, θJA. For the RT8278 packages, the derating
For continuous operation, do not exceed absolute
maximum junction temperature. The maximum power
dissipation depends on the thermal resistance of the IC
package, PCB layout, rate of surrounding airflow, and
difference between junction and ambient temperature. The
maximum power dissipation can be calculated by the
following formula :
curves in Figure 8 allow the designer to see the effect of
rising ambient temperature on the maximum power
dissipation.
PD(MAX) = (TJ(MAX) − TA) / θJA
where TJ(MAX) is the maximum junction temperature, TA is
the ambient temperature, and θJA is the junction to ambient
(a) Copper Area = (2.3 x 2.3) mm2, θJA = 75°C/W
thermal resistance.
For recommended operating condition specifications of
the RT8278, the maximum junction temperature is 125°C
and TA is the ambient temperature. The junction to ambient
thermal resistance, θJA, is layout dependent. For SOP-8
(Exposed Pad) packages, the thermal resistance, θJA, is
75°C/W on a standard JEDEC 51-7 four-layer thermal test
board. The maximum power dissipation at TA=25°C can
be calculated by the following formulas :
(b) Copper Area = 10mm2, θJA = 64°C/W
P D(MAX) = (125°C − 25°C) / (75°C/W) = 1.333W
(min. copper area PCB layout)
P D(MAX) = (125°C − 25°C) / (49°C/W) = 2.04W
(70mm2 copper area PCB layout)
The thermal resistance, θJA, of SOP-8 (Exposed Pad) is
determined by the package architectural design and the
PCB layout design. The package architectural design is
fixed. However, it's possible to increase thermal
performance via better PCB layout copper design. The
thermal resistance, θJA, can be decreased by adding
copper area under the exposed pad of the SOP-8
(Exposed Pad) package.
As shown in Figure 7, the amount of copper area to which
the SOP-8 (Exposed Pad) is mounted on affects thermal
performance. When mounted to the standard SOP-8
(Exposed Pad) (Figure 7a), θJA is 75°C/W. Adding copper
area under the SOP-8 (Exposed Pad) (Figure 7b) reduces
θJA to 64°C/W. Further increasing the copper area to
70mm2 (Figure 7e) will reduce θJA to 49°C/W.
The maximum power dissipation depends on operating
ambient temperature for fixed T J (MAX) and thermal
DS8278-02 March 2011
(c) Copper Area = 30mm2 , θJA = 54°C/W
(d) Copper Area = 50mm2 , θJA = 51°C/W
(e) Copper Area = 70mm2 , θJA = 49°C/W
Figure 7. Themal Resistance vs. Copper Area Layout
Design
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13
RT8278
2.2
Four Layer PCB
Power Dissipation (W)
2.0
1.8
Copper Area
70mm2
50mm2
30mm2
10mm2
Min.Layout
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0.0
0
25
50
75
100
125
Ambient Temperature (°C)
Figure 8. Derating Curves for RT8278 Package
Layout Consideration
`
Follow the PCB layout guidelines for optimum performance
of the RT8278.
`
`
Keep the traces of the main current paths as short and
wide as possible.
Place the input capacitor as close as possible to the
device pins (VIN and GND).
` SW node experiences high frequency voltage swing and
Connect the feedback network behind the output
capacitors. Keep the loop area small. Place the feedback
components near the RT8278.
` Connect all analog grounds to a common node and then
connect the common node to ground behind the output
capacitors.
` An
example of the PCB layout guide is shown in Figure
9 for reference.
should be kept in a small area. Keep analog components
away from the SW node to prevent stray capacitive noise
pick up.
VIN
GND
Input capacitor must
be placed as close
to the IC as possible.
RRT
CIN
BOOT
D
CS
COUT
The feedback components
must be connected as close
to the device as possible.
SW GND
RS
VIN
2
SW
GND
3
4
GND
9
8
RT
7
EN
6
COMP
5
FB
L
VOUT
CC
CP
RC
R1
R2
VOUT
GND
SW should be connected to inductor by
wide and short trace. Keep sensitive
components away from this trace.
Figure 9. PCB Layout Guide
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14
DS8278-02 March 2011
RT8278
Table 4. Suggested Capacitors for CIN and COUT
Location
Component Supplier
Part No.
Capacitance (μF)
Case Size
CIN
MURATA
GRM31CR61E106K
10
1206
CIN
TDK
C3225X5R1E106K
10
1206
CIN
TAIYO YUDEN
TMK316BJ106ML
10
1206
COUT
MURATA
GRM31CR60J476M
47
1206
COUT
TDK
C3225X5R0J476M
47
1210
COUT
MURATA
GRM32ER71C226M
22
1210
COUT
TDK
C3225X5R1C226M
22
1210
DS8278-02 March 2011
www.richtek.com
15
RT8278
Preliminary
Outline Dimension
H
A
M
EXPOSED THERMAL PAD
(Bottom of Package)
Y
J
X
B
F
C
I
D
Dimensions In Millimeters
Dimensions In Inches
Symbol
Min
Max
Min
Max
A
4.801
5.004
0.189
0.197
B
3.810
4.000
0.150
0.157
C
1.346
1.753
0.053
0.069
D
0.330
0.510
0.013
0.020
F
1.194
1.346
0.047
0.053
H
0.170
0.254
0.007
0.010
I
0.000
0.152
0.000
0.006
J
5.791
6.200
0.228
0.244
M
0.406
1.270
0.016
0.050
X
2.000
2.300
0.079
0.091
Y
2.000
2.300
0.079
0.091
X
2.100
2.500
0.083
0.098
Y
3.000
3.500
0.118
0.138
Option 1
Option 2
8-Lead SOP (Exposed Pad) Plastic Package
Richtek Technology Corporation
Richtek Technology Corporation
Headquarter
Taipei Office (Marketing)
5F, No. 20, Taiyuen Street, Chupei City
5F, No. 95, Minchiuan Road, Hsintien City
Hsinchu, Taiwan, R.O.C.
Taipei County, Taiwan, R.O.C.
Tel: (8863)5526789 Fax: (8863)5526611
Tel: (8862)86672399 Fax: (8862)86672377
Email: [email protected]
Information that is provided by Richtek Technology Corporation is believed to be accurate and reliable. Richtek reserves the right to make any change in circuit
design, specification or other related things if necessary without notice at any time. No third party intellectual property infringement of the applications should be
guaranteed by users when integrating Richtek products into any application. No legal responsibility for any said applications is assumed by Richtek.
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DS8278-02 March 2011