TMS28F033 4194304-BIT SYNCHRONOUS FLASH MEMORY SMJS833 – NOVEMBER 1997 V DDE RP CLK QV RY/BY LBA V SSI S/5IO V DDI E WE OE WR WORD/DIS BAA/LRV 60 VSSE VSSE 6 59 VDDE DQ20 7 58 DQ11 DQ21 8 57 DQ10 DQ22 9 56 DQ9 DQ23 10 55 DQ8 DQ24 11 54 DQ7 DQ25 12 53 DQ6 DQ26 13 52 DQ5 DQ27 14 51 DQ4 VDDE 15 50 VSSE VSSE 16 49 VDDE DQ28 17 48 DQ3 DQ29 18 47 DQ2 DQ30 19 46 DQ1 DQ31 20 45 DQ0 A–1 21 44 NC A0 22 43 NC A1 23 42 NC A2 24 41 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 A15 A16 The TMS28F033 is the first synchronous nonvolatile flash memory device to offer a configurable burst interface to 16/32-bit microprocessors and microcontrollers operating at frequencies up to 40 MHz. The TMS28F033 contains 4M bits of main memory that is user-configurable as either three or four independently erasable blocks. In addition to the main memory array, there is a protected overlay memory block that is normally hidden from the memory address map. The following table shows the three- and four-block main-memory-array configurations for both 16-bit and 32-bit data bus widths. Table 1. Memory Configurations DATA BUS WIDTH 3-BLOCK MAIN ARRAY 4-BLOCK MAIN ARRAY PROTECTED OVERLAY BLOCK 16 bits 32K, 160K, and 64K 32K, 96K, 64K, and 64K 12K 32 bits 16K, 80K, and 32K 16K, 48K, 32K, and 32K 6K Embedded program and block-erase functions are fully automated by an on-chip write state machine (WSM), which simplifies these operations and relieves the system microcontroller of these secondary tasks. WSM status can be monitored by the on-chip status register to determine the progress of program/erase tasks. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Copyright 1997, Texas Instruments Incorporated ADVANCE INFORMATION concerns new products in the sampling or preproduction phase of development. Characteristic data and other specifications are subject to change without notice. POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 1 ADVANCE INFORMATION 5 A14 DQ12 VDDE A13 61 A12 4 A11 DQ13 DQ19 A10 62 A9 3 A3 description DQ14 DQ18 V DDI D 63 VSSI V PP D DQ15 2 A8 D 64 DQ17 A7 D 1 A6 D D 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 DQ16 A5 D PAF 80-PIN PACKAGE (T0P VIEW) LBO D D Organization – 512K-Byte Main Array – 24K-Byte Protected Overlay-Block User-Defined x16 or x32 Data Bus Read Transfer Data Rates Up to 100 MBytes / s at Bus Frequencies Up to 40 MHz Burstable Pipelined Read Interface With Programmable Latency, Length, and Order 10 000 Program / Erase Cycles Three Temperature Ranges – Commercial . . . 0°C to 70°C – Extended . . . – 40°C to 85°C – Automotive . . . – 40°C to 125°C 80-Pin Plastic Quad Flatpack (PQFP) (PAF Suffix) Fully Automated On-Chip Erase and Program Operations Three Separate Voltage Supplies – I / O Supply – Configurable 3.3 V / 5 V – Read Supply – 5 V – Programming Supply – 12 V All Inputs / Outputs TTL-Compatible A4 D TMS28F033 4194304-BIT SYNCHRONOUS FLASH MEMORY SMJS833 – NOVEMBER 1997 description (continued) The TMS28F033 flash memory requires 12 V for erasure and programming, and 5 V for memory-array access while interfacing with either a 3.3-V or 5-V bus. The TMS28F033 flash memory is fabricated using CMOS technology and is packaged in an 80-pin plastic quad flatpack (PQFP) (PAF suffix). device symbol nomenclature TMS28F033– X B PAF Q ADVANCE INFORMATION Temperature Range L (Commercial) = 0°C to 70°C E (Extended) = – 40°C to 85°C Q (Automotive) = – 40°C to 125°C Package Type PAF = 80-Pin Plastic Quad Flatpack Program/Erase Endurance B = 10 000 Cycles Speed Option 25 = 25 MHz 33 = 33 MHz 2 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 TMS28F033 4194304-BIT SYNCHRONOUS FLASH MEMORY SMJS833 – NOVEMBER 1997 functional block diagram DQ0 – DQ7, DQ24 – DQ31 DQ8 – DQ23 CLK Output Buffer Output Buffer Input Buffer E Input Buffer OE WE Control Logic and Clocks LBA WR DIS OE / BAA 3/5IO Device Configuration Register Burst State Machine Data Input Register ADVANCE INFORMATION LBO QV RP Default Configuration WORD Read Latch A–1 Write Latch Command State Machine Data Input Register Input Buffer Output Register IP Register Output Register Status Register A0 – A16 Write State Machine Input Buffer LRV Data Comparator RY / BY Read Address Counter Y Decoder Address MUX Write Address Counter X Decoder Y Gating/Sensing 24K-Byte Overlay Block POST OFFICE BOX 1443 Program / Erase Voltage Switch VPP 512K-Byte Main Block • HOUSTON, TEXAS 77251–1443 3 TMS28F033 4194304-BIT SYNCHRONOUS FLASH MEMORY SMJS833 – NOVEMBER 1997 Terminal Functions TERMINAL NAME TYPE† A–1 I Word select address. A–1 is the low-order address for the 16-bit data bus, and selects between the high and low word. A–1 is not used for the 32-bit data bus. A0 – A16 I Address bus. A0 – A16 select one of the 131 072 32-bit segments (double-words), or, with A–1, selects one of the 262 144 16-bit segments (words). A0 is the low-order address for the 32-bit data bus. I/O Data bus. Bidirectional data bus, where for both 16-bit and 32-bit data bus widths, DQ31 is the most significant bit (MSB) and DQ0 is the least significant bit (LSB). The 16-bit data bus uses DQ0 – DQ7 and DQ24 – DQ31. LBA I Load-burst address. For synchronous operation, when LBA = VIL on a rising CLK edge, the address is latched for the beginning of a read or write operation. BAA I Burst-address advance. When BAA = VIL, the burst state machine increments the burst address for each required data beat on the rising CLK edge. For BAA usage, see Table 8 and Table 9. RP I Reset/power-down. When RP = VIL, the device terminates any current-state-machine activity and does not respond to read requests and does not accept write commands. On the rising edge of RP, the device sets/clears the OBEB status register bit (SB1) based on the status of VPP. When VPP VPPH, OBEB is set; if VPP VPPL, OBEB is cleared (see Table 3). E I Chip enable. When E = VIL, the device is enabled for read or write operations. When E = VIH, the device is in standby mode. E is an asynchronous signal. For E usage, see Table 8 and Table 9. OE I Output enable. OE is used for read operations and can be either synchronous or asynchronous (see Table 8 and Table 9). For synchronous OE, when OE = VIL on a rising CLK edge, the output data is latched and becomes valid prior to the next rising CLK edge. OE = VIH during write operations. LBO I Linear-burst order. When LBO= VIL, the address counter is set for linear burst. When LBO = VIH, the address counter is set for interleaved burst. For LBO usage, see Table 9 and Table 12. WR I Write. WR is a synchronous signal that controls the read and write operations. If WR = VIL when the address is latched (LBA = VIL), then the cycle is a write cycle . If WR = VIH when the address is latched, then the cycle is a read cycle. I Write enable. WE is used for write/erase operations and can be either synchronous or asynchronous (see Table 8 and Table 9). For synchronous WE usage, with the first occurrence of WE = VIL (after the address is latched with LBA and WR = VIL) on a rising CLK edge, the input data/command is latched. For asynchronous writes, the data and address are latched on the WE rising edge. WORD I Word enable. WORD is used for selection of the data bus width. When WORD = VIL, the device has a 16-bit data bus, and data is input or output on DQ0 – DQ7 and DQ24 – DQ31, and address A–1 selects between the high and low word. When WORD = VIH, the device has a 32-bit data bus and turns off the A–1 input buffer. For WORD usage, see Table 8 and Table 9. DIS I Disable output. When DIS = VIL, the synchronous OE, DQ’s, and QV signals are disabled. DIS functions as an additional synchronous output enable (opposite in logic to OE). For DIS usage, see Table 8 and Table 9. LRV I Low regulator voltage. When LRV = VIL during a write/erase operation, the LRVS status register bit (SB4) is set (see Table 7). LRV is an asynchronous signal. For LRV usage, see Table 8 and Table 9. QV OD O Data valid. QV is used for read operations. QV = VIL when output data is valid on the data bus for either a single or burst-read operation. When QV = VIH, there is no valid data on the data bus. For QV usage, see Table 8 and Table 9. RY/BY OD O Ready/busy. RY/BY indicates the status of the WSM. When RY/BY = VIL, the WSM is currently active performing an operation. When RY/BY = VIH, the WSM is ready for a new operation. For RY/BY usage, see Table 8 and Table 9. CLK I Clock. Signals on both the address and data buses are transmitted and received relative to this system clock. All synchronous inputs must meet setup and hold times relative to the rising CLK edge. 3/5IO I 3.3/5.0 I/O select. 3/5IO is used to select the external power supply, VDDE, as either 3.3 V or 5 V. Set 3/5IO = VIH for VDDE = 3.3 V operation, and set 3/5IO = VIL for VDDE = 5 V operation. For 3/5IO usage, see Table 8 and Table 9. DQ0 – DQ31 ADVANCE INFORMATION DESCRIPTION WE w † I = input, O = output, OD = open drain, S = power supply 4 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 v TMS28F033 4194304-BIT SYNCHRONOUS FLASH MEMORY SMJS833 – NOVEMBER 1997 Terminal Functions (Continued) TERMINAL NAME TYPE† DESCRIPTION VPP VDDI S Write/erase power supply. VPP is the 12-V power supply for the write/erase operations. S Internal power supply. VDDI is the 5-V power supply for the internal logic. VDDE VSSE S External power supply. VDDE is the 3.3-V/5-V power supply for the inputs and outputs. S Output ground. VSSE is the ground for the outputs DQ0 – DQ31, RY/BY, and QV. VSSI S Input ground. VSSI is the ground for both the inputs and internal logic. NC No connect. These pins are left unconnected inside the memory chip. † I = input, O = output, OD = open drain, S = power supply architecture main memory The TMS28F033 main memory is configurable to either three blocks (DCR5 = 0) or four blocks (DCR5 = 1), see Table 1, and Figure 1 and Figure 2. Address Range x16 Configuration A–1 is LSB Address Range 3FFFFh 1FFFFh Block 2 64K Addresses Block 2 32K Addresses 30000h 18000h 2FFFFh 17FFFh Block 1 160K Addresses 02FFFh Block 1 80K Addresses 08000h 04000h 07FFFh 03FFFh Overlay Block 12K Addresses x32 Configuration A0 is LSB Bl k 0 Block 32K Addresses 00000h 017FFh Overlay Block 6K Addresses Bl k 0 Block 16K Addresses 00000h Figure 1. TMS28F033 With Three-Block Main-Array Memory Map (DCR5 = 0) POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 5 ADVANCE INFORMATION The TMS28F033 uses a blocked architecture to allow independent erasure of selected memory blocks. The block to be erased is selected by using any valid address within the block. Figure 1 and Figure 2 show the memory maps for the two configurations. TMS28F033 4194304-BIT SYNCHRONOUS FLASH MEMORY SMJS833 – NOVEMBER 1997 main memory (continued) Address Range x16 Configuration A–1 is LSB Address Range 3FFFFh 1FFFFh Block 3 64K Addresses Block 3 32K Addresses 30000h 18000h 2FFFFh 17FFFh Block 2 64K Addresses Block 2 32K Addresses 20000h 10000h 1FFFFh 0FFFFh ADVANCE INFORMATION Block 1 96K Addresses 02FFFh 00000h Block 1 48K Addresses 08000h 04000h 07FFFh 03FFFh Overlay Block 12K Addresses x32 Configuration A0 is LSB Bl k 0 Block 32K Addresses 017FFh Overlay Block 6K Addresses 00000h Bl k 0 Block 16K Addresses Figure 2. TMS28F033 With Four-Block Main-Array Memory Map (DCR5 = 1) overlay block The overlay block is a protected memory region that is programmed or erased using special command state machine (CSM) commands (see Table 4 and Table 5). When enabled, the overlay memory block exists from addresses 00000h to 017FFh for x32 addressing, or from 00000h to 02FFFh for x16 addressing. Two status register bits, OBEB and OBS, are available to monitor the overlay block enable/disable process (see Table 7). The overlay block status (OBS) bit indicates whether the overlay block is enabled (OBS = 1) or disabled (OBS = 0) for reading. See Table 2 for the state of the OBS bit for memory-read accessing. The status of the overlay-block-enable bit (OBEB) does not necessarily indicate that the overlay block is enabled, instead OBEB reflects the state of the overlay block control switch. When OBEB = 1, the switch is set, and when OBEB = 0, the switch is not set (see the overlay-block-control functional diagram in Figure 3). See Table 3 for a listing of methods that set/clear the OBEB. Table 2. Read-Accessing of the Overlay Block or Main Array STATE OF OBEB (SB1) 1 1 0 1 † X is a don’t care. 6 STATE OF OBS (SB0) READ ACCESS VPP ≥ VPPH VPP ≤ VPPL X† 1 Overlay Block 0 Main Array 0 Main Array VPPL < VPP < VPPH Not guaranteed Unknown VPP STATUS POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 TMS28F033 4194304-BIT SYNCHRONOUS FLASH MEMORY SMJS833 – NOVEMBER 1997 overlay block (continued) Table 3. Methods of Setting/Clearing the Overlay-Block-Enable Bit (OBEB) METHOD PRIOR STATE OF OBEB X† NEXT STATE OF OBEB 0 Power-on-reset of VDDI with VPP ≥ VPPH X† X† Power-on-reset of VDDI with VPP ≤ VPPL X† 0 0 1 1 0 Toggle RP with VPP ≥ VPPH Toggle RP with VPP ≤ VPPL Issue CSM command 06h Enable/disable overlay block for reads † X is a don’t care. 1 1 OBEB Software Enable OBS SET VPP Q D VPP Overlay Block Control RP / SRESET Power-On Reset CLR Software Disable Figure 3. Overlay-Block-Control Functional Diagram command state machine (CSM) Commands are issued to the CSM using standard microprocessor write timings. The CSM acts as an interface between the external microprocessor and the internal WSM. The available commands are listed in Table 4 and the corresponding descriptions are in Table 5. When a program or erase command is issued to the CSM, the WSM controls the internal sequences and the CSM responds only to status reads. A command is valid only if the exact sequence of writes is completed. After the WSM completes its task, the WSM status bit (SB7) is set to a logic-high level, allowing the CSM to respond to the full command set again. In addition, Ready/Busy (RY/BY) is an optional output that is available to monitor the WSM status. operation Device operations are selected by entering standard JEDEC 8-bit command codes with conventional microprocessor timing into an on-chip CSM through I/O pins DQ0 – DQ7. When the device is powered up, internal reset circuitry initializes the chip to a read-array mode of operation. Changing the mode of operation requires a command code to be entered into the CSM. The on-chip status register allows the progress of various operations to be monitored. The status register is interrogated by entering a read-status-register command into the CSM (cycle 1) and reading the register data on I/O pins DQ0 – DQ7 (cycle 2). Status register bits SB0 through SB7 correspond to DQ0 through DQ7. POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 7 ADVANCE INFORMATION The enable/disable-overlay-block CSM command (06h) is used to enable the overlay block for a read operation, or to disable the overlay block after a read operation. When 06h is issued for overlay-block access, both the overlay-block latch and OBEB are set whether VPP ≥ VPPH or not. However, only the overlay block is enabled (and only OBS is set) if VPP ≥ VPPH. TMS28F033 4194304-BIT SYNCHRONOUS FLASH MEMORY SMJS833 – NOVEMBER 1997 operation (continued) Table 4. Command-State-Machine Codes for Device Mode Selection ADVANCE INFORMATION COMMAND CODE ON DQ0 – DQ7† DEVICE MODE 02h Block-erase setup of overlay block 04h Program setup of overlay block 06h Enable/disable overlay block for reads 0Dh Block-erase confirm of overlay block 20h Block-erase setup of main array 40h Program setup of main array 50h Clear status register 60h Enable/disable low-power programming 70h Read status register 90h Silicon signature selection 96h Load device-configuration register D0h Block-erase confirm of main array F0h Reduced power FFh Read array † DQ0 is the least significant bit. DQ8 – DQ31 can be any valid 2-state level. command definition Once a specific command code has been entered, the WSM executes an internal algorithm that generates the necessary timing signals to program, erase, and verify data. See Table 5 for the CSM command definitions and the data for each of the bus cycles. See Table 6 for the addresses required to access the algorithm selection codes. 8 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 TMS28F033 4194304-BIT SYNCHRONOUS FLASH MEMORY SMJS833 – NOVEMBER 1997 command definition (continued) Table 5. Command Definitions FIRST BUS CYCLE SECOND BUS CYCLE DATA BUS WIDTH OPERATION ADDRESS Read Array x16/x32 Write 00000h† FFh Read Algorithm Selection Code (see Note 1, and Table 6) x16/x32 Write 00000h† Read Status Register x16/x32 Write 00000h† COMMAND CSM INPUT THIRD BUS CYCLE ADDRESS DATA IN/OUT Read RA DO 90h Read A1A0 M/D DCR 70h Read X SRB OPERATION OPERATION ADDRESS DATA IN/OUT Write PA PD(H,L) Write PA PD(H,L) READ OPERATIONS Program Setup/Program of Main Array (see Note 1) Program Setup/Program of Overlay Block (see Note 1) Load DCR x16 x16/x32 x16 x16/x32 x16/x32 Write 00000h† 40h Write A–1 PD(L,H) Write 00000h† 40h Write PA PD Write 00000h† 04h Write A–1 PD(L,H) Write 00000h† 04h Write PA PD Write 00000h† 96h Write X CV ERASE OPERATIONS Block-Erase Setup/ Block-Erase Confirm of Main Array x16/x32 Write 00000h† 20h Write BBA D0h Block-Erase Setup/ Block-Erase Confirm of Overlay Block x16/x32 Write 00000h† 02h Write BBA 0Dh Reduced-Power Mode x16/x32 Write 00000h† F0h Enable/Disable LowPower Programming x16/x32 Write 00000h† 60h Clear Status Register x16/x32 Write 00000h† 50h Enable/Disable Overlay Block for Read x16/x32 Write 00000h† 06h OTHER OPERATIONS † Address is a don’t care for asynchronous writes. NOTE 1: When using x16 (DCR3 = 1 and WORD = VIL), programming can be performed in either two or three cycles by configuring the DCR31 bit (see Table 8). Legend: ADDRESS DATA BBA = Block base address CV = Configuration value PA = Address to be programmed DO = Read data out RA = Read address M/D/DCR = Manufacturer code/device configuration register value X = Don’t care SRB = Status-register data byte on DQ0 – DQ7 PD(L,H) = Data to be programmed at PA (low word, high word) POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 9 ADVANCE INFORMATION PROGRAM OPERATIONS TMS28F033 4194304-BIT SYNCHRONOUS FLASH MEMORY SMJS833 – NOVEMBER 1997 command definition (continued) Table 6. Algorithm Selection Codes (See Note 2) DATA BUS WIDTH 16-Bit (see Note 3) ADVANCE INFORMATION 32-Bit (see Note 4) ADDRESS (A0 – A16) A1 A0 A–1 DATA OUT X0h VIL VIL X Manufacturer Code 0097h X1h VIL VIH X Device Code 0068h X2h VIH VIL X DCR Value DDDDh X0h VIL VIL — Manufacturer Code 00000097h X1h VIL VIH — Device Code 00000068h X2h VIH VIL — DCR Value DD0000DDh NOTES: 2. X is a don’t care. 3. When using the 16-bit data bus, the data lines are DQ0 – DQ7 and DQ23 – DQ31. 4. When using the 32-bit data bus, the data lines are DQ0 – DQ31. status register The status register allows the user to determine whether the state of a program/erase operation is pending or complete. The status register is monitored by writing a read-status command to the CSM and reading the resulting status code on I/O pins DQ0 – DQ7. This operation is valid in either the word-wide (x16) or double-word-wide (x32) mode. The high-order I/Os (DQ8 – DQ31) are set to 000000h internally. After a read-status command has been given, the data appearing on DQ0 – DQ7 remains as status register data until a new command is issued to the CSM. To return the device to other modes of operation, a new command must be issued to the CSM. Status register data is updated on every clock cycle. During periods when the WSM is active, the status register can be read to determine the WSM status. Table 7 defines the status-register bits and their functions. 10 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 TMS28F033 4194304-BIT SYNCHRONOUS FLASH MEMORY SMJS833 – NOVEMBER 1997 status register (continued) Table 7. Status-Register Bit Definitions and Functions FUNCTION DATA SB7 Write-State-Machine (WSM) Status 1 = Ready 0 = Busy SB6 Reserved 0 SB5 (DCR4 = 0) Operation Status (OS) COMMENTS If SB7 = 0 (busy), the WSM has not completed an erase or programming operation. If SB7 = 1 (ready), other operations can be performed. 1 = Commands/operations not successful 0 = Commands/operations successful The WSM sets the OS bit high (SB5 = 1) after an illegal command has been issued, an error has occurred while erasing a block, or as the result of an error while programming a word. If all past operations have completed successfully, then the OS bit remains low (SB5 = 0); however, the WSM cannot clear this bit. SB5 (DCR4 = 1) Erase Status (ES) 1 = Block-erase error 0 = Block-erase good SB5 = 0 indicates that a block-erase has been successful. SB5 = 1 indicates that an erase error has occurred. In this case, the WSM has completed the maximum erase pulses determined by the internal algorithm, but this was insufficient to completely erase the device. SB4 (DCR4 = 0) Low Regulator Voltage Status (LRVS) 1 = LRV asserted 0 = LRV not asserted The LRVS bit is set high (SB4 = 1) when the LRV input is asserted during an erase or program command. The clear-status-register command clears the LRVS bit (SB4 = 0). SB4 (DCR4 = 1) Program Status (PS) 1 = Program error 0 = Program good SB4 = 0 indicates successful programming has occurred at the addressed location. SB4 = 1 indicates that the WSM was unable to correctly program the addressed location. SB3 VPP Status (VPPS) 1 = Program abort: VPP range error 0 = VPP good SB3 provides information on the status of VPP during programming and erasing. If VPP is lower than VPPL after a program or erase command has been issued, SB3 is set to a 1 to indicate that the operation is aborted. SB2 Low-Power Mode (LPM) 1 = Byte-program 0 = Word-program When the LPM bit is set high (SB2 = 1), the WSM programs each word in byte increments. When the LPM bit is low (SB2 = 0), the WSM programs in word (x32 or x16) increments. SB1 Overlay-Block-Enable Bit (OBEB) 1 = Overlay block can be enabled 0 = Overlay block disabled When the OBEB bit, which is VPP-independent, is set (SB1 = 1), the overlay block can be enabled for reads. When the OBEB bit is low (SB1 = 0), the overlay block is disabled for reads. SB0 Overlay-Block Status (OBS) 1 = Overlay block enabled 0 = Overlay block disabled When the OBS bit, with VPP ≥ VPPH, is set (SB0 = 1), the overlay block is enabled for reads. When the OBS bit is cleared (SB0 = 0), the overlay block is disabled for reads. ADVANCE INFORMATION STATUS BIT device configuration register (DCR) The DCR is a user-loaded register that determines many of the device functions (see Table 8). Sixteen configurable bits (DCR0 – DCR7 and DCR24 – DCR31 with DCR26 – 27 reserved) can be set by using the load-DCR CSM command (96h) (see Table 5). The current value of the DCR can be read with CSM command 90h, provided A1 is set to VIH and A0 is set to VIL (see Table 6). POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 11 TMS28F033 4194304-BIT SYNCHRONOUS FLASH MEMORY SMJS833 – NOVEMBER 1997 device configuration defaults The term “default” denotes the state of a bit in the DCR when the device is first powered up or when a power-on reset is performed. These defaults are set at the factory after fabrication. After the CSM command that loads the DCR (96h) is executed, the defaults no longer define the device operation; instead, the new configuration takes effect. To restore the default state, either perform a power-on reset or load the DCR with the reset-state settings using the 96h command sequence. The TMS28F033 has two types of defaults: a fuse-bit-option default and a standard default. The difference between the two types is that a fuse-bit-option default can be optionally set (0 or 1) at the factory, whereas a standard default is always set to 0 at the factory. The DCR has eight fuse-bit-option defaults, DCR0 – DCR7, and eight standard defaults, DCR24 – DCR31. The X-latency bits DCR28 – DCR29 are the only exceptions to these two types of defaults. These bits default to 00 (standard defaults), except when the device is in x16 mode (WORD = VIL) or when OE is asynchronous (DCR1 = 1). In these exceptions, the DCR28 – DCR29 bits function as 10 (see Table 8). It is important to note that even though DCR28 – DCR29 functions as 10 for these exceptions, they are still read (with the DCR read command 90h) as 00, instead of 10. ADVANCE INFORMATION Table 8. Device Configuration Register Bit Definitions and Functions DCR BIT FUNCTION DATA COMMENTS Control pin configuration 0 = Basic Control Pin Set 1 = Enhanced Control Pin Set (see Note 5 and Note 6) When DCR0 = 0, the device functions with the basic pin set, and the internal pullups are enabled for the RP, BAA/LRV, and WORD/DIS pins. When DCR0 = 1, the device functions with the enhanced pin set. See the Terminal Functions table and Table 9 OE functionality 0 = Synchronous OE 1 = Asynchronous OE (see Note 5 and Note 6) When DCR1 = 0, OE functions as a synchronous output enable. When DCR1 = 1, OE functions asynchronously. See the Terminal Functions table and Table 9 WE functionality 0 = Synchronous WE 1 = Asynchronous WE (see Note 5 and Note 6) When DCR2 = 0, WE functions as a synchronous write enable. When DCR2 = 1, WE functions asynchronously. See the Terminal Functions table and Table 9 WORD/DIS functionality 0 = DIS, and x32 mode 1 = WORD (see Note 5 and Note 6) When DCR3 = 0, pin 78 functions as output disable (DIS) and the device is forced into x32 mode. When DCR3 = 1, pin 78 functions as WORD (for x16 mode, set WORD = VIL; and for x32 mode, set WORD = VIH). See the Terminal Functions table and Table 9 DCR4 BAA/LRV functionality 0 = LRV 1 = BAA (see Note 5 and Note 6) When DCR4 = 0, pin 79 functions as low regulator voltage (LRV) and its status can be monitored in SB4. When DCR4 = 1, pin 79 functions as burst address advance (BAA). See the Terminal Functions table and Table 9 DCR5 Main block control 0 = 3 Main Blocks 1 = 4 Main Blocks (see Note 5 and Note 6) When DCR5 = 0, the main memory array has three blocks, as seen in Figure 1. When DCR5 = 1, the main memory array has four blocks, as seen in Figure 2. See Table 1. DCR7, DCR6 Internal timing control Refer to switching characteristics for tCHCH1 and tCHQV (see Note 5 and Note 6) These bits are used to optimize device performance (see switching characteristics table). DCR0 DCR1 DCR2 DCR3 NOTES: 5. The default setting for these bits is set at the factory prior to shipping. 6. These bits return to the default setting after a power-on reset is performed; therefore, it is necessary to program these bits to the desired configuration. 12 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 TMS28F033 4194304-BIT SYNCHRONOUS FLASH MEMORY SMJS833 – NOVEMBER 1997 device configuration defaults (continued) Table 8. Device Configuration Register Bit Definitions and Functions (Continued) DCR8 – DCR23 FUNCTION Reserved for Texas Instruments (TI) and should not be used DATA COMMENTS 0000h 00 01 10 11 = = = = MOD4 (default) MOD8 MOD16 MOD32 (see Note 6) There are four available burst length settings. The MOD4 burst is a modulo burst of four words/double-words for x16/x32, respectively. The other available burst lengths are MOD8, MOD16, and MOD32 (see Table 12). DCR25, DCR24 Burst length DCR27, DCR26 Reserved for TI and should not be used 00 – (default) (see Note 6) Burst latency (X) 00 = OE-controlled (default if in x32 mode and when OE is synchronous) 01 = 3 cycles 10 = 4 cycles (default if in x16 mode or when OE is asynchronous) 11 = 5 cycles (see Note 6) The four X latency possibilities are OE-controlled burst, and 3, 4, or 5 clock cycles for BAA-controlled burst. X latency denotes the number of clock cycles required to access the first word from memory (see Table 10 and Table 11). Burst latency (Y) 0 = 1 cycle (default) 1 = 2 cycles (see Note 6) The two Y latency possibilities are one clock cycle and two clock cycles. Y latency denotes the number of clock cycles required to access the subsequent words to complete the cache fill (see Table 10 and Table 11). One- or two-word write option for x16 mode 0 = Program one word (two-cycle write) (default) 1 = Program two words (three-cycle write) (see Note 6) Applicable for x16 mode only. When DCR31 = 0, only one word (16 bits) is programmed in two cycles for each program command received by the CSM. When DCR31 = 1, two words (32 bits) are programmed in three cycles for each program command received by the CSM (see Table 5). DCR29, DCR28 DCR30 DCR31 NOTES: 5. The default setting for these bits is set at the factory prior to shipping. 6. These bits return to the default setting after a power-on reset is performed; therefore, it is necessary to program these bits to the desired configuration. control pin functions The DCR0 bit is the control pin configuration bit that selects between the basic or enhanced pin set (see Table 8 and Table 9). With the enhanced pin set (DCR0 = 1), five additional pins are available: chip enable (E), data valid (QV), ready/busy (RY/BY), 3.3-V/5-V IO voltage select (3/5IO), and linear burst order (LBO). With the basic pin set (DCR0 = 0), neither QV nor RY/BY are available, both E and LBO are effectively tied low (VIL), and 3/5IO is effectively tied high (VIH). The DCR1 and DCR2 bits determine the synchronous or asynchronous operation of output enable (OE) and write enable (WE), respectively. DCR3 determines the function of pin 78 as either output disable (DIS) or word enable (WORD) (see the Terminal Functions table). When DCR3 = 0 (for DIS usage) the device is forced into using the 32-bit data bus (see Figure 21). When DCR3 = 1, both the 16-bit and 32-bit data buses are available. The DCR4 bit determines the function of pin 79 as either low-regulator-voltage detection (LRV) or burst-address advance (BAA). TI is a trademark of Texas Instruments Incorporated. POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 13 ADVANCE INFORMATION DCR BIT TMS28F033 4194304-BIT SYNCHRONOUS FLASH MEMORY SMJS833 – NOVEMBER 1997 control pin functions (continued) Table 9. DCR-Controlled Pin Functions PIN NUMBER DCR BIT (x) DCRx = 0 DCRx = 1 68 0 Hi-Z QV 69 0 Hi-Z RY/BY 72 0 3.3-V IO 3/5IO 74 0 Chip Enabled E 75 1 Synchronous OE Asynchronous OE 76 2 Synchronous WE Asynchronous WE 78 3 DIS WORD 79 4 LRV BAA 80 0 Linear Burst LBO ADVANCE INFORMATION burst length The burst length, as determined by DCR24 – DCR25, is the length of the data sequence (or number of memory locations) to be read for each entered address. When using BAA (DCR4 = 1), there are four possibilities for burst length: modulo 4 addressing (MOD4), MOD8, MOD16, and MOD32. For MOD4, when the initial address is XXXX0h, the internal burst address order is 0–1–2–3 for linear burst (LBO = VIL). MOD8, MOD16, and MOD32 function as 0–1–2 . . . 6–7, 0–1–2 . . . 14–15, and 0–1–2 . . . 30–31, respectively. Burst delivery is critical word first with wrap around. burst access and burst performance The notation X–Y– . . . –Y is used to denote the X and Y burst latency for the data sequence to be burst. X-latency (DCR28 – DCR29) denotes the number of clock cycles required to access the first word/double-word from memory, and Y-latency (DCR30) denotes the number of clock cycles required to access the subsequent words/double-words to complete the cache fill (see Table 10). The four X-latency possibilities are: OE-controlled, and 3, 4, or 5 clock cycles. The two Y-latency possibilities are 1 and 2 clock cycles. The burst performance for < 25 MHz, < 33 MHz, and < 40 MHz for linear and interleave burst order is listed in Table 11. Table 10. Burst Access Combinations (see Note 7) DEVICE CONFIGURATION REGISTER BITS DCR30 DCR29 DCR28 BURST ACCESS (CLOCK CYCLES TO READ) 0 0 0 X–1– . . . –1 (see Note 8) 0 0 1 3–1– . . . –1 0 1 0 4–1– . . . –1 0 1 1 5–1– . . . –1 1 0 0 X–2– . . . –2 (see Note 8) 1 1 0 4–2– . . . –2 NOTES: 7. These burst access combinations are available for MOD4, MOD8, MOD16, and MOD32. 8. For both DCR30 – DCR28 = 000 and DCR30 – DCR28 = 100, the X-latency is OE-controlled. 14 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 TMS28F033 4194304-BIT SYNCHRONOUS FLASH MEMORY SMJS833 – NOVEMBER 1997 burst access and burst performance (continued) Table 11. Burst Performance (Clock Cycles to Read) x16 Mode x32 Mode LINEAR† FREQUENCY (MHz) INTERLEAVE LINEAR 4–2– . . . –2 4–2– . . . –2 4–2– . . . –2 4–2– . . . –2 5–1– . . . –1 4–1– . . . –1 4–2– . . . –2 — — — A–1 = 0 A–1 = 1 < 25 (see Note 9) 4–2– . . . –2 < 33 (see Note 9) < 40 (see Notes 9 and 10) 5–2– . . . –2 † The state of A–1 when the address is latched (at CLK 1 in Figure 14) NOTES: 9. The Y-latency notation for MOD4 has three 1s/2s (–1–1–1/–2–2–2). For MOD8, there are seven 1s/2s (–1–1–1–1–1–1–1/–2–2–2–2–2–2–2). MOD16 has fifteen 1’s/2’s, and MOD32 has 31 1’s/2’s. 10. To obtain 5–2– . . . –2 (40 MHz), the required DCR settings are 4–2– . . . –2, and asynchronous OE with BAA-controlled burst. Burst suspension is the ability to hold the address advance and the data on the output I/Os DQ0 – DQ7 and DQ24– DQ31 if in x16 mode, or on DQ0 – DQ31 if in x32 mode. For DCR4 = 1, the suspension of a burst sequence is possible by bringing BAA high. To resume the burst, bring BAA low again (see Figure 18). When DCR4 = 0, the suspension of the burst is possible by bringing OE high. To resume the burst, bring OE low again. linear burst order (LBO) When performing a burst read, a single starting address is entered into the device and then the TMS28F033 internally accesses a sequence of locations based on that starting address. The burst sequence is determined by the linear burst order (LBO) setting (see the Terminal Functions table). When LBO = VIL, the burst order is linear 0–1–2–3 . . . .; and when LBO = VIH, the burst order is interleave (see Table 12). Linear burst order is available with MOD4, MOD8, MOD16, and MOD32. Interleave burst order is available only with MOD4, and only with the 16-bit data bus. Table 12. 2-Bit Linear and Interleaved-Burst Sequences (MOD4) ADDRESS A1 – A0 For x32 Mode, AND A0 – A–1 For x16 Mode BURST SEQUENCE Linear (see Note 11) Interleave (see Note 12) DECIMAL BINARY START 2ND 3RD 4TH† START 2ND 3RD 4TH† 0 1 2 3 00 01 10 11 1 2 3 0 01 10 11 00 2 3 0 1 01 10 11 00 3 0 1 2 11 00 01 10 0 1 2 3 00 01 10 11 1 0 3 2 01 00 11 10 2 3 0 1 10 11 00 01 3 2 1 0 11 10 01 00 † Burst sequence continues until OE or BAA is brought high. NOTES: 11. Linear burst is available with both x16 and x32 for MOD4, MOD8, MOD16, and MOD32. For linear burst set LBO=VIL. 12. Interleaved burst is available only with MOD4, and only with the 16-bit data bus. For interleave burst set LBO =VIH. word (X16) write option DCR31 determines the number of write cycles for word-wide programming. For DCR31 = 0, the device performs two-cycle writes, or with DCR31 = 1, the device performs three-cycle writes (see Table 5). See Figure 22 and Figure 24 for synchronous two- and three-cycle writes, respectively. For asynchronous two-cycle writes, see Figure 23. POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 15 ADVANCE INFORMATION burst suspend/resume TMS28F033 4194304-BIT SYNCHRONOUS FLASH MEMORY SMJS833 – NOVEMBER 1997 operation modes for word-wide (x16) or double-word-wide (x32) mode selection ADVANCE INFORMATION In x32 configuration, the memory array is divided into two parts: a lower half that outputs data through I/O pins DQ0– DQ7 and DQ24 – DQ31, and an upper half that outputs data through DQ8 – DQ23. Device operation in either x16 mode or x32 mode is user-selectable by configuring DCR3 = 1. This allows the input WORD logic state to determine either x16 or x32 mode. When WORD is at a logic-high level, the device is in the double-word-wide (x32) mode and data is written to or read from I/O pins DQ0 – DQ31. When WORD is at a logic-low level, the device is in the word-wide (x16) mode and data is written to or read from I/O pins DQ0 – DQ7 and DQ24 – DQ31. In the word-wide mode, I/O pins DQ8 – DQ23 are placed in the high-impedance state and A –1 becomes the low-order address pin that selects either the upper or lower half of the array. Array data from the upper half (DQ0 – DQ7, DQ24 – DQ31) and the lower half (DQ8 – DQ23) are multiplexed in order to appear on DQ0 – DQ7 and DQ24 – DQ31. The operation modes for word-wide and double-word-wide configurations are summarized in Table 13 and Table 14, respectively. 16 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 TMS28F033 4194304-BIT SYNCHRONOUS FLASH MEMORY SMJS833 – NOVEMBER 1997 operation modes for word-wide (x16) or double-word-wide (x32) mode selection (continued) Table 13. Operation Modes for Word-Wide Mode (x16) (See Note 2 and Note 14) MODE CLK A (Addr Bus) E WR WE LBA BAA OE DQ (Data Bus) (see Note 14) QV RY/BY VPP RP L–H Address VIL VIH X VIL X VIH Hi-Z Hi-Z Hi-Z X VIH Latch pipelined read address L–H Address VIL VIH X VIL X VIH Data out VOL Hi-Z X VIH Latch pipelined read address with early overlap L–H Address VIL VIH X VIL X VIL Hi-Z Hi-Z Hi-Z X VIH Wait (prior to first data read) L–H X VIL X X VIH X VIH Hi-Z Hi-Z Hi-Z X VIH Latch read data L–H X X X Hi-Z Hi-Z X X X X X VIL X Hi-Z L–H VIH VIH X Drive read data VIL VIL Data out Hi-Z X Burst read L–H X X X X X VIL VIH X X VIL VIH Hi-Z L–H VIH VIH Data out Burst terminate VIL VIL VOL VOL VIH VIH Data out VOL Hi-Z X VIH VIH Burst suspend (see Note 15) L–H X VIL X X VIH VIH X Data out VOL Hi-Z X VIH Update status during algorithm L–H X VIL X X X X VIL X X X X VIH Read status during algorithm L–H X VIL X X X X X Status out VOL X X VIH Read overlay L–H X VIL X X X X VIL Overlay data out VOL Hi-Z VPPH VIH ADVANCE INFORMATION READ OPERATION MODES Latch non-pipelined read address SYNCHRONOUS WRITE OPERATION MODES Latch write address L–H Address VIL VIL X VIL X VIH X X Hi–Z X VIH Latch write address/data L–H Address VIL VIL VIL VIL X VIH Data in Hi-Z Hi-Z X VIH Latch write data L–H X VIL VIH VIL VIH X VIH Data in ASYNCHRONOUS WRITE OPERATION MODES Hi-Z Hi-Z X VIH X Address VIL Data in Hi-Z Hi-Z X VIH Latch write address/data X L–H X X VIH OTHER OPERATION MODES Standby X X VIH X X X X X Hi-Z Hi-Z X X VIH Reset/deep power down X X X X X X X X Hi-Z Hi-Z VOH X VIL NOTES: 13. X is a don’t care. 14. For x16 mode (WORD = VIL when DCR3 = 1), the data lines are DQ0 – DQ7 and DQ24 – DQ31. 15. This mode freezes the burst counter and holds the current data line values. POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 17 TMS28F033 4194304-BIT SYNCHRONOUS FLASH MEMORY SMJS833 – NOVEMBER 1997 operation modes for word-wide (x16) or double-word-wide (x32) mode selection (continued) Table 14. Operation Modes for Double-Word-Wide Mode (x32) (See Note 13 and Note 16) MODE CLK A (Addr Bus) E WR WE LBA BAA OE DQ (Data Bus) (see Note 16) QV RY/BY VPP RP ADVANCE INFORMATION READ OPERATION MODES Latch non-pipelined read address L–H Address VIL VIH X VIL X VIH Hi-Z Hi-Z Hi-Z X VIH Latch pipelined read address L–H Address VIL VIH X VIL X VIH Data out VOL Hi-Z X VIH Latch pipelined read address with early overlap L–H Address VIL VIH X VIL X VIL Hi-Z Hi-Z Hi-Z X VIH Wait (prior to first data read) L–H X VIL X X VIH X VIH Hi-Z Hi-Z Hi-Z X VIH Latch read data L–H X X X Hi-Z Hi-Z X X X X X VIL X Hi-Z L–H VIH VIH X Drive read data VIL VIL Data out VOL Hi-Z X VIH VIH Burst read L–H X X X X X X VIL VIH Hi-Z X VIL VIH VOL L–H VIH VIH Data out Burst terminate VIL VIL Data out VOL Hi-Z X VIH VIH Burst suspend (see Note 15) L–H X VIL X X VIH VIH X Data out VOL Hi-Z X VIH Update status during algorithm L–H X VIL X X X X VIL X X X X VIH Read status during algorithm L–H X VIL X X X X X Status out VOL X X VIH Read overlay L–H X VIL X X X X VIL Overlay data out VOL Hi-Z VPPH VIH SYNCHRONOUS WRITE OPERATION MODES Latch write address L–H Address VIL VIL X VIL X VIH X X Hi-Z X VIH Latch write address/data L–H Address VIL VIL VIL VIL X VIH Data in Hi-Z Hi-Z X VIH Latch write data L–H X VIL VIH VIL VIH X VIH Data in ASYNCHRONOUS WRITE OPERATION MODES Hi-Z Hi-Z X VIH X Address VIL Data in Hi-Z Hi-Z X VIH Latch write address/data X L–H X X VIH OTHER OPERATION MODES Standby X X VIH X X X X X Hi-Z Hi-Z X X VIH Reset/deep power down X X X X X X X X Hi-Z Hi-Z VOH X VIL NOTES: 13. X is a don’t care. 15. This mode freezes the burst counter and holds the current data line values. 16. For x32 mode (WORD=VIH when DCR3=1, or DCR3=0) the data lines are DQ0 – DQ31. 18 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 TMS28F033 4194304-BIT SYNCHRONOUS FLASH MEMORY SMJS833 – NOVEMBER 1997 clear status register For DCR4 = 0 (LRV usage), the WSM can set the VPP status bit (SB3), the low-regulator-voltage status bit (SB4), and the operation status bit (SB5). For DCR4 = 1, the WSM can set the VPP status bit (SB3), the program status bit (SB4), and the erase status bit (SB5) of the status register. The clear-status-register command (50h) allows the external microprocessor to clear SB3, SB4, and SB5. When the status bits are cleared, the device returns to the read-array mode. load device configuration register The load DCR command is a two-bus-cycle command that loads the device configuration register. When the DCR load command (96h) is written to the CSM, the CSM will set up the device configuration register to be loaded on the next write cycle. On the second cycle, the configuration data DDDDh loads the two bytes of the device configuration register DCR0 – DCR7 and DCR24 – DCR31 (see Table 5 and Table 6). DCR8 – DCR23 and DCR26 – DCR27 are reserved and should be loaded with 0s. There are three read operations available: read array, read algorithm-selection code, and read status register. See Table 13 and Table 14 for the required control signals needed with synchronous reads. D Read array The read-array command consists of two bus cycles, and is listed in Table 5. For synchronous reads on the first bus cycle, the CSM command code FFh on DQ0 – DQ7 and the address 00000h are entered. The second bus cycle begins with the address phase where, for synchronous operation, LBA goes low on a rising clock edge. On the same clock (CLK 1 of Figure 14 for burst reads, or CLK 1 of Figure 27 for single reads), the address is latched and WR is sampled. For a read, WR is set high, and the device is ready for the read-data phase. The data phase follows the address phase by one or more clock cycles, where OE goes low on a rising clock edge and the data is driven onto the bus DQ0 – DQ31 for x32, and DQ0 – DQ7 with DQ24– DQ31 for x16. For single reads, the data is valid for CLK 3 (see Figure 27). For burst reads, on CLK 3 of Figure 14, BAA is brought low to burst the second data segment. OE is kept low for four clock cycles (CLKs 2–5) and BAA is kept low for three CLKs (CLKs 3 – 5), which bursts four words for MOD4. Burst reads for burst lengths MOD8, MOD16, or MOD32 are accomplished by holding OE and BAA low for each data segment in the same way (see Figure 14 through Figure 21). The optional output valid (QV) goes low when valid data is output from the device (see the Terminal Functions table, Figure 14 through Figure 21, and Figure 27). D D Read algorithm-selection code As listed in Table 5, CSM command code 90h is written on DQ0 – DQ7. Two bus cycles are required for this operation: the first to enter the command code and a second to read the manufacturer/device code or DCR value by loading the required A1A0 address bits (see Table 5 and Table 6). By loading a new address, the manufacturer-equivalent code is obtained on DQ0 – DQ7 with both A1 and A0 at a logic-level VIL. Similarly, the device-equivalent code is obtained when A1 is set to VIL and A0 is set to VIH. The device configuration register value is obtained when A1 is set to VIH and A0 is set to VIL. Read status register The status register is read by entering the command code 70h on DQ0 – DQ7. Two bus cycles are required for this operation: one to enter the command code and a second to read the status register (see Table 5). The status register contents are updated on every clock cycle. The device interface is synchronous but supports asynchronous read timings, which hold the address valid and LBA low throughout the address and data phases as required by some microprocessors after power-up (see Figure 13). POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 19 ADVANCE INFORMATION read operations TMS28F033 4194304-BIT SYNCHRONOUS FLASH MEMORY SMJS833 – NOVEMBER 1997 programming operations There are two program operations available: program-setup/program to main array program-setup/program to overlay block. Both are available with synchronous or asynchronous writes. and ADVANCE INFORMATION Both the x16 and x32 data bus configurations have a two-bus-cycle write capability, where in two bus cycles, either one 16-bit word or one 32-bit word is programmed, respectively. In addition, three-cycle writes are available with the 16-bit data bus by configuring DCR31(see Table 8). On the first cycle, which is the command cycle, the CSM command code 40h or 04h is loaded to set up the device for programming either to the main array or to the overlay block array, respectively. On the second cycle, which is the write-data cycle, the data is loaded. After the desired command code and data are loaded, the WSM takes over and correctly sequences the device to complete the program operation. During this time, the CSM responds only to status reads until the program operation has been completed, after which all commands to the CSM become valid again. Once a program command has been issued, the WSM cannot normally be interrupted until the program algorithm is completed. Monitoring of the write operation is possible through the status register or the ready/busy (RY/BY) pin (see Figure 22 and Figure 24). See Figure 22 and Figure 24 for two- and three-cycle synchronous writes respectively. For asynchronous writes, the address and command/data are latched on the rising edge of WE (see Figure 23 for asynchronous write). Taking RP to VIL during programming aborts the program operation. During programming, VPP must remain VPP ≥ VPPH (see Figure 22 and Figure 23). Only 0s are written and compared during a program operation. If 1s are programmed, the memory cell contents do not change and no error occurs. A program-setup command can be aborted by writing FFFFh on DQ0 – D7 and DQ24 – DQ31 (in word-wide mode), or FFFFFFFFh (in double-word-wide mode) during the second cycle. After writing all 1s during the second cycle, the CSM responds only to status reads. When the WSM status bit (SB7) is set to a logic-high level, signifying the nonprogram operation is terminated, all commands to the CSM become valid again. erase operations There are two erase operations that can be performed: block-erase-setup/confirm main array (20h/D0h) and block-erase-setup/confirm overlay block (02h/0Dh). An erase operation must be used to initialize all bits in an array block to 1s. After block-erase confirm is issued, the CSM responds only to status reads until the WSM completes its task. Both of these erase operations are available with synchronous and asynchronous writes. Block erasure inside the memory array sets all bits within the addressed block to logic 1s. Erasure is accomplished only by blocks; data at single address locations within the array cannot be individually erased. The block to be erased is selected by using any valid address within that block. Block erasure is initiated by a command sequence to the CSM: block-erase setup (20h/02h) followed by block-erase confirm (D0h/0Dh) (see Figure 25 and Figure 26). This two-command erase sequence protects against accidental erasure of memory contents. Asynchronous erase-setup and confirm commands are latched on the rising edge of WE, and block addresses are latched during the block-erase-confirm command on the rising edge of WE. For both synchronous and asynchronous operations, when the block-erase-confirm command is complete, the WSM automatically executes a sequence of events to complete the block erasure. During this sequence, the block is programmed with logic 0s, data is verified, all bits in the block are erased, and verification is performed to ensure that all bits are correctly erased. Monitoring of the erase operation is possible through the status register or the ready/busy (RY/BY) pin (see Figure 25 and Figure 26). Taking RP to VIL during erasing aborts the erase operation. During erasing, VPP must remain VPP>=VPPH as seen in Figure 25 and Figure 26. 20 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 TMS28F033 4194304-BIT SYNCHRONOUS FLASH MEMORY SMJS833 – NOVEMBER 1997 reduced power mode The command F0h, when written to the CSM, puts TMS28F033 in reduced-power mode (not to be confused with RP). This mode is used when the chip-enable, E, input is not used and reduced power consumption is needed. However, the device does not have its outputs disabled; instead, it can respond to any CSM command at any time and then its power comes back up. When in reduced power mode, the outputs are still OE-controlled. RP input (reset/deep power-down mode) When RP is high, the memory functions normally. When RP goes low, any CSM activity is terminated immediately. While RP is low, the memory does not respond to read requests and does not accept write commands. When RP goes high, the memory is reinitialized and prepared for normal operation (read mode), and sets/clears OBEB based on VPP (see Table 3). Low-power-program mode is activated by entering the command code 60h. The low-power-programming mode enable/disable is a single-cycle command that toggles the state of the LPM bit in the status register. Depending on the LPM status register bit (see Table 7), the WSM programs by bytes (low-power mode) or by words (normal mode) (see Table 5 for CSM command). low regulator voltage (LRV) LRV is selected for use by setting DCR4 = 0. This signal can be generated by an external power supply monitor and should go low when VPP is out of regulation (VPP ≤ VPPH). The WSM periodically samples the LRV input during erasing and programming. When LRV goes low, the status register SB4 is set, providing a more accurate monitor of VPP than the VPP status bit (SB3). pipelining This device supports efficient bus usage by latching the address on the first clock cycle of a read operation, and then delaying the data phase (delay bringing OE low), thereby allowing the address and data buses to be used by other parts of the system. overlapping data and address phases The address and data phases of consecutive synchronous read or write operations can be overlapped by one or more clock cycles. This is done by bringing LBA low to latch a new address before the completion of the data phase of the current cycle. For overlapping synchronous single reads, and overlapping synchronous single reads with writes, see Figure 27. For overlapping burst reads, see Note C in Figure 14 and Figure 15. For overlapping synchronous write cycles, see Figure 24. POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 21 ADVANCE INFORMATION low-power-program mode TMS28F033 4194304-BIT SYNCHRONOUS FLASH MEMORY SMJS833 – NOVEMBER 1997 BUS OPERATION Start Write Issue Program-Setup Command and Address COMMAND Write program setup COMMENTS Data = 40h for main array or 04h for overlay block Addr = 00000h for synchronous WE or XXXXXh for asynchronous WE Issue Word Data and Address Write See Note A Write Data = Word to be programmed Addr = Address of word to be programmed Read Status-register data. Status register is updated on each rising clock. Wait Check SB7 1 = Ready, 0 = Busy Read Status-Register Bits ADVANCE INFORMATION Repeat for subsequent words. Write read-array command after the last word-program operation to reset the device to read-array mode. No SB7 = 1 ? Yes Full Status-Register Check (optional) See Note B Word-Program Completed FULL STATUS-REGISTER-CHECK FLOW Read Status-Register Bits BUS OPERATION No SB3 = 0 ? COMMAND Wait Check SB3 1 = Detect VPP low (see Note C) Wait Check SB4 1 = Detect LRV low (see Note D) Wait Check SB5 1 = Word-program error (see Note D) VPP Range Error Yes No SB4 = 0 ? COMMENTS LRV Detected Yes No SB5 = 0 ? Word-Program Failed Yes Word-Program Passed NOTES: A. B. C. D. In this flowchart, the use of “word” refers to both 16-bit and 32-bit data-bus widths. Full status-register check can be done after each word or after a sequence of words. SB3 must be cleared before attempting additional program / erase operations. SB4 and SB5 are cleared only by the clear-status-register command, but this does not prevent additional program operation attempts. Figure 4. Automated Programming Flowchart (DCR4 = 0) 22 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 TMS28F033 4194304-BIT SYNCHRONOUS FLASH MEMORY SMJS833 – NOVEMBER 1997 BUS OPERATION Start Write Issue Program-Setup Command and Address COMMENTS Write program setup Data = 40h for main array or 04h for overlay block Addr = 00000h for synchronous WE or XXXXXh for asynchronous WE Write Issue Word Data and Address COMMAND Write See Note A Data = Word to be programmed Addr = Address of word to be programmed Read Status-Register Bits Read Status-register data. Status register is updated on each rising clock. Wait Check SB7 1 = Ready, 0 = Busy ADVANCE INFORMATION Repeat for subsequent words. Write read-array command after the last word-program operation to reset the device to read-array mode. No SB7 = 1 ? Yes Full Status-Register Check (optional) See Note B Word-Program Complete FULL STATUS-REGISTER-CHECK FLOW Read Status-Register Bits BUS OPERATION No SB3 = 0 ? VPP Range Error COMMAND Wait Check SB3 1 = Detect VPP low (see Note C) Wait Check SB4 1 = Word-program error (see Note D) Yes No SB4 = 0 ? COMMENTS Word-Program Failed Yes Word-Program Passed NOTES: A. B. C. D. In this flowchart, the use of “word” refers to both 16-bit and 32-bit data-bus widths. Full status-register check can be done after each word or after a sequence of words. SB3 must be cleared before attempting additional program / erase operations. SB4 is cleared only by the clear-status-register command, but this does not prevent additional program operation attempts. Figure 5. Automated Programming Flowchart (DCR4 = 1) POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 23 TMS28F033 4194304-BIT SYNCHRONOUS FLASH MEMORY SMJS833 – NOVEMBER 1997 BUS OPERATION Start Write Issue Program-Setup Command and Address COMMAND COMMENTS Write program setup Data = 40h for main array or 04h for overlay block Addr = 00000h for synchronous WE or XXXXXh for asynchronous WE Issue First x16-Word Data and Address A–1 Write Write Write Write Issue Second x16-Word Data and Address Addr = A–1 (see Table 3) Data = Second x16 word to be programmed Addr = Address of x16 word to be programmed Read Status-Register Bits No ADVANCE INFORMATION Data = First x16 word to be programmed SB7 = 1 ? Read Status-register data. Status register is updated on each rising clock. Wait Check SB7 1 = Ready, 0 = Busy Repeat for subsequent words. Write read-array command after the last word-program operation to reset the device to read-array mode. Yes Full Status-Register Check (optional) See Note A Word-Program Completed FULL STATUS-REGISTER-CHECK FLOW Read Status-Register Bits BUS OPERATION COMMAND Wait No SB3 = 0 ? COMMENTS Check SB3 1 = VPP Range Error Wait Check SB4 1 = Yes Wait No SB4 = 0 ? LRV Detected Detect VPP low (see Note B) Detect LRV low (see Note C) Check SB5 1 = Word-program error (see Note C) Yes No SB5 = 0 ? Word-Program Failed Yes Word-Program Passed NOTES: A. Full status-register check can be done after each word or after a sequence of words. B. SB3 must be cleared before attempting additional program / erase operations. C. SB4 and SB5 are cleared only by the clear-status-register command, but this does not prevent additional program operation attempts. Figure 6. Automated x16 Word-Programming Flowchart With Three-Cycle Write (DCR4 = 0) 24 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 TMS28F033 4194304-BIT SYNCHRONOUS FLASH MEMORY SMJS833 – NOVEMBER 1997 BUS OPERATION Start Write Issue Program-Setup Command and Address COMMAND COMMENTS Write program setup Data = 40h for main array or 04h for overlay block Addr = 00000h for synchronous WE or XXXXXh for asynchronous WE Issue First x16 Word Data and Address A–1 Issue Second x16 Word Data and Address Write Write Write Write Data = First x16 word to be programmed Addr = A–1 (see Table 3) Data = Second x16 word to be programmed Addr = Address of x16 word to be programmed Status-register data. Status register is updated on each rising clock. Wait Check SB7 1 = Ready, 0 = Busy Repeat for subsequent words. Write read-array command after the last word-program operation to reset the device to read-array mode. No SB7 = 1 ? Read ADVANCE INFORMATION Read Status-Register Bits Yes Full Status-Register Check (optional) See Note A Word-Program Completed FULL STATUS-REGISTER-CHECK FLOW Read Status-Register Bits SB3 = 0 ? No VPP Range Error BUS OPERATION Yes SB4 = 0 ? COMMAND Wait Check SB3 1 = Detect VPP low (see Note B) Wait Check SB4 1 = Word-program error (see Note C) No Word-Program Failed COMMENTS Yes Word-Program Passed NOTES: A. Full status-register check can be done after each word or after a sequence of words. B. SB3 must be cleared before attempting additional program / erase operations. C. SB4 is cleared only by the clear-status-register command, but this does not prevent additional program operation attempts. Figure 7. Automated x16 Word-Programming Flowchart With Three-Cycle Write (DCR4 = 1) POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 25 TMS28F033 4194304-BIT SYNCHRONOUS FLASH MEMORY SMJS833 – NOVEMBER 1997 BUS OPERATION Start Write Issue Erase-Setup Command and Address COMMAND Write erase setup COMMENTS Data = 20h for main array or 02h for overlay block Addr = 00000h for synchronous WE or XXXXXh for asynchronous WE Issue Block-Erase-Confirm and Block Address Write Erase Data = D0h for main array or 0Dh for overlay block Block Addr Read Status-Register Bits ADVANCE INFORMATION Read Status-register data. Status register is updated on each rising clock. Wait Check SB7 1 = Ready, 0 = Busy No SB7 = 1 ? = Address within block to be erased Repeat for subsequent words. Write read-array command after the last word-program operation to reset the device to read-array mode. Yes Full Status-Register Check (optional) See Note A Block-Erase Completed FULL STATUS-REGISTER-CHECK FLOW Read Status-Register Bits BUS OPERATION No SB3 = 0 ? VPP Range Error Yes COMMAND Wait Check SB3 1 = Detect VPP low (see Note B) Wait Check SB4 1 = Detect LRV low (see Note C) Wait Check SB5 1 = Block-erase error (see Note C) No SB4 = 0 ? LRV Detected COMMENTS Yes No SB5 = 0 ? Block-Erase Failed Yes Block-Erase Passed NOTES: A. Full status-register check can be done after each block or after a sequence of blocks. B. SB3 must be cleared before attempting additional program / erase operations. C. SB4 and SB5 are cleared only by the clear-status-register command, but this does not prevent additional erase operation attempts. Figure 8. Automated Block-Erase Flowchart (DCR4 = 0) 26 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 TMS28F033 4194304-BIT SYNCHRONOUS FLASH MEMORY SMJS833 – NOVEMBER 1997 BUS OPERATION Start Write Issue Erase-Setup Command and Address COMMAND Write erase setup COMMENTS Data = 20h for main array or 02h for overlay block Addr = 00000h for synchronous WE or XXXXXh for asynchronous WE Issue Block-Erase-Confirm Command and Block Address Write Erase Data = D0h for main array or 0Dh for overlay block Block Addr Read Status-Register Bits Address within block to be erased Read Status-register data. Status register is updated on each rising clock. Wait Check SB7 1 = Ready, 0 = Busy No SB7 = 1 ? = ADVANCE INFORMATION Repeat for subsequent words. Write read-array command after the last word-program operation to reset the device to read-array mode. Yes Full Status-Register Check (optional) See Note A Block-Erase Completed FULL STATUS-REGISTER-CHECK FLOW Read Status-Register Bits BUS OPERATION No SB3 = 0 ? VPP Range Error Yes SB4 = 1, SB5 = 1 ? Yes COMMAND COMMENTS Wait Check SB3 1 = Detect VPP low (see Note B) Wait Check SB4 and SB5 1 = Block-erase command error Wait Check SB5 1 = Block-erase error (see Note C) Command Sequence Error No No SB5 = 0 ? Block-Erase Failed Yes Block-Erase Passed NOTES: A. Full status-register check can be done after each block or after a sequence of blocks. B. SB3 must be cleared before attempting additional program / erase operations. C. SB5 is cleared only by the clear-status-register command, but this does not prevent additional erase operation attempts. Figure 9. Automated Block-Erase Flowchart (DCR4 = 1) POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 27 TMS28F033 4194304-BIT SYNCHRONOUS FLASH MEMORY SMJS833 – NOVEMBER 1997 absolute maximum ratings over ambient temperature range (unless otherwise noted)† ADVANCE INFORMATION Supply voltage range, VDDI (5 V) (see Note 17) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V Supply voltage range, VDDE (3.3 V) (see Note 17) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 4.6 V Input voltage range, VI (except VPP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to VDDE + 0.5 V Input voltage range, VI (VPP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 14 V Biased junction Temperature, TJ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150_C Ambient temperature, TA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . (L) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 V to 70°C (E) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –40 V to 85°C (Q) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –40 V to 125°C Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –55_C to 150_C Soldering temperature, TSO (IR reflow for 180 seconds) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 225_C Soldering temperature (maximum ramp rate) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6_C/s Thermal resistance, QJA (junction-to-ambient) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50_C/W Data retention (at 55_C ambient) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Years (minimum) Number of erase/write cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 000 Cycles † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTE 17: All voltage values are with respect to VSS. recommended operating conditions VDDI Supply voltage VDDE Output buffer supply voltage VIL VIH Input low voltage Input high voltage VPP VPPL Programming supply voltage VPPH Programming voltage high TA Ambient temperature during read/erase/program 28 MIN NOM MAX 4.5 5 5.5 3/5IO = VIH 3.0 3.3 3.6 3/5IO = VIL 4.5 5.0 5.5 –0.3 0.8 V 2.0 V 12 VDDE + 0.3 12.6 11.4 Programming voltage low 7 11.4 POST OFFICE BOX 1443 UNIT V V V V V L Suffix 0 70 °C E Suffix –40 85 °C Q Suffix –40 125 °C • HOUSTON, TEXAS 77251–1443 TMS28F033 4194304-BIT SYNCHRONOUS FLASH MEMORY SMJS833 – NOVEMBER 1997 double-word/word typical write and block-erase duration (see Notes 18 and 19) BLOCK SIZE ERASE OPERATION WRITE OPERATION ERASE LPP MODE x16 or x32 x16 or x32 x32 6K / 12K TBD TBD 16K / 32K TBD TBD 32K / 64K TBD 48K / 96K TBD 80K / 160K TBD x32 / x16 LOW-POWER PROGRAMMING MODE PROGRAMMING x16 2-CYCLE 3-CYCLE TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD x32 UNIT x16 2-CYCLE 3-CYCLE TBD TBD TBD s TBD TBD TBD s TBD TBD TBD TBD s TBD TBD TBD TBD s TBD TBD TBD TBD s electrical characteristics over recommended ranges of supply voltage and ambient temperature, VDDE = 3.3 V (see Notes 20 through 23) PARAMETER TEST CONDITIONS VOL† VOH† Output low voltage Output high voltage VDDI/VDDE = MIN, IOL = 100 mA VDDI/VDDE = MIN, IOH = –100 mA IDDI_pwdn IDDI power-down current VDDI/VDDE = MAX, RP= VIL ILI Input leakage VIN = GND to VDDE MAX, VDDI = VDDI MAX ILO Output leakage V0 = GND to VDDE MAX, DIS = VIL , VDDI = VDDI MAX IPU Internal pullup current (DIS, RP, LRV pins) (VDDI/VDDE = MIN, VPIN = 2.0 V) or (VDDI/VDDE = MAX, VPIN = 0 V) IDDI Supply current, internal IDDE MIN MAX 0.2 VDDE–0.2 UNIT V V TBD mA ±5 mA ± 10 mA 600 mA VDDI/VDDE = MAX, OE = VIL, at 25 MHz 100 mA Supply current, external VDDI/VDDE = MAX, OE = VIL, at 25 MHz, MOD4, x32 65 mA IPPS Supply current, for slow programming (low-power programming mode) VDDI/VPP/VDDE = MAX 50 mA IERSS Supply current, for slow erasing (low-power programming mode) VDDI/VPP/VDDE = MAX 50 mA 120 mA 120 mA IPPF Supply current, for fast programming VDDI/VPP/VDDE = MAX IERSF Supply current, for fast erasing VDDI/VPP/VDDE = MAX † Dependent on JEDEC standard 8–1A. NOTES: 20. Test results of erasing and programming with VPPL < VPP < VPPH are undefined. 21. Positive current flow is into the device. 22. Test supply voltage range: (4.5-V dc ≤ VDDI ≤ 5.5-V dc) and (3-V dc ≤ VDDE ≤ 3.6-V dc). 23. Device in read mode with OE enabled. POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 20 29 ADVANCE INFORMATION NOTES: 18. Excludes system-level overhead 19. Typical values shown are at TA = 25°C TMS28F033 4194304-BIT SYNCHRONOUS FLASH MEMORY SMJS833 – NOVEMBER 1997 electrical characteristics over recommended ranges of supply voltage and ambient temperature, VDDE = 5 V (see Notes 20, 21, 23, and 24) ADVANCE INFORMATION PARAMETER TEST CONDITIONS VOL† VOH† Output low voltage Output high voltage VDDI/VDDE = MIN, IOL = TBD VDDI/VDDE = MIN, IOH = TBD IDDI_pwdn IDDI power-down current VDDI/VDDE = MAX, RP= VIL ILI Input leakage VIN = GND to VDDE MAX, VDDI = VDDI MAX ILO Output leakage V0 = GND to VDDE MAX, DIS = VIL , VDDI = VDDI MAX IPU Internal pullup current (DIS, RP, LRV pins) (VDDI/VDDE = MIN, VPIN = 2.0 V) or (VDDI/VDDE = MAX, VPIN = 0 V) IDDI Supply current, internal IDDE MIN MAX UNIT 0.2 V TBD mA ±5 mA ± 10 mA TBD mA VDDI/VDDE = MAX, OE = VIL, at 25 MHz 100 mA Supply current, external VDDI/VDDE = MAX, OE = VIL, at 25 MHz, MOD4, x32 TBD mA IPPS Supply current, for slow programming (low-power programming mode) VDDI/VPP/VDDE = MAX 50 mA IERSS Supply current, for slow erasing (low-power programming mode) VDDI/VPP/VDDE = MAX 50 mA 120 mA 120 mA VDDE – 0.2 TBD IPPF Supply current, for fast programming VDDI/VPP/VDDE = MAX IERSF Supply current, for fast erasing VDDI/VPP/VDDE = MAX † Dependent on JEDEC standard 8–1A. NOTES: 20. Test results of erasing and programming with VPPL < VPP < VPPH are undefined. 21. Positive current flow is into the device. 23. Device in read mode with OE enabled. 24. Test supply voltage range: ( 4.5-V dc ≤ VDDI ≤ 5.5-V dc ) and ( 4.5-V dc ≤ VDDE ≤ 5.5-V dc ). V capacitance over recommended ranges of supply voltage and ambient temperature, f = 1 MHz, VI = 0 V PARAMETER Ci Input capacitance Co Output capacitance 30 TEST CONDITION VO = 0 V POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 MIN MAX UNIT 8 pF 12 pF TMS28F033 4194304-BIT SYNCHRONOUS FLASH MEMORY SMJS833 – NOVEMBER 1997 PARAMETER MEASUREMENT INFORMATION IOL VIH Output Under Test VZ VOH VOL VIL CL Voltage Waveforms (see Note A) IOH NOTES: A. CL includes probe and fixture capacitance. B. AC test conditions are driven at VIH and VIL. Timing measurements are made at VOH and VOL levels on both inputs and outputs. Refer to Table 16 for values based on VDDE operating range. ADVANCE INFORMATION Figure 10. Load Circuit and Voltage Waveforms Table 15. AC Test Conditions VDDE RANGE IOL (mA) IOH (mA) VZ† (V) VOL (V) VOH (V) VIL (V) VIH (V) CL (pF) tf (ns) tr (ns) 5 V ± 10% 1.0 –1.0 1.4 0.8 2.0 0.45 2.4 70 <5 <5 3.3 V ± 0.3V 1.0 –1.0 1.4 0.8 2.0 0.45 2.4 70 <5 <5 † VZ is the measured value used to detect the high-impedance state. Table 16. Timing Nomenclature SYMBOL PIN CHARACTERS A Address Inputs C D Q E SYMBOL PIN CONDITION H High Clock (CLK) L Low Data Inputs X Not valid Data Outputs Z High impedance E (Chip Enable) V Valid G OE (Output Enable) D Driven W WE (Write Enable) P RP (Reset/Power-Down) Y RY/BY (Ready/Busy) L LBA (Load Burst Address) B BAA (Burst Address Advance) S DIS (Disable Output) R WR (Write) V VPP (Write/Erase Power Supply) VDDI (Internal Power Supply) 5 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 31 TMS28F033 4194304-BIT SYNCHRONOUS FLASH MEMORY SMJS833 – NOVEMBER 1997 switching characteristics over recommended ranges of supply voltage and ambient temperature range, synchronous read operations (see Figure 11, Figure 14, and Figure 21) 3.3-V VDDE RANGE PARAMETER ADVANCE INFORMATION MIN MAX 5-V VDDE RANGE MIN UNITS MAX tCLK tCH CLK period (see Note 25) High time, clock 10 10 tCL tCLCH Low time, clock 10 10 tCHCL tCHAX Fall time, CLK Hold time, address from CLK high 3 3 ns tCHRL tCHLH Hold time, WR from CLK high 3 3 ns Hold time, LBA from CLK high 5 5 ns tCHBH tCHGH Hold time, BAA from CLK high TBD TBD ns Hold time, OE from CLK high 2 2 ns tCHSH tELCH Hold time, DIS from CLK high 2 2 ns TBD TBD ns tAVCH tRHCH Setup time, address to CLK high 10 10 ns 0 0 ns tLLCH tBLCH Setup time, LBA to CLK high 6 6 ns Setup time, BAA to CLK high TBD TBD ns tGLCH tSLCH Setup time, OE to CLK high 9 9 ns tCHCH1 ns Rise time, CLK 3 3 Setup time, E to CLK high Setup time, WR to CLK high Setup time, DIS to CLK high 12 LBA/CLK high to data latched (OE/CLK), for one wait-state access tCHQD OE/CLK high to data bus driven tCHQV OE/CLK high to data valid tCHQX tCHQZ CLK high to data invalid tCHQL CLK high to QV low ns 4 ns 12 ns 47 47 ns DCR7:6 = 01 43 43 ns DCR7:6 = 1X 40 40 ns 0 0 ns DCR7:6 = 00 22 TBD ns DCR7:6 = 01 26 TBD ns DCR7:6 = 1X 29 TBD ns 5 CLK high to data high Z (see Note 26) POST OFFICE BOX 1443 ns 4 DCR7:6 = 00 tCHQH CLK high to QV high NOTES: 25. tCLK min = max ((tCHCH1 / #ws), tCHQV + tdsu,cpu + tsys) where: tdsu,cpu = data setup time for CPU tsys = system margin #ws = number of wait states (CLKs) from address latched to data latched 26. IOL/IOH = ± 4 mA, value dependent on loading conditions 32 ns • HOUSTON, TEXAS 77251–1443 5 ns 40 40 ns TBD TBD ns TBD TBD ns TMS28F033 4194304-BIT SYNCHRONOUS FLASH MEMORY SMJS833 – NOVEMBER 1997 switching characteristics over recommended ranges of supply voltage and ambient temperature range, synchronous reads with asynchronous OE operations (see Figure 20) 3.3-V VDDE RANGE PARAMETER MIN tGLQD OE low to data bus driven tGLQV OE low to data valid tGHQX tGHQZ MAX 0 5-V VDDE RANGE MIN UNITS MAX 0 ns DCR[7:6] = 00 TBD TBD ns DCR[7:6] = 01 TBD TBD ns DCR[7:6] = 1X TBD TBD ns OE high to data invalid TBD OE high to data high Z TBD TBD ns TBD ns 3.3-V VDDE RANGE MIN tCHEH tCHRH Hold time, E from CLK high tCHWH tCHDX MAX 5-V VDDE RANGE MIN UNITS MAX TBD TBD ns Hold time, WR from CLK high 3 3 ns Hold time, WE from CLK high 2 2 ns Hold time, CLK high to data 3 3 ns tYHVL Hold time, VPP from RY/BY high 0 0 ns tCHYH1 Duration of double-word/word write operation TBD TBD TBD TBD ns tCHYH2 Duration of double-word/word write operation in low-power programming (LPP) mode TBD TBD TBD TBD ns tCHYH3 tCHYH4 Duration of block-erase operation TBD TBD TBD TBD ns Duration of block-erase operation in LPP mode TBD TBD TBD TBD ns tELCH tRLCH Setup time, E to CLK high TBD TBD ns 10 10 ns tWLCH tDVCH Setup time, WE to CLK high 9 9 ns Setup time, data to CLK high 10 10 ns tVHCH tCHYL Setup time, VPP to LBA/CLK high TBD TBD ns CLK high to RY/BY low TBD TBD ns Setup time, WR to CLK high POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 33 ADVANCE INFORMATION timing requirements over recommended ranges of supply voltage and ambient temperature range, synchronous write/erase operations (see Figure 22, Figure 24, and Figure 25) TMS28F033 4194304-BIT SYNCHRONOUS FLASH MEMORY SMJS833 – NOVEMBER 1997 timing requirements over recommended ranges of supply voltage and ambient temperature range, asynchronous write/erase operations (see Figure 23 and Figure 26) 3.3-V VDDE RANGE ADVANCE INFORMATION MIN MAX 5-V VDDE RANGE MIN UNITS MAX tWHWH tWHAX Cycle time, write TBD TBD ns Hold time, address from WE high TBD TBD ns tYHVL Hold time, VPP from RY/BY high 0 0 ns tWHEH tAVWH Hold time, E from WE high TBD TBD ns Setup time, address to WE high TBD TBD ns tELWL tVHWH Setup time, E to WE low TBD TBD ns Setup time, VPP to WE high TBD TBD ns tWL tWH Pulse duration, WE low TBD TBD ns Pulse duration, WE high TBD TBD ns tDVWH tWHDX Data valid to WE high TBD TBD ns WE high to data invalid TBD TBD ns tWHYH1 tWHYH2 Duration of double-word/word operation TBD TBD ns Duration of double-word/word operation in low-power programming (LPP) mode TBD TBD ns tWHYH3 tWHYH4 Duration of block-erase operation TBD TBD ns Duration of block-erase operation in LPP mode TBD TBD ns tWHYL WE high to RY/BY low TBD TBD ns VDDI power-up and reset/power-down (RP) characteristics over recommended ranges of supply voltage and ambient temperature range (see Figure 12) PARAMETER t5HPH tPHCH Power (VDDI) applied to RP high tPL5L t5HVH RP low to power (VDDI) low tVHPH 34 MIN RP high to LBA/CLK high VDDI high to VPP high VPP high to RP high MAX 1 ms 200 ns 0 ns 500 100 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 UNITS ns ns TMS28F033 4194304-BIT SYNCHRONOUS FLASH MEMORY SMJS833 – NOVEMBER 1997 PARAMETER MEASUREMENT INFORMATION tCL tCH tCLCH tCHCL tCLK Figure 11. Clock (CLK) Waveform CLK LBA ADVANCE INFORMATION tPL5L tPHCH RP t5HPH VDDI 2.5 V tVHPH t5HVH VPP 11.4 V Figure 12. VPP / VDDI Power-Up and Reset / Power-Down (RP) Waveforms POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 35 ADVANCE INFORMATION 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 A–1 – A16 (word-wide) A0–A16 (double-word-wide) A1 A0 A2 E WR LBA POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 BAA OE DQ0–DQ7 and DQ24–DQ31 (word-wide) DQ0–DQ31 (double-word-wide) D0 D1 D2 QV RY/BY VDDI/VDDE RP BASIC/ENHANCED PIN SET DCR0 OE MODE DCR1 WE MODE DCR2 DIS/WORD DCR3 LRV/BAA DCR4 BURST LENGTH DCR25,24 BURST LATENCY (X) DCR29,28 BURST LATENCY (Y) DCR30 x16 WRITE OPTION DCR31 Basic pin set (DCR0 = 0) 0 (see Note D) X Optional (see Note E) X X X X X Enhanced pin set (DCR0 = 1) 0 (see Note D) X Optional (see Note E) X X X X X NOTES: A. B. C. D. E. X is a don’t care. See Table 8 through Table 12 for DCR setting descriptions. Burst doesn’t occur while LBA is low. Synchronous and asynchronous OE are available (see Figure 20); DCR1 = 0 and DCR1 = 1, respectively. For DIS usage, see Figure 21. Figure 13. Asynchronous Read Cycles With Device Configuration Register Settings PARAMETER MEASUREMENT INFORMATION WE Template Release Date: 7–11–94 2 TMS28F033 4194304-BIT SYNCHRONOUS FLASH MEMORY SMJS833 – NOVEMBER 1997 36 1 CLK 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 CLK tAVCH tCHAX A–1–A16 (word-wide) A0–A16 (double-word-wide) A0 A1 tELCH E tRHCH WR tCHRL WE tCHLH LBA tBLCH tLLCH tCHBH tCHCH1 tGLCH OE tCHQX tCHQD tCHQZ DQ0–DQ7 and DQ24–DQ31 (word-wide) DQ0–DQ31 (double-word-wide) D0 D1 D2 D3 D1 D2 D3 D0 tCHQL tCHQH QV RY/BY VDDI/VDDE RP BASIC/ENHANCED PIN SET DCR0 OE MODE DCR1 WE MODE DCR2 DIS/ WORD DCR3 LRV/ BAA DCR4 BURST LENGTH DCR25,24 BURST LATENCY (X) DCR29,28 BURST LATENCY (Y) DCR30 x16 WRITE OPTION DCR31 Basic pin set (DCR0=0) 0 (see Note E) X Optional (see Note F) 1 (see Note G) 00 (see Note H) 01 (see Note I) 0 (see Note I) X Enhanced pin set (DCR0=1) 0 (see Note E X Optional (see Note F) 1 (see Note G) 00 (see Note H) 01 (see Note I) X is a don’t care. See Table 8 through Table 12 for DCR setting descriptions. Address A1 can be loaded as early as clock 5 for overlapped burst reads. Linear burst with the enhanced pin set requires LBO = VIL. Synchronous and asynchronous OE are available (see Figure 20); DCR1 = 0 and DCR1 = 1, respectively. For DIS usage, see Figure 21. For synchronous OE (DCR1 = 0), BAA is not required to burst if OE is used to control the burst (DCR[29:28] = 00). 3–1– . . . –1 is available with MOD4, MOD8, MOD16 (see Figure 17), and MOD32. Linear MOD4 burst is available with 3–1–1–1, 4–1–1–1, 5–1–1–1, and 4–2–2–2 (see Figure 19). 37 Figure 14. 3–1–1–1 MOD4 Linear Burst With Device Configuration Register Settings ADVANCE INFORMATION SMJS833 – NOVEMBER 1997 NOTES: A. B. C. D. E. F. G. H. I. X TMS28F033 4194304-BIT SYNCHRONOUS FLASH MEMORY POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 tCHGH tCHQV PARAMETER MEASUREMENT INFORMATION BAA ADVANCE INFORMATION 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 A–1–A16 (word-wide) A1 A3 E WR WE LBA POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 OE DQ0–DQ7 and DQ24–DQ31 (word-wide) D1 D0 D3 D3 D2 D2 D1 D0 QV RY/BY VDDI/VDDE RP BASIC/ENHANCED PIN SET DCR0 See Note E Enhanced pin set (DCR0 = 1) NOTES: A. B. C. D. E. F. G. H. I. OE MODE DCR1 WE MODE DCR2 DIS/WORD DCR3 LRV/BAA DCR4 — — — — X 1 (see Note F) 1 (see Note G) 0 BURST LENGTH DCR25,24 BURST LATENCY (X) DCR29,28 BURST LATENCY (Y) DCR30 x16 WRITE OPTION DCR31 — — — — 00 (see Note H) 10 (see Note I) 0 X X is a don’t care. See Table 8 through Table 12 for DCR setting descriptions. Address A3 can be loaded as early as clock 6 for overlapped burst reads. Interleave burst requires LBO = VIH. Interleave burst is available only with the enhanced pin set. Interleave burst is available only with the 16-bit data bus, which requires DCR3 = 1 with WORD = VIL. For synchronous OE (DCR1 = 0), BAA is not required to burst if OE is used to control the burst (DCR[29:28] = 00). Interleave burst is available only with MOD4. Interleave MOD4 burst is available with 3–1–1–1 and 4–1–1–1. Figure 15. 4–1–1–1 MOD4 Interleave Burst Read With Device Configuration Register Settings PARAMETER MEASUREMENT INFORMATION BAA Template Release Date: 7–11–94 2 TMS28F033 4194304-BIT SYNCHRONOUS FLASH MEMORY SMJS833 – NOVEMBER 1997 38 1 CLK 1 2 3 5 4 6 7 8 9 10 11 12 13 14 15 16 17 18 CLK A–1–A16 (Word-Wide) A0 E WR WE LBA D0 D1 D2 D3 D4 D5 D6 D7 QV RY/BY VDDI/VDDE RP BASIC/ENHANCED PIN SET DCR0 OE MODE DCR1 WE MODE DCR2 DIS/WORD DCR3 LRV/BAA DCR4 BURST LENGTH DCR25,24 BURST LATENCY (X) DCR29,28 BURST LATENCY (Y) DCR30 x16 WRITE OPTION DCR31 Basic pin set (DCR0 = 0) 0 X 1 (see Note D) 1 (see Note E) 01 (see Note F) 11 (see Note G) 0 (see Note G) X Enhanced pin set (DCR0 = 1) 0 X 1 (see Note D) 1 (see Note E) 01 (see Note F) 11 (see Note G) 0 (see Note G) X X is a don’t care. See Table 8 through Table 12 for DCR setting descriptions. Linear burst with the enhanced pin set requires LBO = VIL. 5–1– . . . –1 is available only with the 16-bit data bus, which requires DCR3 = 1 and WORD=VIL. For synchronous OE (DCR1 = 0), BAA is not required to burst if required to burst if OE is used to control the burst (DCR[29:28] = 00). 5–1– . . . –1 is available with MOD4, MOD8, MOD16, and MOD32. Linear MOD8 burst is available with 3–1– . . . –1, 4–1– . . . –1, 5–1– . . . –1, and 4–2– . . . –2. Figure 16. 5–1– . . . –1 MOD8 Linear Burst With Device Configuration Register Settings 39 ADVANCE INFORMATION SMJS833 – NOVEMBER 1997 NOTES: A. B. C. D. E. F. G. TMS28F033 4194304-BIT SYNCHRONOUS FLASH MEMORY POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 OE DQ0–DQ7 and DQ24–DQ31 (Word-Wide) PARAMETER MEASUREMENT INFORMATION BAA ADVANCE INFORMATION 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 A0 E WR WE LBA BAA D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 QV RY/BY VDDI/VDDE RP BASIC/ENHANCED PIN SET DCR0 OE MODE DCR1 WE MODE DCR2 DIS/WORD DCR3 LRV/BAA DCR4 BURST LENGTH DCR25,24 BURST LATENCY (X) DCR29,28 BURST LATENCY (Y) DCR30 x16 WRITE OPTION DCR31 Basic pin set (DCR0 = 0) 0 X Optional 1 (see Note D) 10 (see Note E) 01 (see Note F) 0 (see Note F) X Enhanced pin set (DCR0 = 1) 0 X Optional 1 (see Note D) 10 (see Note E) 01 (see Note F) 0 (see Note F) X NOTES: A. B. C. D. E. F. X is a don’t care. See Table 8 through Table 12 for DCR setting descriptions. Linear burst with the enhanced pin set requires LBO = VIL. For synchronous OE (DCR1 = 0), BAA is not required to burst if OE is used to control the burst (DCR[29:28] = 00). 3–1– . . . –1 is available with MOD4 (see Figure 14), MOD8, MOD16, and MOD32. Linear MOD16 burst is available with 3–1– . . . –1, 4–1– . . . –1, 5–1– . . . –1, and 4–2– . . . –2. Figure 17. 3–1– . . . –1 MOD16 Linear Burst With Device Configuration Register Settings PARAMETER MEASUREMENT INFORMATION POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 OE DQ0–DQ7 and DQ24–DQ31 (word-wide) DQ0–DQ31 (double-word-wide) Template Release Date: 7–11–94 CLK A–1–A16 (word-wide) A0–A16 (double-word-wide) TMS28F033 4194304-BIT SYNCHRONOUS FLASH MEMORY 2 SMJS833 – NOVEMBER 1997 40 1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 CLK A–1–A16 (word-wide) A0–A16 (double-word-wide) A0 E WR WE LBA OE D0 D1 D2 D3 D4 D5 D6 D7 QV RY/BY VDDI/VDDE RP BASIC/ENHANCED PIN SET DCR0 WE MODE DCR2 DIS/WORD DCR3 LRV/BAA DCR4 BURST LENGTH DCR25,24 BURST LATENCY (X) DCR29,28 BURST LATENCY (Y) DCR30 x16 WRITE OPTION DCR31 Basic pin set (DCR0 = 0) 0 X Optional 1 (see Note D) 01 (see Note E) 01 (see Note F) 0 (see Note F) X Enhanced pin set (DCR0 = 1) 0 X Optional 1 (see Note D) 01 (see Note E) 01 (see Note F) 0 (see Note F) X NOTES: A. B. C. D. E. F. X is a don’t care. See Table 8 through Table 12 for DCR setting descriptions. Linear burst with the enhanced pin set requires LBO=VIL. BAA is required to hold the current data and corresponding address for a burst suspend/resume. BAA suspend/resume is available with MOD4, MOD8, MOD16, and MOD32. BAA suspend/resume is available with 3–1– . . . –1, 4–1– . . . –1, 5–1– . . . –1, and 4–2– . . . –2. 41 Figure 18. BAA Suspend/Resume on 3–1– . . . –1 MOD8 Linear Burst With Device Configuration Register Settings ADVANCE INFORMATION SMJS833 – NOVEMBER 1997 OE MODE DCR1 TMS28F033 4194304-BIT SYNCHRONOUS FLASH MEMORY POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 DQ0–DQ7 and DQ24–DQ31 (word-wide) DQ0–DQ31 (double-word-wide) PARAMETER MEASUREMENT INFORMATION BAA ADVANCE INFORMATION 3 5 4 6 7 8 9 10 11 12 13 14 15 16 17 18 A0–A16 (double-word-wide) A0 E WR WE LBA OE POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 DQ0–DQ31 (double-word-wide) D0 D1 D2 D3 QV RY/BY VDDI/VDDE RP BASIC/ENHANCED PIN SET DCR0 OE MODE DCR1 WE MODE DCR2 DIS/WORD DCR3 LRV/BAA DCR4 BURST LENGTH DCR25,24 BURST LATENCY (X) DCR29,28 BURST LATENCY (Y) DCR30 x16 WRITE OPTION DCR31 Basic pin set (DCR0 = 0) 0 X Optional (see Note D) 1 (see Note E) 00 (see Note F) 10 (see Note G) 1 (see Note G) X Enhanced pin set (DCR0 = 1) 0 X Optional (see Note D) 1 (see Note E) 00 (see Note F) 10 (see Note G) 1 (see Note G) X NOTES: A. B. C. D. E. F. G. X is a don’t care. See Table 8 through Table 12 for DCR setting descriptions. Linear burst with the enhanced pin set requires LBO = VIL. 4–2–2–2 is available only with the 32-bit data bus. With DCR3 = 0, the 32-bit data bus is automatically in use. With DCR3 = 1, set WORD=VIH. For synchronous OE (DCR1 = 0), BAA is not required to burst if OE is used to control the burst (DCR[29:28] = 00). 4–2– . . . –2 is available with MOD4, MOD8, MOD16, and MOD32. Linear MOD4 burst is available with 3–1–1–1 (see Figure 14), 4–1–1–1, 5–1–1–1, and 4–2–2–2. Figure 19. 4–2–2–2 MOD4 Linear Burst With Device Configuration Register Settings PARAMETER MEASUREMENT INFORMATION BAA Template Release Date: 7–11–94 CLK TMS28F033 4194304-BIT SYNCHRONOUS FLASH MEMORY 2 SMJS833 – NOVEMBER 1997 42 1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 CLK A–1–A16 (word-wide) A0–A16 (double-word-wide) A0 A1 E WR WE LBA BAA tGHQX tGLQV D0 D1 D2 D3 tGLQD D1 D2 D3 D0 tGHQZ QV RY/BY VDDI/VDDE RP OE MODE DCR1 WE MODE DCR2 DIS/WORD DCR3 LRV/BAA DCR4 BURST LENGTH DCR25,24 BURST LATENCY (X) DCR29,28 BURST LATENCY (Y) DCR30 x16 WRITE OPTION DCR31 Basic pin set (DCR0 = 0) 1 (see Note E) X Optional 1 (see Note F) 00 (see Note G) 01 (see Note H) 0 (see Note H) X Enhanced pin set (DCR0 = 1) 0 (see Note E) X Optional 1 (see Note F) 00 (see Note G) 01 (see Note H) 0 (see Note H) X X is a don’t care. See Table 8 through Table 12 for DCR setting descriptions. Address A1 can be loaded as early as clock 5 for overlapped burst reads. Linear burst with the enhanced pin set requires LBO=VIL. For synchronous OE burst reads see Figure 14 through Figure 19, and Figure 21. For asynchronous OE (DCR1 = 1), BAA is required to burst. 3–1– . . . –1 is available with MOD4, MOD8, MOD16 (see Figure 17), and MOD32. Linear MOD4 burst is available with 3–1–1–1, 4–1–1–1, 5–1–1–1, and 4–2–2–2 (see Figure 19). Figure 20. 3–1–1–1 MOD4 Linear Burst (Asynchronous OE) With Device Configuration Register Settings 43 ADVANCE INFORMATION SMJS833 – NOVEMBER 1997 NOTES: A. B. C. D. E. F. G. H. TMS28F033 4194304-BIT SYNCHRONOUS FLASH MEMORY BASIC/ENHANCED PIN SET DCR0 PARAMETER MEASUREMENT INFORMATION POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 Asynchronous OE DQ0–DQ7 and DQ24–DQ31 (word-wide) DQ0–DQ31 (double-word-wide) ADVANCE INFORMATION 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 E WR WE LBA POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 OE DIS tSLCH DQ0–DQ31 (double-wordwide) D0 D1 D2 D3 D4 D5 D6 tCHSH D7 D12 D13 D14 D15 QV RY/BY VDDI/VDDE RP BASIC/ENHANCED PIN SET DCR0 OE MODE DCR1 WE MODE DCR2 DIS/WORD DCR3 LRV/BAA DCR4 BURST LENGTH DCR25,24 BURST LATENCY (X) DCR29,28 BURST LATENCY (Y) DCR30 x16 WRITE OPTION DCR31 Basic pin set (DCR0 = 0) 0 X 0 (see Note D) 1 (see Note E) 10 (see Note F) 01 (see Note G) 0 (see Note G) X Enhanced pin set (DCR0 = 1) 0 X 0 (see Note D) 1 (see Note E) 10 (see Note F) 01 (see Note G) 0 (see Note G) X NOTES: A. B. C. D. E. F. G. X is a don’t care. See Table 8 through Table 12 for DCR setting descriptions. Linear burst with the enhanced pin set requires LBO=VIL. DIS requires DCR3 =0, available only with the 32-bit data bus. For synchronous OE (DCR1 =0), BAA is not required to burst if OE is used to control the burst (DCR[29:28] = 00). 3–1– . . . –1 is available with MOD4 (see Figure 14), MOD8, MOD16, and MOD32. Linear MOD16 burst is available with 3–1– . . . –1, 4–1– . . . –1, 5–1– . . . –1, and 4–2– . . . –2. Figure 21. DIS Usage on 3–1– . . . –1 MOD16 Linear Burst With Device Configuration Register Settings PARAMETER MEASUREMENT INFORMATION BAA Template Release Date: 7–11–94 A0 TMS28F033 4194304-BIT SYNCHRONOUS FLASH MEMORY CLK A0–A16 (double-wordwide) 3 2 SMJS833 – NOVEMBER 1997 44 1 1 3 2 5 4 6 7 8 9 10 11 13 12 14 15 16 18 17 CLK A–1–A16 (word-wide) A0–A16 (double-word-wide) Write Program-Setup Command Automated Word/DoubleWord Programming Write Valid Address and Data 00000h PA 00000h tELCH tRLCH tCHRH E Write Read-Array Command Read Status Register Bits tCHEH tCHWH WR tWLCH WE BAA tDVCH DQ0–DQ7 and DQ24–DQ31 (word-wide) DQ0–DQ31 (double-word-wide) Data tCHDX Hi-Z Valid SR FFh Hi-Z Hi-Z 40h or 04h tCHYH1, 2 QV tCHYL RY/BY tYHVL tVHCH VPPH VPP VPPL RP BASIC/ENHANCED PIN SET DCR0 OE MODE DCR1 WE MODE DCR2 DIS/WORD DCR3 LRV/BAA DCR4 BURST LENGTH DCR25,24 BURST LATENCY (X) DCR29,28 BURST LATENCY (Y) DCR30 x16 WRITE OPTION DCR31 Basic pin set (DCR0 = 0) 0 0 (see Note D) Optional X (see Note E) XX XX X 0 (see Note F) Enhanced pin set (DCR0 = 1) 0 0 (see Note D) Optional X (see Note E) XX XX X 0 (see Note F) 45 Figure 22. Synchronous Write-Cycle Timing (Two-Cycle Write) With Device Configuration Register Settings ADVANCE INFORMATION SMJS833 – NOVEMBER 1997 NOTES: A. X is a don’t care. PA is the address to be programmed. B. See Table 8 for DCR setting descriptions. C. Wait states can be inserted between the address and data phases of a command or write-data cycle. In addition, the address phase of the write-data cycle can occur on the same CLK as the data phase of the command cycle (see Figure 24). D. For asynchronous two-cycle write timing (DCR2 = 1), see Figure 23. E. For LRV usage (DCR4 = 0), see Figure 3, and for DCR4 = 1, see Figure 5. F. When using the 16-bit data bus (DCR3 = 1 and WORD = VIL), both two-cycle writes (DCR31 = 0) and three-cycle writes (DCR31 = 1) are available. For synchronous three-cycle write timing, see Figure 24. TMS28F033 4194304-BIT SYNCHRONOUS FLASH MEMORY POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 OE PARAMETER MEASUREMENT INFORMATION LBA ADVANCE INFORMATION 5 4 6 7 8 10 9 11 13 12 15 14 16 17 18 Write Valid Address and Data XXXXXh PA A–1–A16 (word-wide) A0–A16 (double-wordwide) Automated Word/ Double-Word Programming Write Read-Array Command XXXXXh tELWL tWHEH Read StatusRegister Bits tWHAX tAVWH E WR tWL tWH tWHWH Asynchronous WE POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 BAA OE DQ0–DQ7 and DQ24–DQ31 (word-wide) DQ0–DQ31 (double-word-wide) tDVWH tWHDX Hi-Z 40h or 04h QV RY/BY Hi-Z Hi-Z Data Valid SR tYHVL FFh tWHYH1, 2 tWHYL tVHWH VPPH VPPL VPP RP BASIC/ENHANCED PIN SET DCR0 OE MODE DCR1 WE MODE DCR2 DIS/WORD DCR3 LRV/BAA DCR4 BURST LENGTH DCR25,24 BURST LATENCY (X) DCR29,28 BURST LATENCY (Y) DCR30 x16 WRITE OPTION DCR31 Basic pin set (DCR0 = 0) 0 1 (see Note D) Optional X (see Note E) XX XX X 0 (see Note F) Enhanced pin set (DCR0 = 1) 0 1 (see Note D) Optional X (see Note E) XX XX X 0 (see Note F) NOTES: A. B. C. D. E. F. X is a don’t care. PA is the address to be programmed. See Table 8 for DCR setting descriptions. For asynchronous writes, the address and data/command are latched on the WE rising edge. For synchronous two-cycle write timing (DCR2 = 0), see Figure 22. For LRV usage (DCR4 = 0), see Figure 4; and for DCR4 = 1, see Figure 5. When using the 16-bit data bus (DCR3 = 1 and WORD = VIL), both two-cycle writes (DCR31 = 0) and three-cycle writes (DCR31 = 1) are available. For asynchronous three-cycle writes, the “write valid address and data” cycle is repeated for the second 16-bit data segment. Figure 23. Asynchronous Write-Cycle Timing (Two-Cycle Write) With Device Configuration Register Settings PARAMETER MEASUREMENT INFORMATION LBA Template Release Date: 7–11–94 Write ProgramSetup Command TMS28F033 4194304-BIT SYNCHRONOUS FLASH MEMORY 3 2 SMJS833 – NOVEMBER 1997 46 1 CLK 1 3 2 4 5 6 7 8 9 10 11 13 12 14 15 16 17 18 CLK Write ProgramSetup Command Write Valid Address and Data Read Status Register Bits Write Read-Array Command PA 00000h 1 or 0 X X...Xh A0–A16 Automated Two 16-bit Word Programming 00000h X A–1 0 or 1 E WR WE OE Data Data DQ0–DQ7 and DQ24–DQ31 (word-wide) Hi–Z Hi–Z Hi–Z 40h or 04h Valid SR FFh QV tCHYH1, 2 RY/BY VPPH VPPL VPP RP BASIC/ENHANCED PIN SET DCR0 OE MODE DCR1 WE MODE DCR2 DIS/WORD DCR3 LRV/BAA DCR4 BURST LENGTH DCR25,24 BURST LATENCY (X) DCR29,28 BURST LATENCY (Y) DCR30 x16 WRITE OPTION DCR31 Basic pin set (DCR0 = 0 0 0 1 (see Note D) X (see Note E) XX XX X 1 (see Note F) Enhanced pin set (DCR0 = 1) 0 0 1 (see Note D) X (see Note E) XX XX X 1 (see Note F) 47 Figure 24. Synchronous Write-Cycle Timing (Three-Cycle Write) with Device Configuration Register Settings ADVANCE INFORMATION SMJS833 – NOVEMBER 1997 NOTES: A. X is a don’t care. PA is the address to be programmed. B. See Table 8 for DCR setting descriptions. C. Wait states can be inserted between the address and data phases of a command or write-data cycle. In addition, wait states can be inserted between the data phase of the current cycle and the address phase of the next cycle (see Figure 22). D. Three-cycle write is available only with the 16-bit data bus, which requires DCR3 = 1 and WORD=VIL. E. For LRV usage (DCR4 = 0) see Figure 6, and for DCR4 = 1 see Figure 7. F. When using the 16-bit data bus (DCR3 = 1 and WORD = VIL), both two-cycle writes (DCR31 = 0) and three-cycle writes (DCR31 = 1) are available. For synchronous two-cycle write timing, see Figure 22. TMS28F033 4194304-BIT SYNCHRONOUS FLASH MEMORY POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 BAA PARAMETER MEASUREMENT INFORMATION LBA ADVANCE INFORMATION 5 4 6 7 8 9 10 11 13 12 14 15 16 17 18 A–1–A16 (word-wide) A0–A16 (double-word-wide) Write EraseConfirm Command BBA Automated Erase Read Status Register Bits Write ReadArray Command 00000h E WR WE BAA POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 OE DQ0–DQ7 and DQ24–DQ31 (word-wide) DQ0–DQ31 (double-word-wide) D0h or 0Dh Hi-Z Hi-Z 20h or 02h Hi-Z Valid SR FFh QV tCHYH3, 4 RY/BY VPPH VPPL VPP RP BASIC/ENHANCED PIN SET DCR0 OE MODE DCR1 WE MODE DCR2 DIS/WORD DCR3 LRV/BAA DCR4 BURST LENGTH DCR25,24 BURST LATENCY (X) DCR29,28 BURST LATENCY (Y) DCR30 x16 WRITE OPTION DCR31 Basic pin set (DCR0 = 0) 0 0 (see Note D) Optional X (see Note E) XX XX X X Enhanced pin set (DCR0 = 1) 0 0 (see Note D) Optional X (see Note E) XX XX X X NOTES: A. X is a don’t care. BBA is the block base address. B. See Table 8 for DCR setting descriptions. C. Wait states can be inserted between the address and data phases of a command or erase-confirm cycle. In addition, the address phase of the erase-confirm cycle can occur on the same CLK as the data phase of the command cycle. D. For asynchronous erase-cycle timing (DCR2 = 1), see Figure 26. E. For LRV usage (DCR4 = 0), see Figure 8; and for DCR4 = 1, see Figure 9. Figure 25. Synchronous Erase-Cycle Timing With Device Configuration Register Settings PARAMETER MEASUREMENT INFORMATION LBA Template Release Date: 7–11–94 Write Erase-Setup Command 00000h TMS28F033 4194304-BIT SYNCHRONOUS FLASH MEMORY 3 2 SMJS833 – NOVEMBER 1997 48 1 CLK 1 3 2 5 4 6 7 8 9 10 11 13 12 14 15 16 17 18 CLK A–1–A16 (word-wide) A0–A16 (doble-word-wide) Write Erase-Setup Command Write Erase-Confirm Command XXXXXh BBA Automated Erase Read Status Register Bits Write ReadArray Command XXXXXh E WR Asynchronous WE OE DQ0–DQ7 and DQ24–DQ31 (word-wide) DQ0–DQ31 (double-word-wide) D0h or 0Dh Hi-Z Hi-Z Hi-Z 20h or 02h Valid SR FFh QV tWHYH3, 4 RY/BY VPPH VPPL VPP RP BASIC/ENHANCED PIN SET DCR0 WE MODE DCR2 DIS/WORD DCR3 LRV/BAA DCR4 BURST LENGTH DCR25,24 BURST LATENCY (X) DCR29,28 BURST LATENCY (Y) DCR30 x16 WRITE OPTION DCR31 Basic pin set (DCR0 = 0) 0 1 (see Note D) Optional X (see Note E) XX XX X X Enhanced pin set (DCR0 = 1) 0 1 (see Note D) Optional X (see Note E) XX XX X X NOTES: A. B. C. D. E. X is a don’t care. BBA is the block base address. See Table 8 for DCR setting descriptions. For asynchronous erase, the address and command are latched on the WE rising edge. For asynchronous erase-cycle timing (DCR2 = 1), see Figure 25. For LRV usage (DCR4 = 0), see Figure 8; and for DCR4 = 1, see Figure 9. 49 Figure 26. Asynchronous Erase-Cycle Timing With Device Configuration Register Settings ADVANCE INFORMATION SMJS833 – NOVEMBER 1997 OE MODE DCR1 TMS28F033 4194304-BIT SYNCHRONOUS FLASH MEMORY POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 BAA PARAMETER MEASUREMENT INFORMATION LBA ADVANCE INFORMATION 4 5 6 7 8 9 11 12 13 14 15 16 17 18 A3 A2 00000h WR WE LBA OE POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 DQ0–DQ7 and DQ24–DQ31 (word-wide) DQ0–DQ31 (double-wordwide) D0 D1 D2 D3 One-Cycle CSM Command QV RY/BY VPP RP BASIC/ENHANCED PIN SET DCR0 OE MODE DCR1 WE MODE DCR2 DIS/WORD DCR3 LRV/BAA DCR4 BURST LENGTH DCR25,24 BURST LATENCY (X) DCR29,28 BURST LATENCY (Y) DCR30 x16 WRITE OPTION DCR31 Basic pin set (DCR0 = 0) 0 (see Note D) 0 (see Note E) Optional 1 (see Note F) X Optional (see Note G) X X Enhanced pin set (DCR0 = 1) 0 (see Note D) 0 (see Note E) Optional 1 (see Note F) X Optional (see Note G) X X NOTES: A. B. C. D. E. F. X is a don’t care. See Table 8 for DCR setting descriptions. LBA (for A1) can go low as early as CLK2. Synchronous and asynchronous OE are available (see Figure 20); DCR1 = 0 and DCR1 = 1, respectively. Synchronous WE is required to perform overlapping writes. For single reads, the number of wait states can be set by selecting BAA usage (DCR4 = 1) and by setting DCR[29:28] = (number of wait states). BAA usage is not required to perform single reads. G. In the timing diagram above, both 1 wait state (CLK 1 to CLK 2) and 2 wait states (CLK 3 to CLK 5) are shown, corresponding to DCR[29:28] = 01 and 10, respectively. OE can be used to control the number of wait states for single reads by setting DCR[29:28] = 00. Figure 27. Overlapping Read/Write Cycles With Device Configuration Register Settings PARAMETER MEASUREMENT INFORMATION BAA Template Release Date: 7–11–94 A1 10 TMS28F033 4194304-BIT SYNCHRONOUS FLASH MEMORY A0 3 2 SMJS833 – NOVEMBER 1997 50 1 CLK A–1–A16 (wordwide) A0–A16 (double-word-wide) E TMS28F033 4194304-BIT SYNCHRONOUS FLASH MEMORY SMJS833 – NOVEMBER 1997 MECHANICAL DATA PAF (R-PQFP-G80) PLASTIC QUAD FLATPACK 0,45 0,25 0,80 64 0,16 M 41 65 40 80 14,20 13,80 18,10 17,20 ADVANCE INFORMATION 12,00 TYP 25 1 24 0,15 NOM 18,40 TYP 20,20 19,80 24,10 23,90 Gage Plane 0,25 0,10 MIN 0°– 8° 2,70 TYP 1,00 0,60 Seating Plane 3,10 MAX 0,10 4040271 / B 03/95 NOTES: A. All linear dimensions are in millimeters. B. This drawing is subject to change without notice. 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