STLC5444 QUAD FEEDER POWER SUPPLY SUPPLIES POWER FOR UP TO FOUR DIGITAL TELEPHONE LINES CONFORMS TO THE CCITT RECOMMENDATIONS FOR POWER FEED AT THE S OR T REFERENCE POINTS SUPPORTS POINT-TO-POINT AND POINT TO MULTIPOINT CONFIGURATIONS EACH OF THE FOUR LINES IS INDIVIDUALLY CONTROLLED HIGH-VOLTAGE BCD TECHNOLOGY SUPPORTING UP TO -130V AUTOMATIC THERMAL SHUTDOWN STATUS CONDITION DETECTION (BY MICROPROCESSOR) FOR EACH LINE: – Low output voltage – Openloop – Current overload – Thermal overload – Normal line condition PROGRAMMABLE CURRENT LIMITING OUTPUT CURRENT UP TO 120mA DESCRIPTION The ISDN Quad Feeder Power Supply (IQFPS) provides a power source for up to four line interfaces. The power source to the device is a local battery or a centralized regulated power supply. It can operate in point-to-point and point-to-multipoint configurations as far as S interface is concerned. By the device microprocessor interface, each powered line is individually controlled and monitored. Therefore, overloads and faults are easy to detect and localize even in a large system. The status conditions detected by the device on each line that may be read by the microprocessor are : low output voltage openloop current overload thermal overload normal line conditions A hardware current limiting programmable feature is available. December 1997 DIP24 PLCC44 ORDERING NUMBERS: STLC5444B1 (DIP24) STLC5444FN (PLCC44) DIP24 PIN CONNECTION (Top view) D1 1 24 D2 D0 2 23 D3 INT 3 22 A0 BGND 4 21 DGND VCC 5 20 ALE ILIM 6 19 WR N.C. 7 18 CS VBB 8 17 RD N.C. 9 16 RESET S0 10 15 S3 S1 11 14 RSRVD VBB 12 13 S2 D94TL102 1/17 STLC5444 D1 VBB N.C. 3 2 1 44 43 42 41 40 A0 D0 4 D3 N.C. 5 D2 INT 6 N.C. VBB PLCC44 PIN CONNECTION (Top view) VBB 7 39 VBB N.C. 8 38 N.C. BGND 9 37 N.C. N.C. 10 36 DGND VCC 11 35 ALE ILIM 12 34 N.C. N.C. 13 33 WR N.C. 14 32 CS VBB 15 31 RD N.C. 16 30 RESET VBB 17 29 VBB S3 N.C. N.C. N.C. S2 N.C. VBB S1 N.C. S0 N.C. 18 19 20 21 22 23 24 25 26 27 28 D94TL103 BLOCK DIAGRAM THERMAL OVERLOAD STATUS GROUP BUS STATUS DETECTOR MUX LINE ENABLE REGISTER BUS ADDRESS BUS 0/2 O/3 INPUT BUS D3/D0 INDIRECT ADDRESS REGISTER BIT 3 2/17 S0 S1 S2 S3 VBB(12) LER EN BGND µP INTERFACE VOLTAGE REFERENCE OUTPUT BUS D3/D0 ALE S DRIVERS LINE ENABLE REGISTER IAR EN INT EN LINE STATUS BUS S DRIVERS DISABLE DGND VCC VBB(8) A0 CS D3/D0 RD WR INT RESET ILIM D94TL104B STLC5444 PIN DESCRIPTION Name No PLCC No DIP D1 1 1 NC 2,4,8,10, 13,14, 16,18, 20,23, 25,26, 28,34, 37,38,44 7,9 Function Bit 1 of the tri state I/O data bus No connection D0 3 2 Bit 0 of the tri state I/O data bus INT 5 3 Active low interrupt output for the µP (open drain) VBB 6,7 15,17 22,29, 39,40 8,12 BGND 9 4 Battery ground line VCC 11 5 +5V supply line ILIM 12 6 Current limit programming S0 19 10 Output of the power switch controller 0 S1 21 11 Output of the power switch controller 1 S2 24 13 Output of the power switch controller 2 RSRVD – 14 Reserved pin: it must be left floating S3 27 15 Output of the power switch controller 3 Battery supply line (negative battery‘s terminal) RESET 30 16 Active high reset input RD 31 17 Active low read input CS 32 18 Active low chip select input WR 33 19 Active low write input ALE 35 20 Active high address latch enable DGND 36 21 Digital ground A0 41 22 Address bit for R/W operations on the data bus D3 42 23 Bit 3 of the I/O tri state data bus D2 43 24 Bit 2 of the I/O tri state data bus FUNCTIONAL DESCRIPTION BGND - Ground Battery ADDRESS LINE (Input) A0 selects source and destination locations for read and write operations on the data bus. A0 must be valid on the falling edge of ALE or during RD and WR if ALE is tied High. CS - Chip Select (Input; Active Low) CS must be Low to enable the read or write operations of the device. Data transfer occurs over the D3-D0 lines. ALE - Address Latch Enable (Input; Active High) ALE is an input control pulse used to strobe the address on the A0 line into the address latch. This signal is active High to admit the input address. The address is latched on the High-Low transition of ALE. While ALE is High, the address latch is transparent. For an unmultiplexed microprocessor bus, ALE must be tied High. D3-D0 - DATA BUS (Input/Output; Three-State) The four bidirectional data bus lines are to exchange information with a microprocessor. D0 is the least significant bit and D3 is the most significant bit. A High on the data bus corresponds to a logical 1. These lines act as input when WR and CS are active and as output when RD and CS are active. When CS is inactive, the D3-D0 pins are placed in a high-impedance state. 3/17 STLC5444 FUNCTIONAL DESCRIPTION (continued) transferred to D3-D0. DGND - Ground Digital ILIM - Current Limit Programming (Input) ILIM programs the current limit of the Output drivers using an external resistor connected between ILIM and VBB. The ILIM pin is 1.25V more positive than VBB. The current limit is 5mA plus 1000 times the current in the external resistor. The programmed current limit applies to each driver. INT - Interrupt (Output; Open-Collector, Active Low) INT augments the Microprocessor Interface by generating an interrupt when a Current Overload Detector (COD) occurs. INT is active whenever any bits in the COD register are active. INT is not latched; when the COD register is zero, INT goes inactive (High). INT will also go inactive if the IQFPS automatically disables the S-output driver that caused the interrupt (due to Thermal Overload), or if the microprocessor disables that line via the Line Enable Register (LER). COD interrupts can be masked via the Indirect Address Register (IAR); RESET always disables the INT pin. RD - Read (Input; Active Low) The active Low read signal is conditioned by CS and transfers internal information to the data bus. If A0 is a logical 0, logic levels of the Indirect Address Register (IAR) and Thermal Shutdown Status bit will be transferred to D3-D0. If A0 is a logical 1, the data addressed by the IAR will be 4/17 RESET - Reset (Input; Active High) RESET initialize the registers in the device, leaving the drivers switched off. S3-S0 - Drivers (Output) S3-S0 each supply power to one line. The outputs can sink up to 120 mA each. The voltage at the line is connected to VBB through a DMOS switch. VBB - Battery Voltage (input) VBB is the internal negative supply voltage. VBB must always be connected to the most negative supply voltage. The MPI Registers will not function properly when the battery power is disconnected, that is, when VBB is floating or grounded. The IQFPS should also be reset if a drastic transient is applied to VBB. VCC - +5V Power Supply (Input) WR - Write (Input; Active Low) The active Low write signal is conditioned by CS and transfers information from the data bus to an internal register selected by A0. If A0 is a logical 1, D3-D0 is written into the Line Enable Register (LER). If A0 is a logical 0, D3-D0 is written into the IAR. LER and IAR are the only two writable registers in the device. STLC5444 DC CHARACTERISTICS (VBB = -54V; VCC = 5V; unless otherwise specified) Symbol Parameter Test Conditions Min. Typ. Max. 2 Unit VIH Input Voltage High Level V VIL Input Voltage Low Level IOH High Level Output Current VOH = 2.4V 400 µA IOL Low Level Output Current VOL = 0.4V 2 mA IIH High Level Input Current VIH = 2V 10 µA IIL Low Level Input Current VIL = 0.8V 60 µA IOZH Output Hi-Z Current High 2.4V < VOZ < VCC 10 µA IOZL Output Hi-Z Current Low 0V < VOZ < 0.4V 10 µA ICC VCC supply Current 1.4 5 mA CL Logic I/O Capacitance 10 0.8 V pF VSAT Saturation Voltage IS = 80mA 2 V Ron Output DMOS Saturation Resistivity IS = 80mA 25 Ω IBB VBB Supply Current VBB = -54V, R LIM = 26.6KΩ, Output Disabled 6 mA ∆ISLIM Delta Limit Current vs. Theoretical Programmed Value ISLIM RLIM = 26.6KΩ, VBB = -96V RLIM = 10.9KΩ, VBB = -54V VLVD Low Voltage Detector Threshold (relative to VBB) S3 - S0 output active ISOL Current Overload Detector Threshold (as % of ISLIM) 75 ISOC Open Loop Detector Threshold 1.5 3.2 ±10% 2.7 3 3 VBB = -110V 3.3 V 90 % 4 mA 100 µA ISZ Si Leakage Current to ground @ Si disabled HLVD Low Voltage Detector Hysteresis 18 200 mV H OLD Open Loop Detector Hysteresis 0.6 1.6 mA HCOD Current Overload Detector Hysteresis 2.4 4.0 mA H1 130°C Thermal Detector Hysteresis 10 °C H2 160°C Thermal Detector Hysteresis 10 °C TH1 Thermal Overload Recovery Time H1 80 µs 5/17 STLC5444 SWITCHING CHARACTERISTICS (VBB = -54V; VCC = 5V; unless otherwise specified) MICROPROCESSOR READ/WRITE TIMING NON MULTIPLEXED MODE (for references see figure 1a and 2b). Symbol tRLRH tRHRL tRLDA tRHDZ tASRL tAHRH tASWL tAHWH tADDA tWLWH tWHWL tDAWH tWHDZ tRES Parameter RD, CS pulse width RD, recovery time T amb: -40 to 0°C and RD, CS low to data available RD or CS high to data Z T amb: -40 to 0°C and Address setup time to READ active Address hold time to READ inactive Address setup time to WRITE active Addess hold time to WRITE inactive Address stable to data available T amb: -40 to 0°C and WR or CS pulse width Write recovery time Data setup time Data hold time T amb: -40 to 0°C and Reset Pulse with T amb: 0 to 70°C +70°C to +85°C Min. 260 200 220 260 130 160 T amb: 0 to 70°C +70°C to +85°C T amb: 0 to 70°C +70°C to +85°C T amb: 0 to 70°C +70°C to +85°C Max. 0 0 30 50 360 390 200 200 100 20 40 200 Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Note: AC timings are tested at 0.8V and 2V with input levels of 0.4V and 2.4V. SWITCHING CHARACTERISTICS (VBB = -54V; VCC = 5V; unless otherwise specified) MICROPROCESSOR READ/WRITE TIMING MULTIPLEXED MODE (for references see figure 1 and 2). Symbol tRLRH tRHRL tRLDA tRHDZ tAHAL tADAL tADAZ tAZRL tAZWL tADDA tWLWH tWHWL tDAWH tWHDZ tRES Parameter RD, CS pulse width RD, recovery time T amb: RD, CS low to data available RD or CS high to data Z T amb: ALE pulse width Address setup time Address hold time Address Z to RD low Address Z to WR Low Address stable to data available T amb: WR or CS pulse width Write recovery time Data setup time Data hold time T amb: Reset Pulse with T amb: 0 to 70°C -40 to 0°C and +70°C to +85°C Min. 260 200 220 260 130 160 T amb: 0 to 70°C -40 to 0°C and +70°C to +85°C T amb: 0 to 70°C -40 to 0°C and +70°C to +85°C T amb: 0 to 70°C -40 to 0°C and +70°C to +85°C Max. 100 60 50 0 0 360 390 200 200 100 20 40 200 Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Note: AC timings are tested at 0.8V and 2V with input levels of 0.4V and 2.4V. Si Timing (at 10% of final value) Symbol tEN tDIS 6/17 Parameter Si output enable time (from LER) Si output disable time (from LER or RESET) Test condition R LOAD = 3kΩ Typ. 2 3 Max. 5 6 Unit µs µs STLC5444 Figure 1: Microprocessor Read Timing. tAHAL ALE tADAL tADAZ AO tCLRL (Note 1) tRHCH (Note 2) CS tAZRL tRHRL tADDA RD tRLRH tRHDZ tRLDA DATA Read Data D94TL108A Notes: 1 - If tCLRL is negative, tRHRL, tRLRH, tAZRL, and tRLDA are measured from CS rather than RD. 2 - If tRHCH is negative, tRHRL, tRLRH and tRHDZ are measured from CS rather than RD. When a read from the LER immediately follows a write to the LER a minimum of 1 µs is required between these operations. Figure 2: Microprocessor Write Timing. tAHAL ALE tADAL tADAZ AO tWHCH (Note 2) CS tWHWL tCLWL (Note 1) tWLWH WR tAZWL DATA tDAWH tWHDZ Write Data (Note 3) INT D94TL109A Notes: 1 - If tCLWL is negative t WHWL and tWLWH are measured from CS rather than WR. 2 - If tWHCH is negative, t WHWL, tWLWH, tDAWH and tWHDZ are measured from CS rather than WR. The propagation delay from the writing of the T/I bit to the effect on the INT pin is approximately 1µs for both mask and enable operations. 7/17 STLC5444 Figure 1a: Microprocessor Read Timing non multiplexed mode. ALE tAHRH AO tCLRL (Note 1) tRHCH (Note 2) CS tASRL tRHRL tADDA RD tRLRH tRHDZ tRLDA DATA Read Data D97TL301A Notes: 1 - If tCLRL is negative, tRHRL, tRLRH, tAZRL, and tRLDA are measured from CS rather than RD. 2 - If tRHCH is negative, tRHRL, tRLRH and tRHDZ are measured from CS rather than RD. When a read from the LER immediately follows a write to the LER a minimum of 1 µs is required between these operations. Figure 2a: Microprocessor Write Timing non multiplexed mode. ALE tASWL t AHWH AO tWHCH (Note 2) CS t WHWL tCLWL (Note 1) WR tWLWH tDAWH DATA t WHDZ Write Data (Note 3) INT D97TL302A Notes: 1 - If tCLWL is negative t WHWL and tWLWH are measured from CS rather than WR. 2 - If tWHCH is negative, t WHWL, tWLWH, tDAWH and tWHDZ are measured from CS rather than WR. The propagation delay from the writing of the T/I bit to the effect on the INT pin is approximately 1µs for both mask and enable operations. 8/17 STLC5444 OPERATIVE DESCRIPTION. Initialization The device is initialized by the RESET pin. In this state the analog drivers are switched off, the Indirect Address Register (IAR) is cleared, and the internally latched address A0 is cleared. Power at Output drivers The voltage at the Output drivers is approximately VBB (more precisely: VBB - VSAT). Analog Section The analog section consists of four line drivers, which are DMOS transistor switches capable of sinking up to 120 mA each. The power to the drivers is derived from the negative supply voltage (VBB). The output voltage to each line is slaved to VBB, and the voltage drop in each driver is approximately 1.5V. Line driver protection is provided through the integration of current limit and over-temperature shutoff. The current limit is hardware-programmable via an external resistor (RLIM) connected between ILIM and VBB. The output limit is : 5mA + 1000 x 1.25V/RLIM. This 1000 x gain makes the ILIM pin susceptible to external noise, care should be taken to connect RLIM as close as possible to the component. The thermal shut-off is internally set at approximately 160oC. At this temperature all the drivers are unconditionally switched off. However, at approximately 130oC, only the drivers that are in the currentoverload condition will be turned off. Status detectors, associated with each of the line drivers, monitor the load conditions on each line by comparing an electrical parameter (e.g., current and voltage at the line) with reference level. The output of each detector can be read by the microprocessor. In addition to these status detectors, the temperature of the device is monitored via integrated temperature detectors. The detectors respond at approximately 130oC and 160oC, as defined above, and the 160oC detector can be monitored by the microprocessor via the MPI. The status detectors provide the following information from each of the lines (all detectors have built-in hysteresis) : *) Low Output Voltage Detection The low-output-voltage status bit becomes active when the voltage across the output DMOS transistor exceeds the proper voltage threshold (VLVD). *) Open Loop Detection The open-loop status bit becomes active when the current on the line drops below a minimum value. *) Current Overload Detection The current-overload status bits become active when the current on the line nears the current limit. These bits active the INT output if COD interrupts are enabled via the IAR Register. *) Thermal Overload Detection If the device temperature reaches 130oC, then all the line drivers in the current-overload condition will be switched off and the corresponding bits in the Thermal Overload Register will be activated. If the device temperature increases to 160oC, all the line drivers will be turned off, and all the bits in the Thermal Overload Register will be activated. The T-bit will also be set, and it can be read along with the Indirect Address Register (IAR) to indicate that all the drivers have been turned off. To initialize any of the bits in the Thermal Overload Register, the microprocessor must first turn off the line drivers that must not be reactivated until the T-bit in the address register is cleared by the temperature detector in the device. MPI Section The MPI allows the user to access the detectors defined in the analog section. The line driver’s status bits are grouped by function. Bits 3-0 of the detectors correspond to lines 3-0, respectively. The status group are : Low Voltage Detector (LVD) Open Loop Detector (OLD) Current Overload Detector (COD) Thermal Overload Register (TOR) The data is not latched in these status groups except in the TOR. Thus, the user should filter (multiple samples) the received data to ensure its integrity. There are two other registers in the MPI: the Indirect Address Register (IAR), and Line Enable Register (LER). The IAR contains 3 bits that address the desired status group or the LER. The IAR is read along with the T-bit defined in the analog section. The microprocessor can read the IAR to check the validity of the address. A 1us delay is required between a write to the LER register, followed by a Read of the same register. Subsequent reads of the LER do not have this constraint. 9/17 STLC5444 The LER is used to enable or disable the individual line drivers. The line drivers will only become active if the corresponding bit in the TOR is inactive. The LER is a read/write register. The MPI is the interface containing the following pins : D3-D0 Bidirectional Data Bus A0 Input Address Line ALE Input Address Latch Enable RD Input Read Enable WR Input Write Enable CS Input Chip Select INT Output COD Interrupt RESET Input Reset pin The 4-bit bidirectional data bus (D3-D0) is used to communicate with the registers. Access to the registers is controlled by CS, RD, WR, ALE, and A0 as shown below. A read or write cycle must be preceded by a valid A0. A0 is latched internally in a transparent latch by ALE. The selection of the status group or the LER is determined by the content of the IAR. The truth table for the MPI control is shown below : CS RD WR A0 0 1 0 0 Write IAR (T bit is read only) 0 0 1 0 Read IAR and T bit 0 1 0 1 Write LER 0 0 1 1 Read status groups or LER 1 X X X No access Indirect Address Register (IAR) and T/I Bit The IAR is 3 bits wide and accessible through the data port, D2-D0. The content of the Indirect Address Register (IAR2-IARO) determines the selection of the status groups or the LER. The thermal overload bit T/I is read and written at the same time as IAR and occupies D3. This register has the following format : Bit Symbol 0 1 2 3 IARO IAR1 IAR2 T/I Bit 0 of the IAR Bit 1 of the IAR Bit 2 of the IAR T bit: (Read only) Logical 0: temperature normal (default value) Logical 1: temperature above 160°C (all drivers shut off) I bit : (write only) Logical 0: INT pin disabled Logical 1: COD interrupts enabled via INT pin‘ IAR2-IAR0 address the status groups and the LER as shown below: 10/17 IAR2 IAR1 IAR0 Select 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 LVD OLD COD LEC RESERVED RESERVED LER TOR STLC5444 The contents and format of the status groups and the LER are as follows : LVD: Bit 0 1 2 3 Logical 1 O0 O1 O2 O3 low voltage low voltage low voltage low voltage Logical 0 (default value) O0 voltage normal O1 voltage normal O2 voltage normal O3 voltage normal The Low Voltage Detector (LVD) indicates the voltage level on the output lines, even when the lines are disabled. The low-voltage condition becomes active (logical 1) if the output reaches the Low Voltage Threshold (VLVD). LEC: Bit Logical 1 SWITCH SWITCH SWITCH SWITCH 0 1 2 3 ON ON ON ON Logical 0 SWITCH OFF SWITCH OFF SWITCH OFF SWITCH OFF The Line Enable Command (LEC) indicates the status of the DMOS SWITCH OUTPUT. OLD: Bit Logical 1 0 1 2 3 O0 open loop O1 open loop O2 open loop O3 open loop Logical 0 (default value) O0 O1 O2 O3 current normal current normal current normal current normal The Open Loop Detector (OLD) indicates the open-loop condition on the output lines. The open-loop condition becomes active (logical 1) if the current on the line drops below the threshold value ISOC. COD: Bit 0 1 2 3 Logical 1 O0 O1 O2 O3 current overload current overload current overload current overload Logical 0 (default value) O0 O1 O2 O3 current normal current normal current normal current normal The Current Overload Detector (COD) indicates the current-overload condition on the output lines. The overload condition becomes active (logical 1) if the output current approaches the value programmed by an external resistor between ILIM and VBB. TOR : Bit Logical 1 (default value) Logical 0 0 1 2 3 O0 operational O1 operational O2 operational O3 operational O0 off O1 off O2 off O3 off The Thermal Overload Register (TOR) contains the overload status of the output line drivers. If the device temperature reaches 130oC, then the output line drivers that are in the current-overload condition will be switched off. The corresponding bits in the TOR will be set to a logical 0. To initialize any of the bits in the TOR, the microprocessor must first turn off the output line drivers via the LER. However, the TOR bits cannot be deactivated if the 160oC detector is active. The µp may re-enable the output drivers via the LER after the TOR condition is removed. The TOR is a read-only register. 11/17 STLC5444 LER : Bit Logical 1 Logical 0 (default value) 0 1 2 3 O0 on O1 on O2 on O3 on O0 off O1 off O2 off O3 off The Line Enable Register (LER) is used to enable or disable the individual output line drivers. The output line will only become active if the corresponding bit in the TOR is set to a logical 1. The LER can be written directly and read indirectly. ABSOLUTE MAXIMUM RATINGS (TA = 0°C to 70°C) Parameter Voltage from Digital Input to DGND Voltage from VCC to DGND Voltage from VBB to DGND 100ns Pulse voltage from Si to DGND (See Notes) Voltage from BGND to DGND Storage Temperature Value -0.4V to VCC -0.4V to +7V -130V to +0.4V -130V to +2V +0.5V, -3V T = -60°C to +150°C Note : Si stands for O0, O1, O2 or O3 outputs. RECOMMENDED OPERATING CONDITIONS Parameter (*) Ambient Temperature for standard type for ext. temperature type Supply Voltage Programmed Limiting Current Symbol1 TA TA VCC VBB DGND BGND ISLIM Min. 0 -40 4.75 -115 0 -3 Max. 70 85 5.25 -38 0 +0.5 120 Units °C °C V V V V mA Note: The test condition is specified with a diode in series with V BB. (*): Specifications in this data sheet are guaranteed by testing from 0°C to +70°C. For extended temperature range types, performance from –40°C to +85°C is guaranteed by characterization and periodic sampling of production units. ORDERING TYPES: STLC5444B1, PDIP24 package: 0 to 70°C Temperature range. STLC5444FN, PLCC44 package: 0 to 70°C Temperature range. STLC5444B1-X, PDIP24 package: -40 to 85°C Temperature range. STLC5444FN-X, PLCC44 package: -40 to 85°C Temperature range. APPLICATION HINT In the Absolute Maximum Ratings table it is specified that the voltage applied on the -Vbat pin should never exceed by more than 0.4V the voltage applied on the Ground pin. As long as the external circuitry assures compliance with the above, no more considerations are needed. In some cases however it may be not possible to exclude that conditions may occur (hot insertion, power supply transients, etc.) where the negative supply has a transient overshoot above ground voltage. Then a protection circuitry that clamps such overshoot can add to the equipment reliability. Such protection can be designed taking into considerations that typically the devices behave as follows: 12/17 - if the Vbat pin is not connected, and the other pins are normally biased, the chip generates on it an open circuit voltage of +420mV. - if all the other pins are normally biased and the -Vbat pin forced at +600mV, a current of 10mA flows into it. At the same time from +5V a current of 4mA is absorbed (this low current from +5V simply means that no parasitic latch-ups are triggered inside the chip). No deterioration of the device occurs. - if all the other pins are normally biased, and the -Vbat pin is forced at +1.5V for a transient period, no deterioration of the device occurs. Transient period can be considered any time interval that lasts for less than 10µs and is not repeated more than 5000 times during the device lifetime. STLC5444 COUNTER FEEDING It is possible that, in some applications, a communication channel that the STLC5444 feeds, is also biased at the other end by another feeding device. What considerations apply to the STLC5444 in this case? Let’s use a generic example for reference (see Fig. 3) Figure 3: Typical PABX connection. S U S STLC5444 D95TL229 S Si Si STLC5444 VBB V BB NT A PABX with S-interfaces may have some of them connected to Terminal Equipments, and one to the S-interface of a Nertwork Termination. The S-interface of the PABX connected to the NT has one channel of the STLC5444 available for feeding. It will be programmed in the ”OFF” state to avoid interference with the feeding coming from the NT (of course the feeding coming from the NT will not be loaded by this PABX connection). The following considerations are relevant in the above example: 1) The VBB of the STLC5444 in the PABX must be equal or more negative than the feeding voltage coming from the NT (unless decoupling diodes are externally provided - see 4) 2) The STLC5444 channel of the PABX must be programmed OFF. PABX 3) In the channel of the STLC5444 on the PABX side, the only effect will be on the relevant LVD bit that will be set to 1 if the feeding voltage coming from the NT is 3V more positive than the local VBB. No interrupts or alarms are generated. 4) It is good common practice to provide every Sinterface with protection circuitry against transient overvoltages (see Fig. 4). This includes a diode in series with each Si pin of the STLC5444. If this is the case, absolute levels of local VBB and NT feeding are no concern at all. (If such diodes are not present, care must be paid to the power supply of the PABX, and to the connected circuits. When the PABX supply is OFF, the NT feeding will find a connection through the relevant channel of the STLC5444 to the VBB point). Figure 4: Protection of the STLC5444 against overvoltage. D2 BGND BGND TPAXX Si D1 FUSE RESISTORS S INTERFACE D3 STLC5444 VBB BATTERY D95TL230 13/17 STLC5444 NOTE Possible effect on the device of a Vbat variation Be aware that a variation of Vbat during operation, when the switches are on can cause anomalous behaviour. To avoid that a turn-off occurs the variation should have a rise time equal or lower than 20V/µs (fig. 5), and a fall time equal or lower than 2.0V/µs (fig.6). Figure 6: Typical fall time behaviour. Figure 5: Typical rise time behaviour. D97TL304 D97TL303 Vbat1 Vbat1 Fail dV/dt > 25V/µs OK dV/dt < 2.0V/µs OK dV/dt < 20V/µs Fail dV/dt > 2.4V/µs Vbat0 14/17 Vbat0 STLC5444 DIP24 PACKAGE MECHANICAL DATA mm DIM. MIN. TYP. inch MAX. MIN. TYP. a1 0.63 0.025 b 0.45 0.018 b1 0.23 b2 0.31 1.27 D E 0.009 0.012 0.050 32.2 15.2 16.68 1.268 0.598 0.657 e 2.54 0.100 e3 27.94 1.100 F MAX. 14.1 0.555 I 4.445 0.175 L 3.3 0.130 15/17 STLC5444 PLCC44 PACKAGE MECHANICAL DATA mm DIM. MIN. TYP. MAX. MIN. TYP. MAX. A 17.4 17.65 0.685 0.695 B 16.51 16.65 0.650 0.656 C 3.65 3.7 0.144 0.146 D 4.2 4.57 0.165 0.180 d1 2.59 2.74 0.102 0.108 d2 E 0.68 14.99 0.027 16 0.590 0.630 e 1.27 0.050 e3 12.7 0.500 F 0.46 0.018 F1 0.71 0.028 G 16/17 inch 0.101 0.004 M 1.16 0.046 M1 1.14 0.045 STLC5444 ESD - The SGS-THOMSON Internal Quality Standards set a target of 2 KV that each pin of the devic e should withstand in a series of tests based on the Human Body Model (MIL-STD 883 Method 3015): with C = 100pF; R = 1500Ω and performing 3 pulses for each pin versus VCC and GND. Device characterization showed that, in front of the SGS-THOMSON Internaly Quality Standards, all pins of STLC5444 withstand at least 1000V. The above points are not expected to represent a pratical limit for the correct device utilization nor for its reliability in the field. Nonetheless they must be mentionned in connection with the applicability of the different SURE 6 requirements to STLC5444. Information furnished is believed to be accurate and reliable. However, SGS-THOMSON Microelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of SGS-THOMSON Microelectronics. Specification mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. SGSTHOMSON Microelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of SGS-THOMSON Microelectronics. 1997 SGS-THOMSON Microelectronics – Printed in Italy – All Rights Reserved SGS-THOMSON Microelectronics GROUP OF COMPANIES Australia - Brazil - Canada - China - France - Germany - Italy - Japan - Korea - Malaysia - Malta - Morocco - The Netherlands Singapore - Spain - Sweden - Switzerland - Taiwan - Thailand - United Kingdom - U.S.A. 17/17