TMS29F008T, TMS29F008B 1048576 BY 8-BIT FLASH MEMORIES D D D D D D D D D " Single Power Supply Supports 5 V 10% Read/Write Operation Organization . . . 1 048576 By 8 Bits Array-Blocking Architecture – One 16K-Byte Boot Sector – Two 8K-Byte Parameter Sectors – One 32K-Byte Sector – Fifteen 64K-Byte Sectors – Any Combination of Sectors Can Be Erased. Supports Full-Chip Erase – Any Combination of Sectors Can Be Marked as Read-Only Boot-Code Sector Architecture – T = Top Sector – B = Bottom Sector Sector Protection – Hardware Protection Method That Disables Any Combination of Sectors From Write or Erase Operations Using Standard Programming Equipment Embedded Program/Erase Algorithms – Automatically Pre-Programs and Erases Any Sector – Automatically Programs and Verifies the Program Data at Specified Address JEDEC Standards – Compatible With JEDEC Byte Pinouts – Compatible With JEDEC EEPROM Command Set Fully Automated On-Chip Erase and Program Operations 100 000 Program/Erase Cycles Low Power Dissipation – 40-mA Typical Active Read for Byte Mode – 60-mA Typical Program/Erase Current – Less Than 100-µA Standby Current – 5 µA in Deep Power-Down Mode D D D D D D All Inputs/Outputs TTL-Compatible Erase Suspend/Resume – Supports Reading Data From, or Programming Data to, a Sector Not Being Erased Hardware-Reset Pin Initializes the Internal-State Machine to the Read Operation 40-Pin Thin Small-Outline Package (TSOP) (DCD Suffix) Detection Of Program/Erase Operation – Data Polling and Toggle Bit Feature of Program/Erase Cycle Completion – Hardware Method for Detection of Program/Erase Cycle Completion Through Ready/Busy (RY/BY) Output Pin High-Speed Data Access at 5-V VCC 10% at Three Temperature Ranges – 80 ns Commercial . . . 0°C to 70°C – 90 ns Commercial . . . 0°C to 70°C – 100 ns Extended . . . –40°C to 85°C – 120 ns Automotive . . . –40°C to 125°C " PRODUCT PREVIEW D SMJS845A – MARCH 1997 – REVISED OCTOBER 1997 PIN NOMENCLATURE A[0 :19] DQ[0 :7] CE OE NC RESET RY / BY VCC VSS WE Address Inputs Data In / Data out Chip Enable Output Enable No Internal Connection Reset / Deep Power Down Ready / Busy Output Power Supply Ground Write Enable Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Copyright 1997, Texas Instruments Incorporated PRODUCT PREVIEW information concerns products in the formative or design phase of development. Characteristic data and other specifications are design goals. Texas Instruments reserves the right to change or discontinue these products without notice. POST OFFICE BOX 1443 Powered by ICminer.com Electronic-Library Service CopyRight 2003 • HOUSTON, TEXAS 77251–1443 1 TMS29F008T, TMS29F008B 1048576 BY 8-BIT FLASH MEMORIES SMJS845A – MARCH 1997 – REVISED OCTOBER 1997 PRODUCT PREVIEW 40-PIN TSOP DCD PACKAGE ( TOP VIEW ) A16 A15 A14 A13 A12 A11 A9 A8 WE RESET NC RY / BY A18 A7 A6 A5 A4 A3 A2 A1 1 40 2 39 3 38 4 37 5 36 6 35 7 34 8 33 9 32 10 31 11 30 12 29 13 28 14 27 15 26 16 25 17 24 18 23 19 22 20 21 A17 VSS NC A19 A10 DQ7 DQ6 DQ5 DQ4 VCC VCC NC DQ3 DQ2 DQ1 DQ0 OE VSS CE A0 description The TMS29F008T/B is an 1 048 576 by 8-bit (8 388 608-bit), 5-V single-supply, programmable read-only memory device that can be electrically erased and reprogrammed. This device is organized as 1 024K by 8 bits, divided into the following 19 sectors: – One 16K-byte boot sector – Two 8K-byte sectors – One 32K-byte sector – Fifteen 64K-byte sectors Any combination of sectors can be marked as read-only or erased. Full-chip erasure is also supported. Sector data protection is afforded by methods that can disable any combination of sectors from write or read operations using standard programming equipment. An on-chip state machine provides an on-board algorithm that automatically pre-programs and erases any sector before it automatically programs and verifies program data at any specified address. The command set is compatible with the JEDEC 8M-bit electrically erasable, programmable read-only memory (EEPROM) command set. A suspend/resume feature allows access to unaltered memory blocks during a section-erase operation. All outputs of this device are TTL-compatible. Additionally, an erase/suspend/resume feature supports reading data from, or programming data to, a sector that is not being erased. 2 POST OFFICE BOX 1443 Powered by ICminer.com Electronic-Library Service CopyRight 2003 • HOUSTON, TEXAS 77251–1443 TMS29F008T, TMS29F008B 1048576 BY 8-BIT FLASH MEMORIES SMJS845A – MARCH 1997 – REVISED OCTOBER 1997 description (continued) Device operations are selected by writing JEDEC-standard commands into the command register using standard microprocessor write timings. The command register acts as an input to an internal-state machine which interprets the commands, controls the erase and programming operations, outputs the status of the device, outputs the data stored in the device, and outputs the device algorithm-selection code. On initial power up, the device defaults to the read mode. A hardware-reset pin initializes the internal-state machine to the read operation. The device has low power dissipation with a 40-mA active read for the byte mode, 60-mA typical program/erase current mode, and less than 100-mA standby current with a 5-mA deep-power-down mode. These devices are offered with 80-, 90-, 100-, and 120-ns access times. Table 1 and Table 2 show the sector-address ranges. The TMS29F008T/B is offered in a 40-pin thin small-outline package (TSOP) (DCD suffix). device symbol nomenclature TMS29F008 T –90 C DCD L PRODUCT PREVIEW Temperature Range Designator L = Commercial (0°C to 70°C) E = Extended (– 40°C to 85°C) Q = Automotive (– 40°C to 125°C) Package Designator DCD = 40-Pin Plastic Dual Small-Outline Package Program/Erase Endurance C = 100 000 Cycles B = 10 000 Cycles Speed Option 80 = 80 ns 90 = 90 ns 100 = 100 ns 120 = 120 ns Boot Code Selection Architecture T = Top Sector B = Bottom Sector Device Number / Description 8M Bits POST OFFICE BOX 1443 Powered by ICminer.com Electronic-Library Service CopyRight 2003 • HOUSTON, TEXAS 77251–1443 3 TMS29F008T, TMS29F008B 1048576 BY 8-BIT FLASH MEMORIES SMJS845A – MARCH 1997 – REVISED OCTOBER 1997 logic symbol† PRODUCT PREVIEW A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 RY / BY RESET CE OE WE 21 20 19 18 17 16 15 14 8 7 36 6 5 4 3 2 1 40 13 37 12 10 22 24 9 FLASH MEMORY 1048576 × 8 0 A 19 G1 [PWR DWN] G2 1, 2 EN (READ) 1C3 (WRITE) A, 3D ∇4 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 0 1048575 A, Z4 25 26 27 28 32 33 34 35 † This symbol is in accordance with ANSI / IEEE Std 91-1984 and IEC Publication 617-12. 4 POST OFFICE BOX 1443 Powered by ICminer.com Electronic-Library Service CopyRight 2003 • HOUSTON, TEXAS 77251–1443 TMS29F008T, TMS29F008B 1048576 BY 8-BIT FLASH MEMORIES SMJS845A – MARCH 1997 – REVISED OCTOBER 1997 block diagram DQ0 – DQ7 RY / BY Buffer RY / BY VCC VSS Erase Voltage Generator Input/Output Buffers WE State Control RESET Command Registers PGM Voltage Generator STB CE PRODUCT PREVIEW Data Latch Chip-Enable Output-Enable Logic OE VCC Detector Timer STB A0 – A19 L a t c h POST OFFICE BOX 1443 Powered by ICminer.com Electronic-Library Service CopyRight 2003 Y-Decoder Y-Gating X-Decoder Cell Matrix A d d r e s s • HOUSTON, TEXAS 77251–1443 5 TMS29F008T, TMS29F008B 1048576 BY 8-BIT FLASH MEMORIES SMJS845A – MARCH 1997 – REVISED OCTOBER 1997 operation See Table 1 and Table 2 for the sector-address ranges of the TMS29F008T/B. Table 1. Top-Boot Sector-Address Ranges† PRODUCT PREVIEW ÁÁÁÁ Á ÁÁÁ ÁÁ ÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁ A19 A18 A17 A16 A15 A14 A13 SECTOR SIZE ADDRESS RANGE SA18 1 1 1 1 1 1 X 16K Byte FC000H – FFFFFH SA17 1 1 1 1 1 0 1 8K Byte FA000H – FBFFFH SA16 1 1 1 1 1 0 0 8K Byte F8000H – F9FFFH SA15 1 1 1 1 0 X X 32K Byte F0000H – F7FFFH SA14 1 1 1 0 X X X 64K Byte E0000H – EFFFFH SA13 1 1 0 1 X X X 64K Byte D0000H – DFFFFH SA12 1 1 0 0 X X X 64K Byte C0000H – CFFFFH SA11 1 0 1 1 X X X 64K Byte B0000H – BFFFFH SA10 1 0 1 0 X X X 64K Byte A0000H – AFFFFH SA9 1 0 0 1 X X X 64K Byte 90000H – 9FFFFH SA8 1 0 0 0 X X X 64K Byte 80000H – 8FFFFH SA7 0 1 1 1 X X X 64K Byte 70000H – 7FFFFH SA6 0 1 1 0 X X X 64K Byte 60000H – 6FFFFH SA5 0 1 0 1 X X X 64K Byte 50000H – 5FFFFH SA4 0 1 0 0 X X X 64K Byte 40000H – 4FFFFH SA3 0 0 1 1 X X X 64K Byte 30000H – 3FFFFH SA2 0 0 1 0 X X X 64K Byte 20000H – 2FFFFH SA1 0 0 0 1 X X X 64K Byte 10000H – 1FFFFH SA0 0 0 0 0 X X X 64K Byte 00000H – 0FFFFH † The address range is A0–A19 6 POST OFFICE BOX 1443 Powered by ICminer.com Electronic-Library Service CopyRight 2003 • HOUSTON, TEXAS 77251–1443 TMS29F008T, TMS29F008B 1048576 BY 8-BIT FLASH MEMORIES SMJS845A – MARCH 1997 – REVISED OCTOBER 1997 operation (continued) ÁÁÁ ÁÁÁ ÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁ ÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁ ÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁ ÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁ ÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁ ÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁ ÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁ ÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁ ÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁ ÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁ ÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁ ÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁ ÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁ ÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁ ÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁ ÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁ ÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁ ÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁ ÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁ ÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁ A19 A18 A17 A16 A15 A14 A13 SECTOR SIZE ADDRESS RANGE SA18 1 1 1 1 X X X 64K Byte F0000H – FFFFFH SA17 1 1 1 0 X X X 64K Byte E0000H – EFFFFH SA16 1 1 0 1 X X X 64K Byte D0000H – DFFFFH SA15 1 1 0 0 X X X 64K Byte C0000H – CFFFFH SA14 1 0 1 1 X X X 64K Byte B0000H – BFFFFH SA13 1 0 1 0 X X X 64K Byte A0000H – AFFFFH SA12 1 0 0 1 X X X 64K Byte 90000H – 9FFFFH SA11 1 0 0 0 X X X 64K Byte 80000H – 8FFFFH SA10 0 1 1 1 X X X 64K Byte 70000H – 7FFFFH SA9 0 1 1 0 X X X 64K Byte 60000H – 6FFFFH SA8 0 1 0 1 X X X 64K Byte 50000H – 5FFFFH SA7 0 1 0 0 X X X 64K Byte 40000H – 4FFFFH SA6 0 0 1 1 X X X 64K Byte 30000H – 3FFFFH SA5 0 0 1 0 X X X 64K Byte 20000H – 2FFFFH SA4 0 0 0 1 X X X 64K Byte 10000H – 1FFFFH SA3 0 0 0 0 1 X X 32K Byte 08000H – 0FFFFH SA2 0 0 0 0 0 1 1 8K Byte 06000H – 07FFFH SA1 0 0 0 0 0 1 0 8K Byte 04000H – 05FFFH SA0 0 0 0 0 0 0 X 16K Byte 00000H – 03FFFH † The address range is A0–A19 POST OFFICE BOX 1443 Powered by ICminer.com Electronic-Library Service CopyRight 2003 • HOUSTON, TEXAS 77251–1443 7 PRODUCT PREVIEW Table 2. Bottom-Boot Sector-Address Ranges† TMS29F008T, TMS29F008B 1048576 BY 8-BIT FLASH MEMORIES SMJS845A – MARCH 1997 – REVISED OCTOBER 1997 operation (continued) See Table 3 for the operation modes of the TMS29F008T/B. Table 3. Operation Modes MODE FUNCTIONS† CE OE WE A0 A1 A6 A9 RESET VIL VIL VIH VIL VIL VIL VID VIH VIL VIL VIH VIH VIL VIL VID VIH Device-Equivalent Code D6h (TMS29F008T-Byte) VIL VIL VIH VIH VIL VIL VID VIH Device-Equivalent Code 58h (TMS29F008B-Byte) VIL VIH VIH VIH A0 A1 A6 A9 X X X X VIH VIH Data out Output disable VIL VIL Standby and write inhibit Write‡ VIH VIL X X X X X X Hi-Z VIL X A0 A1 A6 A9 X VIH X VIH VIH X X X X VIL X VIH X VIL X VIH X VIL X VID X VID VIH X VIL X VIL Hi-Z Algorithm-selection mode 5 V power supply 5-V Read Temporary sector unprotect PRODUCT PREVIEW DQ0–DQ7 Manufacture-Equivalent Code 01h (TMS29F008-Byte) Verify sector protect Hardware reset Hi-Z Data in Data out Legend: VIL = Logic low VIH = Logic high VID = 12.0 ± 0.5 V † X can be VIL or VIH. ‡ See Table 5 for valid address and data during write. read mode A logic-low signal applied to the CE and OE pins allows the output of the TMS29F008T/B to be read. When two or more ’29F008T/B devices are connected in parallel, the output of any one device can be read without interference. The CE pin is for power control and must be used for device selection. The OE pin is for output control, used to gate the data output onto the bus from the selected device. The address-access time (tAVQV) is the delay from stable address to valid output data. The chip-enable (CE) access time (tELQV) is the delay from CE low and stable addresses to valid output data. The output-enable access time (tGLQV) is the delay from OE low to valid output data when CE equals logic low and addresses are stable for at least the duration of tAVQV–tGLQV. standby mode ICC supply current is reduced by applying a logic-high level on CE and RESET to enter the standby mode. In the standby mode, the outputs are placed in the high-impedance state. Applying a CMOS logic-high level on CE and RESET reduces the current to 100 µA. Applying a TTL logic-high level on CE and RESET reduces the current to 1 mA. If the ’29F008T/B is deselected during erasure or programming, the device continues to draw active current until the operation is complete. output disable When OE equals VIH or CE equals VIH, output from the device is disabled and the output pins (DQ0–DQ7) are placed in the high-impedance state. 8 POST OFFICE BOX 1443 Powered by ICminer.com Electronic-Library Service CopyRight 2003 • HOUSTON, TEXAS 77251–1443 TMS29F008T, TMS29F008B 1048576 BY 8-BIT FLASH MEMORIES SMJS845A – MARCH 1997 – REVISED OCTOBER 1997 automatic-sleep mode The ’29F008 has a built-in feature called automatic-sleep mode to minimize device energy consumption which is independent of CE, WE, and OE, and is enabled when addresses remain stable for 300 ns. Typical sleep-mode current is 100 µA. Sleep mode does not affect output data, which remains latched and available to the system. algorithm selection The algorithm-selection mode provides access to a binary code that matches the device with its proper programming and erase command operations. This mode is activated when VID (11.5 V to 12.5 V) is placed on address pin A9. Address pins A1 and A6 must be logic low. Two bytes of code are accessed by toggling address pin A0 from VIL to VIH. Address pins other than A0, A1, and A6 can be at logic low or at logic high. The algorithm-selection mode can also be read by using the command register, which is useful when VID is not available to be placed on address pin A9. Table 4 shows the binary algorithm-selection codes. CODE DQ7 DQ6 DQ5 DQ4 DQ3 DQ2 DQ1 DQ0 Manufacturer-equivalent code 01H 0 0 0 0 0 0 0 1 TMS29F008T-Byte D6H 1 1 0 1 0 1 1 0 TMS29F008B-Byte 58H 0 1 0 1 1 0 0 0 Sector protection 01H 0 0 0 0 0 0 0 1 † A1 = VIL, A6 = VIL, CE = OE = VIL erasure and programming Erasure and programming of the ’29F008 are accomplished by writing a sequence of commands using standard microprocessor write timing. The commands are written to a command register and input to the command-state machine (CSM). The CSM interprets the command entered and initiates program, erase, suspend, and resume operations as instructed. The CSM acts as the interface between the write-state machine (WSM) and external-chip operations. The WSM controls all voltage generation, pulse generation, preconditioning, and verification of memory contents. Program and block-/chip-erase functions are fully automatic. Once the end of a program or erase operation has been reached, the device resets internally to the read mode. If VCC drops below the low-voltage-detect level (VLKO), any programming or erase operation is aborted and subsequent writes are ignored until the VCC level is greater than VLKO. The control pins must be logically correct to prevent unintentional command writes or programming or erasing. command definitions Device operating modes are selected by writing specific address and data sequences into the command register. Table 5 defines the valid command sequences. Writing incorrect address and data values or writing them in the incorrect sequence causes the device to reset to the read mode. The command register does not occupy an addressable memory location. The register is used to store the command sequence, along with the address and data needed by the memory array. Commands are written by setting CE = VIL, OE = VIH, and bringing WE from logic high to logic low. Addresses are latched on the falling edge of WE and data is latched on the rising edge of WE. Holding WE = VIL and toggling CE is an alternative method. See the switching characteristics of the write/erase/program-operations section for specific timing information. POST OFFICE BOX 1443 Powered by ICminer.com Electronic-Library Service CopyRight 2003 • HOUSTON, TEXAS 77251–1443 9 PRODUCT PREVIEW Table 4. Algorithm-Selection Codes (5-V Single Power Supply)† TMS29F008T, TMS29F008B 1048576 BY 8-BIT FLASH MEMORIES SMJS845A – MARCH 1997 – REVISED OCTOBER 1997 command definitions (continued) Table 5. Command Definitions COMMAND PRODUCT PREVIEW Read/reset BUS CYCLES 1ST CYCLE ADDR DATA 1 XXXH F0H 3 555H AAH 2ND CYCLE ADDR DATA 3RD CYCLE ADDR DATA 2AAH 555H 55H F0H 4TH CYCLE ADDR DATA RA 5TH CYCLE ADDR DATA 6TH CYCLE ADDR DATA RD D6H T go Algorithm selection 3 555H AAH 2AAH 55H 555H 90H Program 4 555H AAH 2AAH 55H 555H A0H PA PD Chip erase 6 555H AAH 2AAH 55H 555H 80H 555H AAH 2AAH 55H 555H 10H Sector erase 6 555H AAH 2AAH 55H 555H 80H 555H AAH 2AAH 55H SA 30H Sector-erase suspend 1 XXXH B0H Erase-suspend valid during sector-erase operation Sector-erase resume 1 XXXH 30H Erase-resume valid only after erase-suspend 01H 58H B LEGEND: RA = Address of the location to be read PA = Address of the location to be programmed SA = Address of the sector to be erased Addresses A13–A19 select 1 to 19 sectors. RD = Data to be read at selected address location PD = Data to be programmed at selected address location read/reset command The read or reset mode is activated by writing either of the two read/reset command sequences into the command register. The device remains in this mode until another valid command sequence is input in the command register. Memory data is available in the read mode and can be read with standard microprocessor read-cycle timing. On power up, the device defaults to the read/reset mode. A read/reset command sequence is not required and memory data is available. algorithm-selection command The algorithm-selection command allows access to a binary code that matches the device with the proper programming and erase command operations. After writing the three-bus-cycle command sequence, the first byte of the algorithm-selection code can be read from address XX00h. The second byte of the code can be read from address XX01h (see Table 5). This mode remains in effect until another valid command sequence is written to the device. byte-program command Programming is a four-bus-cycle command sequence. The first three bus cycles put the device into the program-setup state. The fourth bus cycle loads the address location and the data to be programmed into the device. The addresses are latched on the falling edge of WE and the data is latched on the rising edge of WE in the fourth bus cycle. The rising edge of WE starts the program operation. The embedded programming function automatically provides needed voltage and timing to program and verify the cell margin. Any further commands written to the device during the program operation are ignored. 10 POST OFFICE BOX 1443 Powered by ICminer.com Electronic-Library Service CopyRight 2003 • HOUSTON, TEXAS 77251–1443 TMS29F008T, TMS29F008B 1048576 BY 8-BIT FLASH MEMORIES SMJS845A – MARCH 1997 – REVISED OCTOBER 1997 byte-program command (continued) Programming can be performed at any address location in any sequence. When erased, all bits are in a logic-high state. Logic lows are programmed into the device and only an erase operation can change bits from logic lows to logic highs. Attempting to program a 1 into a bit that has been programmed previously to a 0 causes the internal-pulse counter to exceed the pulse-count limit, which sets the exceed-time-limit indicator (DQ5) to a logic-high state. The automatic-programming operation is complete when the data on DQ7 is equivalent to the data written to this bit, at which time the device returns to the read mode and addresses are no longer latched. Figure 8 shows a flowchart of the typical device-programming operation. chip-erase command Chip erase is a six-bus-cycle command sequence. The first three bus cycles put the device into the erase-setup state. The next two bus cycles unlock the erase mode. The sixth bus cycle loads the chip-erase command. This command sequence is required to ensure that the memory contents are not erased accidentally. The rising edge of WE starts the chip-erase operation. Any further commands written to the device during the chip-erase operation are ignored. Figure 10 shows a flowchart of the typical chip-erase operation. sector-erase command Sector-erase is a six-bus-cycle command sequence. The first three bus cycles put the device into the erase-setup state. The next two bus cycles unlock the erase mode and then the sixth bus cycle loads the sector-erase command and the sector-address location to be erased. Any address location within the desired sector can be used. The addresses are latched on the falling edge of WE and the sector-erase command (30h) is latched on the rising edge of WE in the sixth bus cycle. After a delay of 80 µs from the rising edge of WE, the sector-erase operation begins on the selected sector(s). Additional sectors can be selected to be erased concurrently during the sector-erase command sequence. For each additional sector to be selected for erase, another bus cycle is issued. The bus cycle loads the next sector-address location and the sector-erase command. The time between the end of the previous bus cycle and the start of the next bus cycle must be less than 100 µs; otherwise, the new sector location is not loaded. A time delay of 100 µs from the rising edge of the last WE starts the sector-erase operation. If there is a falling edge of WE within the 100 µs time delay, the timer is reset. One to nineteen sector-address locations can be loaded in any sequence. The state of the delay timer can be monitored using the sector-erase delay indicator (DQ3). If DQ3 is at logic low, the time delay has not expired. See the operation status section for a description. Any command other than erase suspend (B0h) or sector erase (30h) written to the device during the sector-erase operation causes the device to exit the sector-erase mode and the contents of the sector(s) selected for erase are no longer valid. To complete the sector-erase operation, re-issue the sector-erase command sequence. The embedded sector-erase function automatically provides needed voltage and timing to program and to verify all of the memory cells prior to electrical erase and then erases and verifies the cell margin automatically. Programming the memory cells prior to erase is not required. See the operation status section for a full description. Figure 12 shows a flowchart of the typical sector-erase operation. POST OFFICE BOX 1443 Powered by ICminer.com Electronic-Library Service CopyRight 2003 • HOUSTON, TEXAS 77251–1443 11 PRODUCT PREVIEW The embedded chip-erase function automatically provides voltage and timing needed to program and to verify all the memory cells prior to electrical erase. It then erases and verifies the cell margin automatically without programming the memory cells prior to erase. TMS29F008T, TMS29F008B 1048576 BY 8-BIT FLASH MEMORIES SMJS845A – MARCH 1997 – REVISED OCTOBER 1997 erase-suspend command The erase-suspend command (B0h) allows interruption of a sector-erase operation to read data from unaltered sectors of the device. Erase-suspend is a one-bus-cycle command. The addresses can be VIL or VIH and the erase-suspend command (B0h) is latched on the rising edge of WE. Once the sector-erase operation is in progress, the erase-suspend command requests the internal write-state machine to halt operation at predetermined breakpoints. The erase-suspend command is valid only during the sector-erase operation and is invalid during programming and chip-erase operations. The sector-erase delay timer expires immediately if the erase-suspend command is issued while the delay is active. After the erase-suspend command is issued, the device takes between 0.1 µs and 15 µs to suspend the operation. The toggle bit must be monitored to determine when the suspend has been executed. When the toggle bit stops toggling, data can be read from sectors that are not selected for erase. Reading from a sector selected for erase can result in invalid data. See the operation status section for a full description. Once the sector-erase operation is suspended, reading from or programming to a sector that is not being erased can be performed. This command is applicable only during sector-erase operation. Any other command written during erase-suspend mode to the suspended sector is ignored. PRODUCT PREVIEW erase-resume command The erase-resume command (30h) restarts a suspended sector-erase operation from the point where it was halted. Erase resume is a one-bus-cycle command. The addresses can be VIL or VIH and the erase-resume command (30h) is latched on the rising edge of WE. When an erase-suspend/erase-resume command combination is written, the internal-pulse counter (exceed timing limit) is reset. The erase-resume command is valid only in the erase-suspend state. After the erase-resume command is executed, the device returns to the valid sector-erase state and further writes of the erase-resume command are ignored. After the device has resumed the sector-erase operation, another erase-suspend command can be issued to the device. operation status The status of the device during an automatic-programming algorithm, chip-erase, or automatic-erase algorithm can be determined in three ways: D D D DQ7: Data polling DQ6: Toggle bit RY/ BY: Ready / busy bit status-bit definitions During operation of the automatic embedded program and erase functions, the status of the device can be determined by reading the data state of designated outputs. The data-polling bit (DQ7) and toggle bit (DQ6) require multiple successive reads to observe a change in the state of the designated output. Table 6 defines the values of the status flags. 12 POST OFFICE BOX 1443 Powered by ICminer.com Electronic-Library Service CopyRight 2003 • HOUSTON, TEXAS 77251–1443 TMS29F008T, TMS29F008B 1048576 BY 8-BIT FLASH MEMORIES SMJS845A – MARCH 1997 – REVISED OCTOBER 1997 status-bit definitions (continued) Table 6. Operation Status Flags† DQ7 DQ6 DQ5 DQ3 DQ2 RY/BY DQ7 T 0 0 T 0 1 No Tog § 0 0 1 No Tog 0 0 T 1 D DQ7¶ D D D T 0 0 D 1§ 1 Program in erase suspend Programming DQ7 T 1 0 0 Programming Program/erase in auto-erase In progress Exceeded time limits Erase suspend mode Erase-suspend Erase-sector address Non-erase sector address 0 0 T 1 1 No Tog # DQ7 T 1 0 No Tog 0 Programming complete D D D D D 1 Sector-/chip-erase complete 1 1 1 1 1 1 Program/erase in auto erase Program in erase suspend Successful operation complete 0 0 † T= toggle, D= data, No Tog= No toggle ‡ DQ4, DQ1, DQ0 are reserved for future use. § DQ2 can be toggled when the sector address applied is an erasing sector. DQ2 cannot be toggled when the sector address applied is a non-erasing sector. DQ2 is used to determine which sectors are erasing and which are not. ¶ Status flags apply when outputs are read from the address of a non-erase-suspend operation. # If DQ5 is high (exceeded timing limits), successive reads from a problem sector causes DQ2 to toggle. data-polling (DQ7) The data-polling-status function outputs the complement of the data latched into the DQ7 data register while the write-state machine is engaged in a program or erase operation. Data bit DQ7 changes from complement to true to indicate the end of an operation. Data-polling is available only during programming, chip-erase, sector-erase, and sector-erase-timing delay. Data-polling is valid after the rising edge of WE in the last bus cycle of the command sequence loaded into the command register. Figure 14 shows a flowchart for data-polling. During a program operation, reading DQ7 outputs the complement of the DQ7 data to be programmed at the selected address location. Upon completion, reading DQ7 outputs the true DQ7 data loaded into the program-data register. During the erase operations, reading DQ7 outputs a logic low. Upon completion, reading DQ7 outputs a logic high. Also, data-polling must be performed at a sector address that is within a sector that is being erased. Otherwise, the status is invalid. When using data-polling, the address should remain stable throughout the operation. During a data-polling read, while OE is logic low, data bit DQ7 can change asynchronously. Depending on the read timing, the system can read valid data on DQ7, while other DQ pins are still invalid. A subsequent read of the device is valid. See Figure 15 for the data-polling timing diagram. toggle bit (DQ6) The toggle-bit status function outputs data on DQ6, which toggles between logic high and logic low while the write-state machine is engaged in a program or erase operation. When DQ6 stops toggling after two consecutive reads to the same address, the operation is complete. The toggle bit is available only during programming, chip erase, sector erase, and sector-erase-timing delay. Toggle-bit data is valid after the rising edge of WE in the last bus cycle of the command sequence loaded into the command register. Figure 16 shows a flowchart of the toggle-bit status-read algorithm. Depending on the read timing, DQ6 can stop toggling while other DQ pins are still invalid and a subsequent read of the device is valid. See Figure 17 for the toggle-bit timing diagram. POST OFFICE BOX 1443 Powered by ICminer.com Electronic-Library Service CopyRight 2003 • HOUSTON, TEXAS 77251–1443 13 PRODUCT PREVIEW DEVICE OPERATION‡ TMS29F008T, TMS29F008B 1048576 BY 8-BIT FLASH MEMORIES SMJS845A – MARCH 1997 – REVISED OCTOBER 1997 exceed time limit (DQ5) Program and erase operations use an internal-pulse counter to limit the number of pulses applied. If the pulse-count limit is exceeded, DQ5 is set to a logic-high data state. This indicates that the program or erase operation has failed. DQ7 does not change from complemented data to true data and DQ6 does not stop toggling when read. To continue operation, the device must be reset. The exceed-time-limit condition occurs when attempting to program a logic-high state into a bit that has been programmed previously to a logic low. Only an erase operation can change bits from logic low to logic high. After reset, the device is functional and can be erased and reprogrammed. sector-load-timer (DQ3) PRODUCT PREVIEW The sector-load-timer status bit, DQ3, is used to determine whether the time to load additional sector addresses has expired. After completion of a sector-erase command sequence, DQ3 remains at a logic low for 100 µs. This indicates that another sector-erase command sequence can be issued. If DQ3 is at a logic high, it indicates that the delay has expired and attempts to issue additional sector-erase commands are ignored. See the sector-erase command section for a description. The data-polling and toggle bit are valid during the 100-µs time delay and can be used to determine if a valid sector-erase command has been issued. To ensure additional sector-erase commands have been accepted, the status of DQ3 should be read before and after each additional sector-erase command. If DQ3 is at a logic low on both reads, the additional sector-erase command was accepted. toggle bit 2 (DQ2) The state of DQ2 determines whether the device is in algorithmic-erase mode or erase-suspend mode. DQ2 toggles if successive reads are issued to the erasing or erase-suspended sector, assuming in case of the latter that the device is in erase-suspend-read mode. It also toggles when DQ5 becomes a logic high due to the timer-exceed limit, and reads are issued to the failed sector. DQ2 does not toggle in any other sector due to DQ5 failure. When the device is in erase-suspend-program mode, successive reads from the non-erase-suspended sector causes a logic high on DQ2. ready/ busy bit (RY/ BY) The RY/ BY bit indicates when the device can accept new commands after performing algorithmic operations. If the RY/ BY (open-drain output) bit is low, the device is busy with either a program or erase operation and does not accept any other commands except for erase suspend. While it is in the erase-suspend mode, RY/ BY remains high. In program mode, the RY/ BY bit is valid (logic low) after the fourth WE pulse. In erase mode, it is valid after the sixth WE pulse. There is a delay period tbusy, after which the RY/ BY bit becomes valid. See Figure 24 for the timing waveform. Since the RY/ BY bit is an open-drain output, several such bits can be combined in parallel with a pullup resistor to VCC. hardware-reset bit (RESET) When the RESET pin is driven to a logic low, it forces the device out of the currently active mode and into a reset state. It also avoids bus contention by placing the outputs into the high-impedance state for the duration of the RESET pulse. During program or erase operation, if RESET is asserted to logic low, the RY/ BY bit remains at logic low until the reset operation is complete. Since this can take anywhere from 1 µs to 20 µs, the RY/ BY bit can be used to sense reset completion or the user can allow a maximum of 20 µs. If RESET is asserted during read mode, then the reset operation is complete within 500 ns. See Figure 1 and Figure 2 for timing specifications. The RESET pin also can be used to drive the device into deep power-down (standby) mode by applying VSS ± 0.3 V to it. ICC4 reads <1 µA typical, and 5 µA maximum for CMOS inputs. Standby mode can be entered anytime, regardless of the condition of CE. 14 POST OFFICE BOX 1443 Powered by ICminer.com Electronic-Library Service CopyRight 2003 • HOUSTON, TEXAS 77251–1443 TMS29F008T, TMS29F008B 1048576 BY 8-BIT FLASH MEMORIES SMJS845A – MARCH 1997 – REVISED OCTOBER 1997 hardware-reset bit (RESET) (continued) Asserting RESET during program or erase can leave erroneous data in the address locations. These locations need to be updated after the device resumes normal operations. A minimum of 50 ns must be allowed after RESET goes high before a valid read can take place. tRL = 500 ns RESET 20 µs max RY/BY Figure 1. Device Reset During a Program or Erase Operation RESET RY/BY 0V Figure 2. Device Reset During Read Mode temporary hardware-sector unprotect feature This feature temporarily enables both programming and erase operations on any combination of one to nineteen sectors that were previously protected. This feature is enabled using high voltage VID (11.5 V to 12.5 V) on the RESET pin, using standard command sequences. Normally, the device is delivered with all sectors unprotected. sector-protect programming The sector-protect programming mode is activated when A6, A0, and CE are at VIL, and address pin A9 and control pin OE are forced to VID. Address pin A1 is set to VIH.The sector-select address pins A13–A19 are used to select the sector to be protected. Address pins A0–A12 and I/O pins must be stable and can be either VIL or VIH. Once the addresses are stable, WE is pulsed low for 100 µs, causing programming to begin on the falling edge of WE and to terminate on the rising edge of WE. Figure 18 is a flowchart of the sector-protect algorithm, and Figure 19 shows a timing diagram of the sector-protect operation. Commands to program or erase a protected sector do not change the data contained in the sector. Attempts to program and erase a protected sector cause the data-polling bit (DQ7) and the toggle bit (DQ6) to operate from 2 µs to 100 µs and then return to valid data. POST OFFICE BOX 1443 Powered by ICminer.com Electronic-Library Service CopyRight 2003 • HOUSTON, TEXAS 77251–1443 15 PRODUCT PREVIEW tRL = 500 ns TMS29F008T, TMS29F008B 1048576 BY 8-BIT FLASH MEMORIES SMJS845A – MARCH 1997 – REVISED OCTOBER 1997 sector-protect verify Verification of the sector-protection programming is activated when WE = VIH, OE = VIL, CE = VIL, and address pin A9 = VID. Address pins A0 and A6 are set to VIL, and A1 is set to VIH. The sector-address pins A13–A19 select the sector that is to be verified. The other addresses can be VIH or VIL. If the sector that was selected is protected, the DQs output 01h. If the sector is not protected, the DQs output 00h. Sector-protect verify can also be read using the algorithm-selection command. After issuing the three-bus-cycle command sequence, the sector-protection status can be read on DQ0. Set address pins A0 = VIL, A1 = VIH, and A6 = VIL, and then the sector address pins A13–A19 select the sector to be verified. The remaining addresses are set to VIL. If the sector selected is protected, DQ0 outputs a logic-high state. If the sector selected is not protected, DQ0 outputs a logic-low state. This mode remains in effect until another valid command sequence is written to the device. Figure 18 is a flowchart of the sector-protect algorithm and Figure 19 shows a timing diagram of the sector-protect operation. PRODUCT PREVIEW sector unprotect Prior to sector unprotect, all sectors must be protected using the sector-protect programming mode. The sector unprotect is activated when address pin A9 and control pin OE are forced to VID. Address pins A1 and A6 are set to VIH while CE and A0 are set to VIL. The sector-select address pins A13–A19 can be VIL or VIH. All sectors are unprotected in parallel and once the inputs are stable, WE is pulsed low for 10 ms, causing the unprotect operation to begin on the falling edge of WE and to terminate on the rising edge of WE. Figure 20 is a flowchart of the sector-unprotect algorithm and Figure 21 shows a timing diagram of the sector-unprotect operation. sector-unprotect verify Verification of the sector unprotect is accomplished when WE = VIH, OE = VIL, CE =VIL and address pin A9 = VID, and then select the sector to be verified. Address pins A1 and A6 are set to VIH, and A0 is set to VIL. The other addresses can be VIH or VIL. If the sector selected is protected, the DQs output 01h. If the sector is not protected, the DQs output 00h. Sector unprotect can also be read using the algorithm-selection command. low VCC write lockout During power-up and power-down operations, write cycles are locked out for VCC less than VLKO. If VCC < VLKO, the command input is disabled and the device is reset to the read mode. On power up, if CE = VIL, WE = VIL, and OE = VIH, the device does not accept commands on the rising edge of WE. The device automatically powers up in the read mode. glitching Pulses of less than 5 ns (typical) on OE, WE, or CE do not issue a write cycle. power supply considerations Each device should have a 0.1-µF ceramic capacitor connected between VCC and VSS to suppress circuit noise. Printed circuit traces to VCC should be appropriate to handle the current demand and minimize inductance. 16 POST OFFICE BOX 1443 Powered by ICminer.com Electronic-Library Service CopyRight 2003 • HOUSTON, TEXAS 77251–1443 TMS29F008T, TMS29F008B 1048576 BY 8-BIT FLASH MEMORIES SMJS845A – MARCH 1997 – REVISED OCTOBER 1997 absolute maximum ratings over ambient temperature range (unless otherwise noted)† Supply voltage range, VCC (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.6 V to 7 V Input voltage range: All inputs except A9, CE, OE (see Note 2) . . . . . . . . . . . . . . . . . . . . – 0.6 V to VCC + 1 V A9, CE, OE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.6 V to 13.5 V Output voltage range (see Note 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.6 V to VCC + 1 V Ambient temperature range during read / erase / program, TA (L) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 70°C (E) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 40°C to 85°C (Q) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 40°C to 125°C Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 65°C to 150°C † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. All voltage values are with respect to VSS. 2. The voltage on any input pin can undershoot to –2 V for periods less than 20 ns (see Figure 4). 3. The voltage on any input or output pin can overshoot to 7 V for periods less than 20 ns (see Figure 5). recommended operating conditions MIN MAX 4.5 5.5 V 0.7 *VCC VCC+0.5 VCC+0.5 V TTL –0.5 0.8 CMOS –0.5 0.8 11.5 12.5 V 3.2 4.2 V Supply voltage VIH High level dc input voltage High-level VIL Low level dc input voltage Low-level VID VLKO Algorithm-selection and sector-protect input voltage TA Ambient temperature TTL CMOS Low VCC lock-out voltage POST OFFICE BOX 1443 Powered by ICminer.com Electronic-Library Service CopyRight 2003 • HOUSTON, TEXAS 77251–1443 2 L version 0 70 E version –40 85 Q version –40 125 UNIT PRODUCT PREVIEW VCC V °C 17 TMS29F008T, TMS29F008B 1048576 BY 8-BIT FLASH MEMORIES SMJS845A – MARCH 1997 – REVISED OCTOBER 1997 electrical characteristics over recommended ranges of supply voltage and ambient temperature PARAMETER TEST CONDITIONS TTL-input level VOH High-level output voltage CMOS-input level PRODUCT PREVIEW CMOS-input level VOL II Low-level output voltage IO IID Output current (leakage) Input current (leakage) MIN VCC = VCC MIN, VCC = VCC MIN, IOH = –2.5 mA IOH = – 100 µA VCC = VCC MIN, VCC = VCC MIN, IOH = – 2.5 mA IOL = 5.8 mA MAX TTL-input level V VCC–0.4 0.85 * VCC VCC = VCC MAX, VIN = VSS to VCC VO = VSS to VCC, CE = VIH A9 or CE or OE = VID MAX High-voltage current (standby) UNIT 2.4 V CE = VIH, VCC = VCC MAX CE = VCC ± 0.2, VCC = VCC MAX 0.45 V ±1 µA ±1 µA 35 µA 1 mA 100 µA ICC1 VCC supply current (standby) ICC2 VCC supply current (see Notes 4 and 5) CE = VIL, OE = VIH 40 mA ICC3 VCC supply current (see Note 6) CE = VIL, OE = VIH 60 mA ICC4 VCC supply current (standby during reset) VCC = VCC MAX, RESET = VSS ± 0.3 V 5 µA 100 µA CMOS-input level ICC5 Automatic sleep mode (see Notes 5 and 7) VIH = VCC ± 0.3 V, VIL = VSS ± 0.3 V NOTES: 4. ICC current in the read mode, switching at 6 MHz 5. IOUT = 0 mA 6. ICC current while erase or program operation is in progress 7. Automatic sleep mode is entered when addresses remain stable for 300 ns. capacitance over recommended ranges of supply voltage and ambient temperature PARAMETER Ci1 Input capacitance (All inputs except A9, CE, OE) Ci2 Co TEST CONDITIONS f = 1 MHz Input capacitance (A9, CE, OE) VI = 0 V, VI = 0 V, Output capacitance VO = 0 V, 18 POST OFFICE BOX 1443 Powered by ICminer.com Electronic-Library Service CopyRight 2003 • HOUSTON, TEXAS 77251–1443 MIN MAX UNIT 7.5 pF f = 1 MHz 9 pF f = 1 MHz 12 pF TMS29F008T, TMS29F008B 1048576 BY 8-BIT FLASH MEMORIES SMJS845A – MARCH 1997 – REVISED OCTOBER 1997 PARAMETER MEASUREMENT INFORMATION 0.5 mA IOL Output Under Test 1.5 V CL = 30 pF (see Note A and Note B) – 0.5 mA 2.4 V IOH 0.45 V NOTES: A. CL includes probe and fixture capacitance. B. The ac testing inputs are driven at 2.4 V for logic high and 0.45 V for logic low. Timing measurements are made at 2 V for logic high and 0.8 V for logic low on both inputs and outputs. Each device should have a 0.1-µF ceramic capacitor connected between VCC and VSS as closely as possible to the device pins. Figure 3. AC Test Output Load Circuit 20 ns 20 ns +0.8 V –0.5 V –2.0 V 20 ns Figure 4. Maximum Negative Overshoot Waveform 20 ns VCC + 2.0 V VCC + 0.5 V 2.0 V 20 ns 20 ns Figure 5. Maximum Positive Overshoot Waveform POST OFFICE BOX 1443 Powered by ICminer.com Electronic-Library Service CopyRight 2003 • HOUSTON, TEXAS 77251–1443 19 PRODUCT PREVIEW 2.0 V 0.8 V TMS29F008T, TMS29F008B 1048576 BY 8-BIT FLASH MEMORIES SMJS845A – MARCH 1997 – REVISED OCTOBER 1997 PARAMETER MEASUREMENT INFORMATION switching characteristics over recommended ranges of supply voltage and ambient temperature, read-only operation PARAMETER ALTERNATE SYMBOL ’29F008-90 MIN MIN MAX MIN MAX MIN MAX tdis(E) tdis(G) Disable time, CE to high impedance ten(E) ten(G) Enable time, CE to low impedance tGHQZ tELQX 0 0 0 0 ns Enable time, OE to low impedance tGLQX 0 0 0 0 ns Hold time, output from address CE or OE change tAXQX 0 0 0 0 ns 20 POST OFFICE BOX 1443 Powered by ICminer.com Electronic-Library Service CopyRight 2003 ns 80 90 100 120 ns 80 90 100 120 ns 40 45 50 55 ns 30 30 30 40 ns 40 ns 30 30 PRODUCT PREVIEW th(D) 120 UNIT Access time, CE Disable time, OE to high impedance 100 ’29F008-120 ta(E) ta(G) tGLQV tEHQZ 90 ’29F008-100 Cycle time, read Access time, OE 80 MAX tc(R) ta(A) Access time, address tAVAV tAVQV tELQV ’29F008-80 • HOUSTON, TEXAS 77251–1443 30 switching characteristics over recommended ranges of supply voltage and ambient temperature, controlled by WE PARAMETER tc(W) tsu(A) Cycle time, write th(A) tsu(D) th(D) MIN TYP ’29F008-90 MAX MIN TYP ’29F008-100 MAX MIN TYP ’29F008-120 MAX MIN TYP MAX UNIT 90 100 120 ns 0 0 0 0 ns Hold time, address 45 50 50 65 ns Setup time, data tDVWH 45 50 50 65 ns Hold time, data valid after WE high tWHDX 0 0 0 0 ns tELWL tEHWH 0 0 0 0 ns 0 0 0 0 ns tWLWH1 tWHWL 45 50 50 65 ns 20 30 30 35 ns tGHWL 0 0 0 0 ns tWHGL1 tWHGL2 0 0 0 0 ns 10 10 10 10 ns tVCEL 50 50 50 50 µs tHVT 4 4 4 4 µs tw(WL) tw(WH) Pulse duration, WE low Hold time, CE Pulse duration, WE high Recovery time, read before write Hold time, OE read Hold time, OE toggle, data Setup time, VCC Transition time, VID (see Notes 8 and 9) tWLWH2 100 100 100 100 µs Pulse duration, WE low (see Note 9) tWLWH3 10 10 10 10 ms Setup time, CE VID to WE (see Note 9) tEHVWL 4 4 4 4 µs Setup time, OE VID to WE (see Notes 8 and 9) tGHVWL 4 4 4 4 µs Cycle time, programming operation tWHWH1 Write recovery time from RY / BY tRB 8 0 8 0 NOTES: 8. Sector-protect timing 9. Sector-unprotect timing 21 PRODUCT PREVIEW 8 0 8 0 µs ns TMS29F008T, TMS29F008B 1 048 576 BY 8-BIT FLASH MEMORIES Pulse duration, WE low (see Note 8) SMJS845A – MARCH 1997 – REVISED OCTOBER 1997 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 80 Setup time, CE tc(W)PR ’29F008-80 tAVAV tAVWL tWLAX Setup time, address tsu(E) th(E) trec(R) ALTERNATE SYMBOL PRODUCT PREVIEW ’29F008-120 tRL 500 500 500 500 ns RESET high time before read tRH 50 50 50 50 ns RESET to power-down time tRPD 20 20 20 20 µs tBUSY 90 90 90 90 ns POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 Cycle time, sector-erase operation tWHWH2 1 Cycle time, chip-erase operation tWHWH3 6 NOTES: 8. Sector-protect timing 9. Sector -unprotect timing MAX MIN TYP MAX 1 50 6 MIN TYP MAX 1 50 6 MIN TYP MAX 1 50 6 UNIT s 50 s Template Release Date: 7–11–94 ’29F008-100 RESET low time TYP TMS29F008T, TMS29F008B 1 048 576 BY 8-BIT FLASH MEMORIES ’29F008-90 MIN Program/erase valid to RY / BY delay tc(W)ER ’29F008-80 ALTERNATE SYMBOL PARAMETER SMJS845A – MARCH 1997 – REVISED OCTOBER 1997 22 switching characteristics over recommended ranges of supply voltage and ambient temperature, controlled by WE (continued) switching characteristics over recommended ranges of supply voltage and ambient temperature, controlled by CE PARAMETER Cycle time, write th(A) tsu(D) Hold time, address th(D) tsu(W) Hold time, data th(W) tw(EL) Hold time, WE tw(EH) trec(R) Pulse duration, CE high Setup time, address Setup time, data Setup time, WE Pulse duration, CE low Recovery time, read before write Setup time, OE th(C) Hold time, OE read Hold time, OE toggle, data ’29F008-80 MIN TYP ’29F008-90 MAX MIN TYP ’29F008-100 MAX MIN TYP ’29F008-120 MAX MIN TYP MAX UNIT tAVAV tAVEL tELAX 80 90 100 120 ns 0 0 0 0 ns 45 50 50 65 ns tDVEH tEHDX 45 50 50 65 ns 0 0 0 0 ns tWLEL tEHWH tELEH1 0 0 0 0 ns 0 0 0 0 ns 45 50 50 65 ns tEHEL tGHEL 20 30 30 35 ns 0 0 0 0 ns tGLEL tEHGL1 tEHGL2 0 0 0 0 ns 0 0 0 0 ns 10 10 10 10 ns 8 8 8 8 µs Cycle time, sector-erase operation tEHEH1 tEHEH2 1 1 1 1 s Cycle time, chip-erase operation tEHEH3 6 Programming operation 50 6 50 6 50 6 50 s 23 TMS29F008T, TMS29F008B 1 048 576 BY 8-BIT FLASH MEMORIES SMJS845A – MARCH 1997 – REVISED OCTOBER 1997 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 tc(W) tsu(A) ALTERNATE SYMBOL PRODUCT PREVIEW TMS29F008T, TMS29F008B 1048576 BY 8-BIT FLASH MEMORIES SMJS845A – MARCH 1997 – REVISED OCTOBER 1997 erase and program performance† PARAMETER TEST CONDITIONS MIN TYP MAX UNIT 1‡ 15§ s µs s Sector-erase time Excludes 00H programming prior to erasure Program word time Excludes system-level overhead 9 11 Program time Excludes system-level overhead 9 9 5200§ 3 600§ 6‡ 50§ Chip-programming time Excludes system-level overhead µs Erase/program cycles 100 000 1 000 000 cycles † The internal algorithms allow for 2.5-ms byte-program time. DQ5 = 1 only after a byte takes the theoretical maximum time to program. A minimal number of bytes can require signficantly more programming pulses than the typical byte. The majority of the bytes program within one or two pulses. This is demonstrated by the typical and maximum programming times listed above. ‡ 25°C, 5-V VCC, 100 000 cycles, typical pattern § Under worst-case conditions: 90°C, 5-V VCC, and 100 000 cycles latchup characteristics (see Note 10) PARAMETER PRODUCT PREVIEW MIN MAX Input voltage with respect to VSS on all pins except I/O pins (including A9 and OE) –1 13 V Input voltage with respect to VSS on all I/O pins –1 VCC + 1 100 V Current – 100 UNIT mA NOTE 10: Includes all pins except VCC test conditions: VCC = 5 V, one pin at a time pin capacitance, all packages (see Note 11) PARAMETER TEST CONDITIONS CIN Input capacitance COUT Output capacitance VIN = 0 VOUT = 0 CIN2 Control pin capacitance VIN = 0 TYP MAX 6 7.5 UNIT pF 8.5 12 pF 8 10 pF MIN MAX NOTE 11: Test conditions TA: 25°C, f = 1 MHz data retention PARAMETER Minimum pattern data retention time 24 POST OFFICE BOX 1443 Powered by ICminer.com Electronic-Library Service CopyRight 2003 TEST CONDITIONS 150°C 10 125°C 20 • HOUSTON, TEXAS 77251–1443 UNIT Years TMS29F008T, TMS29F008B 1048576 BY 8-BIT FLASH MEMORIES SMJS845A – MARCH 1997 – REVISED OCTOBER 1997 read operation tAVAV Valid Addresses Addresses tAVQV CE tEHQZ tELQV OE tGHQZ WE PRODUCT PREVIEW tGLQV tGLQX tAXQX tELQX Valid Data DQ Figure 6. AC Waveform for Read Operation POST OFFICE BOX 1443 Powered by ICminer.com Electronic-Library Service CopyRight 2003 • HOUSTON, TEXAS 77251–1443 25 TMS29F008T, TMS29F008B 1048576 BY 8-BIT FLASH MEMORIES SMJS845A – MARCH 1997 – REVISED OCTOBER 1997 write operation Start Write Bus Cycle 555H / AAH Write Bus Cycle 2AAH / 55H Write Bus Cycle 555H / A0H PRODUCT PREVIEW Write Bus Cycle Program Address / Program Data Poll Device Status Operation Complete ? Yes No Next Address Last Address ? Yes End Figure 7. Program Algorithm 26 POST OFFICE BOX 1443 Powered by ICminer.com Electronic-Library Service CopyRight 2003 • HOUSTON, TEXAS 77251–1443 No TMS29F008T, TMS29F008B 1048576 BY 8-BIT FLASH MEMORIES SMJS845A – MARCH 1997 – REVISED OCTOBER 1997 write operation (continued) tAVAV 555H Addresses 2AAH 555H PA PA tWLAX tAVWL CE tELWL tWHEH OE tWHDX tGHWL tWHWL PRODUCT PREVIEW tWLWH1 WE tWHWH1 tDVWH DQ AAH 55H A0H PD DQ7 DOUT NOTES: A. PA = Address to be programmed B. PD = Data to be programmed C. DQ7 = Complement of data written to DQ7 Figure 8. AC Waveform for Program Operation POST OFFICE BOX 1443 Powered by ICminer.com Electronic-Library Service CopyRight 2003 • HOUSTON, TEXAS 77251–1443 27 TMS29F008T, TMS29F008B 1048576 BY 8-BIT FLASH MEMORIES SMJS845A – MARCH 1997 – REVISED OCTOBER 1997 write operation (continued) tAVAV 555H Addresses 2AAH 555H PA PA tAVEL tELAX tELEH1 CE tEHEL tGHEL OE tDVEH tWLEL tEHWH tWHWH1 PRODUCT PREVIEW WE tEHDX DQ AAH 55H A0H PD DQ7 NOTES: A. PA = Address to be programmed B. PD = Data to be programmed C. DQ7 = Complement of data written to DQ7 Figure 9. Alternate CE-Controlled Write Operation 28 POST OFFICE BOX 1443 Powered by ICminer.com Electronic-Library Service CopyRight 2003 • HOUSTON, TEXAS 77251–1443 DOUT TMS29F008T, TMS29F008B 1048576 BY 8-BIT FLASH MEMORIES SMJS845A – MARCH 1997 – REVISED OCTOBER 1997 chip-erase operation Start Write Bus Cycle 555H / AAH Write Bus Cycle 2AAH / 55H Write Bus Cycle 555H /80H PRODUCT PREVIEW Write Bus Cycle 555H / AAH Write Bus Cycle 2AAH / 55H Write Bus Cycle 555H /10H Poll Device Status Operation Complete ? No Yes End Figure 10. Chip-Erase Algorithm POST OFFICE BOX 1443 Powered by ICminer.com Electronic-Library Service CopyRight 2003 • HOUSTON, TEXAS 77251–1443 29 TMS29F008T, TMS29F008B 1048576 BY 8-BIT FLASH MEMORIES SMJS845A – MARCH 1997 – REVISED OCTOBER 1997 chip-erase operation (continued) tAVAV 555H Addresses 555H 2AAH 555H VA tWLAX tAVWL CE tELWL tWHEH OE tWHDX tGHWL PRODUCT PREVIEW tWHWL tWLWH1 WE tWHWH3 tDVWH DQ 80H AAH 55H 10H NOTES: A. VA = any valid address B. Figure details the last four bus cycles in a six-bus-cycle operation. Figure 11. AC Waveform for Chip-Erase Operation 30 POST OFFICE BOX 1443 Powered by ICminer.com Electronic-Library Service CopyRight 2003 • HOUSTON, TEXAS 77251–1443 DQ7=0 DOUT=FFH TMS29F008T, TMS29F008B 1048576 BY 8-BIT FLASH MEMORIES SMJS845A – MARCH 1997 – REVISED OCTOBER 1997 sector-erase operation Start Write Bus Cycle 555H / AAH Write Bus Cycle 2AAH / 55H Write Bus Cycle 555H / 80H PRODUCT PREVIEW Write Bus Cycle 555H/AAH Write Bus Cycle 2AAH / 55H Write Bus Cycle Sector Address / 30H No DQ3 = 0 ? Yes Load Additional Sectors ? Yes No Poll Device Status No Operation Complete ? Yes End Figure 12. Sector-Erase Algorithm POST OFFICE BOX 1443 Powered by ICminer.com Electronic-Library Service CopyRight 2003 • HOUSTON, TEXAS 77251–1443 31 TMS29F008T, TMS29F008B 1048576 BY 8-BIT FLASH MEMORIES SMJS845A – MARCH 1997 – REVISED OCTOBER 1997 sector-erase operation (continued) tAVAV 555H Addresses 555H 2AAH SA SA tWLAX tAVWL CE tELWL tWHEH OE tWHDX tGHWL PRODUCT PREVIEW tWHWL tWLWH1 WE tWHWH2 tDVWH DQ 80H AAH 55H 30H NOTES: A. SA = Sector address to be erased B. Figure details the last four bus cycles in a six-bus-cycle operation. Figure 13. AC Waveform for Sector-Erase Operation 32 POST OFFICE BOX 1443 Powered by ICminer.com Electronic-Library Service CopyRight 2003 • HOUSTON, TEXAS 77251–1443 DQ7=0 DOUT=FFH TMS29F008T, TMS29F008B 1048576 BY 8-BIT FLASH MEMORIES SMJS845A – MARCH 1997 – REVISED OCTOBER 1997 data-polling operation Start Read DQ0 – DQ7 Addr = VA DQ7 = Data ? Yes No No PRODUCT PREVIEW DQ5 = 1 ? Yes Read DQ0 – DQ7 Addr = VA DQ7 = Data ? Yes No Fail Pass NOTES: A. Polling status bits DQ7 and DQ5 may change asynchronously. Read DQ7 after DQ5 changes states. B. VA = Program address for byte-programming = Selected sector address for sector erase = Any valid address for chip erase Figure 14. Data-Polling Algorithm POST OFFICE BOX 1443 Powered by ICminer.com Electronic-Library Service CopyRight 2003 • HOUSTON, TEXAS 77251–1443 33 TMS29F008T, TMS29F008B 1048576 BY 8-BIT FLASH MEMORIES SMJS845A – MARCH 1997 – REVISED OCTOBER 1997 data-polling operation (continued) AIN Addresses AIN AIN tAVQV tAVQV tELQV tAXQX tELQV CE tGLQV tGLQV OE tGHQZ tWHGL1 WE tGHQX PRODUCT PREVIEW tWHWH1, 2, or 3 DQ DIN NOTES: A. B. C. D. DIN DQ7 DOUT AIN DQ7 = = = = DQ7 DQ7 Last command data written to the device Complement of data written to DQ7 Valid data output Valid address for byte-program, sector-erase, or chip-erase operation Figure 15. AC Waveform for Data-Polling Operation 34 POST OFFICE BOX 1443 Powered by ICminer.com Electronic-Library Service CopyRight 2003 • HOUSTON, TEXAS 77251–1443 DOUT TMS29F008T, TMS29F008B 1048576 BY 8-BIT FLASH MEMORIES SMJS845A – MARCH 1997 – REVISED OCTOBER 1997 toggle-bit operation Start Read DQ0 – DQ7 Addr = VA Read DQ0 – DQ7 Addr = VA DQ6 = Toggle ? No PRODUCT PREVIEW Yes No DQ5 = 1 ? Yes Read DQ0 – DQ7 DQ6 = Toggle ? No Yes Fail Pass NOTE A: Polling status bits DQ6 and DQ5 can change asynchronously. Read DQ6 after DQ5 changes states. Figure 16. Toggle-Bit Algorithm POST OFFICE BOX 1443 Powered by ICminer.com Electronic-Library Service CopyRight 2003 • HOUSTON, TEXAS 77251–1443 35 TMS29F008T, TMS29F008B 1048576 BY 8-BIT FLASH MEMORIES SMJS845A – MARCH 1997 – REVISED OCTOBER 1997 toggle-bit operation (continued) AIN Addresses tAVQV tELQV tELQV CE tGLQV tGLQV OE tWHGL2 PRODUCT PREVIEW WE tWHWH1, 2 or 3 DQ DIN DOUT DQ6 = TOGGLE NOTES: A. B. C. D. DIN DQ6 DOUT AIN = = = = DQ6 = TOGGLE DQ6 = TOGGLE Last command data written to the device Toggle bit output Valid data output Valid address for byte-program, sector-erase, or chip-erase operation Figure 17. AC Waveforms for Toggle-Bit Operation 36 POST OFFICE BOX 1443 Powered by ICminer.com Electronic-Library Service CopyRight 2003 • HOUSTON, TEXAS 77251–1443 DQ6 = STOP TOGGLE TMS29F008T, TMS29F008B 1048576 BY 8-BIT FLASH MEMORIES SMJS845A – MARCH 1997 – REVISED OCTOBER 1997 sector-protect operation Start Select Sector Address A13 – A19 X=1 OE and A9 = VID, CE, A0, and A6 = VIL, A1 = VIH Apply One 100-µs Pulse PRODUCT PREVIEW X = X+1 CE, OE, A0, A6 = VIL, A1 = VIH, A9 = VID Read Data No X = 25 ? No Data = 01H ? Yes Yes Sector Protect Failed Protect Additional Sectors ? Yes No A9 = VIH or VIL Write Reset Command End Figure 18. Sector-Protect Algorithm POST OFFICE BOX 1443 Powered by ICminer.com Electronic-Library Service CopyRight 2003 • HOUSTON, TEXAS 77251–1443 37 TMS29F008T, TMS29F008B 1048576 BY 8-BIT FLASH MEMORIES SMJS845A – MARCH 1997 – REVISED OCTOBER 1997 sector-protect operation (continued) Sector Address A13 – A19 Sector Address VID A9 tAVQV tHVT A6 A1 A0 CE VID PRODUCT PREVIEW OE tGHVWL tHVT tHVT tWLWH2 WE tGLQV DQ DOUT NOTE A: DOUT = 00H if selected sector is not protected, 01H if the sector is protected Figure 19. AC Waveform for Sector-Protect Operation 38 POST OFFICE BOX 1443 Powered by ICminer.com Electronic-Library Service CopyRight 2003 • HOUSTON, TEXAS 77251–1443 TMS29F008T, TMS29F008B 1048576 BY 8-BIT FLASH MEMORIES SMJS845A – MARCH 1997 – REVISED OCTOBER 1997 sector-unprotect operation Start Protect All Sectors X=1 OE, A9 = VID, CE and A0 = VIL, A6 and A1 = VIH Apply One 10-ms Pulse PRODUCT PREVIEW CE, OE, A0 = VIL, A6 and A1 = VIH, A9 = VID Select Sector Address X = X+1 Read Data No No X = 1000 ? Next Sector Address Data = 00H ? Yes Yes Sector Unprotect Failed Last Sector ? No Yes A9 = VIH or VIL Write Reset Command End Figure 20. Sector-Unprotect Algorithm POST OFFICE BOX 1443 Powered by ICminer.com Electronic-Library Service CopyRight 2003 • HOUSTON, TEXAS 77251–1443 39 TMS29F008T, TMS29F008B 1048576 BY 8-BIT FLASH MEMORIES SMJS845A – MARCH 1997 – REVISED OCTOBER 1997 sector-unprotect operation (continued) Sector Address A13 – A19 VID tAVQV A9 tHVT A6 A1 PRODUCT PREVIEW A0 CE VID OE tGHVWL tHVT tHVT tWLWH3 WE tGLQV DQ DOUT NOTE A: DOUT = 00H if selected sector is not protected, 01H if the sector is protected Figure 21. AC Waveform for Sector-Unprotect Operation 40 POST OFFICE BOX 1443 Powered by ICminer.com Electronic-Library Service CopyRight 2003 • HOUSTON, TEXAS 77251–1443 TMS29F008T, TMS29F008B 1048576 BY 8-BIT FLASH MEMORIES SMJS845A – MARCH 1997 – REVISED OCTOBER 1997 temporary sector-unprotect operation Start RESET = VID (see Note A) Perform Erase or Program Operations RESET = VIH Temporary SectorGroup-Unprotect Completed (see Note B) PRODUCT PREVIEW NOTES: A. All protected sectors unprotected B. All previously protected sectors are protected once again Figure 22. Temporary Sector-Unprotect Algorithm 12 V 5V RESET CE WE tVLHT Program or Erase Command Sequence RY / BY Figure 23. Temporary Sector-Unprotect Timing Diagram POST OFFICE BOX 1443 Powered by ICminer.com Electronic-Library Service CopyRight 2003 • HOUSTON, TEXAS 77251–1443 41 TMS29F008T, TMS29F008B 1048576 BY 8-BIT FLASH MEMORIES SMJS845A – MARCH 1997 – REVISED OCTOBER 1997 PARAMETER MEASUREMENT INFORMATION CE The Rising Edge of the Last WE Signal WE Entire Programming or Erase Operations RY / BY tBUSY PRODUCT PREVIEW Figure 24. RY/ BY Timing Diagram During Program/Erase Operations 42 POST OFFICE BOX 1443 Powered by ICminer.com Electronic-Library Service CopyRight 2003 • HOUSTON, TEXAS 77251–1443 TMS29F008T, TMS29F008B 1048576 BY 8-BIT FLASH MEMORIES SMJS845A – MARCH 1997 – REVISED OCTOBER 1997 MECHANICAL DATA DCD (R-PDSO-G**) PLASTIC DUAL SMALL-OUTLINE PACKAGE 40 PIN SHOWN NO. OF PINS ** MAX MIN 40 0.402 (10,20) 0.385 (9,80) 48 0.476 (12,10) 0.469 (11,90) 1 40 0.020 (0,50) A A 0.012 (0,30) 0.004 (0,10) 0.008 (0,21) M 21 PRODUCT PREVIEW 20 0.728 (18,50) 0.720 (18,30) 0.795 (20,20) 0.780 (19,80) 0.041 (1,05) 0.037 (0,95) 0.006 (0,15) NOM 0.047 (1,20) MAX Seating Plane 0.028 (0,70) 0.020 (0,50) 0.004 (0,10) 0.010 (25,00) NOM 4073307/B 07/96 NOTES: A. All linear dimensions are in inches (millimeters). B. This drawing is subject to change without notice. POST OFFICE BOX 1443 Powered by ICminer.com Electronic-Library Service CopyRight 2003 • HOUSTON, TEXAS 77251–1443 43 IMPORTANT NOTICE Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgement, including those pertaining to warranty, patent infringement, and limitation of liability. TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily performed, except those mandated by government requirements. CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE (“CRITICAL APPLICATIONS”). TI SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, AUTHORIZED, OR WARRANTED TO BE SUITABLE FOR USE IN LIFE-SUPPORT DEVICES OR SYSTEMS OR OTHER CRITICAL APPLICATIONS. INCLUSION OF TI PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TO BE FULLY AT THE CUSTOMER’S RISK. In order to minimize risks associated with the customer’s applications, adequate design and operating safeguards must be provided by the customer to minimize inherent or procedural hazards. TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other intellectual property right of TI covering or relating to any combination, machine, or process in which such semiconductor products or services might be or are used. TI’s publication of information regarding any third party’s products or services does not constitute TI’s approval, warranty or endorsement thereof. Copyright 1998, Texas Instruments Incorporated Powered by ICminer.com Electronic-Library Service CopyRight 2003