TI TMS29F800B

TMS29F800T, TMS29F800B
1048576 BY 8-BIT/ 524288 BY 16-BIT
FLASH MEMORIES
SMJS835B – MAY 1997 – REVISED OCTOBER 1997
D
D
D
D
D
D
D
D
D
D
"
Single Power Supply Supports 5 V 10%
Read/Write Operation
Organization . . . 1 048576 By 8 Bits
524 288 By 16 Bits
Array-Blocking Architecture
– One 16K-Byte/One 8K-Word Boot Sector
– Two 8K-Byte/4K-Word Parameter Sectors
– One 32K-Byte/16K-Word Sector
– Fifteen 64K-Byte/32K-Word Sectors
– Any Combination of Sectors Can Be
Erased. Supports Full-Chip Erase
– Any Combination of Sectors Can Be
Marked as Read-Only
Boot-Code Sector Architecture
– T = Top Sector
– B = Bottom Sector
Sector Protection
– Hardware Protection Method That
Disables Any Combination of Sectors
From Write or Erase Operations Using
Standard Programming Equipment
Embedded Program/Erase Algorithms
– Automatically Pre-Programs and Erases
Any Sector
– Automatically Programs and Verifies the
Program Data at Specified Address
JEDEC Standards
– Compatible With JEDEC Byte Pinouts
– Compatible With JEDEC EEPROM
Command Set
Fully Automated On-Chip Erase and
Program Operations
100 000 Program/Erase Cycles
Low Power Dissipation
– 40-mA Typical Active Read for Byte Mode
– 50-mA Typical Active Read for Word
Mode
– 60-mA Typical Program/Erase Current
– Less Than 100-µA Standby Current
– 5 µA in Deep Power-Down Mode
All Inputs/Outputs TTL-Compatible
D
D
D
D
D
Erase Suspend/Resume
– Supports Reading Data From, or
Programming Data to, a Sector Not
Being Erased
Hardware-Reset Pin Initializes the
Internal-State Machine to the Read
Operation
Package Options
– 44-Pin Plastic Small-Outline Package
(PSOP) (DBJ Suffix)
– 48-Pin Thin Small-Outline Package
(TSOP) (DCD Suffix)
Detection Of Program/Erase Operation
– Data Polling and Toggle Bit Feature of
Program/Erase Cycle Completion
– Hardware Method for Detection of
Program/Erase Cycle Completion
Through Ready/Busy (RY/BY) Output Pin
High-Speed Data Access at 5-V VCC 10%
at Three Temperature Ranges
– 80 ns
Commercial . . . 0°C to 70°C
– 90 ns
Commercial . . . 0°C to 70°C
– 100 ns
Extended . . . –40°C to 85°C
– 120 ns
Automotive . . . –40°C to 125°C
"
PRODUCT PREVIEW
D
PIN NOMENCLATURE
A[0:18]
BYTE
DQ[0:14]
DQ15/A–1
CE
OE
NC
RESET
RY / BY
VCC
VSS
WE
Address Inputs
Byte/Word Enable
Data In / Data out
Data In/Out (Word-Wide Mode)
Low-Order Address (Byte-Wide Mode)
Chip Enable
Output Enable
No Internal Connection
Reset / Deep Power Down
Ready / Busy Output
Power Supply
Ground
Write Enable
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright  1997, Texas Instruments Incorporated
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251–1443
1
TMS29F800T, TMS29F800B
1048576 BY 8-BIT/ 524288 BY 16-BIT
FLASH MEMORIES
SMJS835B – MAY 1997 – REVISED OCTOBER 1997
PRODUCT PREVIEW
44-PIN PSOP
DBJ PACKAGE
(TOP VIEW)
RY/BY
A18
A17
A7
A6
A5
A4
A3
A2
A1
A0
CE
VSS
OE
DQ0
DQ8
DQ1
DQ9
DQ2
DQ10
DQ3
DQ11
1
44
2
43
3
42
4
41
5
40
6
39
7
38
8
37
9
36
10
35
11
34
12
33
13
32
14
31
15
30
16
29
17
28
18
27
19
26
20
25
21
24
22
23
RESET
WE
A8
A9
A10
A11
A12
A13
A14
A15
A16
BYTE
VSS
DQ15/A–1
DQ7
DQ14
DQ6
DQ13
DQ5
DQ12
DQ4
VCC
description
The TMS29F800T/B is an 1 048 576 by 8-bit / 524 288 by 16-bit (8 388 608-bit), 5-V single-supply, programmable
read-only memory device that can be electrically erased and reprogrammed. This device is organized as
1 048 576 by 8 bits or 524 288 by 16 bits, divided into 19 sectors:
–
One 16K-byte/8K-word boot sector
–
Two 8K-byte/4K-word sectors
–
One 32K-byte/16K-word sector
–
Fifteen 64K-byte/32K-word sectors
Any combination of sectors can be marked as read-only or erased. Full-chip erasure is also supported.
Sector data protection is afforded by methods that can disable any combination of sectors from write or read
operations using standard programming equipment. An on-chip state machine provides an on-board algorithm
that automatically pre-programs and erases any sector before it automatically programs and verifies program
data at any specified address. The command set is compatible with that of the Joint Electronic Device
Engineering Council (JEDEC) standards and is compatible with the JEDEC 8M-bit electrically erasable,
programmable read-only memory (EEPROM) command set. A suspend/resume feature allows access to
unaltered memory blocks during a section-erase operation. All outputs of this device are TTL-compatible.
Additionally, an erase/suspend/resume feature supports reading data from, or programming data to, a sector
that is not being erased.
2
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251–1443
TMS29F800T, TMS29F800B
1048576 BY 8-BIT/ 524288 BY 16-BIT
FLASH MEMORIES
SMJS835B – MAY 1997 – REVISED OCTOBER 1997
A15
A14
A13
A12
A11
A10
A9
A8
NC
NC
WE
RESET
NC
NC
RY / BY
A18
A17
A7
A6
A5
A4
A3
A2
A1
1
48
2
47
3
46
4
45
5
44
6
43
7
42
8
41
9
40
10
39
11
38
12
37
13
36
14
35
15
34
16
33
17
32
18
31
19
30
20
29
21
28
22
27
23
26
24
25
A16
BYTE
VSS
DQ15 / A–1
DQ7
DQ14
DQ6
DQ13
DQ5
DQ12
DQ4
VCC
DQ11
DQ3
DQ10
DQ2
DQ9
DQ1
DQ8
DQ0
OE
VSS
CE
A0
description (continued)
Device operations are selected by writing JEDEC-standard commands into the command register using
standard microprocessor write timings. The command register acts as an input to an internal-state machine
which interprets the commands, controls the erase and programming operations, outputs the status of the
device, outputs the data stored in the device, and outputs the device algorithm-selection code. On initial power
up, the device defaults to the read mode. A hardware-reset pin initializes the internal-state machine to the read
operation.
The device has low power dissipation with a 40-mA active read for the byte mode, 50-mA active read for the
word mode, 60-mA typical program/erase current mode, and less than 100-mA standby current with a 5-mA
deep-power-down mode. These devices are offered with 80-, 90-, 100-, and 120-ns access times. Table 1 and
Table 2 show the sector-address ranges. The TMS29F800T/B is offered in a 44-pin plastic small-outline
package (PSOP) (DBJ suffix) and a 48-pin thin small-outline package (TSOP) (DCD suffix).
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251–1443
3
PRODUCT PREVIEW
48-PIN TSOP
DCD PACKAGE
(TOP VIEW)
TMS29F800T, TMS29F800B
1048576 BY 8-BIT/ 524288 BY 16-BIT
FLASH MEMORIES
SMJS835B – MAY 1997 – REVISED OCTOBER 1997
device symbol nomenclature
TMS29F800
T
–90
C
DCD
L
Temperature Range
L = Commercial (0°C to 70°C)
E = Extended (– 40°C to 85°C)
Q = Automotive (– 40°C to 125°C)
Package Designator
DCD = 48-Pin Plastic Dual Small-Outline Package
DBJ = 44-Pin Plastic Small-Outline Package
Program/Erase Endurance
C = 100 000 Cycles
B = 10 000 Cycles
PRODUCT PREVIEW
Speed Option
80 = 80 ns
90 = 90 ns
100 = 100 ns
120 = 120 ns
Boot Code Selection Architecture
T = Top Sector
B = Bottom Sector
Device Number / Description
8M Bits
4
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251–1443
TMS29F800T, TMS29F800B
1048576 BY 8-BIT/ 524288 BY 16-BIT
FLASH MEMORIES
SMJS835B – MAY 1997 – REVISED OCTOBER 1997
logic symbol for 44-pin package†
RY / BY
RESET
BYTE
CE
OE
WE
11
10
9
8
7
6
5
4
42
41
40
39
38
37
36
35
34
3
2
0
A
0
524 287
18
1
44
33
22
14
43
G1
[PWR DWN]
G2 1, 2 EN (READ)
1C3 (WRITE)
A, 3D
∇4
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15 / A–1
FLASH
MEMORY
524288 × 16
PRODUCT PREVIEW
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
A16
A17
A18
A, Z4
15
17
19
21
24
26
28
30
16
18
20
22
25
27
29
31
† This symbol is in accordance with ANSI / IEEE Std 91-1984 and IEC Publication 617-12.
Pin numbers shown are for the DBJ package.
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251–1443
5
TMS29F800T, TMS29F800B
1048576 BY 8-BIT/ 524288 BY 16-BIT
FLASH MEMORIES
SMJS835B – MAY 1997 – REVISED OCTOBER 1997
logic symbol for 48-pin package†
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
A16
A17
A18
PRODUCT PREVIEW
RY / BY
RESET
BYTE
CE
OE
WE
25
24
23
22
21
20
19
18
8
7
6
5
4
3
2
1
48
17
16
0
A
0
524 287
18
15
12
47
26
28
11
G1
[PWR DWN]
G2 1, 2 EN (READ)
1C3 (WRITE)
A, 3D
∇4
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15 / A–1
FLASH
MEMORY
524288 × 16
A, Z4
29
31
33
35
38
40
42
44
30
32
34
36
39
41
43
45
† This symbol is in accordance with ANSI / IEEE Std 91-1984 and IEC Publication 617-12.
Pin numbers shown are for the DCD package.
6
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251–1443
TMS29F800T, TMS29F800B
1048576 BY 8-BIT/ 524288 BY 16-BIT
FLASH MEMORIES
SMJS835B – MAY 1997 – REVISED OCTOBER 1997
block diagram
DQ0 – DQ15
RY / BY
Buffer
RY / BY
VCC
VSS
Erase Voltage
Generator
Input/Output Buffers
WE
State Control
BYTE
RESET
Command Registers
PGM Voltage
Generator
STB
CE
PRODUCT PREVIEW
Data Latch
Chip-Enable
Output-Enable
Logic
OE
VCC Detector
Timer
STB
A0 – A18
L
a
t
c
h
A–1
POST OFFICE BOX 1443
Y-Decoder
Y-Gating
X-Decoder
Cell Matrix
A
d
d
r
e
s
s
• HOUSTON, TEXAS 77251–1443
7
TMS29F800T, TMS29F800B
1048576 BY 8-BIT/ 524288 BY 16-BIT
FLASH MEMORIES
SMJS835B – MAY 1997 – REVISED OCTOBER 1997
operation
See Table 1 and Table 2 for the sector-address ranges of the TMS29F800T/B.
Table 1. Top-Boot Sector-Address Ranges†
PRODUCT PREVIEW
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A18
A17
A16
A15
A14
A13
A12
SECTOR SIZE
(x8) ADDRESS RANGE
SA18
1
1
1
1
1
1
X
16K-Byte
FC000H–FFFFFH
7E000H–7FFFFH
SA17
1
1
1
1
1
0
1
8K-Byte
FA000H–FBFFFH
7D000H–7DFFFH
SA16
1
1
1
1
1
0
0
8K-Byte
F8000H–F9FFFH
7C000H–7CFFFH
SA15
1
1
1
1
0
X
X
32K-Byte
F0000H–F7FFFH
78000H–7BFFFH
SA14
1
1
1
0
X
X
X
64K-Byte
E0000H–EFFFFH
70000H–77FFFH
SA13
1
1
0
1
X
X
X
64K-Byte
D0000H–DFFFFH
68000H–6FFFFH
SA12
1
1
0
0
X
X
X
64K-Byte
C0000H–CFFFFH
60000H–67FFFH
58000H–5FFFFH
SA11
1
0
1
1
X
X
X
64K-Byte
B0000H–BFFFFH
SA10
1
0
1
0
X
X
X
64K-Byte
A0000H–AFFFFH
50000H–57FFFH
SA9
1
0
0
1
X
X
X
64K-Byte
90000H–9FFFFH
48000H–4FFFFH
SA8
1
0
0
0
X
X
X
64K-Byte
80000H–8FFFFH
40000H–47FFFH
SA7
0
1
1
1
X
X
X
64K-Byte
70000H–7FFFFH
38000H–3FFFFH
SA6
0
1
1
0
X
X
X
64K-Byte
60000H–6FFFFH
30000H–37FFFH
SA5
0
1
0
1
X
X
X
64K-Byte
50000H–5FFFFH
28000H–2FFFFH
SA4
0
1
0
0
X
X
X
64K-Byte
40000H–4FFFFH
20000H–27FFFH
SA3
0
0
1
1
X
X
X
64K-Byte
30000H–3FFFFH
18000H–1FFFFH
SA2
0
0
1
0
X
X
X
64K-Byte
20000H–2FFFFH
10000H–17FFFH
SA1
0
0
0
1
X
X
X
64K-Byte
10000H–1FFFFH
08000H–0FFFFH
SA0
0
0
0
0
X
X
X
64K-Byte
00000H–0FFFFH
00000H–07FFFH
† The address range is A–1 – A18 in byte mode.
The address range is A0–A18 in word mode.
8
(x16) ADDRESS RANGE
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251–1443
TMS29F800T, TMS29F800B
1048576 BY 8-BIT/ 524288 BY 16-BIT
FLASH MEMORIES
SMJS835B – MAY 1997 – REVISED OCTOBER 1997
operation (continued)
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ÁÁ
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ÁÁ
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ÁÁ
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ÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁ
A18
A17
A16
A15
A14
A13
A12
SECTOR SIZE
(x8) ADDRESS RANGE
(x16) ADDRESS RANGE
SA18
1
1
1
1
X
X
X
64K-Byte
F0000H–FFFFFH
78000H–7FFFFH
SA17
1
1
1
0
X
X
X
64K-Byte
E0000H–EFFFFH
70000H–77FFFH
SA16
1
1
0
1
X
X
X
64K-Byte
D0000H–DFFFFH
68000H–6FFFFH
SA15
1
1
0
0
X
X
X
64K-Byte
C0000H–CFFFFH
60000H–67FFFH
SA14
1
0
1
1
X
X
X
64K-Byte
B0000H–BFFFFH
58000H–5FFFFH
SA13
1
0
1
0
X
X
X
64K-Byte
A0000H–AFFFFH
50000H–57FFFH
SA12
1
0
0
1
X
X
X
64K-Byte
90000H–9FFFFH
48000H–4FFFFH
SA11
1
0
0
0
X
X
X
64K-Byte
80000H–8FFFFH
40000H–47FFFH
SA10
0
1
1
1
X
X
X
64K-Byte
70000H–7FFFFH
38000H–3FFFFH
SA9
0
1
1
0
X
X
X
64K-Byte
60000H–6FFFFH
30000H–37FFFH
SA8
0
1
0
1
X
X
X
64K-Byte
50000H–5FFFFH
28000H–2FFFFH
SA7
0
1
0
0
X
X
X
64K-Byte
40000H–4FFFFH
20000H–27FFFH
SA6
0
0
1
1
X
X
X
64K-Byte
30000H–3FFFFH
18000H–1FFFFH
SA5
0
0
1
0
X
X
X
64K-Byte
20000H–2FFFFH
10000H–17FFFH
SA4
0
0
0
1
X
X
X
64K-Byte
10000H–1FFFFH
08000H–0FFFFH
SA3
0
0
0
0
1
X
X
32K-Byte
08000H–0FFFFH
04000H–07FFFH
SA2
0
0
0
0
0
1
1
8K-Byte
06000H–07FFFH
03000H–03FFFH
SA1
0
0
0
0
0
1
0
8K-Byte
04000H–05FFFH
02000H–02FFFH
SA0
0
0
0
0
0
0
X
16K-Byte
00000H–03FFFH
00000H–01FFFH
† The address range is A–1 – A18 in byte mode.
The address range is A0–A18 in word mode.
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251–1443
9
PRODUCT PREVIEW
Table 2. Bottom-Boot Sector-Address Ranges†
TMS29F800T, TMS29F800B
1048576 BY 8-BIT/ 524288 BY 16-BIT
FLASH MEMORIES
SMJS835B – MAY 1997 – REVISED OCTOBER 1997
operation (continued)
See Table 3 and Table 4 for the operation modes of the TMS29F800T/B.
Table 3. Byte-Operation Mode (BYTE = VIL)
FUNCTIONS†
MODE
OE
WE
A0
A1
A6
A9
RESET
VIL
VIL
VIH
VIL
VIL
VIL
VID
VIH
Manufacturer-Equivalent Code 01h
(TMS29F800T/B – Byte)
VIL
VIL
VIH
VIH
VIL
VIL
VID
VIH
Device-Equivalent Code D6h
(TMS29F800T – Byte)
VIL
VIL
VIH
VIH
VIL
VIL
VID
VIH
Device-Equivalent Code 58h
(TMS29F800B – Byte)
VIL
VIH
VIH
VIH
A0
A1
A6
A9
X
X
X
X
VIH
VIH
Data out
Output disable
VIL
VIL
Standby and write inhibit
Write‡
VIH
VIL
X
X
X
X
X
X
Hi-Z
VIL
X
A0
A1
A6
A9
X
VIH
X
VIH
VIH
X
X
X
X
VIL
X
VIH
X
VIL
X
VIH
X
VIL
X
VID
X
VID
VIH
X
VIL
X
VIL
Hi-Z
Algorithm-selection mode
3 V power supply
3-V
Read
Temporary sector unprotect
PRODUCT PREVIEW
DQ0 DQ7
DQ0–DQ7
CE
Verify sector protect
Hardware reset
Hi-Z
Data in
Data out
Legend:
VIL = Logic 0
VIH = Logic 1
VID = 12.0 ± 0.5 V
† X can be VIL or VIH.
‡ See Table 6 for valid address and data during write.
Table 4. Word-Operation Mode (BYTE =VIH)
MODE
FUNCTIONS†
DQ0 DQ15
DQ0–DQ15
CE
OE
WE
A0
A1
A6
A9
RESET
VIL
VIL
VIH
VIL
VIL
VIL
VID
VIH
Manufacturer-Equivalent Code 01h
(TMS29F800T/B – Word)
VIL
VIL
VIH
VIH
VIL
VIL
VID
VIH
Device-Equivalent Code 22D6h
(TMS29F800T – Word)
VIL
VIL
VIH
VIH
VIL
VIL
VID
VIH
Device-Equivalent Code 2258h
(TMS29F800B – Word)
VIL
VIL
VIH
VIH
A1
A6
A9
X
X
X
VIH
VIH
Data out
X
Standby and write inhibit
Write‡
VIH
VIL
VIL
VIH
X
A0
Output disable
X
X
X
X
X
A0
A1
A6
A9
X
VIL
X
VIH
VIH
Hi-Z
VIH
X
X
X
X
X
X
VIL
X
VIL
X
VIH
X
VIL
X
VIH
X
VIL
X
VID
X
VID
VIH
VIL
Hi-Z
Algorithm-selection mode
3 V power supply
3-V
Read
Temporary sector unprotect
Verify sector protect
Hardware reset
Legend:
VIL = Logic 0
VIH = Logic 1
VID = 12.0 ± 0.5 V
† X can be VIL or VIH.
‡ See Table 6 for valid address and data during write.
10
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251–1443
Hi-Z
Data in
Data out
TMS29F800T, TMS29F800B
1048576 BY 8-BIT/ 524288 BY 16-BIT
FLASH MEMORIES
SMJS835B – MAY 1997 – REVISED OCTOBER 1997
read mode
A logic-low signal applied to the CE and OE pins allows the output of the TMS29F800T/B to be read. When two
or more ’29F800T/B devices are connected in parallel, the output of any one device can be read without
interference. The CE pin is for power control and must be used for device selection. The OE pin is for output
control and is used to gate the data output onto the bus from the selected device.
The address-access time (tAVQV) is the delay from stable address to valid output data. The chip-enable (CE)
access time (tELQV) is the delay from CE low and stable addresses to valid output data. The output-enable
access time (tGLQV) is the delay from OE low to valid output data when CE equals logic low and addresses are
stable for at least the duration of tAVQV–tGLQV.
standby mode
ICC supply current is reduced by applying a logic-high level on CE and RESET to enter the standby mode. In
the standby mode, the outputs are placed in the high-impedance state. Applying a CMOS logic-high level on
CE and RESET reduces the current to 100 µA. Applying a TTL logic-high level on CE and RESET reduces the
current to 1 mA. If the ’29F800T/B is deselected during erasure or programming, the device continues to draw
active current until the operation is complete.
When OE equals VIH or CE equals VIH, output from the device is disabled and the output pins (DQ0–DQ15) are
placed in the high-impedance state.
automatic-sleep mode
The ’29F800 has a built-in feature called automatic-sleep mode to minimize device energy consumption which
is independent of CE, WE, and OE, and is enabled when addresses remain stable for 300 ns. Typical
sleep-mode current is 100 µA. Sleep mode does not affect output data, which remains latched and available
to the system.
algorithm selection
The algorithm-selection mode provides access to a binary code that matches the device with its proper
programming and erase command operations. This mode is activated when VID (11.5 V to 12.5 V) is placed on
address pin A9. Address pins A1 and A6 must be logic low. Two bytes of code are accessed by toggling address
pin A0 from VIL to VIH. Address pins other than A0, A1, and A6 can be at logic low or at logic high.
The algorithm-selection mode can also be read by using the command register, which is useful when VID is not
available to be placed on address pin A9. Table 5 shows the binary algorithm-selection codes.
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ÁÁ
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ÁÁ
ÁÁÁ
ÁÁ
ÁÁÁ
ÁÁ
ÁÁÁ
ÁÁ
ÁÁÁÁÁ
ÁÁÁ
ÁÁÁ
ÁÁÁ
ÁÁÁ
ÁÁ
ÁÁÁ
ÁÁÁ
ÁÁ
ÁÁÁ
ÁÁÁ
ÁÁ
ÁÁÁ
ÁÁ
ÁÁÁ
ÁÁ
ÁÁÁ
ÁÁ
ÁÁÁÁÁ
ÁÁÁ
ÁÁÁ
ÁÁÁ
ÁÁÁ
ÁÁ
ÁÁÁ
ÁÁÁ
ÁÁ
ÁÁÁ
ÁÁÁ
ÁÁ
ÁÁÁ
ÁÁ
ÁÁÁ
ÁÁ
ÁÁÁ
ÁÁ
Table 5. Algorithm-Selection Codes (5-V Single Power Supply)†
CODE
DQ15
DQ14
DQ13
DQ12
DQ11
DQ10
DQ9
DQ8
DQ7
DQ6
DQ5
DQ4
DQ3
DQ2
DQ1
DQ0
Manufacturerequivalent code
01H
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
TMS29F800T–Byte
D6H
A–1
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
1
1
0
1
0
1
1
0
TMS29F800B–Byte
58H
A–1
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
0
1
0
1
1
0
0
0
TMS29F800T
22D6H
0
0
1
0
0
0
1
0
1
1
0
1
0
1
1
0
TMS29F800B
2258H
0
0
1
0
0
0
1
0
0
1
0
1
1
0
0
0
01H
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
Sector protection
† A1 = VIL, A6 = VIL, CE = VIL, OE = VIL
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251–1443
11
PRODUCT PREVIEW
output disable
TMS29F800T, TMS29F800B
1048576 BY 8-BIT/ 524288 BY 16-BIT
FLASH MEMORIES
SMJS835B – MAY 1997 – REVISED OCTOBER 1997
erasure and programming
Erasure and programming of the ’29F800 are accomplished by writing a sequence of commands using standard
microprocessor write timing. The commands are written to a command register and input to the command-state
machine (CSM). The CSM interprets the command entered and initiates program, erase, suspend, and resume
operations as instructed. The CSM acts as the interface between the write-state machine (WSM) and
external-chip operations. The WSM controls all voltage generation, pulse generation, preconditioning, and
verification of memory contents. Program and block-/chip-erase functions are fully automatic. Once the end of
a program or erase operation has been reached, the device resets internally to the read mode. If VCC drops
below the low-voltage-detect level (VLKO), any programming or erase operation is aborted and subsequent
writes are ignored until the VCC level is greater than VLKO. The control pins must be logically correct to prevent
unintentional command writes or programming or erasing.
command definitions
PRODUCT PREVIEW
Device operating modes are selected by writing specific address and data sequences into the command
register. Table 6 defines the valid command sequences. Writing incorrect address and data values or writing
them in the incorrect sequence causes the device to reset to the read mode. The command register does not
occupy an addressable memory location. The register is used to store the command sequence, along with the
address and data needed by the memory array. Commands are written by setting CE = VIL, OE = VIH, and
bringing WE from logic high to logic low. Addresses are latched on the falling edge of WE and data is latched
on the rising edge of WE. Holding WE = VIL and toggling CE is an alternative method. See the switching
characteristics of the write/erase/program-operations section for specific timing information.
12
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251–1443
TMS29F800T, TMS29F800B
1048576 BY 8-BIT/ 524288 BY 16-BIT
FLASH MEMORIES
SMJS835B – MAY 1997 – REVISED OCTOBER 1997
command definitions (continued)
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Table 6. Command Definitions
1ST CYCLE
BUS
CYCLES
ADDR
DATA
Read/reset
(word)
1
xxxxH
xxF0H
Read/reset
(byte)
1
xxx
F0H
Read/reset
(word)
3
555H
Read/reset
(byte)
3
2AAH
go
Algorithm
selection (word)
2ND CYCLE
3RD CYCLE
4TH CYCLE
ADDR
DATA
ADDR
DATA
ADDR
DATA
xxAAH
2AAH
xx55H
555H
xxF0H
RA
RD
AAH
555H
55H
2AAH
F0H
RA
RD
5TH CYCLE
6TH CYCLE
ADDR
DATA
ADDR
DATA
22D6H
T
3
Algorithm
g
selection (byte)
3
Program (word)
Program (byte)
555H
xxAAH
2AAH
xx55H
2AAH
AAH
555H
55H
4
555H
xxAAH
2AAH
4
2AAH
AAH
555H
Chip erase
(word)
6
555H
xxAAH
Chip erase
(byte)
6
2AAH
Sector erase
(word)
6
Sector erase
(byte)
555H
xx90H
01H
2258H
B
D6H
T
2AAH
90H
01H
xx55H
555H
xxA0H
PA
PD
55H
2AAH
A0H
PA
PD
2AAH
xx55H
555H
xx80H
555H
xxAAH
2AAH
xx55H
555H
xx10H
AAH
555H
55H
2AAH
80H
2AAH
AAH
555H
55H
2AAH
10H
555H
xxAAH
2AAH
xx55H
555H
xx80H
555H
xxAAH
2AAH
xx55H
SA
xx30H
6
2AAH
AAH
555H
55H
2AAH
80H
2AAH
AAH
555H
55H
SA
30H
Sector-erase
suspend (word)
1
XXXXH
xxB0H
Erase suspend valid during sector-erase operation
Sector-erase
suspend (byte)
1
XXX
B0H
Erase suspend valid during sector-erase operation
Sector-erase
resume (word)
1
XXXXH
xx30H
Erase resume valid only after erase-suspend operation
Sector-erase
resume (byte)
1
XXX
30H
Erase resume valid only after erase-suspend operation
58H
B
LEGEND:
RA = Address of the location to be read
PA = Address of the location to be programmed
SA = Address of the sector to be erased
Addresses A12 – A18 select 1 to 19 sectors.
RD = Data to be read at selected address location
PD = Data to be programmed at selected address location
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PRODUCT PREVIEW
COMMAND
TMS29F800T, TMS29F800B
1048576 BY 8-BIT/ 524288 BY 16-BIT
FLASH MEMORIES
SMJS835B – MAY 1997 – REVISED OCTOBER 1997
read/reset command
The read or reset mode is activated by writing either of the two read/reset command sequences into the
command register. The device remains in this mode until another valid command sequence is input in the
command register. Memory data is available in the read mode and can be read with standard microprocessor
read-cycle timing.
On power up, the device defaults to the read/reset mode. A read/reset command sequence is not required and
memory data is available.
algorithm-selection command
The algorithm-selection command allows access to a binary code that matches the device with the proper
programming and erase command operations. After writing the three-bus-cycle command sequence, the first
byte of the algorithm-selection code can be read from address XX00h. The second byte of the code can be read
from address XX01h (see Table 6). This mode remains in effect until another valid command sequence is written
to the device.
PRODUCT PREVIEW
program command
Programming is a four-bus-cycle command sequence. The first three bus cycles put the device into the
program-setup state. The fourth bus cycle loads the address location and the data to be programmed into the
device. The addresses are latched on the falling edge of WE while the data is latched on the rising edge of WE
in the fourth bus cycle. The rising edge of WE starts the program operation. The embedded programming
function automatically provides needed voltage and timing to program and verify the cell margin. Any further
commands written to the device during the program operation are ignored.
Programming can be performed at any address location in any sequence. When erased, all bits are in a
logic-high state. Logic lows are programmed into the device. Only an erase operation can change bits from logic
lows to logic highs. Attempting to program a 1 into a bit that has been programmed previously to a 0 causes
the internal-pulse counter to exceed the pulse-count limit, which sets the exceed-time-limit indicator (DQ5) to
a logic-high state. The automatic-programming operation is complete when the data on DQ7 is equivalent to
the data written to bit DQ5, at which time the device returns to the read mode and addresses are no longer
latched. Figure 9 shows a flowchart of the typical device-programming operation.
chip-erase command
Chip erase is a six-bus-cycle command sequence. The first three bus cycles put the device into the erase-setup
state. The next two bus cycles unlock the erase mode. The sixth bus cycle loads the chip-erase command. This
command sequence is required to ensure that the memory contents are not erased accidentally. The rising edge
of WE starts the chip-erase operation. Any further commands written to the device during the chip-erase
operation are ignored.
The embedded chip-erase function automatically provides voltage and timing needed to program and to verify
all the memory cells prior to electrical erase. It then erases and verifies the cell margin automatically without
programming the memory cells prior to erase.
Figure 12 shows a flowchart of the typical chip-erase operation.
14
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TMS29F800T, TMS29F800B
1048576 BY 8-BIT/ 524288 BY 16-BIT
FLASH MEMORIES
SMJS835B – MAY 1997 – REVISED OCTOBER 1997
sector-erase command
Sector-erase is a six-bus-cycle command sequence. The first three bus cycles put the device into the
erase-setup state. The next two bus cycles unlock the erase mode and then the sixth bus cycle loads the
sector-erase command and the sector-address location to be erased. Any address location within the desired
sector can be used. The addresses are latched on the falling edge of WE and the sector-erase command (30h)
is latched on the rising edge of WE in the sixth bus cycle. After a delay of 80 µs from the rising edge of WE, the
sector-erase operation begins on the selected sector(s).
Additional sectors can be selected to be erased concurrently during the sector-erase command sequence. For
each additional sector to be selected for erase, another bus cycle is issued. The bus cycle loads the next
sector-address location and the sector-erase command. The time between the end of the previous bus cycle
and the start of the next bus cycle must be less than 100 µs; otherwise, the new sector location is not loaded.
A time delay of 100 µs from the rising edge of the last WE starts the sector-erase operation. If there is a falling
edge of WE within the 100 µs time delay, the timer is reset.
Any command other than erase suspend (B0h) or sector erase (30h) written to the device during the
sector-erase operation causes the device to exit the sector-erase mode and the contents of the sector(s)
selected for erase are no longer valid. To complete the sector-erase operation, re-issue the sector-erase
command sequence.
The embedded sector-erase function automatically provides needed voltage and timing to program and to verify
all of the memory cells prior to electrical erase and then erases and verifies the cell margin automatically.
Programming the memory cells prior to erase is not required.
See the operation status section for a full description. Figure 14 shows a flowchart of the typical sector-erase
operation.
erase-suspend command
The erase-suspend command (B0h) allows interruption of a sector-erase operation to read data from unaltered
sectors of the device. Erase-suspend is a one-bus-cycle command. The addresses can be VIL or VIH and the
erase-suspend command (B0h) is latched on the rising edge of WE. Once the sector-erase operation is in
progress, the erase-suspend command requests the internal write-state machine to halt operation at
predetermined breakpoints. The erase-suspend command is valid only during the sector-erase operation and
is invalid during programming and chip-erase operations. The sector-erase delay timer expires immediately if
the erase-suspend command is issued while the delay is active.
After the erase-suspend command is issued, the device takes between 0.1 µs and 15 µs to suspend the
operation. The toggle bit must be monitored to determine when the suspend has been executed. When the
toggle bit stops toggling, data can be read from sectors that are not selected for erase. Reading from a sector
selected for erase can result in invalid data. See the operation status section for a full description.
Once the sector-erase operation is suspended, reading from or programming to a sector that is not being erased
can be performed. This command is applicable only during sector-erase operation. Any other command written
during erase-suspend mode to the suspended sector is ignored.
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PRODUCT PREVIEW
One to nineteen sector-address locations can be loaded in any sequence. The state of the delay timer can be
monitored using the sector-erase delay indicator (DQ3). If DQ3 is at logic low, the time delay has not expired.
See the operation status section for a description.
TMS29F800T, TMS29F800B
1048576 BY 8-BIT/ 524288 BY 16-BIT
FLASH MEMORIES
SMJS835B – MAY 1997 – REVISED OCTOBER 1997
erase-resume command
The erase-resume command (30h) restarts a suspended sector-erase operation from the point where it was
halted. Erase resume is a one-bus-cycle command. The addresses can be VIL or VIH and the erase-resume
command (30h) is latched on the rising edge of WE. When an erase-suspend/erase-resume command
combination is written, the internal-pulse counter (exceed timing limit) is reset. The erase-resume command
is valid only in the erase-suspend state. After the erase-resume command is executed, the device returns to
the valid sector-erase state and further writes of the erase-resume command are ignored. After the device has
resumed the sector-erase operation, another erase-suspend command can be issued to the device.
operation status
The status of the device during an automatic-programming algorithm, chip-erase, or automatic-erase algorithm
can be determined in three ways:
PRODUCT PREVIEW
D
D
D
DQ7: Data polling
DQ6: Toggle bit
RY/ BY: Ready / busy bit
status-bit definitions
During operation of the automatic embedded program and erase functions, the status of the device can be
determined by reading the data state of designated outputs. The data-polling bit (DQ7) and toggle bit (DQ6)
require multiple successive reads to observe a change in the state of the designated output. Table 7 defines
the values of the status flags.
16
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1048576 BY 8-BIT/ 524288 BY 16-BIT
FLASH MEMORIES
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status-bit definitions (continued)
Table 7. Operation Status Flags†
DQ7
DQ6
DQ5
DQ3
DQ2
RY/BY
DQ7
T
0
0
T
0
1
No Tog
§
0
0
1
No Tog
0
0
T
1
D
DQ7¶
D
D
D
T
0
0
D
1§
1
Program in erase suspend
Programming
DQ7
T
1
0
0
Programming
Program/erase in auto-erase
In progress
Exceeded time limits
Erase-sector address
Erase suspend mode
Erase-suspend
Non-erase sector address
0
0
T
1
1
No Tog
#
DQ7
T
1
0
No Tog
0
Programming complete
D
D
D
D
D
1
Sector-/chip-erase complete
1
1
1
1
1
1
Program/erase in auto erase
Program in erase suspend
Successful operation
complete
0
0
† T= toggle, D= data, No Tog= No toggle
‡ DQ4, DQ1, DQ0 are reserved for future use.
§ DQ2 can be toggled when the sector address applied is an erasing sector. DQ2 cannot be toggled when the sector address applied is a
non-erasing sector. DQ2 is used to determine which sectors are erasing and which are not.
¶ Status flags apply when outputs are read from the address of a non-erase-suspend operation.
# If DQ5 is high (exceeded timing limits), successive reads from a problem sector causes DQ2 to toggle.
data-polling (DQ7)
The data-polling-status function outputs the complement of the data latched into the DQ7 data register while
the write-state machine (WSM) is engaged in a program or erase operation. Data bit DQ7 changes from
complement to true to indicate the end of an operation. Data-polling is available only during programming,
chip-erase, sector-erase, and sector-erase-timing delay. Data-polling is valid after the rising edge of WE in the
last bus cycle of the command sequence loaded into the command register. Figure 16 shows a flowchart for
data-polling.
During a program operation, reading DQ7 outputs the complement of the DQ7 data to be programmed at the
selected address location. Upon completion, reading DQ7 outputs the true DQ7 data loaded into the
program-data register. During the erase operations, reading DQ7 outputs a logic low. Upon completion, reading
DQ7 outputs a logic high. Also, data-polling must be performed at a sector address that is within a sector that
is being erased. Otherwise, the status is invalid. When using data-polling, the address should remain stable
throughout the operation.
During a data-polling read, while OE is logic low, data bit DQ7 can change asynchronously. Depending on the
read timing, the system can read valid data on DQ7, while other DQ pins are still invalid. A subsequent read
of the device is valid. See Figure 17 for the data-polling timing diagram.
toggle bit (DQ6)
The toggle-bit status function outputs data on DQ6, which toggles between logic high and logic low while the
WSM is engaged in a program or erase operation. When DQ6 stops toggling after two consecutive reads to the
same address, the operation is complete. The toggle bit is available only during programming, chip erase, sector
erase, and sector-erase-timing delay. Toggle-bit data is valid after the rising edge of WE in the last bus cycle
of the command sequence loaded into the command register. Figure 18 shows a flowchart of the toggle-bit
status-read algorithm. Depending on the read timing, DQ6 can stop toggling while other DQ pins are still invalid
and a subsequent read of the device is valid. See Figure 19 for the toggle-bit timing diagram.
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PRODUCT PREVIEW
DEVICE OPERATION‡
TMS29F800T, TMS29F800B
1048576 BY 8-BIT/ 524288 BY 16-BIT
FLASH MEMORIES
SMJS835B – MAY 1997 – REVISED OCTOBER 1997
exceed time limit (DQ5)
Program and erase operations use an internal-pulse counter to limit the number of pulses applied. If the
pulse-count limit is exceeded, DQ5 is set to a logic-high data state. This indicates that the program or erase
operation has failed. DQ7 does not change from complemented data to true data and DQ6 does not stop
toggling when read. To continue operation, the device must be reset.
The exceed-time-limit condition occurs when attempting to program a logic-high state into a bit that has been
programmed previously to a logic low. Only an erase operation can change bits from logic low to logic high. After
reset, the device is functional and can be erased and reprogrammed.
sector-load-timer (DQ3)
PRODUCT PREVIEW
The sector-load-timer status bit, DQ3, is used to determine whether the time to load additional sector addresses
has expired. After completion of a sector-erase command sequence, DQ3 remains at a logic low for 100 µs.
This indicates that another sector-erase command sequence can be issued. If DQ3 is at a logic high, it indicates
that the delay has expired and attempts to issue additional sector-erase commands are ignored. See the
sector-erase command section for a description.
The data-polling and toggle bit are valid during the 100-µs time delay and can be used to determine if a valid
sector-erase command has been issued. To ensure additional sector-erase commands have been accepted,
the status of DQ3 should be read before and after each additional sector-erase command. If DQ3 is at a logic
low on both reads, the additional sector-erase command was accepted.
toggle bit 2 (DQ2)
The state of DQ2 determines whether the device is in algorithmic-erase mode or erase-suspend mode. DQ2
toggles if successive reads are issued to the erasing or erase-suspended sector, assuming in case of the latter
that the device is in erase-suspend-read mode. It also toggles when DQ5 becomes a logic high due to the
timer-exceed limit, and reads are issued to the failed sector. DQ2 does not toggle in any other sector due to DQ5
failure. When the device is in erase-suspend-program mode, successive reads from the non-erase-suspended
sector causes a logic high on DQ2.
ready/ busy bit (RY/ BY)
The RY/ BY bit indicates when the device can accept new commands after performing algorithmic operations.
If the RY/ BY (open-drain output) bit is low, the device is busy with either a program or erase operation and does
not accept any other commands except for erase suspend. While it is in the erase-suspend mode, RY/ BY
remains high. In program mode, the RY/ BY bit is valid (logic low) after the fourth WE pulse. In erase mode, it
is valid after the sixth WE pulse. After a delay period, tbusy, RY/ BY becomes valid. See Figure 28 for the timing
waveform.
Since the RY/ BY bit is an open-drain output, several such bits can be combined in parallel with a pullup resistor
to VCC.
hardware-reset bit (RESET)
When the RESET pin is driven to a logic low, it forces the device out of the currently active mode and into a reset
state. It also avoids bus contention by placing the outputs into the high-impedance state for the duration of the
RESET pulse.
During program or erase operation, if RESET is asserted to logic low, the RY/ BY bit remains at logic low until
the reset operation is complete. Since this can take from 1 µs to 20 µs, the RY/ BY bit can be used to sense reset
completion or the user can allow a maximum of 20 µs. If RESET is asserted during read mode, then the reset
operation is complete within 500 ns. See Figure 1 and Figure 2 for timing specifications.
The RESET pin also can be used to drive the device into deep power-down (standby) mode by applying
VSS ± 0.3 V to it. ICC4 reads <1 µA typical, and 5 µA maximum for CMOS inputs. Standby mode can be entered
anytime, regardless of the condition of CE.
18
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TMS29F800T, TMS29F800B
1048576 BY 8-BIT/ 524288 BY 16-BIT
FLASH MEMORIES
SMJS835B – MAY 1997 – REVISED OCTOBER 1997
hardware-reset bit (RESET) (continued)
Asserting RESET during program or erase can leave erroneous data in the address locations. These locations
need to be updated after the device resumes normal operations. A minimum of 50 ns must be allowed after
RESET goes high before a valid read can take place.
tRL = 500 ns
RESET
20 µs max
RY/BY
Figure 1. Device Reset During a Program or Erase Operation
tRL = 500 ns
PRODUCT PREVIEW
RESET
RY/BY
0V
Figure 2. Device Reset During Read Mode
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TMS29F800T, TMS29F800B
1048576 BY 8-BIT/ 524288 BY 16-BIT
FLASH MEMORIES
SMJS835B – MAY 1997 – REVISED OCTOBER 1997
word- / byte-mode configuration
The BYTE pin is used to set the device configuration. If BYTE is at a logic 1, the device is in word mode with
all data outputs valid and the DQ15 / A–1 output representing DQ15. Similarly, if BYTE is at a logic 0, the device
is in byte mode with only DQ0 – DQ7 valid. The remaining outputs are in high-impedance mode and DQ15 / A–1
is used as an input for the least significant bit (A1) address function. See Figure 3 and Figure 4 for timing
specifications.
CE
OE
tELFH
BYTE
PRODUCT PREVIEW
DQ8 – DQ14
DQ8 – DQ14
DQ8 – DQ14
tFHQV
DQ15/A – 1
A–1
DQ15
Figure 3. Word-Mode Configuration
CE
OE
tELFL
BYTE
DQ8 – DQ14
DQ8 – DQ14
DQ8 – DQ14
tFLQV
DQ15/A – 1
DQ15
A–1
Figure 4. Byte-Mode Configuration
temporary hardware-sector unprotect feature
This feature temporarily enables both programming and erase operations on any combination of one to nineteen
sectors that were previously protected. The unprotect feature is enabled using high voltage VID (11.5 V to
12.5 V) on the RESET pin, using standard command sequences.
Normally, the device is delivered with all sectors unprotected.
20
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1048576 BY 8-BIT/ 524288 BY 16-BIT
FLASH MEMORIES
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sector-protect programming
The sector-protect programming mode is activated when A6, A0, and CE are at VIL, and address pin A9 and
control pin OE are forced to VID. Address pin A1 is set to VIH.The sector-select address pins A12–A18 are used
to select the sector to be protected. Address pins A0–A11 and I/O pins must be stable and can be either VIL or
VIH. Once the addresses are stable, WE is pulsed low for 100 µs, causing programming to begin on the falling
edge of WE and to terminate on the rising edge of WE. Figure 20 is a flowchart of the sector-protect algorithm
and Figure 21 shows a timing diagram of the sector-protect operation.
Commands to program or erase a protected sector do not change the data contained in the sector. Attempts
to program and erase a protected sector cause the data-polling bit (DQ7) and the toggle bit (DQ6) to operate
from 2 ms to 100 ms and then return to valid data.
sector-protect verify
Sector-protect verify can also be read using the algorithm-selection command. After issuing the three-bus-cycle
command sequence, the sector-protection status can be read on DQ0. Set address pins
A0 = VIL, A1 = VIH, and A6 = VIL, and then the sector address pins A12–A18 select the sector to be verified.
The remaining addresses are set to VIL. If the sector selected is protected, DQ0 outputs a logic-high state. If
the sector selected is not protected, DQ0 outputs a logic-low state. This mode remains in effect until another
valid command sequence is written to the device. Figure 20 is a flowchart of the sector-protect algorithm and
Figure 21 shows a timing diagram of the sector-protect operation.
sector unprotect
Prior to sector unprotect, all sectors must be protected using the sector-protect programming mode. The sector
unprotect is activated when address pin A9 and control pin OE are forced to VID. Address pins A1 and A6 are
set to VIH while CE and A0 are set to VIL. The sector-select address pins A12–A18 can be VIL or VIH. All sectors
are unprotected in parallel and once the inputs are stable, WE is pulsed low for 10 ms, causing the unprotect
operation to begin on the falling edge of WE and to terminate on the rising edge of WE. Figure 22 is a flowchart
of the sector-unprotect algorithm and Figure 23 shows a timing diagram of the sector-unprotect operation.
sector-unprotect verify
Verification of the sector unprotect is accomplished when WE = VIH, OE = VIL, CE =VIL, and address pin
A9 = VID, and then select the sector to be verified. Address pins A1 and A6 are set to VIH, and A0 is set to VIL.
The other addresses can be VIH or VIL. If the sector selected is protected, the DQs output 01h. If the sector is
not protected, the DQs output 00h. Sector unprotect can also be read using the algorithm-selection command.
low VCC write lockout
During power-up and power-down operations, write cycles are locked out for VCC less than VLKO. If VCC < VLKO,
the command input is disabled and the device is reset to the read mode. On power up, if CE = VIL, WE = VIL,
and OE = VIH, the device does not accept commands on the rising edge of WE. The device automatically powers
up in the read mode.
glitching
Pulses of less than 5 ns (typical) on OE, WE, or CE do not issue a write cycle.
power supply considerations
Each device should have a 0.1-µF ceramic capacitor connected between VCC and VSS to suppress circuit noise.
Printed circuit traces to VCC should be appropriate to handle the current demand and minimize inductance.
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251–1443
21
PRODUCT PREVIEW
Verification of the sector-protection programming is activated when WE = VIH, OE = VIL, CE = VIL, and address
pin A9 = VID. Address pins A0 and A6 are set to VIL, and A1 is set to VIH. The sector-address pins A12–A18
select the sector that is to be verified. The other addresses can be VIH or VIL. If the sector that was selected
is protected, the DQs output 01h. If the sector is not protected, the DQs output 00h.
TMS29F800T, TMS29F800B
1048576 BY 8-BIT/ 524288 BY 16-BIT
FLASH MEMORIES
SMJS835B – MAY 1997 – REVISED OCTOBER 1997
absolute maximum ratings over ambient temperature range (unless otherwise noted)†
Supply voltage range, VCC (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.6 V to 7 V
Input voltage range: All inputs except A9, CE, OE (see Note 2) . . . . . . . . . . . . . . . . . . . . – 0.6 V to VCC + 1 V
A9, CE, OE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.6 V to 13.5 V
Output voltage range (see Note 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.6 V to VCC + 1 V
Ambient temperature range during read / erase / program, TA
(L) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 70°C
(E) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 40°C to 85°C
(Q) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 40°C to 125°C
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 65°C to 150°C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. All voltage values are with respect to VSS.
2. The voltage on any input pin can undershoot to –2 V for periods less than 20 ns (see Figure 6).
3. The voltage on any input and output pin can overshoot to 7 V for periods less than 20 ns (see Figure 7).
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PRODUCT PREVIEW
recommended operating conditions
VCC
MAX
4.5
5.5
V
0.7 *VCC
VCC+0.5
VCC+0.5
V
TTL
–0.5
0.8
CMOS
–0.5
0.8
11.5
12.5
V
3.2
4.2
V
L version
0
70
E version
–40
85
Q version
–40
125
TTL
VIH
High level dc input voltage
High-level
VIL
Low level dc input voltage
Low-level
VID
VLKO
Algorithm-selection and sector-protect input voltage
TA
Ambient temperature
22
MIN
Supply voltage
CMOS
Low VCC lock-out voltage
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251–1443
2
UNIT
V
°C
TMS29F800T, TMS29F800B
1048576 BY 8-BIT/ 524288 BY 16-BIT
FLASH MEMORIES
SMJS835B – MAY 1997 – REVISED OCTOBER 1997
electrical characteristics over recommended ranges of supply voltage and ambient temperature
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TEST CONDITIONS
TTL-input level
VOH
High-level output voltage
CMOS-input level
CMOS-input level
VOL
II
Low-level output voltage
IO
IID
Output current (leakage)
Input current (leakage)
VCC supply current (standby)
ICC2
VCC supply
y current
(see Note 4 and Note 7)
ICC3
ICC4
IOH = –2.5 mA
IOH = – 100 µA
VCC = VCC MIN,
VCC = VCC MIN,
IOH = – 2.5 mA
IOL = 5.8 mA
MAX
TTL-input level
CMOS-input level
UNIT
2.4 V
V
VCC–0.4
0.85 * VCC
VCC = VCC MAX, VIN = VSS to VCC
VO = VSS to VCC, CE = VIH
A9 or CE or OE = VID MAX
High-voltage current (standby)
ICC1
MIN
VCC = VCC MIN,
VCC = VCC MIN,
CE = VIH, VCC = VCC MAX
CE = VCC ± 0.2,
VCC = VCC MAX
Byte
0.45
V
±1
µA
±1
µA
35
µA
1
mA
100
µA
40
mA
CE = VIL, OE = VIH
50
VCC supply current (see Note 5)
CE = VIL, OE = VIH
60
mA
VCC supply current (standby during reset)
VCC = VCC MAX,
RESET = VSS ± 0.3 V
5
µA
100
µA
Word
ICC5
Automatic sleep mode (see Note 6 and Note 7)
VIH = VCC ± 0.3 V, VIL = VSS ± 0.3 V
NOTES: 4. ICC current in the read mode, switching at 6 MHz
5. ICC current while erase or program operation is in progress
6. Automatic sleep mode is entered when addresses remain stable for 300 ns.
7. IOUT = 0 mA
capacitance over recommended ranges of supply voltage and ambient temperature
PARAMETER
Ci1
Input capacitance (All inputs except A9, CE, OE)
Ci2
Co
TEST CONDITIONS
f = 1 MHz
Input capacitance (A9, CE, OE)
VI = 0 V,
VI = 0 V,
Output capacitance
VO = 0 V,
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251–1443
MIN
MAX
UNIT
7.5
pF
f = 1 MHz
9
pF
f = 1 MHz
12
pF
23
PRODUCT PREVIEW
PARAMETER
TMS29F800T, TMS29F800B
1048576 BY 8-BIT/ 524288 BY 16-BIT
FLASH MEMORIES
SMJS835B – MAY 1997 – REVISED OCTOBER 1997
PARAMETER MEASUREMENT INFORMATION
0.5 mA
IOL
Output
Under
Test
1.5 V
CL = 30 pF
(see Note A and Note B)
– 0.5 mA
2.4 V
IOH
2V
0.8 V
0.45 V
PRODUCT PREVIEW
NOTES: A. CL includes probe and fixture capacitance.
B. The ac testing inputs are driven at 2.4 V for logic high and 0.45 V for logic low. Timing measurements are made
at 2 V for logic high and 0.8 V for logic low on both inputs and outputs. Each device should have a 0.1-µF ceramic
capacitor connected between VCC and VSS as closely as possible to the device pins.
Figure 5. AC Test Output Load Circuit
20 ns
20 ns
+0.8 V
–0.5 V
–2.0 V
20 ns
Figure 6. Maximum Negative Overshoot Waveform
20 ns
VCC + 2.0 V
VCC + 0.5 V
2.0 V
20 ns
20 ns
Figure 7. Maximum Positive Overshoot Waveform
24
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251–1443
TMS29F800T, TMS29F800B
1048576 BY 8-BIT/ 524288 BY 16-BIT
FLASH MEMORIES
SMJS835B – MAY 1997 – REVISED OCTOBER 1997
switching characteristics over recommended ranges of supply voltage and ambient temperature,
read-only operation
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PARAMETER
tc(R)
ta(A)
Cycle time, read
ta(E)
ta(G)
Access time, CE
tdis(E)
tdis(G)
Disable time, CE to high impedance
ten(E)
ten(G)
tAVAV
tAVQV
tELQV
’29F800-80
’29F800-90
MIN
MIN
MAX
80
MAX
90
’29F800-100
MIN
MAX
100
’29F800-120
MIN
MAX
120
UNIT
ns
80
90
100
120
ns
80
90
100
120
ns
tGLQV
tEHQZ
40
45
50
55
ns
30
30
30
40
ns
30
30
30
40
ns
Enable time, CE to low impedance
tGHQZ
tELQX
0
0
0
0
ns
Enable time, OE to low impedance
tGLQX
0
0
0
0
ns
Hold time, output from address CE
or OE change
tAXQX
0
0
0
0
ns
Access time, OE
Disable time, OE to high impedance
PRODUCT PREVIEW
th(D)
Access time, address
ALTERNATE
SYMBOL
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251–1443
25
PRODUCT PREVIEW
Cycle time, write
th(A)
tsu(D)
Hold time, address
th(D)
tsu(E)
Hold time, data valid after WE high
th(E)
tw(WL)
Hold time, CE
tw(WH)
trec(R)
Pulse duration, WE high
Setup time, address
Setup time, data
Setup time, CE
Pulse duration, WE low
Recovery time, read before write
Hold time, OE read
Hold time, OE toggle, data
Setup time, VCC
Transition time, VID
(see Note 8 and Note 9)
’29F800-90
MAX
MIN
TYP
’29F800-100
MAX
MIN
TYP
’29F800-120
MAX
MIN
TYP
MAX
UNIT
tAVAV
tAVWL
tWLAX
80
90
100
120
ns
0
0
0
0
ns
45
50
50
65
ns
tDVWH
tWHDX
45
50
50
65
ns
0
0
0
0
ns
tELWL
tWHEH
0
0
0
0
ns
0
0
0
0
ns
tWLWH1
tWHWL
45
50
50
65
ns
20
30
30
35
ns
tGHWL
tWHGL1
0
0
0
0
ns
0
0
0
0
ns
tWHGL2
tVCEL
10
10
10
10
ns
50
50
50
50
µs
tHVT
4
4
4
4
µs
tWLWH2
tWLWH3
100
100
100
100
µs
Pulse duration, WE low (see Note 9)
10
10
10
10
ms
Setup time, CE VID to WE
(see Note 9)
tEHVWL
4
4
4
4
µs
Setup time, OE VID to WE
(see Notes 8 and 9)
tGHVWL
4
4
4
4
µs
Pulse duration, WE low (see Note 8)
tc(W)PR
(W)PR
TYP
Cycle
y
time,, programming
g
g
operation
Byte
Word
Write recovery time from RY / BY
tWHWH1
8
8
8
8
µs
14
14
14
14
µs
tRB
tRL
0
0
0
0
ns
RESET low time
500
500
500
500
ns
RESET high time before read
tRH
50
50
50
50
ns
tRPD
tRPD
20
20
20
20
µs
5
5
5
5
µs
tBUSY
tELFL / tELFH
90
90
90
90
ns
5
5
5
5
ns
RESET to power-down time
RESET to CE/WE low
Program/erase valid to RY / BY delay
CE to BYTE switching low or high
NOTES: 8. Sector-protect timing
9. Sector-unprotect timing
Template Release Date: 7–11–94
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
tc(W)
tsu(A)
’29F800-80
MIN
TMS29F800T, TMS29F800B
1 048 576 BY 8-BIT OR 524288 BY 16-BIT
FLASH MEMORIES
ALT
SYMBOL
PARAMETER
SMJS835B – MAY 1997 – REVISED OCTOBER 1997
26
switching characteristics over recommended ranges of supply voltage and ambient temperature, controlled by WE
switching characteristics over recommended ranges of supply voltage and ambient temperature, controlled by WE
(continued)
PARAMETER
BYTE switching low to output 3-state
BYTE switching high to output active
tc(W)ER
Cycle time, sector-erase operation
Cycle time, chip-erase operation
ALT
SYMBOL
’29F800-80
MIN
TYP
tFLQZ
tFHQV
tWHWH2
tWHWH3
’29F800-90
MAX
TYP
’29F800-100
MAX
MIN
TYP
’29F800-120
MAX
MIN
TYP
MAX
UNIT
30
30
40
40
ns
80
90
100
120
ns
1
6
MIN
1
50
6
1
50
6
1
50
6
s
50
s
27
SMJS835B – MAY 1997 – REVISED OCTOBER 1997
TMS29F800T, TMS29F800B
1 048 576 BY 8-BIT OR 524288 BY 16-BIT
FLASH MEMORIES
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
PRODUCT PREVIEW
PRODUCT PREVIEW
Cycle time, write
th(A)
tsu(D)
Hold time, address
th(D)
tsu(W)
Hold time, data
th(W)
tw(EL)
Hold time, WE
tw(EH)
trec(R)
Pulse duration, CE high
Setup time, address
Setup time, data
Setup time, WE
Pulse duration, CE low
Recovery time, read before write
Setup time, OE
th(C)
Hold time, OE read
Hold time, OE toggle, data
Programming operation
Byte
Word
Cycle time, sector-erase operation
Cycle time, chip-erase operation
BYTE switching low to output 3-state
TYP
’29F800-90
MAX
MIN
TYP
’29F800-100
MAX
MIN
TYP
’29F800-120
MAX
MIN
TYP
MAX
UNIT
tAVAV
tAVEL
tELAX
80
90
100
120
ns
0
0
0
0
ns
45
50
50
65
ns
tDVEH
tEHDX
45
50
50
65
ns
0
0
0
0
ns
tWLEL
tEHWH
tELEH1
0
0
0
0
ns
0
0
0
0
ns
45
50
50
65
ns
tEHEL
tGHEL
tGLEL
20
30
30
35
ns
0
0
0
0
ns
0
0
0
0
ns
tEHGL1
tEHGL2
0
0
0
0
ns
10
10
10
10
ns
tEHEH1
tEHEH2
tEHEH3
tFLQZ
8
8
8
8
µs
14
14
14
14
µs
1
6
1
50
30
6
1
50
30
6
1
50
40
6
s
50
s
40
ns
Template Release Date: 7–11–94
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
tc(W)
tsu(A)
’29F800-80
MIN
TMS29F800T, TMS29F800B
1 048 576 BY 8-BIT OR 524288 BY 16-BIT
FLASH MEMORIES
ALTERNATE
SYMBOL
PARAMETER
SMJS835B – MAY 1997 – REVISED OCTOBER 1997
28
switching characteristics over recommended ranges of supply voltage and ambient temperature, controlled by CE
TMS29F800T, TMS29F800B
1048576 BY 8-BIT/ 524288 BY 16-BIT
FLASH MEMORIES
SMJS835B – MAY 1997 – REVISED OCTOBER 1997
erase and program performance†
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
1‡
15§
s
Sector-erase time
Excludes 00H programming prior to
erasure
Program word time
Excludes system-level overhead
9
11
5200
µs
Program byte time
Excludes system-level overhead
9
9
3 600§
µs
6‡
50§
s
Chip-programming time
Excludes system-level overhead
Erase/program cycles
100 000 1 000 000
cycles
† The internal algorithms allow for 2.5-ms byte-program time. DQ5 = 1 only after a byte takes the theoretical maximum time to program. A minimal
number of bytes can require signficantly more programming pulses than the typical byte. The majority of the bytes program within one or two
pulses. This is demonstrated by the typical and maximum programming time listed above.
‡ 25°C, 5-V VCC, 100 000 cycles, typical pattern
§ Under worst-case conditions: 90°C, 5-V VCC, 100 000 cycles
latchup characteristics (see Note 10)
PARAMETER
MAX
–1
13
V
Input voltage with respect to VSS on all I/O pins
–1
VCC + 1
100
V
Current
– 100
UNIT
PRODUCT PREVIEW
MIN
Input voltage with respect to VSS on all pins except I/O pins (including A9 and OE)
mA
NOTE 10: Includes all pins except VCC test conditions: VCC =5 V, one pin at a time
pin capacitance, all packages (see Note 11)
PARAMETER
TEST CONDITIONS
CIN
Input capacitance
COUT
Output capacitance
VIN = 0
VOUT = 0
CIN2
Control pin capacitance
VIN = 0
TYP
MAX
6
7.5
UNIT
pF
8.5
12
pF
8
10
pF
MIN
MAX
NOTE 11: Test conditions: TA = 25°C, f = 1 MHz
data retention
PARAMETER
Minimum pattern data retention time
POST OFFICE BOX 1443
TEST CONDITIONS
150°C
10
125°C
20
• HOUSTON, TEXAS 77251–1443
UNIT
Years
29
TMS29F800T, TMS29F800B
1048576 BY 8-BIT/ 524288 BY 16-BIT
FLASH MEMORIES
SMJS835B – MAY 1997 – REVISED OCTOBER 1997
read operation
tAVAV
Valid Addresses
Addresses
tAVQV
CE
tEHQZ
tELQV
OE
tGHQZ
PRODUCT PREVIEW
tGLQV
WE
tGLQX
tAXQX
tELQX
Valid Data
DQ
Figure 8. AC Waveform for Read Operation
30
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251–1443
TMS29F800T, TMS29F800B
1048576 BY 8-BIT/ 524288 BY 16-BIT
FLASH MEMORIES
SMJS835B – MAY 1997 – REVISED OCTOBER 1997
write operation
Start
Write Bus Cycle
2AAH/AAH or
555H / XXAAH
Write Bus Cycle
555H/55H or
2AAH / XX55H
Write Bus Cycle
2AAH/A0H or
555H / XXA0H
PRODUCT PREVIEW
Write Bus Cycle
Program Address / Program Data
Poll Device Status
Operation
Complete
?
No
Yes
No
Next Address
Last
Address
?
Yes
End
Figure 9. Program Algorithm
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251–1443
31
TMS29F800T, TMS29F800B
1048576 BY 8-BIT/ 524288 BY 16-BIT
FLASH MEMORIES
SMJS835B – MAY 1997 – REVISED OCTOBER 1997
write operation (continued)
tAVAV
555H
Addresses
2AAH
555H
PA
PA
tWLAX
tAVWL
CE
tELWL
tWHEH
OE
tWHDX
tGHWL
tWHWL
PRODUCT PREVIEW
tWLWH1
WE
tWHWH1
tDVWH
DQ
NOTES: A.
B.
C.
D.
xxAAH
xx55H
xxA0H
PD
PA = Address to be programmed
PD = Data to be programmed
DQ7 = Complement of data written to DQ7
Timing diagram shown is for word-mode operation.
Figure 10. AC Waveform for Program Operation
32
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251–1443
DQ7
DOUT
TMS29F800T, TMS29F800B
1048576 BY 8-BIT/ 524288 BY 16-BIT
FLASH MEMORIES
SMJS835B – MAY 1997 – REVISED OCTOBER 1997
write operation (continued)
tAVAV
555H
Addresses
2AAH
555H
PA
PA
tAVEL
tELAX
tELEH
CE
tEHEL
tGHEL
OE
tDVEH
tWLEL
tEHWH
tWHWH1
WE
DQ
NOTES: A.
B.
C.
D.
xxAAH
xx55H
xxA0H
PD
DQ7
PRODUCT PREVIEW
tEHDX
DOUT
PA=Address to be programmed
PD = Data to be programmed
DQ7 = Complement of data written to DQ7
Timing diagram shown is for word-mode operation.
Figure 11. Alternate CE-Controlled Write Operation
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251–1443
33
TMS29F800T, TMS29F800B
1048576 BY 8-BIT/ 524288 BY 16-BIT
FLASH MEMORIES
SMJS835B – MAY 1997 – REVISED OCTOBER 1997
chip-erase operation
Start
Write Bus Cycle
2AAH/AAH or
555H / XXAAH
Write Bus Cycle
555H/55H or
2AAH / XX55H
Write Bus Cycle
2AAH/80H or
555H / XX80H
PRODUCT PREVIEW
Write Bus Cycle
2AAH/AAH or
555H / XXAAH
Write Bus Cycle
555H/55H or
2AAH / XX55H
Write Bus Cycle
2AAH/10H or
555H / XX10H
Poll Device Status
Operation
Complete
?
No
Yes
End
Figure 12. Chip-Erase Algorithm
34
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251–1443
TMS29F800T, TMS29F800B
1048576 BY 8-BIT/ 524288 BY 16-BIT
FLASH MEMORIES
SMJS835B – MAY 1997 – REVISED OCTOBER 1997
chip-erase operation (continued)
tAVAV
555H
Addresses
555H
2AAH
555H
VA
tWLAX
tAVWL
CE
tELWL
tWHEH
OE
tWHDX
tGHWL
tWHWL
PRODUCT PREVIEW
tWLWH1
WE
tWHWH3
tDVWH
DQ
xx80H
xxAAH
xx55H
xx10H
DQ7=0
DOUT=FFH
NOTES: A. VA = any valid address
B. Figure details the last four bus cycles in a six-bus-cycle operation.
C. Timing diagram shown is for word-mode operation.
Figure 13. AC Waveform for Chip-Erase Operation
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251–1443
35
TMS29F800T, TMS29F800B
1048576 BY 8-BIT/ 524288 BY 16-BIT
FLASH MEMORIES
SMJS835B – MAY 1997 – REVISED OCTOBER 1997
sector-erase operation
Start
Write Bus Cycle
2AAH/AAH or
555H / XXAAH
Write Bus Cycle
555H/55H or
2AAH / XX55H
Write Bus Cycle
2AAH/80H or
555H / XX80H
PRODUCT PREVIEW
Write Bus Cycle
2AAH/AAH or
555H/XXAAH
Write Bus Cycle
555H/55H or
2AAH / XX55H
Write Bus Cycle
Sector Address /
30H (Byte)/xx30H (Word)
No
DQ3 = 0
?
Yes
Load
Additional
Sectors
?
Yes
No
Poll Device Status
No
Operation
Complete
?
Yes
End
Figure 14. Sector-Erase Algorithm
36
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251–1443
TMS29F800T, TMS29F800B
1048576 BY 8-BIT/ 524288 BY 16-BIT
FLASH MEMORIES
SMJS835B – MAY 1997 – REVISED OCTOBER 1997
sector-erase operation (continued)
tAVAV
555H
Addresses
555H
2AAH
SA
SA
tWLAX
tAVWL
CE
tELWL
tWHEH
OE
tWHDX
tGHWL
tWHWL
PRODUCT PREVIEW
tWLWH1
WE
tWHWH2
tDVWH
DQ
xx80H
xxAAH
xx55H
xx30H
DQ7=0
DOUT=FFH
NOTES: A. SA = Sector address to be erased
B. Figure details the last four bus cycles in a six-bus-cycle operation.
C. Timing diagram shown is for word-mode operation.
Figure 15. AC Waveform for Sector-Erase Operation
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251–1443
37
TMS29F800T, TMS29F800B
1048576 BY 8-BIT/ 524288 BY 16-BIT
FLASH MEMORIES
SMJS835B – MAY 1997 – REVISED OCTOBER 1997
data-polling operation
Start
Read DQ0 – DQ7
Addr = VA
DQ7 =
Data
?
Yes
No
No
PRODUCT PREVIEW
DQ5 = 1
?
Yes
Read DQ0 – DQ7
Addr = VA
DQ7 =
Data
?
Yes
No
Fail
Pass
NOTES: A. Polling status bits DQ7 and DQ5 may change asynchronously.
Read DQ7 after DQ5 changes states.
B. VA = Program address for byte-programming
= Selected sector address for sector erase
= Any valid address for chip erase
Figure 16. Data-Polling Algorithm
38
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251–1443
TMS29F800T, TMS29F800B
1048576 BY 8-BIT/ 524288 BY 16-BIT
FLASH MEMORIES
SMJS835B – MAY 1997 – REVISED OCTOBER 1997
data-polling operation (continued)
AIN
Addresses
AIN
AIN
tAVQV
tAVQV
tELQV
tAXQX
tELQV
CE
tGLQV
tGLQV
OE
tGHQZ
tWHGL1
WE
tGHQX
DQ
DIN
NOTES: A.
B.
C.
D.
DIN
DQ7
DOUT
AIN
DQ7
=
=
=
=
DQ7
DQ7
PRODUCT PREVIEW
tWHWH1, 2, or 3
DOUT
Last command data written to the device
Complement of data written to DQ7
Valid data output
Valid address for byte-program, sector-erase, or chip-erase operation
Figure 17. AC Waveform for Data-Polling Operation
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251–1443
39
TMS29F800T, TMS29F800B
1048576 BY 8-BIT/ 524288 BY 16-BIT
FLASH MEMORIES
SMJS835B – MAY 1997 – REVISED OCTOBER 1997
toggle-bit operation
Start
Read DQ0 – DQ7
Addr = VA
Read DQ0 – DQ7
Addr = VA
DQ6 =
Toggle
?
No
PRODUCT PREVIEW
Yes
No
DQ5 = 1
?
Yes
Read DQ0 – DQ7
DQ6 =
Toggle
?
No
Yes
Fail
Pass
NOTE A: Polling status bits DQ6 and DQ5 can change
asynchronously. Read DQ6 after DQ5 changes
states.
Figure 18. Toggle-Bit Algorithm
40
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251–1443
TMS29F800T, TMS29F800B
1048576 BY 8-BIT/ 524288 BY 16-BIT
FLASH MEMORIES
SMJS835B – MAY 1997 – REVISED OCTOBER 1997
toggle-bit operation (continued)
AIN
Addresses
tAVQV
tELQV
tELQV
CE
tGLQV
tGLQV
OE
tWHGL2
WE
DQ
DIN
DOUT
DQ6 = TOGGLE
NOTES: A.
B.
C.
D.
DIN
DQ6
DOUT
AIN
PRODUCT PREVIEW
tWHWH1, 2 or 3
=
=
=
=
DQ6 = TOGGLE
DQ6 = TOGGLE
DQ6 = STOP
TOGGLE
Last command data written to the device
Toggle bit output
Valid data output
Valid address for byte-program, sector-erase, or chip-erase operation
Figure 19. AC Waveforms for Toggle-Bit Operation
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251–1443
41
TMS29F800T, TMS29F800B
1048576 BY 8-BIT/ 524288 BY 16-BIT
FLASH MEMORIES
SMJS835B – MAY 1997 – REVISED OCTOBER 1997
sector-protect operation
Start
Select Sector Address
A12 – A18
X=1
OE and A9 = VID,
CE, A0, and A6 = VIL,
A1 = VIH
PRODUCT PREVIEW
Apply One 100-µs
Pulse
X = X+1
CE, OE, A0, A6 = VIL,
A1 = VIH,
A9 = VID
Read Data
No
X = 25
?
No
Data = 01H
?
Yes
Yes
Sector Protect
Failed
Protect
Additional
Sectors
?
No
A9 = VIH or VIL
Write Reset Command
End
Figure 20. Sector-Protect Algorithm
42
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251–1443
Yes
TMS29F800T, TMS29F800B
1048576 BY 8-BIT/ 524288 BY 16-BIT
FLASH MEMORIES
SMJS835B – MAY 1997 – REVISED OCTOBER 1997
sector-protect operation (continued)
Sector Address
A18 – A12
Sector Address
VID
A9
tAVQV
tHVT
A6
A1
A0
CE
VID
tGHVWL
tHVT
tHVT
PRODUCT PREVIEW
OE
tWLWH2
WE
tGLQV
DQ
DOUT
NOTE A: DOUT = 00H if selected sector is not protected,
01H if the sector is protected
Figure 21. AC Waveform for Sector-Protect Operation
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251–1443
43
TMS29F800T, TMS29F800B
1048576 BY 8-BIT/ 524288 BY 16-BIT
FLASH MEMORIES
SMJS835B – MAY 1997 – REVISED OCTOBER 1997
sector-unprotect operation
Start
Protect All Sectors
X=1
OE, A9 = VID,
CE and A0 = VIL,
A6 and A1 = VIH
Apply One
10-ms Pulse
PRODUCT PREVIEW
CE, OE, A0 = VIL,
A6 and A1 = VIH,
A9 = VID
Select Sector Address
X = X+1
Read Data
No
No
X = 1000
?
Next Sector
Address
Data = 00H
?
Yes
Yes
Sector Unprotect
Failed
Last
Sector
?
No
Yes
A9 = VIH or VIL
Write Reset Command
End
Figure 22. Sector-Unprotect Algorithm
44
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251–1443
TMS29F800T, TMS29F800B
1048576 BY 8-BIT/ 524288 BY 16-BIT
FLASH MEMORIES
SMJS835B – MAY 1997 – REVISED OCTOBER 1997
sector-unprotect operation (continued)
Sector Address
A18 – A12
VID
tAVQV
A9
tHVT
A6
A1
PRODUCT PREVIEW
A0
CE
VID
OE
tGHVWL
tHVT
tHVT
tWLWH3
WE
tGLQV
DQ
DOUT
NOTE A: DOUT = 00H if selected sector is not protected,
01H if the sector is protected
Figure 23. AC Waveform for Sector-Unprotect Operation
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251–1443
45
TMS29F800T, TMS29F800B
1048576 BY 8-BIT/ 524288 BY 16-BIT
FLASH MEMORIES
SMJS835B – MAY 1997 – REVISED OCTOBER 1997
temporary sector-unprotect operation
Start
RESET = VID
(see Note A)
Perform Erase or
Program Operations
RESET = VIH
PRODUCT PREVIEW
Temporary SectorGroup-Unprotect
Completed (see Note B)
NOTES: A. All protected sectors unprotected
B. All previously protected sectors are protected once again
Figure 24. Temporary Sector-Unprotect Algorithm
12 V
5V
RESET
CE
WE
tVLHT
Program or Erase Command Sequence
RY / BY
Figure 25. Temporary Sector-Unprotect Timing Diagram
46
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251–1443
TMS29F800T, TMS29F800B
1048576 BY 8-BIT/ 524288 BY 16-BIT
FLASH MEMORIES
SMJS835B – MAY 1997 – REVISED OCTOBER 1997
PARAMETER MEASUREMENT INFORMATION
CE
OE
BYTE
tELFL,
tELFH
Data Output
(DQ0 – DQ7)
Data Output (DQ0 – DQ14)
DQ15 Output
DQ15 / A–1
Address Input
PRODUCT PREVIEW
DQ0 – DQ14
tFLQZ
Figure 26. BYTE Timing Diagram for Read Operation
CE
The Falling Edge of the Last WE Signal
WE
BYTE
tSET
(tAS)
tHOLD
(tAH)
Figure 27. BYTE Timing Diagram for Write Operation
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251–1443
47
TMS29F800T, TMS29F800B
1048576 BY 8-BIT/ 524288 BY 16-BIT
FLASH MEMORIES
SMJS835B – MAY 1997 – REVISED OCTOBER 1997
PARAMETER MEASUREMENT INFORMATION
CE
The Rising Edge of the Last WE Signal
WE
Entire Programming or Erase Operations
RY / BY
tBUSY
PRODUCT PREVIEW
Figure 28. RY/ BY Timing Diagram During Program/Erase Operations
48
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251–1443
TMS29F800T, TMS29F800B
1048576 BY 8-BIT/ 524288 BY 16-BIT
FLASH MEMORIES
SMJS835B – MAY 1997 – REVISED OCTOBER 1997
DBJ (R-PDSO-G44)
PLASTIC SMALL-OUTLINE PACKAGE
0,45
0,35
1,27
0,16 M
44
23
13,40
13,20
16,10
15,90
0,15 NOM
22
28,30
28,10
PRODUCT PREVIEW
1
Gage Plane
0,25
0°– 8°
0,95
0,65
Seating Plane
2,63 MAX
0,50 MIN
0,10
4073325 / C 09/95
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion.
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251–1443
49
TMS29F800T, TMS29F800B
1048576 BY 8-BIT/ 524288 BY 16-BIT
FLASH MEMORIES
SMJS835B – MAY 1997 – REVISED OCTOBER 1997
DCD (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
48 PIN SHOWN
1
48
0.050 (1,27)
A
0.012 (0,30)
0.004 (0,10)
0.008 (0,21) M
25
24
PRODUCT PREVIEW
0.728 (18,50)
0.720 (18,30)
0.795 (20,20)
0.780 (19,80)
0.041 (1,05)
0.037 (0,95)
0.006 (0,15)
NOM
0.047 (1,20) MAX
Seating Plane
0.028 (0,70)
0.020 (0,50)
0.004 (0,10)
PINS**
40
48
56
A MAX
0.402
(10,20)
0.476
(12,10)
0.555
(14,10)
A MIN
0.386
(9,80)
0.469
(11,90)
0.516
(13,10)
DIM
0.010 (0,25) NOM
4073307/B 11/96
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
50
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251–1443
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