TNETE211 ThunderLAN TO IEEE 802.12 PHYSICAL MEDIA DEPENDENT INTERFACE FOR 100VG-AnyLAN SPWS019 – MAY 1995 D D D PCI Bus D D D D D D D TNETE211 Physical Media Independent (PMI) Device TNETE100 ThunderLAN Supports Packet Data Transmission and Reception by Providing a 4-Channel Stream Structure at the MII Supports Power Management With Microsoft Advanced Power Management IEEE Standard 1149.1† Test-Access Port (JTAG) Single 5-V Supply 0.8-µm CMOS Technology PCMCIA-Compatible, Small-Footprint Surface-Mount Package 80-Pin JEDEC Plastic Quad Flatpack (PN Suffix) Operating Temperature Range: 0_C to 70_C Physical Media Dependent Device (PMD) 100VGAnyLAN Figure 1. Typical Application description The TNETE211 interfaces the ThunderLAN TNETE100’s IEEE 802.3u media independent interface to an IEEE 802.12 physical media-dependent device for 100VG-AnyLAN operation. The TNETE211 is responsible for quartet channeling, scrambling the transmission data into five-bit data quintets, and encoding the resulting quintets into six-bit (5B6B) symbols. The TNETE211 also adds the preamble, start-frame delimiter, and end-frame delimiter to each channel. Quartet channeling refers to the process of dividing the MAC frame data octets into five-bit data quintets and alloting them sequentially among the four transmission pair channels. The data scrambler alters the five-bit quintet into a randomized bit pattern which is helpful in reducing radio-frequency interference and signal cross talk between channels. The 5B6B symbol encoding transforms the five-bit randomized pattern into predetermined six-bit symbols. This provides a balanced data pattern with an equal number of zeroes and ones for clock transition synchronization for receive circuitry. This symbol encoding also has the added benefit of being an error-checking mechanism. Compliant with IEEE Standard 1149.1-1990 (JTAG), the TNETE211 provides a five-pin test-access port that is used for boundary-scan testing. The TNETE211 is available in an 80-pin plastic quad flat package. † IEEE Standard 1149.1–1990, IEEE Standard Test Access Port and Boundary-Scan Architecture ThunderLAN is a trademark of Texas Instruments Incorporated. Microsoft is a trademark of Microsoft Corporation. Copyright 1995, Texas Instruments Incorporated ADVANCE INFORMATION concerns new products in the sampling or preproduction phase of development. Characteristic data and other specifications are subject to change without notice. • POST OFFICE BOX 655303 DALLAS, TEXAS 75265 POST OFFICE BOX 1443 HOUSTON, TEXAS 77251–1443 • 1 ADVANCE INFORMATION D D The PCI Local Bus Specification, Revision 2.0, should be used as a reference with this document. The TNETE211 Interfaces the ThunderLAN (TNETE100) Media Independent Interface (MII) to a 100VG-AnyLAN IEEE 802.12 Physical Media Dependent (PMD) Interface Device Single Consistent Driver Interface for 100VG Architectures Industry-Standard Interface to Multiple IEEE 802.12-Compliant PMD Devices Supports the Control Signaling Between the Medium Access Control (MAC) or Repeater MAC (RMAC) and the PMD Device TNETE211 ThunderLAN TO IEEE 802.12 PHYSICAL MEDIA DEPENDENT INTERFACE FOR 100VG-AnyLAN SPWS019 – MAY 1995 CLK VSS PRLSREN PTLSWEN PRXEN TDI TMAN1 TMAN0 TRST DEVSEL4 DEVSEL3 DEVSEL2 DEVSEL1 DEVSEL0 VDD TMS TCLK VSS TDO VDD pin assignments 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 ADVANCE INFORMATION MRST VSS MDIO VSS MDCLK VDD MRXER MRXDV MRXD3 MRXD2 MRXD1 MRXD0 VSS MRCLK VSS MCRS MCOL VDD MTXER MTXEN 1 60 2 59 3 58 4 57 5 56 6 55 7 54 8 53 9 52 10 51 11 50 12 49 13 48 14 47 15 46 16 45 17 44 18 43 19 42 20 41 2 • PTLS2 VDD PRLS0 PRLS1 CONFIG0 CONFIG1 CONFIG2 CONFIG3 VDD PMRST V SS PTLS0 PTLS1 MTXD1 MTXD0 V SS MTCLK V SS MTXD3 MTXD2 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 POST OFFICE BOX 655303 DALLAS, TEXAS 75265 POST OFFICE BOX 1443 HOUSTON, TEXAS 77251–1443 • PTXEN VSS POSCEN VDD PTXD3 PTXD2 PTXD1 PTXD0 VSS PRXD3 PRXD2 PRXD1 PRXD0 VSS PRXCLK VDD PRLSDIR VSS PRLS3 PRLS2 TNETE211 ThunderLAN TO IEEE 802.12 PHYSICAL MEDIA DEPENDENT INTERFACE FOR 100VG-AnyLAN SPWS019 – MAY 1995 functional block diagram Scramblers/ Descramblers MRST MDIO MDCLK 5 5 PMRST PTLS[0–2] 6 MRXER MRXDV PRLS[0–3] MRCLK MCRS PRLSDIR MRXD[0–3] 5 6 PRXCLK MII Interface Logic PMD Interface Logic MCOL MTXER MTXEN 5 5 PRXD[0–3] PTXD[0–3] 6 ADVANCE INFORMATION 5 POSCEN MTXD[0–3] PTXEN MTCLK PRXEN 5 5 PTLSWEN 6 PRLSREN CLK CONFIG[0–3] 5B6B Encoders/ Decoders DEVSEL[0–4] Configuration Port TRST IEEE 1149 TestAccess Port TMAN[0–1] TDI TDO TCLK TMS • POST OFFICE BOX 655303 DALLAS, TEXAS 75265 POST OFFICE BOX 1443 HOUSTON, TEXAS 77251–1443 • 3 TNETE211 ThunderLAN TO IEEE 802.12 PHYSICAL MEDIA DEPENDENT INTERFACE FOR 100VG-AnyLAN SPWS019 – MAY 1995 Pin Functions Following is a list of TNETE211 physical media independent (PMI) pins and their functions. Assignment of pin numbers follows the order necessary to allow ThunderLAN and IEEE 802.12-compliant PMD devices to be laid out without any traces crossing. Pin names use the convention of indicating active low signals with an overbar. All ThunderLAN signals begin with an M (for MII). All manufacturing test signals begin with a T (for Test). All network interface signals begin with a P (for Physical Media Dependent). PIN NAME NO. TYPE† DESCRIPTION PHYSICAL MEDIA INDEPENDENT INTERFACE PINS (DEMAND-PRIORITY MODE) ADVANCE INFORMATION MRST 1 I MII reset. MRST resets signal to the PMD front end (active low). MDIO 3 I/O MDCLK 5 I Management data clock. MDCLK is the serial management interface to PMD chip. MRXER 7 O Receive error. MRXER indicates reception of a coding error on received data. MRXDV 8 O Receive data valid. MRXDV indicates data on MRXD[0–3] is valid. MRXD3 MRXD2 MRXD1 MRXD0 9 10 11 12 O Receive data. MRXD[0–3] represents the nibble receive data from the PMD front end. The PMI indicates the priority of the incoming frames on these pins on the cycle before the assertion of MRXDV (the cycle before frame reception begins). MRXD1 indicates the transmission priority of the received frame. A value of zero indicates normal transmission, a value of one indicates priority transmission. Data on these pins is always synchronous to MRCLK. MRCLK 14 O Receive clock. MRCLK is the receive clock source from the PMI front end. MCRS 16 O Carrier sense. MCRS is not used in VG operation, but is connected to the TNETE100 MII for completeness. Management data I / O. MDIO is the serial management interface to PMD chip. MCOL 17 O Collision sense. MCOL indicates that the PMI is transmitting on the physical media. • MCOL (active low) is used to acknowledge a transmission request. TNETE100 must begin frame transmission 50 MTCLK cycles after the assertion (low) of MCOL. MCOL is held asserted low until the PMI has completed all transmission tasks. MTXER 19 I Transmit error. MTXER allows coding errors to be propagated across the MII. MTXEN 20 I Transmit enable. MTXEN indicates valid transmit data on MTXD[0 – 3]. MTXD3 MTXD2 MTXD1 MTXD0 21 22 23 24 I Transmit data. MTXD[0–3] represents the nibble transmit data from TNETE100; when MTXEN is asserted, these pins carry data transmissions. When MTXEN is not asserted (frame transmission not in progress), these pins carry control information. • MTXD0 asserted (high) indicates TNETE100 is requesting frame transmission. • MTXD1 indicates the transmission priority required. A value of zero indicates normal transmission; a value of one indicates priority transmission. Data/control on these pins is always synchronous to MTCLK. MTCLK 26 O Transmit clock. MTCLK is the transmit clock source from the PMI front end. Used to clock transmit and control data into the PMI device. † I = input, O = output, and I / O = 3-state input / output 4 • POST OFFICE BOX 655303 DALLAS, TEXAS 75265 POST OFFICE BOX 1443 HOUSTON, TEXAS 77251–1443 • TNETE211 ThunderLAN TO IEEE 802.12 PHYSICAL MEDIA DEPENDENT INTERFACE FOR 100VG-AnyLAN SPWS019 – MAY 1995 Pin Functions (Continued) PIN NAME NO. TYPE† DESCRIPTION CONFIGURATION PINS (WIRE TYPE) CONFIG0 CONFIG1 CONFIG2 CONFIG3 28 29 30 31 I Configuration. CONFIG[0–3] indicate the current wire configuration of the PMI. PMRST 33 O PMD reset/detect. PMRST, when seen low, resets the PMD. PTLS0 PTLS1 PTLS2 35 36 37 O Transmit line status. The PTLS[0–2] pins are used to set the current transmit line state. PRLS0 PRLS1 PRLS2 PRLS3 39 40 41 42 I Receive line state. The PRLS[0–3] pins are used to determine the current receive-line state from the PMD. PRLSDIR 44 I PMD RLS direct. When the PRLSDIR pin is asserted high, this pin allows the TNETE211 PMD pins to directly connect to the IEEE 802.12 MII interface. When low, this pin allows the TNETE211 PMD pins to directly connect to the AT&T ATT2X01. PRXCLK 46 I Receive data clock. PRXCLK is the receive data clock reference. PRXD0 PRXD1 PRXD2 PRXD3 48 49 50 51 I Receive data. PRXD[0–3] are used to transfer the data streams received from the PMD. PTXD0 PTXD1 PTXD2 PTXD3 53 54 55 56 O Transmit data. PTXD0[0–3] transmit data to the PMD device. POSCEN 58 O Oscillator enable. POSCEN is used to enable the TNET211 30-MHz oscillator. When POSCEN is high, the oscillator is driven to the TNETE211. When POSCEN is low, the oscillator is disabled. The POSCEN is mainly used for power-down functions. PTXEN 60 O Transmit enable. PTXEN indicates valid data on the PTXD[0–3] pins. PRXEN 61 O Receive enable. PRXEN causes the PMD to drive the received data to the PRXD[0–3] pins. PTLSWEN 62 O Transmit line state write enable. PTLSWEN indicates when the PTLS[0–2] pins are valid. PRLSREN 63 O Receive line state read enable. PRLSREN indicates when the PRLS[0–3] pins are valid. CLK 65 I Main clock. CLK is the 30-MHz clock pin used to drive all internal transmit and line state control functions. ADVANCE INFORMATION PHYSICAL MEDIA DEPENDENT (PMD) PINS (PINS CONNECTING TO THE IEEE 802.12-COMPLIANT PMD DEVICE) DEVSEL0 67 DEVSEL1 68 Device select. DEVSEL[0–4] are used for PMI device selection. The device number in the MII is DEVSEL2 69 I compared with these pins for the MII read-and-write operations. DEVSEL3 70 DEVSEL4 71 † I = input, O = output, I / O = 3-state input / output • POST OFFICE BOX 655303 DALLAS, TEXAS 75265 POST OFFICE BOX 1443 HOUSTON, TEXAS 77251–1443 • 5 TNETE211 ThunderLAN TO IEEE 802.12 PHYSICAL MEDIA DEPENDENT INTERFACE FOR 100VG-AnyLAN SPWS019 – MAY 1995 Pin Functions (Continued) PIN NAME NO. TYPE† DESCRIPTION TEST PORT TRST 72 I Test reset. TRST is used for asynchronous reset of the test port controller (optional). ADVANCE INFORMATION TMAN0 TMAN1 73 74 I Manufacture test. TMAN[0–1] are used for manufacture test functions. TMAN0 TMAN1 Description 0 0 Unit in place. All internal pullup resistors on all input pins are disabled. 0 1 Reserved 1 0 Reserved 1 1 Normal operation. All input pins’ internal pullup resistors are enabled. TDI 75 I Test data input. TDI serially shifts test data and test instructions into the device during operation of the test port. TDO 77 O Test data output. TDO serially shifts test data and test instructions out of the device during operation of the test port. TCLK 79 I Test clock. TCLK clocks state information and test data into and out of the device during operation of the test port. TMS 80 I Test mode select. TMS controls the state of the test port controller within the TNETE211. POWER VSS 2, 4, 13, 15, 25, 27, 34, 43, 47, 52, 59, 64, 78 PWR Ground pins VDD 6, 18, 32, 38, 45, 57, 66, 76 PWR Supply voltage † I = input, O = output, PWR = power 6 • POST OFFICE BOX 655303 DALLAS, TEXAS 75265 POST OFFICE BOX 1443 HOUSTON, TEXAS 77251–1443 • TNETE211 ThunderLAN TO IEEE 802.12 PHYSICAL MEDIA DEPENDENT INTERFACE FOR 100VG-AnyLAN SPWS019 – MAY 1995 absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage range, VDD (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.5 V to 7 V Input voltage range (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.5 V to 7 V Output voltage range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.5 V to 7 V Maximum operating case temperature, TC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95°C Operating free-air temperature range, TA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 70°C Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 65°C to 150°C † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTE 1: Voltage values are with respect to VSS, and all VSS pins should be routed so as to minimize inductance to system ground. recommended operating conditions VDD Supply voltage (5 V only) VSS Ground MIN NOM MAX UNIT 4.75 5 5.25 V VDD + 0.3 0.8 V High-level input voltage 2 IOH IOL High-level output current TTL outputs –4 mA Low-level output current (see Note 3) TTL outputs 4 mA Low-level input voltage, TTL-level signal (see Note 2) – 0.3 V TA Operating free-air temperature 0 70 °C NOTES: 2. The algebraic convention, where the more negative (less positive) limit is designated as a minimum, is used for logic-voltage levels only. 3. Output current of 2 mA is sufficient to drive five low-power Schottky TTL loads or ten advanced low-power Schottky TTL loads (worst case). electrical characteristics over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) TEST CONDITIONS ‡ PARAMETER VOH High-level output voltage, TTL-level signal VOL Low-level output voltage, TTL-level signal VDD = MIN, VDD = MAX, IOH = MAX IOL = MAX IO High impedance output current High-impedance VDD = MIN, VDD = MIN, VO = VDD VO = 0 V II IDD Input current Supply current VI = VSS to VDD VDD = MAX Ci Input capacitance, any input f = 1 MHz, MIN Others at 0 V Co Output capacitance, any output or input / output f = 1 MHz, Others at 0 V ‡ For conditions shown as MIN / MAX, use the appropriate value specified under the “recommended operating conditions”. • POST OFFICE BOX 655303 DALLAS, TEXAS 75265 POST OFFICE BOX 1443 HOUSTON, TEXAS 77251–1443 • MAX 2.4 UNIT V 0.5 10 – 10 V µA "1 µA 400 mA 10 pF 10 pF 7 ADVANCE INFORMATION 0 VIH VIL TNETE211 ThunderLAN TO IEEE 802.12 PHYSICAL MEDIA DEPENDENT INTERFACE FOR 100VG-AnyLAN SPWS019 – MAY 1995 PARAMETER MEASUREMENT INFORMATION Outputs are driven to a minimum high-logic level of 2.4 V and to a maximum low-logic level of 0.6 V. These levels are compatible with TTL devices. Output transition times are specified as follows: For a high-to-low transition on either an input or output signal, the level at which the signal is said to be no longer high is 2 V and the level at which the signal is said to be low is 0.8 V. For a low-to-high transition, the level at which the signal is said to be no longer low is 0.8 V and the level at which the signal is said to be high is 2 V, as shown below. The rise and fall times are not specified but are assumed to be those of standard TTL devices, which are typically 1.5 ns. 2 V (high) 0.8 V (low) ADVANCE INFORMATION test measurement The test-load circuit shown in Figure 2 represents the programmable load of the tester pin electronics that are used to verify timing parameters of TNETE211 output signals. IOL Test Point VLOAD CL TTL Output Under Test IOH Where: IOL IOH VLOAD CL = Refer to IOL in recommended operating conditions = Refer to IOH in recommended operating conditions = 1.5 V, typical dc-level verification or 0.7 V, typical timing verification = 18 pF, typical load-circuit capacitance Figure 2. Test-Load Circuit 8 • POST OFFICE BOX 655303 DALLAS, TEXAS 75265 POST OFFICE BOX 1443 HOUSTON, TEXAS 77251–1443 • TNETE211 ThunderLAN TO IEEE 802.12 PHYSICAL MEDIA DEPENDENT INTERFACE FOR 100VG-AnyLAN SPWS019 – MAY 1995 MII receive timing requirements† PARAMETER tsu(MTx pins) th(MTx pins) MIN MAX UNIT Setup time of inputs MTXD[0–3], MTXEN, MTXER (see Note 4) 10 ns Hold time of inputs MTXD[0–3], MTXEN, MTXER (see Note 4) >0 ns MII transmit switching characteristics† PARAMETER MIN MAX UNIT ADVANCE INFORMATION td(MRx pins) MRCLK to output delay for MRXD[0–3], MRXDV, and MRXER (see Note 5) 0 15 ns † Both MCRS and MCOL are driven asynchronously by the PMI. NOTES: 4. MTXD[0–3] is driven by the reconciliation sublayer synchronous to the MTCLK. MTXEN is asserted and deasserted by the reconciliation sublayer synchronous to the MTCLK rising edge. MTXER is driven synchronous to the rising edge of MTCLK. 5. MRXD[0–3] is driven by the PMI on the falling edge of MRCLK. It is sampled by the reconciliation sublayer synchronous to the edge of MRCLK. MRXD[0–3] timing must be met during clock periods where MRXDV is asserted. MRXDV is asserted and deasserted by the PMI on the falling edge of MRCLK. It is sampled by the reconciliation sublayer synchronous to the rising edge of MRCLK. MRXER is driven by the PMI on the falling edge of MRCLK. It is sampled by the reconciliation sublayer synchronous to the rising edge of MRCLK. MRXER timing must be met during clock periods when MRXDV is asserted. MRCLK MRXD[0–3], MRXDV, MRXER td(MRx pins) MTCLK MTXD[0–3], MTXEN, MTXER tsu(MTx pins) th(MTx pins) Figure 3. MII Transmit and Receive Timing • POST OFFICE BOX 655303 DALLAS, TEXAS 75265 POST OFFICE BOX 1443 HOUSTON, TEXAS 77251–1443 • 9 TNETE211 ThunderLAN TO IEEE 802.12 PHYSICAL MEDIA DEPENDENT INTERFACE FOR 100VG-AnyLAN SPWS019 – MAY 1995 MDIO timing requirements td(MDCLKH-MDIOV) Delay time, MDIO valid from MDCLK high (see Note 6) MIN MAX 0 25 MIN MAX UNIT ns MDIO switching characteristics PARAMETER tsu(MDIOV-MDCLKH) Setup time, MDIO valid to MDCLK high (see Note 7) th(MDCLKH-MDIOX) Hold time, MDCLK high to MDIO changing (see Note 7) ns 15 ns NOTES: 6. When the MDIO signal is sourced by the PMI, it is sampled by TNETE100 synchronous to the rising edge of MDCLK. 7. MDIO is a bidirectional signal that can be sourced by TNETE100 or the PMI. MDCLK ADVANCE INFORMATION MDIO td(MDCLKH-MDIOV) Figure 4. Management Data I/O Timing (Sourced by PMI) MDCLK MDIO tsu(MDIOV-MDCLKH) th(MDCLKH-MDIOX) Figure 5. Management Data I/O Timing [Sourced by Station Management Entity (STA)] 10 • POST OFFICE BOX 655303 DALLAS, TEXAS 75265 POST OFFICE BOX 1443 HOUSTON, TEXAS 77251–1443 • UNIT 15 TNETE211 ThunderLAN TO IEEE 802.12 PHYSICAL MEDIA DEPENDENT INTERFACE FOR 100VG-AnyLAN SPWS019 – MAY 1995 PRXD timing requirements (see Figure 6) PARAMETER MIN MAX UNIT td(CLK-PRXENL) td(CLK-PRXENH) Delay time, CLK to PRXEN low >0 15 ns Delay time, CLK to PRXEN high >0 15 ns th(PRXCLK-PRXD) tsu(PRXD-PRXCLK) Hold time, PRXCLK to PRXD changing >0 ns Setup time, PRXD valid to PRXCLK 10 ns CLK td(CLK-PRXENL) td(CLK-PRXENH) ADVANCE INFORMATION PRXEN PRXCLK th(PRXCLK-PRXD) tsu(PRXD-PRXCLK) PRXD[0–3] Figure 6. Receive Data Timing • POST OFFICE BOX 655303 DALLAS, TEXAS 75265 POST OFFICE BOX 1443 HOUSTON, TEXAS 77251–1443 • 11 TNETE211 ThunderLAN TO IEEE 802.12 PHYSICAL MEDIA DEPENDENT INTERFACE FOR 100VG-AnyLAN SPWS019 – MAY 1995 TDATA timing requirements (see Figure 7) PARAMETER MIN MAX UNIT td(CLK-PTXENL) td(CLK-PTXENH) Delay time, CLK to PTXEN low >0 15 ns Delay time, CLK to PTXEN high >0 15 ns td(CLK-PTXDV) Delay time, CLK to PTXD valid >0 15 ns MIN MAX CLK td(CLK-PTXENH) td(CLK-PTXENL) PTXEN ADVANCE INFORMATION td(CLK-PTXDV) PTXD[0–3] Figure 7. Transmit Data Timing PRLS timing requirements (see Figure 8) PARAMETER UNIT td(CLK-PRLSRENL) td(CLK-PRLSRENH) Delay time, CLK to PRLSREN low >0 15 ns Delay time, CLK to PRLSREN high >0 15 ns tsu(PRLSV-CLK) Setup time, PRLS valid to rising edge of CLK 10 ns th(CLK-PRLSX) Hold time, CLK to PRLS changing >0 ns CLK td(CLK-PRLSRENH) td(CLK-PRLSRENL) PRLSREN tsu(PRLSV-CLK) th(CLK-PRLSX) PRLS[0–3] Figure 8. PRLS Timing 12 • POST OFFICE BOX 655303 DALLAS, TEXAS 75265 POST OFFICE BOX 1443 HOUSTON, TEXAS 77251–1443 • TNETE211 ThunderLAN TO IEEE 802.12 PHYSICAL MEDIA DEPENDENT INTERFACE FOR 100VG-AnyLAN SPWS019 – MAY 1995 TLS timing requirements (see Figure 9) PARAMETER td(CLK-PTLSWENL) td(CLK-PTLSV) MIN MAX UNIT Delay time, CLK to PTLSWEN low >0 15 ns Delay time, CLK to PTLS[0–2] valid >0 15 ns CLK td(CLK-PTLSWENL) PTLSWEN td(CLK-PTLSV) ADVANCE INFORMATION PTLS[0–2] Figure 9. TLS Timing • POST OFFICE BOX 655303 DALLAS, TEXAS 75265 POST OFFICE BOX 1443 HOUSTON, TEXAS 77251–1443 • 13 TNETE211 ThunderLAN TO IEEE 802.12 PHYSICAL MEDIA DEPENDENT INTERFACE FOR 100VG-AnyLAN SPWS019 – MAY 1995 MECHANICAL DATA PN (S-PQFP-G80) PLASTIC QUAD FLATPACK 0,27 0,17 0,50 0,08 M 41 60 ADVANCE INFORMATION 61 40 80 21 0,13 NOM 1 20 Gage Plane 9,50 TYP 0,25 12,20 SQ 11,80 14,20 SQ 13,80 0,05 MIN 0°– 7° 0,75 0,45 1,45 1,35 Seating Plane 0,08 1,60 MAX 4040135 / B10/94 NOTES: A. All linear dimensions are in millimeters. B. This drawing is subject to change without notice. C. Falls within JEDEC MO-136 14 • POST OFFICE BOX 655303 DALLAS, TEXAS 75265 POST OFFICE BOX 1443 HOUSTON, TEXAS 77251–1443 • IMPORTANT NOTICE Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgement, including those pertaining to warranty, patent infringement, and limitation of liability. TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in accordance with TI’s standard warranty. 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