TI TPA2012D2RTJR

TPA2012D2
YZH
RTJ
www.ti.com
SLOS438C – DECEMBER 2004 – REVISED MARCH 2007
2.1 W/CH STEREO FILTER-FREE CLASS-D AUDIO POWER AMPLIFIER
FEATURES
APPLICATIONS
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(1)
Output Power By Package:
– QFN:
– 2.1 W/Ch Into 4 Ω at 5 V
– 1.4 W/Ch Into 8 Ω at 5 V
– 720 mW/Ch Into 8 Ω at 3.6 V
– WCSP:
– 1.2 W/Ch Into 4 Ω at 5 V(1)
– 1.3 W/Ch Into 8 Ω at 5 V
– 720 mW/Ch Into 8 Ω at 3.6 V
Only Two External Components Required
Power Supply Range: 2.5 V to 5.5 V
Independent Shutdown Control for Each
Channel
Selectable Gain of 6, 12, 18, and 24 dB
Internal Pulldown Resistor On Shutdown Pins
High PSRR: 77 dB at 217 Hz
Fast Startup Time (3.5 ms)
Low Supply Current
Low Shutdown Current
Short-Circuit and Thermal Protection
Space Saving Packages
– 2,01 mm X 2,01 mm NanoFree™ WCSP
(YZH)
– 4 mm X 4 mm Thin QFN (RTJ) with
PowerPAD™
Wireless or Cellular Handsets and PDAs
Portable DVD Player
Notebook PC
Portable Radio
Portable Gaming
Educational Toys
USB Speakers
DESCRIPTION
The TPA2012D2 is a stereo, filter-free, Class-D
audio amplifier (class-D amp) available in a WCSP,
QFN, or PWP package. The TPA2012D2 only
requires two external components for operation.
The TPA2012D2 features independent shutdown
controls for each channel. The gain can be selected
to 6, 12, 18, or 24 dB utilizing the G0 and G1 gain
select pins. High PSRR and differential architecture
provide increased immunity to noise and RF
rectification. In addition to these features, a fast
startup time and small package size make the
TPA2012D2 class-D amp an ideal choice for both
cellular handsets and PDAs.
Thermally limited
2.50
PO − Output Power − W
WCSP Thermally Limited Region
VDD = 2.5 V, 1%
2
VDD = 2.5 V, 10%
VDD = 3.6 V, 1%
1.50
VDD = 3.6 V, 10%
VDD = 5 V, 1%
VDD = 3.6 V, 10%
1
0.50
0
4
9
14
19
24
29
34
RL − Load Resistance − W
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
NanoFree, PowerPAD are trademarks of Texas Instruments.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2004–2007, Texas Instruments Incorporated
TPA2012D2
www.ti.com
SLOS438C – DECEMBER 2004 – REVISED MARCH 2007
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
DESCRIPTION (CONTINUED)
The TPA2012D2 is capable of driving 1.4 W/Ch at 5 V or 720 mW/Ch at 3.6 V into 8 Ω. The TPA2012D2 is also
capable of driving 4 Ω. The TPA2012D2 is thermally limited in WCSP and may not achieve 2.1 W/Ch for 4 Ω.
The maximum output power in the WCSP is determined by the ability of the circuit board to remove heat. The
output power versus load resistance graph below shows thermally limited region of the WCSP in relation to the
QFN package. The TPA2012D2 provides thermal and short circuit protection.
AVAILABLE OPTIONS
TA
–40°C to 85°C
PACKAGE
PART NUMBER
SYMBOL
2 mm x 2 mm, 16-ball WCSP (YZH)
TPA2012D2YZH
AKR
4 mm x 4 mm, 20-pin QFN (RTJ)
TPA2012D2RTJ
AKS
ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature (unless otherwise noted) (1)
VSS
Supply voltage, AVDD, PVDD
VI
Input voltage
VALUE
UNIT
In active mode
–0.3 to 6.0
V
In shutdown mode
–0.3 to 7.0
V
–0.3 to VDD + 0.3
V
Continuous total power dissipation
See Dissipation Rating Table
TA
Operating free-air temperature range
–40 to 85
°C
TJ
Operating junction temperature range
–40 to 150
°C
Tstg
Storage temperature range
–65 to 85
°C
(1)
Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
DISSIPATION RATING TABLE
(1)
PACKAGE
TA = 25°C
POWER RATING (1)
DERATING
FACTOR
TA = 75°C
POWER RATING
TA = 85°C
POWER RATING
RTJ
5.2 W
41.6 mW/°C
3.12 W
2.7 W
YZH
1.2 W
9.12 mW/°C
690 mW
600 mW
This data was taken using 2 oz trace and copper pad that is soldered directly to a JEDEC standard 4-layer 3 in × 3 in PCB.
RECOMMENDED OPERATING CONDITIONS
2
MIN
MAX
VSS
Supply voltage
AVDD, PVDD
2.5
5.5
VIH
High-level input voltage
SDL, SDR, G0, G1
1.3
VIL
Low-level input voltage
SDL, SDR, G0, G1
TA
Operating free-air temperature
÷40
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UNIT
V
V
0.35
V
85
°C
TPA2012D2
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SLOS438C – DECEMBER 2004 – REVISED MARCH 2007
ELECTRICAL CHARACTERISTICS
TA = 25°C (unless otherwise noted)
PARAMETER
TEST CONDITIONS
|VOO|
Output offset voltage (measured differentially)
Inputs ac grounded, AV = 6 dB,
VDD = 2.5 to 5.5 V
PSRR
Power supply rejection ratio
VDD = 2.5 to 5.5 V
Vicm
Common-mode input voltage
MIN
TYP
MAX
5
25
mV
–75
0.5
UNIT
–55
dB
VDD–0.8
V
–50
dB
CMRR
Common-mode rejection ration
Inputs shorted together,
VDD = 2.5 to 5.5 V
|IIH|
High-level input current
VDD = 5.5 V, VI = VDD
50
µA
|IIL|
Low-level input current
VDD = 5.5 V, VI = 0 V
5
µA
IDD
Supply current
–69
VDD = 5.5 V, No load or output filter
6
9
VDD = 3.6 V, No load or output filter
5
7.5
VDD = 2.5 V, No load or output filter
4
6
Shutdown mode
rDS(on)
f(sw)
Static drain-source on-state resistance
1.5
VDD = 5.5 V
500
VDD = 3.6 V
570
VDD = 2.5 V
700
Output impedance in shutdown mode
V(SDR, SDL)= 0.35 V
Switching frequency
VDD = 2.5 V to 5.5 V
G0, G1 = 0.35 V
Closed-loop voltage gain
300
µA
mΩ
2
250
mA
kΩ
350
5.5
6
6.5
G0 = VDD, G1 = 0.35 V
11.5
12
12.5
G0 = 0.35 V, G1 = VDD
17.5
18
18.5
G0, G1 = VDD
23.5
24
24.5
kHz
dB
OPERATING CHARACTERISTICS
TA = 25°C, RL = 8 Ω (unless otherwise noted)
PARAMETER
PO
Output power (per channel)
TEST CONDITIONS
RL = 8 Ω
RL = 4 Ω
THD+N
Total harmonic distortion plus noise
Channel crosstalk
kSVR
Supply ripple rejection ratio
CMRR
Common mode rejection ratio
Input impedance
Vn
MIN
TYP
VDD = 5.0 V, f = 1 kHz, THD = 10%
1.4
VDD = 3.6 V, f = 1 kHz, THD = 10%
0.72
VDD = 5.0 V, f = 1 kHz, THD = 10%
2.1
PO = 1 W, VDD = 5 V, AV = 6 dB,
f = 1 kHz
0.14%
PO = 0.5 W, VDD = 5 V, AV = 6 dB,
f = 1 kHz
0.11%
f = 1 kHz
–85
VDD = 5 V, AV = 6 dB,
f = 217 Hz
–77
VDD = 3.6 V, AV = 6 dB,
f = 217 Hz
–73
VDD = 3.6 V, VIC = 1 Vpp,
f = 217 Hz
–69
Av = 6 dB
28.1
Av = 12 dB
17.3
Av = 18 dB
9.8
Av = 24 dB
5.2
Start-up time from shutdown
VDD = 3.6 V
Output voltage noise
VDD = 3.6 V, f = 20 to 20 kHz,
Inputs are ac grounded, AV = 6 dB
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3.5
No weighting
35
A weighting
27
MAX
UNIT
W
dB
dB
dB
kΩ
ms
µV
3
TPA2012D2
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SLOS438C – DECEMBER 2004 – REVISED MARCH 2007
BLOCK DIAGRAM
V DD
to Battery
CS
INR+
OUTR+
Gain
Adjust
Right Input
PWM
H−
Bridge
OUTR−
INR−
Internal
Oscillator
GND
OUTL+
INL+
Gain
Adjust
Left Input
PWM
H−
Bridge
OUTL−
INL−
G0
G1
SDR
300 k
Bias
Circuitry
Short−Circuit
Protection
SDL
300 k
4
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Gain
V/V
dB
G1
G0
0
0
2
6
0
1
4
12
1
0
8
18
1
1
16
24
TPA2012D2
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SLOS438C – DECEMBER 2004 – REVISED MARCH 2007
Terminal Functions
TERMINAL
NAME
I/O
DESCRIPTION
QFN
WCSP
INR+
16
D1
I
Right channel positive input
INR-
17
C1
I
Right channel negative input
INL+
20
A1
I
Left channel positive input
INL-
19
B1
I
Left channel negative input
SDR
8
B3
I
Right channel shutdown terminal (active low)
SDL
7
B4
I
Left channel shutdown terminal (active low)
G0
15
C2
I
Gain select (LSB)
G1
1
B2
I
Gain select (MSB)
3, 13
A2
I
Power supply (Must be same voltage as AVDD)
AVDD
9
D2
I
Analog supply (Must be same voltage as PVDD)
PGND
4, 12
C4
I
Power ground
AGND
18
C3
I
Analog ground
OUTR+
14
D3
O
Right channel positive differential output
OUTR-
11
D4
O
Right channel negative differential output
OUTL+
2
A3
O
Left channel positive differential output
OUTL-
5
A4
O
Left channel negative differential output
6, 10
N/A
PVDD
NC
No internal connection
Thermal Pad
Connect the thermal pad of QFN or PWP package to PCB GND
B1
INL−
G1
SDR
SDL
C1
INR−
G0
AGND
PGND
D1
INR+
AVDD
OUTR+
OUTR−
16
INR+
OUTL−
17
G0
1
G1
2
OUTL+
OUTR+ 14
3
PVDD
PVDD
13
4
PGND
PGND
12
5
OUTL−
OUTR− 11
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NC
OUTL+
18
INR−
PVDD
19
AVDD
INL+
20
AGND
A4
SDR
A3
SDL
A2
NC
A1
INL−
RTJ PIN OUT
TOP VIEW
INL+
WCSP PIN OUT
TOP VIEW
6
7
8
9
10
15
5
TPA2012D2
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SLOS438C – DECEMBER 2004 – REVISED MARCH 2007
TEST SET-UP FOR GRAPHS (per channel)
CI
TPA2012D2
RI
IN+
+
Measurement
Output
CI
-
OUT+
+
Load
RI
INVDD
+
OUT-
30 kHz
Low Pass
Filter
Measurement
Input
-
GND
1 mF
VDD
-
6
(1)
CI was Shorted for any Common-Mode input voltage measurement.
(2)
A 33-µH inductor was placed in series with the load resistor to emulate a small speaker for efficiency measurements.
(3)
The 30–kHz low–pass filter is required even if the analyzer has an internal low–pass filter. An RC low pass filter (100
Ω, 47 nF) is used on each output for the data sheet graphs.
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TPA2012D2
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SLOS438C – DECEMBER 2004 – REVISED MARCH 2007
TYPICAL CHARACTERISTICS
TOTAL HARMONIC DISTORTION
vs
OUTPUT POWER
1
3.6 V
0.1
5V
0.1
PO − Output Power − W
1
2.5 V
1
3.6 V
0.1
5V
0.1
PO − Output Power − W
RL = 4 ,
f = 1 kHz,
AV 24 dB
2.5 V
1
3.6 V
0.1
5V
0.01
0.01
3
0.1
1
4
PO − Output Power − W
Figure 3.
TOTAL HARMONIC DISTORTION
vs
OUTPUT POWER
TOTAL HARMONIC DISTORTION
vs
FREQUENCY
TOTAL HARMONIC DISTORTION
vs
FREQUENCY
1
1
3.6 V
0.1
5V
0.1
1
1
VDD = 2.5 V,
RL = 4 W,
CI = 1 mF,
AV = 6 dB
350 mW
0.1
240 mW
0.01
20
4
120 mW
100
1k
f − Frequency − Hz
PO − Output Power − W
THD+N − Total Harmonic Distortion + Noise − %
RL = 4 ,
f = 1 kHz,
AV 6 dB
0.01
0.01
VDD = 2.5 V,
RL = 8 W,
CI = 1 mF,
AV = 6 dB
260 mW
0.1
180 mW
0.01
20
10 k 20 k
90 mW
100
1k
f − Frequency − Hz
10 k 20 k
Figure 4.
Figure 5.
Figure 6.
TOTAL HARMONIC DISTORTION
vs
FREQUENCY
TOTAL HARMONIC DISTORTION
vs
FREQUENCY
TOTAL HARMONIC DISTORTION
vs
FREQUENCY
1
1
275 mW
825 mW
0.1
550 mW
100
1k
f − Frequency − Hz
Figure 7.
10 k 20 k
VDD = 3.6 V,
RL = 8 W,
CI = 1 mF,
AV = 6 dB
THD+N − Total Harmonic Distortion + Noise − %
1
VDD = 3.6 V,
RL = 4 W,
CI = 1 mF,
AV = 6 dB
THD+N − Total Harmonic Distortion + Noise − %
THD+N − Total Harmonic Distortion + Noise − %
10
Figure 2.
2.5 V
0.01
20
1
20
Figure 1.
THD+N − Total Harmonic Distortion + Noise − %
THD+N − Total Harmonic Distortion + Noise − %
RL = 8 ,
f = 1 kHz,
AV 6 dB
0.01
0.01
3
20
10
10
THD+N − Total Harmonic Distortion + Noise − %
2.5 V
0.01
0.01
TOTAL HARMONIC DISTORTION
vs
OUTPUT POWER
20
RL = 8 ,
f = 1 kHz,
AV 24 dB
THD+N − Total Harmonic Distortion + Noise − %
THD+N − Total Harmonic Distortion + Noise − %
20
10
TOTAL HARMONIC DISTORTION
vs
OUTPUT POWER
190 mW
560 mW
0.1
375 mW
0.01
20
100
1k
f − Frequency − Hz
10 k 20 k
Figure 8.
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VDD = 5 V,
RL = 4 W,
CI = 1 mF,
AV = 6 dB
550 mW
0.1
1.65 W
1.1 W
0.01
20
100
1k
f − Frequency − Hz
10 k 20 k
Figure 9.
7
TPA2012D2
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SLOS438C – DECEMBER 2004 – REVISED MARCH 2007
TYPICAL CHARACTERISTICS (continued)
TOTAL HARMONIC DISTORTION
vs
FREQUENCY
SUPPLY CURRENT
vs
SHUTDOWN VOLTAGE
6
VDD = 5 V,
RL = 8 W,
CI = 1 mF,
AV = 6 dB
VDD = 5 V
380 mW
5
I DD − Supply Current − mA
THD+N − Total Harmonic Distortion + Noise − %
1
SUPPLY CURRENT
vs
SUPPLY VOLTAGE
1.16 W
0.1
775 mW
VDD = 3.6 V
4
VDD = 2.5 V
3
2
1
0.01
20
100
1k
f − Frequency − Hz
10 k
20 k
0
No Output Filter
0
1
2
3
4
VSD − Shutdown Voltage − V
5
Figure 10.
Figure 11.
Figure 12.
SUPPLY CURRENT
vs
OUTPUT POWER
SUPPLY CURRENT
vs
OUTPUT POWER
CROSSTALK
vs
FREQUENCY
800
0
1200
IDD is for Both Channels
IDD is for Both Channels
700
500
400
300
VDD = 5 V, RL = 8 W, 33 mH
200
600
400
200
0.6
0.8
1
1.2
1.4
1.6
0
PO − Output Power/Channel − W
−60
2.5 V R to L
3.6 V L to R
5 V L to R
3.6 V R to L
5 V R to L
1k
f − Frequency − Hz
Figure 16.
10 k 20 k
PSRR − Power Supply Rejection Ratio − dB
Crosstalk − dB
1k
f − Frequency − Hz
POWER SUPPLY
REJECTION RATIO
vs
FREQUENCY
−100
8
100
POWER SUPPLY
REJECTION RATIO
vs
FREQUENCY
−40
100
2.2
CROSSTALK
vs
FREQUENCY
−30
20
2
Figure 15.
−20
−120
0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8
PO − Output Power/Channel − W
5 V L to R
Figure 14.
RI = 4 W
2.5 V L to R
3.6 V L to R
3.6 V R to L
−140
20
Figure 13.
0
−80
5 V R to L
−120
VDD = 2.5 V, RL = 4 W, 33 mH
−40
−30
Inputs AC, Grounded,
CI = 1 mF,
RI = 4 W,
AV = 6 dB
PSRR − Power Supply Rejection Ratio − dB
0.4
2.5 V L to R
−100
0
0.2
2.5 V R to L
−80
VDD = 3.6 V, RL = 4 W, 33 mH
VDD = 2.5 V, RL = 8 W, 33 mH
0
−60
VDD = 5 V, RL = 4 W, 33 mH
VDD = 3.6 V, RL = 8 W, 33 mH
100
0
−40
800
Crosstalk − dB
I DD − Supply Current − mA
I DD − Supply Current − mA
600
RI = 8 W
−20
1000
−50
VDD = 2.7 V
−60
−70
−80
VDD = 3.6 V
−90
−100
20
VDD = 5 V
100
1k
f − Frequency − Hz
10 k
Figure 17.
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20 k
−40
10 k 20 k
Inputs AC Grounded,
CI = 1 mF,
RI = 8 W,
AV = 6 dB
−50
VDD = 2.7 V
−60
−70
−80
VDD = 3.6 V
−90
VDD = 5 V
−100
20
100
1k
f − Frequency − Hz
Figure 18.
10 k 20 k
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SLOS438C – DECEMBER 2004 – REVISED MARCH 2007
TYPICAL CHARACTERISTICS (continued)
COMMOM-MODE
REJECTION RATIO
vs
COMMON-MODE
INPUT VOLTAGE
COMMON-MODE
REJECTION RATIO
vs
FREQUENCY
−50
−20
VDD = 5.5 V
−40
−60
−80
−55
−60
−65
C1 − High, 3.6 V
C1 − Amp, 512 mV
C1 − Duty, 12%
VDD
200 mV/div
VDD = 3.6 V
0
VIC = 1 VPP,
RL = 8 W,
AV = 6 dB
VDD = 2.5 V
VDD = 3.6 V
VOUT
20 mV/div
VDD = 2.5 V
CMRR − Common-Mode Rejection Ratio − dB
20
CMRR − Common-Mode Rejection Ratio − dB
GSM POWER
SUPPLY REJECTION
vs
TIME
−70
VDD = 5 V
−75
−100
1
2
3
4
5
VICR − Common-Mode Input Voltage Range − V
10 k 20 k
Figure 19.
Figure 20.
Figure 21.
POWER SUPPLY REJECTION
vs
FREQUENCY
SUPLY VOLTAGE
REJECTION RATIO
vs
DC COMMON-MODE VOLTAGE
POWER DISSIPATION
vs
OUTPUT POWER
−20
−20
−40
−40
−60
−60
−80
−80
−100
−100
−120
−120
−140
−140
Output
−160
500
1000
1500
2000
f − Frequency − Hz
0
0
−160
2500
−10
0.7
RL = 8 W,
VIN = 200 mVPP
f = 217 Hz
−20
VDD = 3.6 V
−30
VDD = 5 V
−40
VDD = 2.7 V
−50
−60
−70
Class-AB,
VDD = 3.6 V
0.5
Class-AB,
VDD = 3.6 V
0.4
RL = 8 Ω
QFN
0.2
RL = 8 Ω
Powers are per Channel
0
0
0.5
1
1.5
2
2.5
3
3.5
4
4.5
5
RL = 4 Ω
0.3
0.1
−80
−90
0
RL = 4 Ω
0.6
PD − Power Dissipation − W
CI = 1 mF,
Inputs AC Grounded,
AV = 6 dB
VDD = 3.6 V
Input
k SVR − Supply Voltage Rejection Ratio − dB
0
Supply Signal Ripple − V
1k
f − Frequency − Hz
t − Time − 2 ms/div
Power-Supply Rejection Output − V
0
0
100
20
0.2
0.4
0.6
0.8
1
1.2
1.4
PO − Output Power − W
DC Common Mode Voltage − V
Figure 22.
Figure 23.
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Figure 24.
9
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SLOS438C – DECEMBER 2004 – REVISED MARCH 2007
TYPICAL CHARACTERISTICS (continued)
POWER DISSIPATION
vs
OUTPUT POWER
1.4
EFFICIENCY
vs
OUTPUT POWER
RL = 4 Ω
90
1.2
Class-AB, VDD = 5 V
RL = 8 Ω
RL = 4 Ω
0.6
VDD = 3.6
VDD = 2.5 VV
60
50
40
Class-AB
30
QFN
0.4
VDD = 5 V
70
RL = 8 Ω
0.2
10
Powers are per Channel
0
0
0.5
1
1.5
0
2
2.5
0.5
2
Powers are per Channel
0
2.5
0
0.2
0.4
0.6
0.8
1
EFFICIENCY
vs
OUTPUT POWER
1.4
0.5
Class-AB,
VDD = 3.6 V
RL = 8 Ω
RL = 4 Ω
0.3
WCSP
RL = 8 Ω
0.2
0.8
1
1.2
Class-AB, VDD = 5 V
RL = 8 Ω
0.8
WCSP
0.6
0.4
RL = 8 Ω
PO − Output Power − W
1
1.5
2
WCSP
0
0
0.2
0.6
OUTPUT POWER
vs
SUPPLY VOLTAGE
VDD = 5 V
1.6
PO − Output Power − W
VDD = 3.6 V
60
50
40
Class-AB, VDD = 5 V
30
WCSP
20
RL = 4 W,
THD+N = 10%
1.8
80
RL = 4 W,
THD+N = 1%
1.4
1.2
RL = 8 W,
THD+N = 10%
1
0.8
0.6
0.4
10
RL = 8 W,
THD+N = 1%
0.2
0
0.2
0.4
0.6
0.8
1
PO − Output Power − W
1.2
1.4
0
2.5
0.8
1
Figure 30.
2
RL = 8 Ω
70
0.4
1.2
PO − Output Power − W
Figure 29.
90
Efficiency − %
Class-AB, VDD = 5 V
10
2.5
EFFICIENCY
vs
OUTPUT POWER
0
40
PO − Output Power − W
Figure 28.
100
50
20
Powers are per Channel
0.5
VDD = 5 V
60
30
RL = 4 Ω
0
1.4
VDD = 3.6 V
70
0
0.6
80
1
0.2
0.4
RL = 4 Ω
90
RL = 4 Ω
Powers are per Channel
0.2
1.4
100
Class-AB, VDD = 5 V
1.2
1.2
PO − Output Power − W
POWER DISSIPATION
vs
OUTPUT POWER
PD − Power Dissipation − W
PD − Power Dissipation − W
10
POWER DISSIPATION
vs
OUTPUT POWER
0.1
3
Figure 31.
10
QFN
Figure 27.
Class-AB, VDD = 3.6 V
0
Class-AB
40
Figure 26.
0.6
0
50
Figure 25.
RL = 4 Ω
0.4
1.5
60
PO − Output Power − W
PO − Output Power − W
0.7
1
VDD = 2.5 V
20
Powers are per Channel
0
VDD = 3.6 V
70
30
QFN
20
Efficiency − %
0.8
VDD = 5 V
80
Efficiency − %
1
RL = 8 Ω
90
80
Efficiency − %
PD − Power Dissipation − W
100
100
RL = 4 Ω
Class-AB, VDD = 5 V
EFFICIENCY
vs
OUTPUT POWER
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3.5
4
4.5
VDD − Supply Voltage − V
Figure 32.
5
1.4
1.6
TPA2012D2
www.ti.com
SLOS438C – DECEMBER 2004 – REVISED MARCH 2007
APPLICATION INFORMATION
To Battery
4.7 mF
1 mF
0.1 mF
PVDD*
INL−
0.1 mF
AVDD
OUTL+
1 nF
INL+
0.1 mF
DAC
OUTL−
1 nF
0.1 mF
INR−
OUTR+
INR+
1 nF
0.1 mF
OUTR−
Shutdown
Control
SDL
G0
SDR
1 nF
G1
PGND
AGND
* For QFN, an additional capacitor is recomended for the second PVDD pin.
Figure 33. Typical Application Circuit
V DD
to Battery
V DD
CS
CI
INR+
Right
Differential
Input
Gain
Adjust
H−
Bridge
PWM
INR+
OUTR−
INR−
Right
Single−Ended
Input
OUTR+
Gain
Adjust
CI
CI
H−
Bridge
PWM
OUTR−
CI
Internal
Oscillator
to Battery
CS
OUTR+
INR−
GND
Internal
Oscillator
GND
CI
INL+
Left
Differential
Input
OUTL+
Gain
Adjust
PWM
H−
Bridge
OUTL−
INL−
CI
INL+
Left CI
Single−Ended
Input
PWM
H−
Bridge
OUTL−
CI
G0
G0
G1
G1
SDR
OUTL+
Gain
Adjust
INL−
SDR
300 k
Bias
Circuitry
300 k
Short−Circuit
Protection
Bias
Circuitry
Short−Circuit
Protection
SDL
SDL
300 k
300 k
Figure 34. TPA2012D2 Application Schematic
With Differential Input and Input Capacitors
Figure 35. TPA2012D2 Application Schematic
With Single-Ended Input
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11
TPA2012D2
www.ti.com
SLOS438C – DECEMBER 2004 – REVISED MARCH 2007
Decoupling Capacitor (CS)
The TPA2012D2 is a high-performance Class-D audio amplifier that requires adequate power supply decoupling
to ensure the efficiency is high and total harmonic distortion (THD) is low. For higher frequency transients,
spikes, or digital hash on the line a good low equivalent-series-resistance (ESR) ceramic capacitor, typically 1
µF, placed as close as possible to the device PVDD lead works best. Placing this decoupling capacitor close to
the TPA2012D2 is important for the efficiency of the Class-D amplifier, because any resistance or inductance in
the trace between the device and the capacitor can cause a loss in efficiency. For filtering lower-frequency noise
signals, a 4.7 µF or greater capacitor placed near the audio power amplifier would also help, but it is not
required in most applications because of the high PSRR of this device.
Table 1. Gain Setting
G1
G0
GAIN
(V/V)
GAIN
(dB)
INPUT IMPEDANCE
(RI)
(kΩ)
0
0
2
6
28.1
0
1
4
12
17.3
1
0
8
18
9.8
1
1
16
24
5.2
Input Capacitors (CI)
The TPA2012D2 does not require input coupling capacitors if the design uses a differential source that is biased
from 0.5 V to VDD– 0.8 V. If the input signal is not biased within the recommended common-mode input range, if
high pass filtering is needed (see Figure 34), or if using a single-ended source (see Figure 35), input coupling
capacitors are required.
The input capacitors and input resistors form a high-pass filter with the corner frequency, fc, determined in
Equation 1.
1
fc +
ǒ2p RIC IǓ
(1)
The value of the input capacitor is important to consider as it directly affects the bass (low frequency)
performance of the circuit. Speakers in wireless phones cannot usually respond well to low frequencies, so the
corner frequency can be set to block low frequencies in this application. Not using input capacitors can increase
output offset.
Equation 2 is used to solve for the input coupling capacitance.
1
CI +
ǒ2p RI f cǓ
(2)
If the corner frequency is within the audio band, the capacitors should have a tolerance of ±10% or better,
because any mismatch in capacitance causes an impedance mismatch at the corner frequency and below.
12
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TPA2012D2
www.ti.com
SLOS438C – DECEMBER 2004 – REVISED MARCH 2007
BOARD LAYOUT
In making the pad size for the WCSP balls, it is recommended that the layout use nonsolder mask defined
(NSMD) land. With this method, the solder mask opening is made larger than the desired land area, and the
opening size is defined by the copper pad width. Figure 36 and Table 2 shows the appropriate diameters for a
WCSP layout. The TPA2012D2 evaluation module (EVM) layout is shown in the next section as a layout
example.
Copper
Trace Width
Solder
Pad Width
Solder Mask
Opening
Copper Trace
Thickness
Solder Mask
Thickness
Figure 36. Land Pattern Dimensions
Table 2. Land Pattern Dimensions (1) (2) (3) (4)
SOLDER PAD
DEFINITIONS
COPPER
PAD
Nonsolder mask
defined (NSMD)
275 µm
(+0.0, -25 µm)
(1)
(2)
(3)
(4)
(5)
(6)
(7)
SOLDER MASK
OPENING
(5)
375 µm (+0.0, -25 µm)
COPPER
THICKNESS
STENCIL (6) (7)
OPENING
STENCIL
THICKNESS
1 oz max (32 µm)
275 µm x 275 µm Sq.
(rounded corners)
125 µm thick
Circuit traces from NSMD defined PWB lands should be 75 µm to 100 µm wide in the exposed area inside the solder mask opening.
Wider trace widths reduce device stand off and impact reliability.
Best reliability results are achieved when the PWB laminate glass transition temperature is above the operating the range of the
intended application.
Recommend solder paste is Type 3 or Type 4.
For a PWB using a Ni/Au surface finish, the gold thickness should be less 0.5 mm to avoid a reduction in thermal fatigue performance.
Solder mask thickness should be less than 20 µm on top of the copper circuit pattern
Best solder stencil performance is achieved using laser cut stencils with electro polishing. Use of chemically etched stencils results in
inferior solder paste volume control.
Trace routing away from WCSP device should be balanced in X and Y directions to avoid unintentional component movement due to
solder wetting forces.
Component Location
Place all the external components very close to the TPA2012D2. Placing the decoupling capacitor, CS, close to
the TPA2012D2 is important for the efficiency of the Class-D amplifier. Any resistance or inductance in the trace
between the device and the capacitor can cause a loss in efficiency.
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13
TPA2012D2
www.ti.com
SLOS438C – DECEMBER 2004 – REVISED MARCH 2007
Trace Width
Recommended trace width at the solder balls is 75 µm to 100 µm to prevent solder wicking onto wider PCB
traces.
For high current pins (PVDD, PGND, and audio output pins) of the TPA2012D2, use 100-µm trace widths at the
solder balls and at least 500-µm PCB traces to ensure proper performance and output power for the device.
For the remaining signals of the TPA2012D2, use 75-µm to 100-µm trace widths at the solder balls. The audio
input pins (INR+/- and INL+/-) must run side-by-side to maximize common-mode noise cancellation.
EFFICIENCY AND THERMAL INFORMATION
The maximum ambient temperature depends on the heat-sinking ability of the PCB system. The derating factor
for the packages are shown in the dissipation rating table. Converting this to θJA for the QFN package:
1
q
+
+ 1 + 24°CńW
JA
0.041
Derating Factor
(3)
Given θJA of 24°C/W, the maximum allowable junction temperature of 150°C, and the maximum internal
dissipation of 1.5W (0.75 W per channel) for 2.1 W per channel, 4-Ω load, 5-V supply, from Figure 25, the
maximum ambient temperature can be calculated with the following equation.
T Max + T Max * q P
+ 150 * 24 (1.5) + 114°C
A
J
JA Dmax
(4)
Equation 4 shows that the calculated maximum ambient temperature is 114°C at maximum power dissipation
with a 5-V supply and 4-Ω a load. The TPA2012D2 is designed with thermal protection that turns the device off
when the junction temperature surpasses 150°C to prevent damage to the IC. Also, using speakers more
resistive than 4-Ω dramatically increases the thermal performance by reducing the output current and increasing
the efficiency of the amplifier.
OPERATION WITH DACs AND CODECs
In using Class-D amplifiers with CODECs and DACs, sometimes there is an increase in the output noise floor
from the audio amplifier. This occurs when mixing of the output frequencies of the CODEC/DAC mix with the
switching frequencies of the audio amplifier input stage. The noise increase can be solved by placing a low-pass
filter between the CODEC/DAC and audio amplifier. This filters off the high frequencies that cause the problem
and allow proper performance. See Figure 33 for the block diagram.
FILTER FREE OPERATION AND FERRITE BEAD FILTERS
A ferrite bead filter can often be used if the design is failing radiated emissions without an LC filter and the
frequency sensitive circuit is greater than 1 MHz. This filter functions well for circuits that just have to pass FCC
and CE because FCC and CE only test radiated emissions greater than 30 MHz. When choosing a ferrite bead,
choose one with high impedance at high frequencies, and very low impedance at low frequencies. In addition,
select a ferrite bead with adequate current rating to prevent distortion of the output signal.
Use an LC output filter if there are low frequency (< 1 MHz) EMI sensitive circuits and/or there are long leads
from amplifier to speaker.
Figure 37 shows typical ferrite bead and LC output filters.
Ferrite
Chip Bead
OUTP
1 nF
Ferrite
Chip Bead
OUTN
1 nF
Figure 37. Typical Ferrite Chip Bead Filter (Chip bead example: TDK: MPZ1608S221A)
14
Submit Documentation Feedback
PACKAGE OPTION ADDENDUM
www.ti.com
27-Feb-2007
PACKAGING INFORMATION
Orderable Device
Status (1)
Package
Type
Package
Drawing
Pins Package Eco Plan (2)
Qty
TPA2012D2RTJR
ACTIVE
QFN
RTJ
20
3000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
TPA2012D2RTJRG4
ACTIVE
QFN
RTJ
20
3000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
TPA2012D2RTJT
ACTIVE
QFN
RTJ
20
250
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
TPA2012D2RTJTG4
ACTIVE
QFN
RTJ
20
250
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
TPA2012D2YZHR
ACTIVE
DSBGA
YZH
16
3000 Green (RoHS &
no Sb/Br)
SNAGCU
Level-1-260C-UNLIM
TPA2012D2YZHT
ACTIVE
DSBGA
YZH
16
250
SNAGCU
Level-1-260C-UNLIM
Green (RoHS &
no Sb/Br)
Lead/Ball Finish
MSL Peak Temp (3)
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 1
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