TPA2016D2 YZH www.ti.com ............................................................................................................................................................. SLOS524B – JUNE 2008 – REVISED JUNE 2008 1.7-W/Ch Stereo Class-D Audio Amplifier with Dynamic Range Compression and AGC FEATURES 1 • • • • • • • • 23 • • • • • • • • • • Filter-Free Class-D Architecture 1.7 W/Ch Into 8 Ω at 5 V (10% THD+N) 750 mW/Ch Into 8 Ω at 3.6 V (10% THD+N) Power Supply Range: 2.5 V to 5.5 V Flexible Operation With/Without I2C Programmable DRC/AGC Parameters Digital I2C Volume Control Selectable Gain from –28 dB to 30 dB in 1-dB Steps (when compression is used) Selectable Attack, Release and Hold Times 4 Selectable Compression Ratios Low Supply Current: 3.5 mA Low Shutdown Current: 0.2 µA High PSRR: 80 dB Fast Start-up Time: 5 ms AGC Enable/Disable Function Limiter Enable/Disable Function Short-Circuit and Thermal Protection Space-Saving Package – 2,2 mm × 2,2 mm Nano-Free™ WCSP (YZH) APPLICATIONS • • • • • • • • Wireless or Cellular Handsets and PDAs Portable Navigation Devices Portable DVD Player Notebook PCs Portable Radio Portable Games Educational Toys USB Speakers DESCRIPTION The TPA2016D2 is a stereo, filter-free Class-D audio power amplifier with volume control, dynamic range compression (DRC) and automatic gain control (AGC). It is available in a 2.2 mm x 2.2 mm WCSP package. The DRC/AGC function in the TPA2016D2 is programmable via a digital I2C interface. The DRC/AGC function can be configured to automatically prevent distortion of the audio signal and enhance quiet passages that are normally not heard. The DRC/AGC can also be configured to protect the speaker from damage at high power levels and compress the dynamic range of music to fit within the dynamic range of the speaker. The gain can be selected from –28 dB to +30 dB in 1-dB steps. The TPA2016D2 is capable of driving 1.7 W/Ch at 5 V or 750 mW/Ch at 3.6 V into 8 Ω load. The device features independent software shutdown controls for each channel and also provides thermal and short circuit protection. In addition to these features, a fast start-up time and small package size make the TPA2016D2 an ideal choice for cellular handsets, PDAs and other portable applications. SIMPLIFIED APPLICATION DIAGRAM To Battery 10 mF AVDD PVDDL PVDDR TPA2016D2 CIN 1 mF INL– Analog Baseband or Codec OUTL+ INL+ INR– INR+ OUTL– OUTR+ 2 I C Clock Digital Baseband 2 I C Data Master Shutdown OUTR– SCL SDA SDZ AGND PGND 1 2 3 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Nano-Free is a trademark of Texas Instruments. All other trademarks are the property of their respective owners. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2008, Texas Instruments Incorporated TPA2016D2 SLOS524B – JUNE 2008 – REVISED JUNE 2008 ............................................................................................................................................................. www.ti.com These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. FUNCTIONAL BLOCK DIAGRAM 2 I C Interface IC shutdown SDA SCL Bias and References 2 I C Interface & Control SDZ AVDD PVDDL C IN Differential INL+ Input Left OUTL+ INLVolume Control Power Stage Class-D Modulator OUTL- 1uF AGC Reference AGC PVDDR C IN INR- Differential INR+ Input Right OUTR+ Volume Control Power Stage Class-D Modulator OUTR- 1uF AGND PGND DEVICE PINOUT YZH (WCSP) PACKAGE (Top View) INR– INR+ INL+ INL– A1 A2 A3 A4 AVDD SCL SDA AGND B1 B2 B3 B4 PVDDR SDZ PGND PVDDL C1 C2 C3 C4 OUTR+ OUTR– OUTL– OUTL+ D1 D2 D3 D4 2 Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s): TPA2016D2 TPA2016D2 www.ti.com ............................................................................................................................................................. SLOS524B – JUNE 2008 – REVISED JUNE 2008 TERMINAL FUNCTIONS TERMINAL NAME I/O/P DESCRIPTION WCSP INR+ A2 I Right channel positive audio input INR– A1 I Right channel negative audio input INL+ A3 I Left channel positive audio input INL– A4 I Left channel negative audio input SDZ C2 I Shutdown terminal (active low) SDA B3 I/O I2C data interface SCL B2 I I2C clock interface OUTR+ D1 O Right channel positive differential output OUTR– D2 O Right channel negative differential output OUTL+ D4 O Left channel positive differential output OUTL– D3 O Left channel negative differential output AVDD B1 P Analog supply (must be the same as PVDDR and PVDDL) AGND B4 P Analog ground (all GND pins need to be connected) PVDDR C1 P Right channel power supply (must be the same as AVDD and PVDDL) PGND C3 P Power ground (all GND pins need to be connected) PVDDL C4 P Left channel power supply (must be the same as AVDD and PVDDR) ABSOLUTE MAXIMUM RATINGS (1) over operating free-air temperature range (unless otherwise noted). VALUE / UNIT VDD Supply voltage AVDD, PVDDR, PVDDL –0.3 V to 6.0 V SDZ, INR+, INR–, INL+, INL– Input voltage –0.3 V to VDD+0.3 V SDA, SCL –0.3 V to 6.0 V See Dissipation Ratings Table Continuous total power dissipation TA Operating free-air temperature range –40°C to +85°C TJ Operating junction temperature range –40°C to +150°C Tstg Storage temperature range ESD Electro-Static Discharge Tolerance, all pins RLOAD (1) –65°C to +150°C Human Body Model (HBM) 2 KV Charged Device Model (CDM) 500 V 6.4 Ω Minimum load resistance Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. DISSIPATION RATINGS TABLE (1) (1) PACKAGE TA ≤ +25°C DERATING FACTOR TA = +70°C TA = +85°C 16-ball WCSP 1.25 W 10 mW/°C 0.8 W 0.65 W Dissipations ratings are for a 2-side, 2-plane PCB. 3 Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s): TPA2016D2 TPA2016D2 SLOS524B – JUNE 2008 – REVISED JUNE 2008 ............................................................................................................................................................. www.ti.com AVAILABLE OPTIONS (1) (1) (2) TA PACKAGED DEVICES (2) PART NUMBER SYMBOL –40°C to 85°C 16-ball, 2,2 mm × 2,2 mm WCSP (+0.01 mm/ -0.09 mm tolerance) TPA2016D2 YZHR CCJ TPA2016D2 YZHT CCJ For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI Web site at www.ti.com The YZH packages are only available taped and reeled. The suffix R indicates a reel of 3000; the suffix T indicates a reel of 250. RECOMMENDED OPERATING CONDITIONS MIN MAX VDD Supply voltage AVDD, PVDDR, PVDDL 2.5 5.5 VIH High-level input voltage SDZ, SDA, SCL 1.3 VIL Low-level input voltage SDZ, SDA, SCL TA Operating free-air temperature UNIT V V –40 0.6 V +85 °C ELECTRICAL CHARACTERISTICS at TA = 25°C, VDD = 3.6 V, SDZ = 1.3 V, and RL = 8 Ω + 33 µH (unless otherwise noted). PARAMETER VDD ISDZ ISWS IDD TEST CONDITIONS Supply voltage range Shutdown quiescent current Software shutdown quiescent current Supply current TYP MAX 2.5 UNIT 3.6 5.5 SDZ = 0.35 V, VDD = 2.5 V 0.1 1 SDZ = 0.35 V, VDD = 3.6 V 0.2 1 SDZ = 0.35 V, VDD = 5.5 V 0.3 1 SDZ = 1.3 V, VDD = 2.5 V 35 50 SDZ = 1.3 V, VDD = 3.6 V 50 60 SDZ = 1.3 V, VDD = 5.5 V 75 100 VDD = 2.5 V 3.5 4.5 VDD = 3.6 V 3.7 4.7 VDD = 5.5 V 4.5 5.5 300 325 kHz 1 µA fSW Class D Switching Frequency IIH High-level input current VDD = 5.5 V, SDZ = 5.8 V IIL Low-level input current VDD = 5.5 V, SDZ = –0.3 V tSTART Start-up time 2.5 V ≤ VDD ≤ 5.5 V no pop, CIN ≤ 1 µF POR Power on reset ON threshold POR Power on reset hysteresis 275 –1 2 CMRR Input common mode rejection Voo Output offset voltage VDD = 3.6 V, AV = 6 dB, RL = 8 Ω, inputs ac grounded ZOUT Output Impedance in shutdown mode SDZ = 0.35 V Gain accuracy Compression and limiter disabled, Gain = 0 to 30 dB Power supply rejection ratio VDD = 2.5 V to 4.7 V 4 –10 V µA µA mA µA 5 RL = 8 Ω, Vicm = 0.5 V and Vicm = VDD – 0.8 V, differential inputs shorted PSRR MIN ms 2.3 V 0.2 V –70 dB 0 10 2 –0.25 kΩ 0.25 -80 mV dB dB Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s): TPA2016D2 TPA2016D2 www.ti.com ............................................................................................................................................................. SLOS524B – JUNE 2008 – REVISED JUNE 2008 OPERATING CHARACTERISTICS at TA = 25°C, VDD = 3.6V, SDZ = 1.3 V, RL = 8 Ω +33 µH, and AV = 6 dB (unless otherwise noted). PARAMETER TEST CONDITIONS kSVR VDD = 3.6 Vdc with ac of 200 mVPP at 217 Hz power-supply ripple rejection ratio THD+N Total harmonic distortion + noise MIN TYP faud_in = 1 kHz; PO = 550 mW; VDD = 3.6 V 0.1% faud_in = 1 kHz; PO = 1 W; VDD = 5 V 0.1% faud_in = 1 kHz; PO = 630 mW; VDD = 3.6 V 1% faud_in = 1 kHz; PO = 1.4 W; VDD = 5 V 1% NfonF Output integrated noise Av = 6 dB 44 NfoA Output integrated noise Av = 6 dB floor, A-weighted 33 FR Frequency response Av = 6 dB Pomax η Maximum output power Efficiency MAX –68 20 UNIT dB µV µV 20000 Hz THD+N = 10%, VDD = 5 V, RL = 8 Ω 1.72 W THD+N = 10%, VDD = 3.6 V, RL = 8 Ω 750 mW THD+N = 1%, VDD = 5 V, RL = 8 Ω 1.4 W THD+N = 1% , VDD = 3.6 V, RL = 8 Ω 630 mW THD+N = 1%, VDD = 3.6 V, RL = 8 Ω, PO= 0.63 W 90% THD+N = 1%, VDD = 5 V, RL = 8 Ω, PO = 1.4 W 90% TEST SET-UP FOR GRAPHS TPA2016D2 CI + Measurement Output – IN+ OUT+ Load CI IN– VDD + OUT– 30 kHz Low-Pass Filter + Measurement Input – GND 1 mF VDD – (1) All measurements were taken with a 1-µF CI (unless otherwise noted.) (2) A 33-µH inductor was placed in series with the load resistor to emulate a small speaker for efficiency measurements. (3) The 30-kHz low-pass filter is required, even if the analyzer has an internal low-pass filter. An RC low-pass filter (1 kΩ 4.7 nF) is used on each output for the data sheet graphs. 5 Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s): TPA2016D2 TPA2016D2 SLOS524B – JUNE 2008 – REVISED JUNE 2008 ............................................................................................................................................................. www.ti.com I2C TIMING CHARACTERISTICS For I2C Interface Signals Over Recommended Operating Conditions (unless otherwise noted) PARAMETER fSCL Frequency, SCL tW(H) Pulse duration, SCL high tW(L) tSU(1) TEST CONDITIONS MIN No wait states TYP MAX UNIT 400 kHz 0.6 µs Pulse duration, SCL low 1.3 µs Setup time, SDA to SCL 100 ns th1 Hold time, SCL to SDA 10 ns t(buf) Bus free time between stop and start condition 1.3 µs tSU2 Setup time, SCL to start condition 0.6 µs th2 Hold time, start condition to SCL 0.6 µs tSU3 Setup time, SCL to stop condition 0.6 µs tw(L) tw(H) SCL t su1 th1 SDA Figure 1. SCL and SDA Timing SCL t(buf) th2 tsu2 tsu3 Start Condition Stop Condition SDA Figure 2. Start and Stop Conditions Timing 6 Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s): TPA2016D2 TPA2016D2 www.ti.com ............................................................................................................................................................. SLOS524B – JUNE 2008 – REVISED JUNE 2008 TYPICAL CHARACTERISTICS with C(DECOUPLE) = 1 µF, CI = 1 µF. All THD + N graphs are taken with outputs out of phase (unless otherwise noted). All data is taken on left channel. Table of Graphs FIGURE Quiescent supply current vs Supply voltage Figure 3 Supply current vs Supply voltage in shutdown Figure 4 Output level vs Input level Figure 5 Output level vs Input level Figure 6 Output level vs Input level Figure 7 Output level vs Input level Figure 8 Output level vs Input level Figure 9 Total harmonic distortion + noise vs Frequency Figure 10 Total harmonic distortion + noise vs Frequency Figure 11 Total harmonic distortion + noise vs Output power Figure 12 Supply ripple rejection ratio vs Frequency Figure 13 Efficiency vs Output power (per channel) Figure 14 Total power dissipation vs Total output power Figure 15 Total supply current vs Total output power Figure 16 Output power vs Supply voltage Figure 17 Shutdown time Figure 18 Startup time Figure 19 SUPPLY CURRENT vs SUPPLY VOLTAGE IN SHUTDOWN 10 100 8 80 IDD − Supply Current − µA IDD − Quiescent Supply Current − µA QUIESCENT SUPPLY CURRENT vs SUPPLY VOLTAGE 6 4 2 0 2.5 3.5 4.5 VDD − Supply Voltage − V 5.5 SDZ = VDD, SWS = 1 60 40 SDZ = 0 V 20 0 2.5 G001 Figure 3. 3.5 4.5 VDD − Supply Voltage − V 5.5 G002 Figure 4. 7 Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s): TPA2016D2 TPA2016D2 SLOS524B – JUNE 2008 – REVISED JUNE 2008 ............................................................................................................................................................. www.ti.com OUTPUT LEVEL vs INPUT LEVEL WITH 2:1 COMPRESSION 20 10 10 Output Level − dBV 20 0 −10 Limiter Limiter Limiter Limiter Limiter Limiter Limiter Limiter Limiter −20 −40 −50 −40 RL = 8 Ω + 33 µH VSupply = 5 V Fixed Gain = Max Gain = 30 dB Compression Ratio = 1:1 −30 −20 −10 = −6.5 = −4.5 = −2.5 = −0.5 = 1.5 = 3.5 = 5.5 = 7.5 =9 0 Output Level − dBV 10 0 Output Level − dBV −30 −10 10 Input Level − dBV G004 OUTPUT LEVEL vs INPUT LEVEL WITH 8:1 COMPRESSION 20 Limiter Level = 9 dBV RL = 8 Ω + 33 µH VSupply = 5 V Compression Ratio = 4:1 Max Gain = 30 dB Fixed Gain = −15 Fixed Gain = −12 Fixed Gain = −9 Fixed Gain = −6 Fixed Gain = −3 Fixed Gain = 0 Fixed Gain = 3 Fixed Gain = 6 Fixed Gain = −27 Fixed Gain = −24 Fixed Gain = −21 Fixed Gain = −18 −50 −30 −10 0 −10 −20 −30 Fixed Gain = −27 Fixed Gain = −24 Fixed Gain = −21 Fixed Gain = −18 Fixed Gain = −15 −40 −50 −70 10 −50 −30 Fixed Gain = −12 Fixed Gain = −9 Fixed Gain = −6 Fixed Gain = −3 Fixed Gain = 0 Fixed Gain = 3 −10 10 Input Level − dBV G005 G006 Figure 7. Figure 8. OUTPUT LEVEL vs INPUT LEVEL TOTAL HARMONIC DISTORTION + NOISE vs FREQUENCY Limiter Level = 9 dBV RL = 8 Ω + 33 µH VSupply = 5 V Fixed Gain = 0 dB Max Gain = 30 dB −10 −20 −30 Compression Compression Compression Compression −40 −50 Limiter Level = 9 dBV RL = 8 Ω + 33 µH VSupply = 5 V Compression Ratio = 8:1 Max Gain = 30 dB 10 Input Level − dBV −50 −70 −50 OUTPUT LEVEL vs INPUT LEVEL WITH 4:1 COMPRESSION −40 0 −30 Figure 6. −30 10 Fixed Gain = −12 Fixed Gain = −9 Fixed Gain = −6 Fixed Gain = −3 Fixed Gain = 0 Fixed Gain = 3 Fixed Gain = 6 Fixed Gain = 9 Fixed Gain = 12 −20 G003 −20 20 −10 Figure 5. −10 −50 −70 0 −50 −70 10 Input Level − dBV 20 Limiter Level = 9 dBV RL = 8 Ω + 33 µH VSupply = 5 V Fixed Gain (2:1) Compression Ratio = 2:1 Max Gain = 30 dB −40 Output Level − dBV −30 Level Level Level Level Level Level Level Level Level −30 Input Level − dBV −10 Ratio = 1:1 Ratio = 2:1 Ratio = 4:1 Ratio = 8:1 10 THD+N − Total Harmonic Distortion + Noise − % Output Level − dBV OUTPUT LEVEL vs INPUT LEVEL WITH LIMITER ENABLED 10 Gain = 6 dB RL = 8 Ω + 33 µH VSupply = 3.6 V 1 PO = 0.25 W PO = 0.05 W 0.1 PO = 0.5 W 0.01 0.001 20 G007 Figure 9. 100 1k f − Frequency − Hz 10k 20k G008 Figure 10. 8 Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s): TPA2016D2 TPA2016D2 www.ti.com ............................................................................................................................................................. SLOS524B – JUNE 2008 – REVISED JUNE 2008 10 Gain = 6 dB RL = 8 Ω + 33 µH VSupply = 5 V 1 PO = 0.5 W PO = 0.1 W 0.1 0.01 PO = 1 W 0.001 20 100 1k 10k f − Frequency − Hz 20k Gain = 6 dB RL = 8 Ω + 33 µH f = 1 kHz 10 VSupply = 3.6 V 1 VSupply = 5 V 0.1 0.01 0.01 0.1 1 G009 3 G010 Figure 11. Figure 12. SUPPLY RIPPLE REJECTION RATIO EFFICIENCY vs OUTPUT POWER (PER CHANNEL) 100 0 Gain = 6 dB RL = 8 Ω + 33 µH Right Channel −10 −20 80 −30 −40 −50 VCC = 5 V VCC = 2.5 V −60 VDD = 2.5 V 60 VDD = 3.6 V Gain = 6 dB RL = 8 Ω + 33 µH f = 1 kHz 20 VCC = 3.6 V −80 20 100 1k 10k 0 0.0 20k VDD = 5 V 40 −70 f − Frequency − Hz 0.5 1.0 1.5 PO − Output Power (Per Channel) − W G011 Figure 13. Figure 14. TOTAL POWER DISSIPATION vs TOTAL OUTPUT POWER TOTAL SUPPLY CURRENT vs TOTAL OUTPUT POWER 0.5 2.0 G012 1.0 Gain = 6 dB RL = 8 Ω + 33 µH f = 1 kHz 0.4 IDD − Total Supply Current − A PD − Total Power Dissipation − W 100 PO − Output Power − W Efficiency − % KSVR − Supply Ripple Rejection Ratio − dB TOTAL HARMONIC DISTORTION + NOISE vs OUTPUT POWER THD+N − Total Harmonic Distortion + Noise − % THD+N − Total Harmonic Distortion + Noise − % TOTAL HARMONIC DISTORTION + NOISE vs FREQUENCY VDD = 3.6 V 0.3 VDD = 5 V VDD = 2.5 V 0.2 0.1 0.0 Gain = 6 dB RL = 8 Ω + 33 µH f = 1 kHz VDD = 3.6 V 0.8 0.6 VDD = 5 V VDD = 2.5 V 0.4 0.2 0.0 0 1 2 3 PO − Total Output Power − W 4 0 G013 Figure 15. 1 2 3 PO − Total Output Power − W 4 G014 Figure 16. 9 Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s): TPA2016D2 TPA2016D2 SLOS524B – JUNE 2008 – REVISED JUNE 2008 ............................................................................................................................................................. www.ti.com OUTPUT POWER vs SUPPLY VOLTAGE PO − Output Power − W 2.5 Gain = 6 dB RL = 8 Ω + 33 µH f = 1 kHz 2.0 1.5 THD = 10% 1.0 THD = 1% 0.5 0.0 2.5 3.0 3.5 4.0 4.5 5.0 VCC − Supply Voltage − V 5.5 G015 Figure 17. 1 Output SWS Disable 0.75 Voltage - V 0.5 0.25 0 -0.25 -0.5 -0.75 -1 0 200m 400m 600m 800m 1m 1.2m 1.4m 1.6m 1.8m 2m 7m 8m 9m 10m t - Time - s Figure 18. Shutdown Time 1 Output 0.75 SWS Enable Voltage - V 0.5 0.25 0 -0.25 -0.5 -0.75 -1 0 1m 2m 3m 4m 5m 6m t - Time - s Figure 19. Startup Time 10 Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s): TPA2016D2 TPA2016D2 www.ti.com ............................................................................................................................................................. SLOS524B – JUNE 2008 – REVISED JUNE 2008 APPLICATION INFORMATION AUTOMATIC GAIN CONTROL The Automatic Gain Control (AGC) feature provides continuous automatic gain adjustment to the amplifier through an internal PGA. This feature enhances the perceived audio loudness and at the same time prevents speaker damage from occurring (Limiter function). The AGC function attempts to maintain the audio signal gain as selected by the user through the Fixed Gain, Limiter Level, and Compression Ratio variables. Other advanced features included are Maximum Gain and Noise Gate Threshold. Table 1 describes the function of each variable in the AGC function. Table 1. TPA2016D2 AGC Variable Descriptions VARIABLE DESCRIPTION Maximum Gain The gain at the lower end of the compression region. Fixed Gain The normal gain of the device when the AGC is inactive. The fixed gain is also the initial gain when the device comes out of shutdown mode or when the AGC is disabled. Limiter Level The value that sets the maximum allowed output amplitude. Compression Ratio The relation between input and output voltage. Noise Gate Threshold Below this value, the AGC holds the gain to prevent breathing effects. Attack Time The minimum time between two gain decrements. Release Time The minimum time between two gain increments. Hold Time The time it takes for the very first gain increment after the input signal amplitude decreases. 11 Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s): TPA2016D2 TPA2016D2 SLOS524B – JUNE 2008 – REVISED JUNE 2008 ............................................................................................................................................................. www.ti.com The AGC works by detecting the audio input envelope. The gain changes depending on the amplitude, the limiter level, the compression ratio, and the attack and release time. The gain changes constantly as the audio signal increases and/or decreases to create the compression effect. The gain step size for the AGC is 0.5 dB. If the audio signal has near-constant amplitude, the gain does not change. Figure 20 shows how the AGC works. INPUT SIGNAL Limiter threshold Limiter threshold B C D E A GAIN OUTPUT SIGNAL Limiter threshold Release Time Hold Time Attack Time Limiter threshold A. Gain decreases with no delay; attack time is reset. Release time and hold time are reset. B. Signal amplitude above limiter level, but gain cannot change because attack time is not over. C. Attack time ends; gain is allowed to decrease from this point forward by one step. Gain decreases because the amplitude remains above limiter threshold. All times are reset D. Gain increases after release time finishes and signal amplitude remains below desired level. All times are reset after the gain increase. E. Gain increases after release time is finished again because signal amplitude remains below desired level. All times are reset after the gain increase. Figure 20. Input and Output Audio Signal vs Time Since the number of gain steps is limited the compression region is limited as well. The following figure shows how the gain changes vs. the input signal amplitude in the compression region. 12 Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s): TPA2016D2 TPA2016D2 Gain - dB www.ti.com ............................................................................................................................................................. SLOS524B – JUNE 2008 – REVISED JUNE 2008 VIN - dBV Figure 21. Input Signal Voltage vs Gain Thus the AGC performs a mapping of the input signal vs. the output signal amplitude. This mapping can be modified according to the variables from Table 1. The following graphs and explanations show the effect of each variable to the AGC independently and which considerations should be taken when choosing values. Fixed Gain: The fixed gain determines the initial gain of the AGC. Set the gain using the following variables: • Set the fixed gain to be equal to the gain when the AGC is disabled. • Set the fixed gain to maximize SNR. • Set the fixed gain such that it will not overdrive the speaker. Increasing Fixed Gain G xe d Decreasing Fixed Gain 1: 1 Fi VOUT - dBV ai n = 3 Fi x dB ed G ai n = 6 dB Figure 22 shows how the fixed gain influences the input signal amplitude vs. the output signal amplitude state diagram. The dotted 1:1 line is displayed for reference. The 1:1 line means that for a 1dB increase in the input signal, the output increases by 1dB. VIN - dBV Figure 22. Output Signal vs Input Signal State Diagram Showing Different Fixed Gain Configurations If the Compression function is enabled, the Fixed Gain is adjustable from –28dB to 30dB. If the Compression function is disabled, the Fixed gain is adjustable from 0dB to 30dB. Limiter Level: The Limiter level sets the maximum amplitude allowed at the output of the amplifier. The limiter should be set with the following constraints in mind: • Below or at the maximum power rating of the speaker • Below the minimum supply voltage in order to avoid clipping Figure 23 shows how the limiter level influences the input signal amplitude vs. the output signal amplitude state diagram. 13 Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s): TPA2016D2 TPA2016D2 SLOS524B – JUNE 2008 – REVISED JUNE 2008 ............................................................................................................................................................. www.ti.com Limiter Level= 630mW Limiter Level= 500mW VOUT - dBV Limiter Level = 400 mW Increasing Limiter Level Decreasing Limiter Level VIN - dBV Figure 23. Output Signal vs Input Signal State Diagram Showing Different Limiter Level Configurations The limiter level and the fixed gain influence each other. If the fixed gain is set high, the AGC has a large limiter range. The fixed gain is set low, the AGC has a short limiter range. Figure 24 illustrates the two examples: Small Fixed Gain 1: 1 VOUT - dBV Large Fixed Gain VIN - dBV Figure 24. Output Signal vs. Input Signal State Diagram Showing Same Limiter Level Configurations with Different Fixed Gain Configurations Compression Ratio: The compression ratio sets the relation between input and output signal outside the limiter level region. The compression ratio compresses the dynamic range of the audio. For example if the audio source has a dynamic range of 60dB and compression ratio of 2:1 is selected, then the output has a dynamic range of 30dB. Most small form factor speakers have small dynamic range. Compression ratio allows audio with large dynamic range to fit into a speaker with small dynamic range. The compression ratio also increases the loudness of the audio without increasing the peak voltage. The higher the compression ratio, the louder the perceived audio. For example: • A compression ratio of 4:1 is selected (meaning that a 4dB change in the input signal results in a 1dB signal change at the output) • A fixed gain of 0dB is selected and the maximum audio level is at 0dBV. When the input signal decreases to –32dBV, the amplifier increases the gain to 24dB in order to achieve an output of –8dBV. The output signal amplitude equation is: Output signal amplitude = Input signal initial amplitude - |Current input signal amplitude| Compression ratio (1) In this example: -8dBV = 0dBV - | - 32 dBV| 4 (2) 14 Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s): TPA2016D2 TPA2016D2 www.ti.com ............................................................................................................................................................. SLOS524B – JUNE 2008 – REVISED JUNE 2008 The gain change equation is: æ ö 1 Gain change = ç 1 ÷ × Input signal change Compression ratio ø è (3) 1ö æ 24 dB = ç 1 - ÷ × 32 4ø è (4) Consider the following when setting the compression ratio: • Dynamic range of the speaker • Fixed gain level • Limiter Level • Audio Loudness vs Output Dynamic Range. Figure 25 shows different settings for dynamic range and different fixed gain selected but no limiter level. Rotation Point@ higher gain 8 :1 4 :1 2 Increasing Fixed Gain :1 VOUT - dBV 1 Rotation Point@ lower gain :1 8 :1 Decreasing 4 :1 2: 1 1 :1 VIN - dBV Figure 25. Output Signal vs Input Signal State Diagram Showing Different Compression Ratio Configurations with Different Fixed Gain Configurations The rotation point is always at Vin = 10dBV. The rotation point is not located at the intersection of the limiter region and the compression region. By changing the fixed gain the rotation point will move in the y-axis direction only, as shown in the previous graph. Interaction between compression ratio and limiter range: The compression ratio can be limited by the limiter range. Note that the limiter range is selected by the limiter level and the fixed gain. For a setting with large limiter range, the amount of gain steps in the AGC remaining to perform compression are limited. Figure 26 shows two examples, where the fixed gain was changed. 1. Small limiter range yielding a large compression region (small fixed gain). 2. Large limiter range yielding a small compression region (large fixed gain). 15 Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s): TPA2016D2 TPA2016D2 SLOS524B – JUNE 2008 – REVISED JUNE 2008 ............................................................................................................................................................. www.ti.com Small Compression Region Large Limiter Range Rotation Point @ higher gain Large Compression Region 1: 1 VOUT - dBV Rotation Point @ lower gain Small Limiter Range VIN - dBV Figure 26. Output Signal vs Input Signal State Diagram Showing the Effects of the Limiter Range to the Compression Region Input Signal Amplitude - Vrms Noise Gate Threshold: The noise gate threshold prevents the AGC from changing the gain when there is no audio at the input of the amplifier. The noise gate threshold stops gain changes until the input signal is above the noise gate threshold. Select the noise gate threshold to be above the noise but below the minimum audio at the input of the amplifier signal. A filter is needed between delta-sigma CODEC/DAC and TPA2016D2 for effectiveness of the noise gate function. The filter eliminates the out-of-band noise from delta-sigma modulation and keeps the CODEC/DAC output noise lower than the noise gate threshold. No Audio Noise Gate Threshold time Gain - dB Gain does not change in this region time Figure 27. Time Diagram Showing the Relationship Between Input Signal Amplitude, Noise Gate Threshold and Gain Versus Time Maximum Gain: This variable limits the number of gain steps in the AGC. This feature is useful in order to accomplish a more advanced output signal vs. input signal transfer characteristic. For example, to prevent the gain from going above a certain value, reduce the maximum gain. However, this variable will affect the limiter range and the compression region. If the maximum gain is decreased, the limiter range and/or compression region is reduced. Figure 28 illustrates the effects. 16 Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s): TPA2016D2 TPA2016D2 www.ti.com ............................................................................................................................................................. SLOS524B – JUNE 2008 – REVISED JUNE 2008 1: 1 VOUT - dBV Max Gain Max Gain = 30dB = 22dB VIN - dBV Figure 28. Output Signal vs. Input Signal State Diagram Showing Different Maximum Gains A particular application requiring maximum gain of 22dB, for example. Thus, set the maximum gain at 22dB. The amplifier gain will never have a gain higher than 22dB; however, this will reduce the limiter range. Attack, Release, and Hold time: • The attack time is the minimum time between gain decreases. • The release time is the minimum time between gain increases. • The hold time is the minimum time between a gain decrease (attack) and a gain increase (release). The hold time can be deactivated. Hold time is only valid if greater than release time. Successive gain decreases are never faster than the attack time. Successive gain increases are never faster than the release time. All time variables (attack, release and hold) start counting after each gain change performed by the AGC. The AGC is allowed to decrease the gain (attack) only after the attack time finishes. The AGC is allowed to increase the gain (release) only after the release time finishes counting. However, if the preceding gain change was an attack (gain increase) and the hold time is enabled and longer than the release time, then the gain is only increased after the hold time. The hold time is only enabled after a gain decrease (attack). The hold time replaces the release time after a gain decrease (attack). If the gain needs to be increased further, then the release time is used. The release time is used instead of the hold time if the hold time is disabled. The attack time should be at least 100 times shorter than the release and hold time. The hold time should be the same or greater than the release time. It is important to select reasonable values for those variables in order to prevent the gain from changing too often or too slow. Figure 29 illustrates the relationship between the three time variables. 17 Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s): TPA2016D2 TPA2016D2 SLOS524B – JUNE 2008 – REVISED JUNE 2008 ............................................................................................................................................................. www.ti.com Input Signal Amplitue (Vrms) Gain dB Time end Attack time Time reset Release time Hold timer not used after first gain increase Hold time time Figure 29. Time Diagram Showing the Relation Between the Attack, Release, and Hold Time vs Input Signal Amplitude and Gain Figure 30 shows a state diagram of the input signal amplitude vs. the output signal amplitude and a summary of how the variables from table 1 described in the preceding pages affect them. Fixed Gain Rotation Point 8:1 ¥:1 1: 1 4:1 2:1 nR sio 1 :1 A tta R c el k ea Ti se m e Ti m e Noise Gate Threshold VOUT - dBV r es mp Co Limiter Level ion eg Maximum Gain VIN - dBV 10 dBV Figure 30. Output Signal vs. Input Signal State Diagram 18 Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s): TPA2016D2 TPA2016D2 www.ti.com ............................................................................................................................................................. SLOS524B – JUNE 2008 – REVISED JUNE 2008 TPA2016D2 AGC OPERATION The TPA2016D2 is controlled by the I2C interface. The correct start-up sequence is: 1. Apply the supply voltage to the AVDD and PVDD (L, R)pins. 2. Apply a voltage above VIH to the SDZ pin. The TPA2016D2 powers up the I2C interface and the control logic. By default, the device is in active mode (SWS = 0). After a few milliseconds the amplifier will enable the class-D output stage and become fully operational. 3. The amplifier starts at a gain of 0 dB and the AGC starts ramping the gain after the input signal exceeds the noise gate threshold. CAUTION: Do not interrupt the start-up sequence after changing SDZ from VIL to VIH. Do not interrupt the start-up sequence after changing SWS from 0 to 1. The default conditions of TPA2016D2 allows audio playback without I2C control. Refer to Table 4 for entire default conditions. There are several options to disable the amplifier: • Write SPK_EN_R = 0 and SPK_EN_L = 0 to the register (0x01, 6 and 0x01, 7). This write disables each speaker amplifier, but leaves all other circuits operating. • Write SWS = 1 to the register (0x01, 5). This action disables most of the amplifier functions. • Apply VIL to SDZ. This action shuts down all the circuits and has very low quiescent current consumption. This action resets the registers to its default values. CAUTION: Do not interrupt the shutdown sequence after changing SDZ from VIH to VIL. Do not interrupt the shutdown sequence after changing SWS from 1 to 0. TPA2016D2 AGC RECOMMENDED SETTINGS Table 2. Recommended AGC Settings for Different Types of Audio Source (VDD = 3.6V) AUDIO SOURCE COMPRESSION RATIO ATTACK TIME (ms/6 dB) RELEASE TIME (ms/6 dB) HOLD TIME (ms) FIXED GAIN (dB) LIMITER LEVEL (dBV) Pop Music 4:1 1.28 to 3.84 986 to 1640 137 6 7.5 Classical 2:1 2.56 1150 137 6 8 Jazz 2:1 5.12 to 10.2 3288 — 6 8 Rap/ Hip Hop 4:1 1.28 to 3.84 1640 — 6 7.5 Rock 2:1 3.84 4110 — 6 8 Voice/ News 4:1 2.56 1640 — 6 8.5 GENERAL I2C OPERATION The I2C bus employs two signals, SDA (data) and SCL (clock), to communicate between integrated circuits in a system. The bus transfers data serially one bit at a time. The address and data 8-bit bytes are transferred most significant bit (MSB) first. In addition, each byte transferred on the bus is acknowledged by the receiving device with an acknowledge bit. Each transfer operation begins with the master device driving a start condition on the bus and ends with the master device driving a stop condition on the bus. The bus uses transitions on the data terminal (SDA) while the clock is at logic high to indicate start and stop conditions. A high-to-low transition on SDA indicates a start and a low-to-high transition indicates a stop. Normal data-bit transitions must occur within the low time of the clock period. Figure 31 shows a typical sequence. The master generates the 7-bit slave 19 Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s): TPA2016D2 TPA2016D2 SLOS524B – JUNE 2008 – REVISED JUNE 2008 ............................................................................................................................................................. www.ti.com address and the read/write (R/W) bit to open communication with another device, and then waits for an acknowledge condition. The TPA2016D2 holds SDA low during the acknowledge clock period to indicate acknowledgment. When this acknowledgment occurs, the master transmits the next byte of the sequence. Each device is addressed by a unique 7-bit slave address plus R/W bit (1 byte). All compatible devices share the same signals via a bidirectional bus using a wired-AND connection. An external pull-up resistor must be used for the SDA and SCL signals to set the logic high level for the bus. When the bus level is 5 V, use pull-up resistors between 1 kΩ and 2 kΩ. 8- Bit Data for Register (N) 8- Bit Data for Register (N+1) Figure 31. Typical I2C Sequence There is no limit on the number of bytes that can be transmitted between start and stop conditions. When the last word transfers, the master generates a stop condition to release the bus. A generic data transfer sequence is shown in Figure 31. SINGLE-AND MULTIPLE-BYTE TRANSFERS The serial control interface supports both single-byte and multi-byte read/write operations for all registers. During multiple-byte read operations, the TPA2016D2 responds with data, one byte at a time, starting at the register assigned, as long as the master device continues to respond with acknowledgments. The TPA2016D2 supports sequential I2C addressing. For write transactions, if a register is issued followed by data for that register and all the remaining registers that follow, a sequential I2C write transaction has occurred. For I2C sequential write transactions, the register issued then serves as the starting point, and the amount of data subsequently transmitted, before a stop or start is transmitted, determines the number of registers written. SINGLE-BYTE WRITE As Figure 32 shows, a single-byte data write transfer begins with the master device transmitting a start condition followed by the I2C device address and the read/write bit. The read/write bit determines the direction of the data transfer. For a write data transfer, the read/write bit must be set to '0'. After receiving the correct I2C device address and the read/write bit, the TPA2016D2 responds with an acknowledge bit. Next, the master transmits the register byte corresponding to the TPA2016D2 internal memory address being accessed. After receiving the register byte, the TPA2016D2 again responds with an acknowledge bit. Next, the master device transmits the data byte to be written to the memory address being accessed. After receiving the register byte, the TPA2016D2 again responds with an acknowledge bit. Finally, the master device transmits a stop condition to complete the single-byte data write transfer. Start Condition Acknowledge A6 A5 A4 A3 A2 A1 I2C Device Address and Read/Write Bit A0 R/W ACK A7 Acknowledge A6 A5 A4 A3 A2 A1 A0 ACK D7 Register Acknowledge D6 D5 D4 D3 Data Byte D2 D1 D0 ACK Stop Condition Figure 32. Single-Byte Write Transfer 20 Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s): TPA2016D2 TPA2016D2 www.ti.com ............................................................................................................................................................. SLOS524B – JUNE 2008 – REVISED JUNE 2008 MULTIPLE-BYTE WRITE AND INCREMENTAL MULTIPLE-BYTE WRITE A multiple-byte data write transfer is identical to a single-byte data write transfer except that multiple data bytes are transmitted by the master device to the TPA2016D2 as shown in Figure 33. After receiving each data byte, the TPA2016D2 responds with an acknowledge bit. Register Figure 33. Multiple-Byte Write Transfer SINGLE-BYTE READ As Figure 34 shows, a single-byte data read transfer begins with the master device transmitting a start condition followed by the I2C device address and the read/write bit. For the data read transfer, both a write followed by a read are actually executed. Initially, a write is executed to transfer the address byte of the internal memory address to be read. As a result, the read/write bit is set to a '0'. After receiving the TPA2016D2 address and the read/write bit, the TPA2016D2 responds with an acknowledge bit. The master then sends the internal memory address byte, after which the TPA2016D2 issues an acknowledge bit. The master device transmits another start condition followed by the TPA2016D2 address and the read/write bit again. This time the read/write bit is set to '1', indicating a read transfer. Next, the TPA2016D2 transmits the data byte from the memory address being read. After receiving the data byte, the master device transmits a not-acknowledge followed by a stop condition to complete the single-byte data read transfer. Repeat Start Condition Start Condition Acknowledge A6 A5 A1 A0 R/W ACK A7 I2C Device Address and Read/Write Bit Acknowledge A6 A5 A4 A0 ACK Not Acknowledge Acknowledge A6 A5 A1 A0 R/W ACK D7 D6 I2C Device Address and Read/Write Bit Register D1 D0 ACK Stop Condition Data Byte Figure 34. Single-Byte Read Transfer MULTIPLE-BYTE READ A multiple-byte data read transfer is identical to a single-byte data read transfer except that multiple data bytes are transmitted by the TPA2016D2 to the master device as shown in Figure 35. With the exception of the last data byte, the master device responds with an acknowledge bit after receiving each data byte. Repeat Start Condition Start Condition Acknowledge A6 A0 R/W ACK A7 I2C Device Address and Read/Write Bit Acknowledge A6 A5 Register A0 ACK Acknowledge A6 A0 R/W ACK D7 I2C Device Address and Read/Write Bit Acknowledge D0 ACK D7 First Data Byte Acknowledge Not Acknowledge D0 ACK D7 D0 ACK Other Data Bytes Last Data Byte Stop Condition Figure 35. Multiple-Byte Read Transfer 21 Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s): TPA2016D2 TPA2016D2 SLOS524B – JUNE 2008 – REVISED JUNE 2008 ............................................................................................................................................................. www.ti.com Register Map Table 3. TPA2016D2 Register Map Register Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 1 SPK_EN_R SPL_EN_L SWS FAULT_R FAULT_L Thermal 1 NG_EN 2 0 0 ATK_time [5] ATK_time [4] ATK_time [3] ATK_time [2] ATK_time [1] ATK_time [0] 3 0 0 REL_time [5] REL_time [4] REL_time [3] REL_time [2] REL_time [1] REL_time [0] 4 0 0 Hold_time [5] Hold_time [4] Hold_tme [3] Hold_time [2] Hold_time [1] Hold_time [0] 5 0 0 FixedGain [5] FixedGain [4] FixedGain [3] FixedGain [2] FixedGain [1] FixedGain [0] 6 Output Limiter Disable NoiseGate Threshold [1] NoiseGate Threshold [2] Output Limiter Level [4] Output Limiter Level [3] Output Limiter Level [2] Output Limiter Level [1] Output Limiter Level [0] 7 Max Gain [3] Max Gain [2] Max Gain [1] Max Gain [0] 0 0 Compression Ratio [1] Compression Ratio [0] The default register map values are given in Table 4. Table 4. TPA2016D2 Default Register Values Table Register 0x01 0x02 0x03 0x04 0x05 0x06 0x07 Default C3h 05h 0Bh 00h 06h 3Ah C2h Any register above address 0x08 is reserved for testing and should not be written to because it may change the function of the device. If read, these bits may assume any value. Some of the default values can be reprogrammed through the I2C interface and written to the EEPROM. This function is useful to speed up the turn-on time of the device and minimizes the number of I2C writes. If this is required, contact your local TI representative. The TPA2016D2 I2C address is 0xB0 (binary 10110000) for writing and 0xB1 (binary 10110001) for reading. If a different I2C address is required, please contact your local TI representative. See the General I2C operation section for more detail. The following tables show the details of the registers, the default values, and the values that can be programmed through the I2C interface. 22 Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s): TPA2016D2 TPA2016D2 www.ti.com ............................................................................................................................................................. SLOS524B – JUNE 2008 – REVISED JUNE 2008 IC FUNCTION CONTROL (Address: 1) REGISTER ADDRESS I2C BIT 01 (01H) – IC Function Control LABEL DEFAULT DESCRIPTION 7 SPK_EN_R 1 (enabled) Enables right amplifier 6 SPK_EN_L 1 (enabled) Enables left amplifier 5 SWS 0 (enabled) Shutdown IC when bit = 1 4 FAULT_R 0 Changes to a 1 when there is a short on the right channel. Reset by writing a 0. 3 FAULT_L 0 Changes to a 1 when there is a short on the left channel. Reset by writing a 0 2 Thermal 0 Changes to a 1 when die temperature is above 150°C 1 UNUSED 1 0 NG_EN 1 (enabled) Enables Noise Gate function SPK_EN_R: Enable bit for the right-channel amplifier. Amplifier is active when bit is high. This function is gated by thermal and returns once the IC is below the threshold temperature. SPK_EN_L: Enable bit for the left-channel amplifier. Amplifier is active when bit is high. This function is gated by thermal and returns once the IC is below the threshold temperature SWS: Software shutdown control. The device is in software shutdown when the bit is '1' (control, bias and oscillator are inactive). When the bit is '0' the control, bias and oscillator are enabled. Fault_L: This bit indicates that an over-current event has occurred on the left channel with a '1'. This bit is cleared by writing a '0' to it. Fault_R: This bit indicates that an over-current event has occurred on the right channel with a '1'. This bit is cleared by writing a '0' to it. Thermal: This bit indicates a thermal shutdown that was initiated by the hardware with a '1'. This bit is deglitched and latched, and can be cleared by writing a '0' to it. NG_EN: Enable bit for the Noise Gate function. This function is enabled when this bit is high. This function can only be enabled when the Compression ratio is not 1:1. AGC ATTACK CONTROL (Address: 2) REGISTER ADDRESS 02 (02H) – AGC Control I2C BIT LABEL DEFAULT 7:6 Unused 00 5:0 ATK_time 000101 (6.4 ms/6 dB) DESCRIPTION AGC Attack time (gain ramp down) Per Step Per 6 dB 90% Range 000001 0.1067 ms 1.28 ms 5.76 ms 000010 0.2134 ms 2.56 ms 11.52 ms 000011 0.3201 ms 3.84 ms 17.19 ms 000100 0.4268 ms 5.12 ms 23.04 ms (time increases by 0.1067 ms with every step) 111111 ATK_time 6.722 ms 80.66 ms 362.99 ms These bits set the attack time for the AGC function. The attack time is the minimum time between gain decreases. 23 Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s): TPA2016D2 TPA2016D2 SLOS524B – JUNE 2008 – REVISED JUNE 2008 ............................................................................................................................................................. www.ti.com AGC RELEASE CONTROL (Address: 3) REGISTER ADDRESS I2C BIT 03 (03H) – AGC Release Control 7:6 Unused 00 5:0 REL_time 001011 (1.81 sec/6 dB) LABEL DEFAULT DESCRIPTION AGC Release time (gain ramp down) Per Step Per 6 dB 90% Range 000001 0.0137 s 0.1644 s 0.7398 s 000010 0.0274 s 0.3288 s 1.4796 s 000011 0.0411 s 0.4932 s 2.2194 s 000100 0.0548 s 0.6576 s 2.9592 s (time increases by 0.0137 s with every step) 111111 REL_time 0.8631 s 10.36 s 46.6 s These bits set the release time for the AGC function. The release time is the minimum time between gain increases. AGC HOLD TIME CONTROL (Address: 4) REGISTER ADDRESS I2C BIT 04 (04H) – AGC Hold Time Control 7:6 Unused 00 5:0 Hold_time 000000 (Disabled) LABEL DEFAULT DESCRIPTION AGC Hold time Per Step 000000 Hold Time Disable 000001 0.0137 s 000010 0.0274 s 000011 0.0411 s 000100 0.0548 s (time increases by 0.0137 s with every step) 111111 Hold_time 0.8631 s These bits set the hold time for the AGC function. The hold time is the minimum time between a gain decrease (attack) and a gain increase (release). The hold time can be deactivated. 24 Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s): TPA2016D2 TPA2016D2 www.ti.com ............................................................................................................................................................. SLOS524B – JUNE 2008 – REVISED JUNE 2008 AGC FIXED GAIN CONTROL (Address: 5) REGISTER ADDRESS 05 (05H) – AGC Fixed Gain Control I2C BIT LABEL DEFAULT 7:6 Unused 00 5:0 Fixed Gain 00110 (6dB) DESCRIPTION Sets the fixed gain of the amplifier: two's compliment Gain 100100 –28 dB 100101 –27 dB 100110 –26 dB (gain increases by 1 dB with every step) 111101 –3 dB 111110 –2 dB 111111 –1 dB 000000 0 dB 000001 1 dB 000010 2 dB 000011 3 dB (gain increases by 1dB with every step) Fixed Gain 011100 28 dB 011101 29 dB 011110 30 dB These bits are used to select the fixed gain of the amplifier. If the Compression is enabled, fixed gain is adjustable from –28dB to 30dB. If the Compression is disabled, fixed gain is adjustable from 0dB to 30dB. 25 Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s): TPA2016D2 TPA2016D2 SLOS524B – JUNE 2008 – REVISED JUNE 2008 ............................................................................................................................................................. www.ti.com AGC CONTROL (Address: 6) REGISTER ADDRESS 06 (06H) – AGC Control I2C BIT 7 6:5 LABEL DEFAULT DESCRIPTION Output Limiter Disable 0 (enable) Disables the output limiter function. Can only be disabled when the AGC compression ratio is 1:1 (off) NoiseGate Threshold 01 (4mVrms) Select the threshold of the noise gate Threshold 00 4:0 Output Limiter Level 11010 (6.5dBV) 1 mVrms 01 4 mVrms 10 10 mVrms 11 20 mVrms Output Power (Wrms) Peak Output Voltage (Vp) dBV 00000 0.03 0.67 –6.5 00001 0.03 0.71 –6 00010 0.04 0.75 –5.5 Selects the output limiter level (Limiter level increases by 0.5dB with every step) 11101 0.79 3.55 8 11110 0.88 3.76 8.5 11111 0.99 3.99 9 Output Limiter Disable This bit disables the output limiter function when set to 1. Can only be disabled when the AGC compression ratio is 1:1 NoiseGate Threshold These bits set the threshold level of the noise gate. NoiseGate Threshold is only functional when the compression ratio is not 1:1 Output Limiter Level These bits select the output limiter level. Output Power numbers are for 8Ω load. AGC CONTROL (Address: 7) REGISTER ADDRESS 07 (07H) – AGC Control I2C BIT 7:4 LABEL Max Gain DEFAULT 1100 (30 dB) DESCRIPTION Selects the maximum gain the AGC can achieve Gain 0000 18 dB 0001 19 dB 0010 20 dB (gain increases by 1 dB with every step) 3:2 Unused 00 1:0 Compression Ratio 10 (4:1) 1100 30 dB 00 1:1 (off) 01 2:1 10 4:1 11 8:1 Selects the compression ratio of the AGC Ratio Compression Ratio These bits select the compression ratio. Output Limiter is enabled by default when the compression ratio is not 1:1. Max Gain These bits select the maximum gain of the amplifier. In order to maximize the use of the AGC, set the Max Gain to 30dB 26 Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s): TPA2016D2 TPA2016D2 www.ti.com ............................................................................................................................................................. SLOS524B – JUNE 2008 – REVISED JUNE 2008 DECOUPLING CAPACITOR S) The TPA2016D2 is a high-performance Class-D audio amplifier that requires adequate power supply decoupling to ensure the efficiency is high and total harmonic distortion (THD) is low. For higher frequency transients, spikes, or digital hash on the line, a good low equivalent-series-resistance (ESR) 1-µF ceramic capacitor (typically) placed as close as possible to the device PVDD (L, R) lead works best. Placing this decoupling capacitor close to the TPA2016D2 is important for the efficiency of the Class-D amplifier, because any resistance or inductance in the trace between the device and the capacitor can cause a loss in efficiency. For filtering lower-frequency noise signals, a 4.7 µF or greater capacitor placed near the audio power amplifier would also help, but it is not required in most applications because of the high PSRR of this device. INPUT CAPACITORS I) The input capacitors and input resistors form a high-pass filter with the corner frequency, fC, determined in Equation 5. 1 fC = (2p ´ RI ´ CI ) (5) The value of the input capacitor is important to consider as it directly affects the bass (low frequency) performance of the circuit. Speakers in wireless phones cannot usually respond well to low frequencies, so the corner frequency can be set to block low frequencies in this application. Not using input capacitors can increase output offset. Equation 6 is used to solve for the input coupling capacitance. If the corner frequency is within the audio band, the capacitors should have a tolerance of ±10% or better, because any mismatch in capacitance causes an impedance mismatch at the corner frequency and below. 1 CI = (2p ´ RI ´ fC ) (6) BOARD LAYOUT In making the pad size for the WCSP balls, it is recommended that the layout use non solder mask defined (NSMD) land. With this method, the solder mask opening is made larger than the desired land area, and the opening size is defined by the copper pad width. Figure 36 and Table 5 shows the appropriate diameters for a WCSP layout. The TPA2016D2 evaluation module (EVM) layout is shown in the next section as a layout example. 27 Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s): TPA2016D2 TPA2016D2 SLOS524B – JUNE 2008 – REVISED JUNE 2008 ............................................................................................................................................................. www.ti.com Figure 36. Land Pattern Dimensions Table 5. Land Pattern Dimensions (1) (1) (2) (3) (4) (5) (6) (7) SOLDER PAD DEFINITIONS COPPER PAD SOLDER MASK (5) OPENING COPPER THICKNESS Non solder mask defined (NSMD) 275 µm (+0.0, –25 µm) 375 µm (+0.0, –25 µm) 1 oz max (32 µm) (2) (3) (4) STENCIL (6) (7) OPENING 275 µm × 275 µm Sq. (rounded corners) STENCIL THICKNESS 125 µm thick Circuit traces from NSMD defined PWB lands should be 75 µm to 100 µm wide in the exposed area inside the solder mask opening. Wider trace widths reduce device stand off and impact reliability. Best reliability results are achieved when the PWB laminate glass transition temperature is above the operating the range of the intended application. Recommend solder paste is Type 3 or Type 4. For a PWB using a Ni/Au surface finish, the gold thickness should be less 0.5 mm to avoid a reduction in thermal fatigue performance. Solder mask thickness should be less than 20 µm on top of the copper circuit pattern Best solder stencil performance is achieved using laser cut stencils with electro polishing. Use of chemically etched stencils results in inferior solder paste volume control. Trace routing away from WCSP device should be balanced in X and Y directions to avoid unintentional component movement due to solder wetting forces. COMPONENT LOCATION Place all the external components very close to the TPA2016D2. Placing the decoupling capacitor, CS, close to the TPA2016D2 is important for the efficiency of the Class-D amplifier. Any resistance or inductance in the trace between the device and the capacitor can cause a loss in efficiency. TRACE WIDTH Recommended trace width at the solder balls is 75 µm to 100 µm to prevent solder wicking onto wider PCB traces. For high current pins (PVDD (L, R), PGND, and audio output pins) of the TPA2016D2, use 100-µm trace widths at the solder balls and at least 500-µm PCB traces to ensure proper performance and output power for the device. For the remaining signals of the TPA2016D2, use 75-µm to 100-µm trace widths at the solder balls. The audio input pins (INR± and INL±) must run side-by-side to maximize common-mode noise cancellation 28 Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s): TPA2016D2 TPA2016D2 www.ti.com ............................................................................................................................................................. SLOS524B – JUNE 2008 – REVISED JUNE 2008 EFFICIENCY AND THERMAL INFORMATION The maximum ambient temperature depends on the heat-sinking ability of the PCB system. The derating factor for the packages are shown in the dissipation rating table. Converting this to θJA for the WCSP package: 100°C/W (7) Given θJA of 100°C/W, the maximum allowable junction temperature of 150°C, and the maximum internal dissipation of 0.4 W (0.2 W per channel) for 1.5 W per channel, 8-Ω load, 5-V supply, from Figure 14, the maximum ambient temperature can be calculated with the following equation. TA Max = TJMax - qJA PDMAX = 150 - 100 (0.4) = 110°C (8) Equation 8 shows that the calculated maximum ambient temperature is 110°C at maximum power dissipation with a 5-V supply and 8-Ω a load. The TPA2016D2 is designed with thermal protection that turns the device off when the junction temperature surpasses 150°C to prevent damage to the IC. Also, using speakers more resistive than 8-Ω dramatically increases the thermal performance by reducing the output current and increasing the efficiency of the amplifier. OPERATION WITH DACS AND CODECS In using Class-D amplifiers with CODECs and DACs, sometimes there is an increase in the output noise floor from the audio amplifier. This occurs when mixing of the output frequencies of the CODEC/DAC mix with the switching frequencies of the audio amplifier input stage. The noise increase can be solved by placing a low-pass filter between the CODEC/DAC and audio amplifier. This filters off the high frequencies that cause the problem and allow proper performance. See the functional block diagram. FILTER FREE OPERATION AND FERRITE BEAD FILTERS A ferrite bead filter can often be used if the design is failing radiated emissions without an LC filter and the frequency sensitive circuit is greater than 1 MHz. This filter functions well for circuits that just have to pass FCC and CE because FCC and CE only test radiated emissions greater than 30 MHz. When choosing a ferrite bead, choose one with high impedance at high frequencies, and low impedance at low frequencies. In addition, select a ferrite bead with adequate current rating to prevent distortion of the output signal. Use an LC output filter if there are low frequency (< 1 MHz) EMI sensitive circuits and/or there are long leads from amplifier to speaker. Figure 37 shows typical ferrite bead and LC output filters. Ferrite Chip Bead OUTP 1 nF Ferrite Chip Bead OUTN 1 nF Figure 37. Typical Ferrite Bead Filter (Chip bead example: TDK: MPZ1608S221A) 29 Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s): TPA2016D2 PACKAGE OPTION ADDENDUM www.ti.com 30-Jun-2008 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Eco Plan (2) Qty TPA2016D2RGPR PREVIEW QFN RGP 20 3000 TBD Call TI Call TI TPA2016D2RGPT PREVIEW QFN RGP 20 250 TBD Call TI Call TI TPA2016D2YZHR ACTIVE DSBGA YZH 16 3000 Green (RoHS & no Sb/Br) SnAgCu Level-1-260C-UNLIM TPA2016D2YZHT ACTIVE DSBGA YZH 16 250 SnAgCu Level-1-260C-UNLIM Green (RoHS & no Sb/Br) Lead/Ball Finish MSL Peak Temp (3) (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. 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Addendum-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 17-Jun-2008 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel Diameter Width (mm) W1 (mm) TPA2016D2YZHR DSBGA YZH 16 3000 178.0 TPA2016D2YZHT DSBGA YZH 16 250 178.0 A0 (mm) B0 (mm) K0 (mm) P1 (mm) 8.4 2.18 2.18 0.81 4.0 8.0 Q1 8.4 2.18 2.18 0.81 4.0 8.0 Q1 Pack Materials-Page 1 W Pin1 (mm) Quadrant PACKAGE MATERIALS INFORMATION www.ti.com 17-Jun-2008 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) TPA2016D2YZHR DSBGA YZH 16 3000 217.0 193.0 35.0 TPA2016D2YZHT DSBGA YZH 16 250 217.0 193.0 35.0 Pack Materials-Page 2 D: Max = 2160 µm, Min = 2100 µm E: Max = 2137 µm, Min = 2077 µm IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. 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