SLUS559B − APRIL 2003 − REVISED JULY 2004 D Load Overcurrent and Undercurrent FEATURES D Compliant to Power Over Ethernet IEEE D D D D D D D D 802.3af Standard Two-Point 25-kΩ Resistor Discovery Capacitive Detection for Non-Compliant Legacy Loads Power Classification Controlled di/dt Ramp Power-Up and Power-Down for EMI Reduction Current Management for Charging Powered Device Bulk Capacitance Electronic Circuit Breaker Fault detection Input Undervoltage Lockout (UVLO) D D D D D D D D Detection 12-Bit Port Current and Voltage Acquisition Standard Slave I2C Serial Interface 5-Bit Serial Address Selectability Discovery and/or Classification Bypass Modes Selectable Via Register Opto-Coupler Compatible SDA and SCL Lines for System Ground Isolation Dual Color LED Driver for Port Status Hardware FAULT Interrupt Single +48-V Supply Capable APPLICATIONS D PoE Switches D Mid-Span Injectors APPLICATION DIAGRAM SWITCH/HUB CT Choke POWERED DTR RJ−45 w/grn 1 TX 2 CT Choke 3 RX 6 4 RJ−45 w/grn 1 grn grn w/org w/org org org blue blue CT Choke RX 2 3 CT Choke TX 6 4 PPTC Fuse TPS2383 PSE P (1 Port) N V48 GND 5 7 w/blue w/blue w/brn w/brn brn G 8 RS 568A brn 5 7 PD Signature 8 PD DC/DC Supply 568A Up to 350 feet of category 5 cable RG Optically Coupled I2C Serial Bus + 48−V Supply − MSP430 Controller UDG−03061 ! "#$ %!& % "! "! '! ! !( ! %% )*& % "!+ %! !!$* $%! !+ $$ "!!& Copyright 1999 − 2004, Texas Instruments Incorporated www.ti.com 1 SLUS559B − APRIL 2003 − REVISED JULY 2004 DESCRIPTION The TPS2383 family of products are power sourcing equipment power managers (PSEPM) that are compliant to the power-over-ethernet (PoE) IEEE 802.3af Standard. A PSEPM port can discover, classify and deliver power to a powered device (PD) capable of accepting PoE twisted pair cable. The TPS2383 is fully programmable by the user. This allows for the detection and powering of both fully compliant 802.3 devices as well as custom detection of legacy devices. The TPS2383 PSEPM can individually manage power for up to eight ethernet ports. All operations of the TPS2383 are controlled through register read and write operations over a standard (slave) I2C serial interface. The TPS2383 has dual SDA lines to allow easy application of opto-coupler circuitry to maintain ethernet port isolation when a ground based controller is used. Each TPS2383 has five selection pins making it possible to address up to 32 devices on the I2C bus and allows individual control and monitoring of up to 256 ethernet ports from a single master I2C controller. Per-port write registers initiate and manipulate the flow of the discovery, classification, and power-up states while the read registers contain status information of the enable process, faults, classification value, and real time port operating current and voltage. Per-port status LED drivers are provided which can be manually controlled through the serial I/O. The TPS2383 is available in a full function 64-pin LQFP. External N-channel MOSFETs switch port power. High-voltage (HV) gate drive ensures that these FETs are fully enhanced, resulting in lower power dissipation and enabling the use of lower costs FETs. The TPS2383 generates its HV gate supply from the 48-V port power, simplifying system power supply design. An external 3.3-V digital supply is also used. This supply can be active when 48-V power is not present which allows the user to access the part through the serial I/O in this case. A 5-V analog supply is used to power port LEDs and internal analog functions. Due to the very low quiescent current, both the 3.3-V and 5-V supply can be generated from the +48-V power bus with minimal external components. An internal power-on-reset (POR) circuit with an ORed external input pin resets all registers positions to a known safe state upon power up. 2 www.ti.com SLUS559B − APRIL 2003 − REVISED JULY 2004 These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. ABSOLUTE MAXIMUM RATINGS over operating free-air temperature range unless otherwise noted(1) TPS2383 Input voltage range, VCC UNIT V48, 1P, 2P, 3P, 4P, 5P, 6P, 7P, 8P, 1N, 2N, 3N, 4N, 5N, 6N, 7N, 8N −0.5 to 65 1RS, 2RS, 3RS, 4RS, 5RS, 6RS, 7RS, 8RS, 1G, 2G, 3G, 4G, 5G, 6G, 7G, 8G −0.5 to 12 VL −0.5 to 3.9 V5 −0.5 to 6 SCL_I, SDA_I, SDA_O, INTB, A1, A2, A3, A4, A5, EN, PORB V −0.5 to 6 Storage temperature, Tstg −55 to 150 Operating temperature, TJ 0 to 70 °C C Lead temperature, Tsol, 1,6 mm (1/16 inch) from case for 10 seconds 260 (1) Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. All voltages are with respect to GND. Currents are positive into and negative out of, the specified terminal. RECOMMENDED OPERATING CONDITIONS MIN Input voltage, VV48 44 Operating junction temperature, TJ 0 NOM MAX UNIT 48 57 V 70 °C MAX UNIT ELECTROSTATIC DISCHARGE (ESD) PROTECTION Human body model 1.5 CDM 1 Machine model kV 0.2 ORDERING INFORMATION PACKAGED DEVICES(2) TA LQFP−64 (PM) 0°C to 70°C TPS2383PM (2) The PM package is available taped and reeled. Add R suffix to device type (e.g.TPS2383PMR) to order quantities of 2,500 devices per reel. www.ti.com 3 SLUS559B − APRIL 2003 − REVISED JULY 2004 ELECTRICAL CHARACTERISTICS VV48= 48 V, RT = 120 kΩ, 0°C to 70°C, and TA = TJ (unless otherwise noted) TEST CONDITIONS PARAMETER MIN TYP MAX UNIT POWER SUPPLIES Quiescent current, V48 Off mode (all ports) 3 5 Powered mode (all ports) 5 10 3 15 Quiescent current, V5 Powered mode (all ports), Quiescent current, VL Powered mode (all ports), VV5 = 5 V VVL = 3.3 V Internal analog supply, V10 Internal reference(1) Input UVLO Internal POR timeout (I2C) After all supplies are good (8 CLK periods) Internal POR timeout (state machine) After all supplies are good (65536 CLK periods) 0.28 4 9.75 10.50 11.50 2.475 2.500 2.525 28 37 40 mA V 8 CLKs 65536 LED OUTPUTS High-level output voltage, L1 through L8 Low-level output voltage, L1 through L8 Tri−state leakage(1) ISRC = 5 mA ISINK = 5 mA 4 0.75 V µA 0.1 ANALOG CIRCUITS − PORT VOLTAGE CONTROL LOOP Input resistance, nP to nN 240 400 15.0 17.5 Discovery voltage, high 7.5 Discovery voltage, low 3.5 Classification voltage A/B select = B Loop power supply feedthru loop control range C(1) 640 kΩ 8.8 9.5 V 4.4 5.5 1.5 Discovery short-circuit current mV 3 Port output, undervoltage 40 42 44 Port output, overvoltage 51 53 55 Classification current limit ClassLimit1 = 0, ClassLimit2 = 0 160 ClassLimit1 = 1, ClassLimit2 = 0 80 ClassLimit1 = 0, ClassLimit2 = 1 40 ClassLimit1 = 1, ClassLimit2 = 1 20 mA V mA N-CHANNEL MOSFET GATE CONTROL Gate turn-off MOSFET RDS(on) Maximum gate voltage 8 10 Gate turn-off delay time from overcurrent fault Gate turn-off timer from UV/OV fault After port enabled and ramped up, (1024 CLK periods) UV/OV spike timer, power quality warning(1) (256 CLK periods) Gate turn-off timer from overload fault (32768 CLK periods) NOTE: (1) Ensured by design. Not production tested. 4 Ω 200 www.ti.com 12 V 7.5 µs 1024 256 32768 CLKs SLUS559B − APRIL 2003 − REVISED JULY 2004 ELECTRICAL CHARACTERISTICS VV48= 48 V, RT = 120 kΩ, 0°C to 70°C, and TA = TJ (unless otherwise noted) TEST CONDITIONS MIN TYP MAX Overload threshold voltage 165 187 207 Peak current threshold voltage 175 213 250 50 100 Reset voltage, CINT 10 100 Maximum swing, CR 4.5 6.0 Input leakage, nRS 10 PARAMETER UNIT LOW-SIDE CURRENT-SENSE Overload timout Maximum swing, CINT ANALOG-TO-DIGITAL CONVERTER A/D resistive scaling(1) 9 RRD = 1 kΩ 11 Referenced to port #1 RRS = 0.5 Ω 35 A/D load current scaling(1) A/D load voltage scaling(1) RRS = 0.5 Ω 4.72 −5% 0% ILOAD = 50 mA, ILOAD = 300 mA, A/D port voltage conversion VPORT = 5 V VPORT = 45 V RRS = 0.5 Ω 236 RRS = 0.5 Ω 1416 V mV V count/kΩ 5% count/mA 33.6 A/D load current conversion ms µA 72 Port-to-port resistance variation A/D classificatin scaling(1) mV count/V count 168 1512 DIGITAL I/O Logic input threshold voltage, SCL, SDA_I, A1 through A5, EN, PORB 1.5 Input hysteresis, SCL, SDA_I 250 Input hysteresis, EN, PORB 150 Input pull-down resistance, EN, PORB V mV 50 Pull-up current, A0, A1, A2, A3, A4, A5 10 kΩ 25 Drain = 6 V Logic low output voltage, SDA_O ISINK = 3 mA Drain = 6 V 200 10 µA ISINK = 3 mA 200 mV Logic high leakage, INTB Logic low output voltage, INTB DIGITAL I/O TIMING I2C CHARACTERISTICS 10 µA A Logic high leakage, SDA_O Clock frequency, SCL Pulse duration 0 SCL high 1.3 SCL low 0.6 Rise time, SCL, SDA(1) Fall time, SCL, SDA(1) mV 400 kHz µss 300 300 Setup time SDA to SCL 250 Hold time SCL to SDA ns 0 Bus free time between startup and stop 1.3 Setup time SCL to start condition 0.6 Hold time start condition to SCL 0.6 Setup time, SCL to stop condition 0.6 µss NOTE: (1) Ensured by design. Not production tested. www.ti.com 5 SLUS559B − APRIL 2003 − REVISED JULY 2004 TERMINAL FUNCTIONS TERMINAL NAME PIN I/O DESCRIPTION POWER AND GROUND AG1 26 I Analog ground 1. Analog ground of the V5, V10 and V48 power systems. It should be externally tied to the common copper 48-V return plane. This pin should carry the low side of two de-coupling capacitors tied to V48 and V10 AG2 51 I Analog ground 2. Analog ground, which ties to the substrate and ESD of the device. It should be externally tied to the common copper 48-V return plane. AG1 and AG2 must be tied together directly for lowest noise operation. DG 56 I Digital ground. It connects to the internal logic ground bus. It should be externally tied to the common copper 48V return plane. In addition a 0.1uF de−coupling capacitor should terminate as close to this node and the VL pin as possible. RG 29 I Reference ground. A precision sense of the external ground plane. It should also be used as the ground guard ring for the integration capacitor (CINT). It should be the closest ground to the low side of the 0.5-Ω current sense resistors, as well as RD, CINT, and RT. It should tie to common copper 48-V return plane. V10 28 O +10V analog supply.Connects to the internal analog power bus. This voltage is generated internally. This pin should not be tied to any external supplies. A 0.1-µF de-coupling capacitor should terminate as close to this node and the AG2 pin as possible. This pin can be used for external generation of V5. V48 27 I +48V input to the device. This supply can have a range of 44 V to 57 V. This pin should be de-coupled with a 0.1-µF capacitor from V48 to AG2 placed as close to the device as possible. V5 25 I External +5V analog supply.Connects to the internal analog power bus. This supplies the LED output drivers and internal analog circuits. A 0.1-µF de-coupling capacitor should terminate as close to this node and the AG1 pin as possible. VL 54 I External +3.3V logic supply. This pin connects to the internal logic power bus. This is the supply voltage for the internal device logic. A 0.1-µF de-coupling capacitor should terminate as close to this node and the DG pin as possible. This pin can be powered from V5 by using a 4.22-kΩ resistor from V5 to VL.. PORT ANALOG SIGNALS 6 1P 1 I 2P 8 I 3P 9 I 4P 16 I 5P 33 I 6P 40 I 7P 41 I 8P 48 I 1N 2 I 2N 7 I 3N 10 I 4N 15 I 5N 34 I 6N 39 I 7N 42 I 8N 47 I Port positive. +48V load sense pin. Terminal voltage is monitored and controlled differentially with respect to nN. Optionally, if the application warrants it, this high-side path can be protected with the use of a self-resetting poly fuse. Port negative. −48V load return sense pin. The low side of the load is switched and protected with the external N-channel MOSFET. www.ti.com SLUS559B − APRIL 2003 − REVISED JULY 2004 TERMINAL FUNCTIONS (continued) TERMINAL NAME PIN I/O DESCRIPTION PORT ANALOG SIGNALS (continued) 1G 3 O 2G 6 O 3G 11 O 4G 14 O 5G 35 O 6G 38 O 7G 43 O 8G 46 O 1RS 4 I 2RS 5 I 3RS 12 I 4RS 13 I 5RS 36 I 6RS 37 I 7RS 44 I 8RS 45 I Port gate. Connect to the gate of an external N-channel MOSFET. During turn-on, this pin is controlled by a linear current amplifier (LCA) such that the load current ramps up from zero to a maximum sourcing current of 425 mA. This pin is driven to as high as 10 V. During controlled turn-off, this pin is driven such that the load current ramps down from a maximum of 425 mA to zero. The capacitor on the CR pin is utilized to generate the ramp control signal voltages. During a fault turn-off this pin is discharged quickly with a low on-resistance internal switch. Port resistor sense. This is the kelvin sense path for the high potential end of the load current sense resistor. Parameters controlled by the load current sense resistor include: the average undercurrent/overcurrent and peak-load current thresholds, the peak PD inrush current limit during startup, and the nominal classification current levels. Use a 0.5-Ω load current sense resistor to be compliant to the 802.3 specification levels. ANALOG SIGNALS CR 50 I Ramp capacitor. During load power up and down, this capacitor is used as the di/dt current slew capacitor. A 1.5-V peak triangular waveform is present on this pin during ramp up/down. Connect a 0.1-µF capacitor from this pin to AG2 and a 120-kΩ resistor at RT to meet the 802.3af specification timing levels. CT 52 I Timing capacitor. This capacitor and the resistor on the RT pin set the internal clock frequency of the device. This clock is used for the internal state machine, integrating A/D counters, POR time-out, and fault and delay timers of each port. Use a 100-pF to 470-pF capacitor for CT and a 120-kΩ resistor on RT to set the internal clock in a range of 100 kHz to 500 kHz. This timing can be overridden by driving the CT pin with a 0 V to 5 V square wave with a frequency from 0 kHz to 500 kHz. CINT 30 I This capacitor is used for the ramp A/D converter signal integration. Connect a 0.033-µF capacitor from this pin to RG. For minimal errors due to dielectric absorption, use a poly or Teflon capacitor type. Ceramic types can be used, but note the increased conversion error. L1 17 O L2 18 O L3 19 O L4 20 O L5 21 O L6 22 O L7 23 O L8 24 O RD 32 I The discovery current-sense resistor is connected in the path from the RD pin to RG ground. The discovery current-sense resistor sets the discovery value to 25-kΩ (nominal) when a 665-Ω value is used. For best noise performance, de-couple this pin with a 0.68-µF, ceramic capacitor to RG ground. RT 31 I Bias set resistor. This resistor sets all precision bias currents within the device. This pin is forced to an internal 1.25-V reference voltage level. The current that flows into this resistor due to the applied 1.25-V bias is replicated and used throughout the device. This resistor also works in conjunction with the capacitors on CR, CT and CINT to set internal timing values. Use a 120-kΩ resistor to be compliant to the requirements of 802.3af. LED lamp drivers. Dual or single color LEDs can be connected to each of these pins. Each pin indicates the state of the corresponding port. This is a tri-state port that is under full control of the host micro-controller. As such it can also be used as a data port, or general-purpose output driver. www.ti.com 7 SLUS559B − APRIL 2003 − REVISED JULY 2004 TERMINAL FUNCTIONS (continued) TERMINAL NAME PIN I/O DESCRIPTION DIGITAL SIGNALS A1 64 I A2 63 I A3 62 I A4 61 I A5 60 I EN 53 I This pin is normally to be held low. It has been reserved for future expansion of the TPS238x device family INTB 59 O PORB 49 I This is an open drain output that goes low if a fault condition is produced on any of the eight ports. This pin can be used to override the internal POR. When held low, the I2C interface, all the state machines, and registers are held in reset. When all internal and external supplies are within specification, and this pin is set to a logic high level, the POR delay begins. The I2C interface and registers becomes active within eight CLK periods of this event and communications to read or preset registers can begin. The reset delay for the remainder of the device then extinguishes within 65536 CLK periods. SCL_I 55 I SDA_I 58 I SDA_O 57 O Addresses 1 through 5. This is the I2C address select input. Select the appropriate binary address on these pins by connecting this pin to device ground for a logic low and tying this pin to the VL pin for a logic high. Serial clock input pin for the I2C interface. Serial data input pin for the I2C interface. When jumpered with the SDA_O pin, this connection becomes the standard bi-directional serial data line (SDA). Serial data open drain output for the I2C interface. When jumpered with the SDA_I pin, this connection becomes the standard bi-directional serial data line (SDA). This is a high-voltage open drain output that can drive opto-coupler LEDs directly from the +48-V bus with an external, series current limiting resistor. PACKAGE DESCRIPTION 1 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 2 47 3 46 4 45 5 44 6 43 7 42 8 41 9 40 10 39 11 38 12 37 13 36 14 35 15 34 33 16 1718 19 20 21 22 23 24 25 26 27 28 29 30 31 32 L1 L2 L3 L4 L5 L6 L7 L8 V5 AG1 V48 V10 RG CINT RT RD 1P 1N 1G 1RS 2RS 2G 2N 2P 3P 3N 3G 3RS 4RS 4G 4N 4P CR PORB A1 A2 A3 A4 A5 INTB SDA_I SDA_O DG SCL_I VL EN CT AG2 PM PACKAGE (TOP VIEW) 8 www.ti.com 8P 8N 8G 8RS 7RS 7G 7N 7P 6P 6N 6G 6RS 5RS 5G 5N 5P SLUS559B − APRIL 2003 − REVISED JULY 2004 FUNCTIONAL DESCRIPTION The TPS2383 architecture has been designed to work efficiently with simple low-cost controllers such as those in the MSP430 family of devices. Reference design and code examples for complete PSE management are available from TI for the TPS2383/MSP430 chipset solution. The PSEPM discovery method, as defined in the IEEE 802.3af Standard, uniquely identifies a powered device 25-kΩ resistor. Use of low-level probe signals during discovery prevents damage to non-802.3 devices. The use of a point-to-point slope detection method for the PD 25-kΩ resistor measurement allows accurate detection, even if series steering diodes are present at the PD. For legacy loads, capacitive detection can be enabled. In this mode the TPS2383 A/D is used to measure the loads capacitive value. After a successful discovery of the PD, the TPS2383 has a classification feature to identify the expected PD power level based on a current signature from the PD. The classification current level is measured at a reduced terminal voltage of 17.5 V and classified with 12 bits of resolution. The controller can then use this information to classify per the levels of the IEEE 802.3af standard or use levels custom to the application. Knowledge of the expected load power allows the power sourcing equipment to be built with a smaller and less expensive system power supply. For installations where classification is not needed, and reduced power-up time is desired, classification can be bypassed by setting the appropriate bits in the per-port write register. In classification and powered modes, the PSEPM drives an external low side N-channel MOSFET for control of the 48-V return line. The use of an external N-channel MOSFET enables selection of very low RDS(on) devices to minimize board power dissipation in enclosures that may be controlling 100’s of ports. Current sensing is performed with a low value resistor, again minimizing board power dissipation. In discovery mode, due to the very low current used, an internal N-channel MOSFET is utilized in conjunction with an external, high value, current sense resistor. The TPS2383 identifies all fault conditions defined in the PoE IEEE 802.3af Standard. The monitored conditions include input undervoltage lockout (UVLO), output undervoltage (UV) and overvoltage (OV), average and peak overcurrent detection, average undercurrent detection, and run current. If a fault condition is detected during power ramp or at any other time, the PSEPM circuit breaks by disconnecting the 48-V return line and then updates the fault status of the corresponding port register. When the TPS2383 is disabled the PSEPM ramps the current down at a controlled rate and the PSEPM changes states to a lower power sleep mode. To maintain full compliance to Underwriters Laboratory (UL), IEC950 SELV and NEMKO safety standards an optional, low cost self-resetting PTC fuse can be added to the unswitched +48-V line to protect the system supply and wiring infrastructure from secondary building wiring faults. When the PSEPM is enabled and a PD is discovered and optionally classified, power is ramped to the PD at a controlled current ramp rate to reduce EMI. Upon completion of the current ramp up, the port current remains limited at less than 400 mA. Upon startup the port can remain in current limit for a timed value of 50 ms which allows the bulk filter capacitance of the PD to charge. Once a PD is successfully powered and the external N-channel MOSFET is fully on, the average and peak current to the PD is continuously monitored. A disconnected load is detected if the average current falls below 10 mA. An overcurrent is detected if the average current exceeds 375 mA and/or the peak current exceeds 425 mA. If any of these conditions exist, status bits are set in the per-port read register set and the power is removed from the load. For maximum rejection of external wiring and power supply noise sources during the measurement of line current, voltage, resistance or capacitance in discovery, classification and powered modes, a proprietary low noise A/D converter is used. Converted measurements are processed and compared with digital set-points for limit compliance. The 12-bit conversion of this data-acquisition system is available through the read register enabling measurement of the discovery resistance, classification current and powered mode port running current and voltage. This is a valuable feature in ethernet switch management as it allows monitoring of real-time parameters across the system network. The TPS2383 is available in a full function 64 pin LQFP package. www.ti.com 9 SLUS559B − APRIL 2003 − REVISED JULY 2004 TPS2383 Evaluation Board The full performance features of the TPS2383/MSP430 chipset can be demonstrated with the TPS2383EVM−001 evaluation board. The TPS2383EVM−001 is a scaleable system that can be expanded to support 48 ports using a single microcontroller. This evaluation design can be used as a hardware/firmware template for modification to specific customer requirements. Please contact Texas Instruments or refer to the TPS2383EVM−001 Users Guide (SLUU168) for complete information. FUNCTIONAL BLOCK DIAGRAM TPS2383 Chip Power Supply Management PSE Port Section PSE PORT 8 PSE PORT 7 PSE PORT 6 PSE PORT 5 PSE PORT 4 PSE PORT 3 PSE PORT 2 PSE PORT 1 V48 ANALOG SUPPLY V10 WRITE REGISTER POR PORB PORT INTERFACE 4 Pins/Port (32 PINS) PORT PORT CONTROLLER MONITOR STATE and FET READ REGISTER MACHINE CONTROL INPUT UVLO INTERNAL ANALOG BUS V5 INTERNAL DIGITAL BUS VL RAMP STATE MACHINE POWER RAMP CONTROL LED DRIVERS MUX 12 BIT A/D A/D STATE MACHINE SCL VOLTAGE SDA_I REFERENCE 2 WIRE SERIAL IO SLAVE I2C CONTROLLER MASTER SEQUENCER STATE MACHINE CHIP BIAS SDA_O MAIN OSC and CLK ANALOG CONTROL LOGIC LED DRIVERS L1−L8 (8 PINS) FUTURE ENHANCEMENT INTB DEVICE ADDRESS and INTERRUPT A1 A2 A3 A4 A5 PORT ADDRESS PINS A1 − A5 10 EN CT GNDS (2 ANA PINS, 1 DIG PIN) www.ti.com RT RG CINT RD CR UDG−03062 SLUS559B − APRIL 2003 − REVISED JULY 2004 TPS2383 BLOCK DIAGRAM − SHARED PORT ANALOG RESOURCES Poly PTC Fuse BBR550, 90 V, 0.55 A +48 V 8 to 1 MUX C1 0.47 µF N Overload Timer NEGOUT 0.187 V 4 to 1 MUX 4 to 1 MUX P VUV Ramp State Machine Current Command Offset Correction + 12-bit A/D UV/OV Filter Port State Machine Voltage Control A/D State Machine CINT 0.033µF + + + 8 to 1 MUX Power to Ethernet XFMR POSOUT VOV + Discovery/ Class Spike Filter TPS2383 Port Resources TPS2383 Shared Resources A/B select A Linear Current B Controller 250 µA + 4 to 1 MUX 2 µA RS 1.5 V Rs 0.5 Overcurrent + 25 µA G 0.213 V + + 7-µs Digital Filter RG 8:1 1 of 8 channels 50 Fast Ramp 32 Slow Ramp 26 RD CR CR 0.1 µF AG1 RD 665 Ω CD 0.68 µF 51 AG2 48 V RTN UDG−03063 www.ti.com 11 SLUS559B − APRIL 2003 − REVISED JULY 2004 FUNCTIONAL DESCRIPTION SEPM STATE MACHINES The TPS2383 has circuit resources that are common to each port and circuit resources that are shared by all ports. Five independent state machines are used to control the common and shared PSEPM resources. Port control, UV/OV/OC and overload protection are all features that are common to each port. Data acquisition and power ramping are shared functions for all the ports. The master sequencer state machine is used to index the port presently being serviced and to distribute the shared resources to the currently selected port. The single master sequencer is responsible for incrementally accessing ports 1 through 8 and allowing those ports to process register data when they are accessed. Ports 1 through 8 each have a port sequencer, which controls all the power enabling and fault protection functions of the port per the register commands. The A/D has an A/D Sequencer that triggers, cycles and signals the port and master sequencer upon completion. The ramp sequencer controls the power ramping resource and is triggered by the port and master sequencer and provides a completion signal when power ramping is over. Upon power-up the master sequencer is enabled and running after a POR delay and begins acting on register commands. A shorter POR delay releases the reset on the I2C function and registers before the port reset is removed. This arrangement allows for register setup and polling over the I2C bus quickly upon power up but ensures that power cannot be applied until the power supply is fully energized and stable. The default power-up state for all command registers is a null condition. The state sequence order of the TPS2383 is discovery, classification and power delivery if a POE compliant device is detected on the other end of the data cable. The master sequencer powers-up in a default free-running mode. The TPS2383 also has a JOG mode. By setting the JOG_MODE register bit high, the master sequencer then no longer runs freely, but increments to the next sequential port each time the JOG register bit is set to a logic 1. The JOG bit is self-cleared once the port increments to the next position. Sequencing starts with port 1 and ends with port 8 and then repeats. The port sequencer signals status information to the master sequencer and skips over disabled ports. When the master sequencer detects an enabled port, it pauses at that port until discovery, classification and power-up is complete before proceeding to the next. When the master sequencer reaches a powered port, it pauses and take a reading of the ports run-time current and/or voltage before proceeding to the next port. When a powered PD load is disconnected, the disconnect event can be detected the next time that port is selected by the master sequencer. When the disable bit of a powered port is set in the corresponding register, that operation is completed the next time the master sequencer selects that port. An overcurrent fault event shuts down the offending port independent of any sequencer state. DUAL COLOR LED DRIVERS The LED driver pins (L1 through L8) can be used to drive single or dual, color LEDs. These LEDs are intended to provide installation or service personnel with the necessary information to install and troubleshoot the system infrastructure. The Ln pins have internal tri-state drivers. These LEDs can be controlled directly from the I2C registers. The reset state of all the LEDs is tri-state. Cross-conduction logic disables both internal high- and low-side MOSFETS if an attempt is made to enable both transistors on a given port. These are high current (10-mA) drivers that can be used for other applications such as the drive of optocouplers or electromechanical devices, or can just be used as an 8-bit data port. 12 www.ti.com SLUS559B − APRIL 2003 − REVISED JULY 2004 FUNCTIONAL DESCRIPTION I2C INTERFACE The serial interface used in the TPS2383 is a standard two-wire I2C slave architecture core. The standard bi-directional SDA lines of the I2C architecture are broken out into an independent input and output path. This feature simplifies, earth grounded, controller applications that require opto-isolators to keep the 48-V return of the ethernet power system floating. For applications where opto-isolation is not required, the bi-directional property of the SDA line can be restored by connecting SDA_I to SDA_O. The SCL line is a unidirectional input only line as the TPS2383 is always accesses as a slave device and it never controls the bus. Data transfers that require a data-flow reversal on the SDA line are four-byte operations. This occurs during a TPS2383 port read access cycle where a slave address byte is sent, followed by a port/register address byte write. A second slave address byte is sent followed by the data byte read using the port/register setup from the second byte in the sequence. Data write transfers to the TPS2383 do not require a data-flow reversal and as such only a three-byte operation is required. The sequence in this case is to send a slave address byte, followed by a write of the port/register address followed by a write of the data byte for the addressed port. The I2C access cycle consists of the following steps 1 through 7 and is also shown in Figure 4. 1. Start sequence (S) 2. Slave address field 3. Read/write 4. Acknowledge 5. Port/register address or data field 6. Acknowledge/not acknowledge 7. Stop sequence (P) The I2C interface and the port read write registers are held in active reset until input voltage is within specification and the internal POR timer has timed out. Start/Stop The high-to-low transition of SDA while SCL is high defines the start condition. The low-to-high transition of SDA while SCL is high defines the stop condition. The master device initiates all start and stop conditions. A first serial packet enclosed within start and stop bits, consists of a seven-bit address field, read/write bit, and the acknowledge bit. The acknowledge bit is always generated by the device receiving the address or data field. Five of the seven address bits are used by the TPS2383. The sixth and seventh bit is a placeholder for future expansion. During a write operation to the TPS2383 from the master device, the data field is eight bits. During a read operation where the TPS2383 is writing to the master device, the data field is also eight bits. www.ti.com 13 14 www.ti.com Figure 1. I2C Read/Write Cycles SDA_O SDA_I Read Cycle SDA_O SDA_I Write Cycle SDA SCL Start Bit Start Bit Register/Port Address Device Address R/W=0 Ack Bit D7 D6 R2 R1 R0 P2 P1 P0 A7 A6 A5 A4 A3 A2 A1 A0 R/W Bit Register/Port Address Clock 0 Device Address R/W=0 Ack Bit R/W Bit Clock 1 D7 D6 R2 R1 R0 P2 P1 P0 Clock 1 A7 A6 A5 A4 A3 A2 A1 A0 Start Condition(S) Start/Stop Sequence Ack Bit Ack Bit Start Bit R/W=1 Device Address Ack Bit R/W Bit A7 A6 A5 A4 A3 A2 A1 A0 Data from Master to TPS2383 Ack Stop Bit Bit Stop Condition (P) D7 D6 D5 D4 D3 D2 D1 D0 Clock 1 Ack Bit D7 D6 D5 D4 D3 D2 D1 D0 Data from TPS2383 to Master Stop Bit SLUS559B − APRIL 2003 − REVISED JULY 2004 UDG−03060 SLUS559B − APRIL 2003 − REVISED JULY 2004 FUNCTIONAL DESCRIPTION Chip Address The address field of the TPS2383 is eight bits and contains five bits of device address select, a read/write bit, and two reserved bits per Table 1. The leading two bits are reserved for future port expansion, and must be set to 0 for address acknowledge. The five device address select bits follow this. These bits are compared against the hard-wired state of the corresponding, device address select pins (A1 through A5). When the field contents are equivalent to the pin logic states, the device is addressed. These bits are followed by a least significant bit (LSB), which is used to set the read or write condition (1 for read and 0 for write). Following a start condition and an address field, the TPS2383 responds with an acknowledgement by pulling the SDA line low during the ninth clock cycle if the address field is equivalent to the value programmed by the pins. The SDA line remains a stable low while the ninth clock pulse is high. Table 1. Address Selection Field BIT FUNCTION A7 Future expansion (set to 0) A6 Future expansion (set to 0) A5 Device address. Compared with A5 A4 Device address. Compared with A4 A3 Device address. Compared with A3 A2 Device address. Compared with A2 A1 Device address. Compared with A1 A0 Read/write Port/Register Cycle After the chip address cycle, the TPS2383 accepts eight bits of port/register select data as defined in Table 2. The SCL line high-to-low transition after the eighth data bit then latches the selection of the appropriate internal register for the follow on data read or write operation. After latching the eight-bit data field, the TPS2383 pulls the SDA line low for one clock cycle. Data Write Cycle For a data write sequence, after the Port/Register address cycle, the TPS2383 accepts the eight bits of data. The data is latched into the previously selected Write Register, and the TPS2383 generates a data acknowledge pulse by pulling the SDA line low for one clock cycle. To reset the interface, the host or master subsequently generates a Stop bit by releasing the SDA line during the clock-high portion of an SCL pulse. www.ti.com 15 SLUS559B − APRIL 2003 − REVISED JULY 2004 FUNCTIONAL DESCRIPTION Data Read Cycle For a data read sequence, after the register acknowledge bit, the master device generates a Stop condition. This is followed by a second Start condition, and retransmitting the device address as described in Chip Address above. For this cycle, however, the R/W bit is set to a 1 to signal the read operation. The TPS2383 again responds with an acknowledge pulse. The address acknowledge is then followed by sequentially presenting each of the eight data bits on the SDA line (MSB first), to be read by the host device on the rising edges of SCL. After eight bits are transmitted, the host acknowledges by pulling the SDA line high for one clock pulse. The completed data transfer is terminated with the host generating a Stop condition. Table 2. Register/Port Addressing BIT FUNCTION D7 Future expansion D6 Future expansion D5 R2, register select MSB D4 R1, register select D3 R0, register select LSB D2 P2, port address MSB D1 P1, port address D0 P0, port address LSB STATE 000 = 001 = 010 = 011 = 100 = 101 = Control (common Write register) Port Status (per port Read register) Port Control (per port Write register) A2D Register low byte (common read register) A2D Register high byte (common read register) Chip identification/revision (common read register) 000 = 001 = 010 = 011 = 100 = 101 = 110 = 111 = Port 1 Port 2 Port 3 Port 4 Port 5 Port 6 Port 7 Port 8 Port/Register Cycle Table 3. Common Control Write Register, Register Address = 000 (Common Register) BIT 16 FUNCTION STATE PRESET STATE D7 Jog_mode 0 = Normal mode 1 = Jog mode 0 D6 Jog 0 = Don’t jog 1 = Jog. This bit is self-clearing. It does not need to be reset to a 0 for each new jog. 0 D5 Bypass ramp 0 = Normal mode 1 = Bypass power−up ramp and powered mode for all ports 0 D4 Disconnect disable 0 = Normal mode 1 = Disable the effect of the logic signal from the Disconnect detection circuits. This is an expansion function for future parts. This bit should be set to a logic 1 0 D3 Bypass discovery 0 = Normal mode 1 = Bypass discovery mode. 0 D2 Bypass sample 0 = Normal mode 1 = Bypass current sample of all powered ports. 0 D1 Bypass classification 0 = Normal mode 1 = Bypass classification of all ports. 0 D0 Discovery fault disable 0 = Normal mode 1 = Disable the effect of the logic signal from the Discovery circuits. This is an expansion function for future parts. This bit should be set to a logic 1. 0 www.ti.com SLUS559B − APRIL 2003 − REVISED JULY 2004 FUNCTIONAL DESCRIPTION Port Status Registers The Port Status registers (address 001) contain port−specific information regarding the operational or faulted state of each of the eight Ethernet ports, as shown in Tables 4 and 5. In addition, the Port 1 Status register (Register/Port address xx00/1000) bits D6:D3 contain the current usage information of some of the common hardware resources, as they are accessed in the servicing of the port presently selected by the master sequencer. Table 4. Port Status Port 1 Read Register, Register Address = 001, Port Address = 000 BIT FUNCTION STATE PRESET STATE D7 Port service 0 = Port not selected 1 = Port selected and being serviced 0 D6 Down 0 = Selected port is being ramped up 1 = Selected port is not being ramped up 1 D5 Ramp ServiceB 0 = Selected port is using the RAMP module 1 = Selected port is not using the RAMP module 1 D4 Current SampleB 0 = Selected port current is being acquired 1 = Selected port current is not being acquired 1 D3 A to D ServiceB 0 = Discovery/classification data acquisition in process 1 = A/D not performing discovery/classification 1 D2 Fault status (MSB) D1 Fault status D0 Fault status (LSB) 000 = Reset state 001 = UV/OV fault/spike 010 = UV/OV spike 011 = Peak over−current fault 100 = Overload fault 101 = Discovery Fail 110 = Load disconnect 111 = Reserved for future www.ti.com 000 17 SLUS559B − APRIL 2003 − REVISED JULY 2004 FUNCTIONAL DESCRIPTION Table 5. Port Status Read Register, Register Address = 001, Port Address = 001−111 (Port 2 through Port 8) BIT FUNCTION PRESET STATE STATE 0 = Port not selected 1 = Port selected and being serviced D7 Port service 0 D6 Spare 0 D5 Spare 1 D4 Spare 1 D3 Spare 1 D2 Fault status (MSB) D1 Fault status D0 Fault status (LSB) 000 = Reset state 001 = UV/OV fault/spike 010 = UV/OV spike 011 = Peak over−current fault 100 = Overload fault 101 = Discovery Fail 110 = Load disconnect 111 = Reserved for future 000 Port Control Registers The Port Control registers’ (address 010) bit maps are shown in the following tables. These registers contain port-specific control bits, accessible over the I2C bus, for setting the port powered and port LED modes. To conserve hardware resources, some common control functions have been assigned to available bit locations within these registers. To clarify usage, these common functions are identified as such in the table RANK column. Table 6. Port Control Write Register, Register Address = 010, Port Address = 000 (Port 1 Register) BIT FUNCTION D7 Port fault disable D6 POR disable D5 Software RESET RANK PRESET STATE 0 = Normal mode 1 = Disable the port overload and UV/OV timers 0 Common 0 = Normal POR timing 1 = Force POR to a non-reset state 0 Common 0 = Normal operation 1 = Reset all circuits and start a device POR timing cycle 0 0 Port D4 LED blink enable Port 0 = LED is continuous 1 = Blink the enabled LED at a fast-blink rate. Note fast-blink rate (in milliseconds) equivalent to 0.00013 x TPS2383 clock (CLK). This could be as fast as 65 ms for a 500-kHz, TPS2383 clock. D3 LED low-side enable Port 1 = Enable the low-side FET and drive the LED pin low 0 D2 LED high-side enable Port 1 = Enable the high-side FET and drive the LED pin to V5 0 Port 00 = Port OFF or disable 01 = Discovery − classification − power on sequence 10 = Sample powered-mode current 11 = Power-down an active port 0 D1 Enable modes D0 18 STATE www.ti.com SLUS559B − APRIL 2003 − REVISED JULY 2004 FUNCTIONAL DESCRIPTION Table 7. Port Control Write Register, Register Address = 010, Port Address = 001 (Port 2 Register) BIT FUNCTION D7 Port fault disable D6 Spare RANK Port STATE 0 = Normal mode 1 = Disable the port overload and UV/OV timers PRESET STATE 0 0 Common Class Limit2, Class Limit1 0,0 = 160-mA classification current limit 0,1 = 80-mA classification current limit 1,0 = 40-mA classification current limit 1,1 = 20-mA classification current limit 0 D5 Class limit 1 D4 LED blink enablle Port 0 = LED is on continuous. 1 = Blink the enabled LED at a fast-blink rate. Note fast-blink rate (in milliseconds) equivalent to 0.00013 x TPS2383 clock (CLK). This could be as fast as 65 ms for a 500-kHz, TPS2383 clock. 0 D3 LED low-side enable Port 1 = Enable the low-side FET and drive the LED pin low 0 D2 LED high-side enable Port 1 = Enable the high-side FET and drive the LED pin to V5 0 Enable modes Port 00 = Port OFF or disable 01 = Discovery − classification − power on sequence 10 = Sample powered-mode current 11 = Power-down an active port 0 D1 D0 Table 8. Port Control Write Register, Register Address = 010, Port Address = 010 (Port 3 Register) BIT FUNCTION D7 Port fault disable D6 Spare RANK Port STATE 0 = Normal mode 1 = Disable the port overload and UV/OV timers PRESET STATE 0 0 Common Class Limit2, Class Limit1 0,0 = 160-mA classification current limit 0,1 = 80-mA classification current limit 1,0 = 40-mA classification current limit 1,1 = 20-mA classification current limit 0 D5 Class limit 2 D4 LED blink enablle Port 0 = LED is on continuous. 1 = Blink the enabled LED at a fast-blink rate. Note fast-blink rate (in milliseconds) equivalent to 0.00013 x TPS2383 clock (CLK). This could be as fast as 65 ms for a 500-kHz TPS2383 clock. 0 D3 LED low-side enable Port 1 = Enable the low-side FET and drive the LED pin low 0 D2 LED high-side enable Port 1 = Enable the high-side FET and drive the LED pin to V5 0 Port 00 = Port OFF or disable 01 = Discovery − classification − power on sequence 10 = Sample powered-mode current 11 = Power-down an active port 0 D1 Enable modes D0 www.ti.com 19 SLUS559B − APRIL 2003 − REVISED JULY 2004 FUNCTIONAL DESCRIPTION Table 9. Port Control Write Register, Register Address = 010, Port Address = 011 (Port 4 Register) BIT FUNCTION D7 Port fault disable D6 Spare D5 A/D input select D4 LED blink enablle D3 D2 RANK Port STATE 0 = Normal mode 1 = Disable the port overload and UV/OV timers PRESET STATE 0 0 0 = Normal mode − select port currents 1 = Select port voltage 0 Port 0 = LED is on continuous. 1 = Blink the enabled LED at a ”fast blink” rate. Note ”fast blink” rate (in milliseconds) equivalent to 0.00013 x TPS2383 clock (CLK). This could be as fast as 65ms for a 500 kHz TPS2383 clock. 0 LED low-side enable Port 1 = Enable the low-side FET and drive the LED pin low 0 LED high-side enable Port 1 = Enable the high-side FET and drive the LED pin to V5 0 Port 00 = Port OFF or disable 01 = Discovery − classification − power on sequence 10 = Sample powered-mode current 11 = Power-down an active port 0 Common D1 Enable modes D0 Table 10. Port Control Write Register, Register Address = 010, Port Address = 100−111 (Port 5 through Port 8 Register) BIT FUNCTION D7 Port fault disable D6 Spare D5 Spare RANK Port STATE 0 = Normal mode 1 = Disable the port overload and UV/OV timers PRESET STATE 0 0 0 D4 LED blink enablle Port 0 = LED is on continuous. 1 = Blink the enabled LED at a ”fast blink” rate. Note ”fast blink” rate (in milliseconds) equivalent to 0.00013 x TPS2383 clock (CLK). This could be as fast as 65ms for a 500 kHz TPS2383 clock. D3 LED low-side enable Port 1 = Enable the low-side FET and drive the LED pin low 0 D2 LED high-side enable Port 1 = Enable the high-side FET and drive the LED pin to V5 0 Port 00 = Port OFF or disable 01 = Discovery − classification − power on sequence 10 = Sample powered-mode current 11 = Power-down an active port 0 D1 Enable modes D0 0 Run Current/Voltage During power delivery, the average value of the port running current or voltage is available from the read register. The slope type converter used produces 12 bits of input offset corrected conversion with a typical integration or averaging period of approximately one line cycle (16 ms). The actual averaging period is set by the CLK frequency and is equivalent to 8192 periods of that frequency. The lower eight bits of this conversion are available at the port register 011. The remaining upper four bits and A/D status bits are available at register 100. The converter span is 4096 bits. The A/D conversion port displays the real time counter output and holds the final static value at the completion of conversion 20 www.ti.com SLUS559B − APRIL 2003 − REVISED JULY 2004 FUNCTIONAL DESCRIPTION Table 11. Common Analog to Digital Conversion Port Read Register, Register Address = 011 BIT FUNCTION D7 A2D bit 7 D6 A2D bit 6 D5 A2D bit 5 D4 A2D bit 4 D3 A2D bit 3 D2 A2D bit 2 D1 A2D bit 1 D0 A2D bit 0 STATE PRESET STATE A/D lower bits Table 12. Common Analog to Digital Conversion Port Read Register, Register Address = 100 BIT FUNCTION STATE D7 A2D zero cross 0 = CINT is above zero threshold 1 = CINT is below zero threshold D6 A2D overflow 1 = A2D overflow detected D5 Reserved for test D4 Reserved for test D3 A2D bit 11 D2 A2D bit 10 D1 A2D bit 9 D0 A2D bit 8 PRESET STATE A/D upper bits Table 13. Chip Identification/Revision Read Register, Register Address = 101 BIT FUNCTION D7 Rev ID MSB D6 Rev ID D5 Rev ID LSB D4 Device ID MSB D3 Device ID D2 Device ID D1 Device ID D0 Device ID LSB STATE Internally hardwired (function of revision) PRESET STATE 0 1 www.ti.com 21 SLUS559B − APRIL 2003 − REVISED JULY 2004 APPLICATION INFORMATION SWITCH/HUB POWERED DTR RJ−45 CT Choke 1 TX 2 CT Choke 3 RX 6 4 RJ−45 w/grn w/grn grn 2 w/org org org blue blue CT Choke RX grn w/org 1 3 CT Choke TX 6 4 PPTC Fuse TPS2383 PSE P (1 Port) N V48 GND 5 7 G 8 RS 568A w/blue w/blue w/brn w/brn brn brn 5 7 PD Signature 8 PD DC/DC Supply 568A Up to 350 feet of category 5 cable RG Optically Coupled I2C Serial Bus + 48−V Supply − MSP430 Controller UDG−03061 Figure 2. System Block Diagram 22 www.ti.com SLUS559B − APRIL 2003 − REVISED JULY 2004 APPLICATION INFORMATION V5 SCL BUS I2C BUS SDA BUS INTB BUS CT 0.1 µF 120 pF CR 0.1 µF +48V BUS NEG POS 4.22 kΩ V5 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 A1 A2 A3 A4 A5 INTB SDA_I SDA_O DG SCL_I VL EN CT AG2 CR PORB 46 4 1RS 8RS 45 5 2RS 7RS 44 6 2G 7G 43 7 2N 7N 42 8 2P 7P 41 9 3P 6P 40 10 3N 6N 39 11 3G 6G 38 12 3RS 6RS 37 13 4RS 5RS 36 14 4G 5G 35 15 4N 5N 34 16 4P 5P 33 L1 L2 L3 L4 L5 L6 L7 L8 V5 AG1 V48 V10 RG CINT RT RD 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 TPS2383 OCTAL PSE CONTROLLER 17 RJ45−1/ RJ45−2/ Xformer Xformer RJ45−3/ RJ45−4/ Xformer 8G RJ45−5/ 1G Xformer 0.47 µF 47 3 RJ45−6/ 0.5 Ω IRFD110 0.5 Ω 48 8N Xformer 0.47 µF 8P 1N RJ45−7/ 0.47 µF 1P 2 Xformer 0.5 Ω IRFD110 0.5 Ω 1 RJ45−8/ 0.47 µF Xformer Xformer PORB 0.47 µF 0.5 Ω 0.5 Ω IRFD110 0.47 µF 0.47 µF 0.5 Ω 0.5 Ω IRFD110 0.47 µF V5 CD 0.68 µF 0.1 µF 0.1 µF 0.1 µF CINT 0.033 µF RD 665 Ω RT 120 kΩ Kelvin RS Sense V5 100 Ω Green Green Green Green Green Green Green Green 100 Ω Red 100 Ω Red 100 Ω Red 100 Ω Red 100 Ω Red 100 Ω Red 100 Ω Red 100 Ω Red PORT 1 PORT 2 PORT 3 PORT 4 PORT 5 PORT 6 PORT 7 PORT 8 STATUS STATUS STATUS STATUS STATUS STATUS STATUS STATUS UDG−03064 * All fuses are Self Resetting BBR550, Raychem Figure 3. Typical Eight-Port Application www.ti.com 23 SLUS559B − APRIL 2003 − REVISED JULY 2004 APPLICATION INFORMATION Controller VDD SCL Bus SDA Bus Controller GND CMOS HEX Inverter CMOS HEX Inverter OP1 PS9701 220 Ω OP2 PS9701 OP3 PS9701 220 Ω Isolated Ethernet Power System 330 Ω 1 kΩ 1 kΩ Floating +5V Floating GND 60 59 58 57 56 55 SCL_I 61 DG 62 SDA_O 63 SDA_I 64 54 53 52 51 50 49 TPS2383 UDG−03065 Figure 4. Using Optoisolators for I2C Bus/System Ground Isolation 24 www.ti.com SLUS559B − APRIL 2003 − REVISED JULY 2004 APPLICATION INFORMATION 0.1 µF 49 PORB 50 CR 51 AG2 52 CT 53 EN 54 VL 58 SDA_I 55 59 INTB SCL_I 60 A5 56 61 A4 DG 62 A3 57 63 A2 SDA_O 64 A1 4.22 kΩ L2 L3 L4 L5 L6 L7 L8 V5 AG1 V48 V10 RG CINT RT 18 19 20 21 22 23 24 25 26 27 28 29 30 31 +48 V Bus Positive 47 Ω +5 V + +48 V Bus Negative 32 L1 17 No LED Drive RD TPS2383 0.1 µF 0.1 µF 80 V NMOS 5 V LDO OUT GND IN +8 V 0.1 µF 10 µF Tantalum UDG−03066 Figure 5. V5 and VL Generation from Single +48-V Supply www.ti.com 25 MECHANICAL DATA MTQF008A – JANUARY 1995 – REVISED DECEMBER 1996 PM (S-PQFP-G64) PLASTIC QUAD FLATPACK 0,27 0,17 0,50 0,08 M 33 48 49 32 64 17 0,13 NOM 1 16 7,50 TYP Gage Plane 10,20 SQ 9,80 12,20 SQ 11,80 0,25 0,05 MIN 0°– 7° 0,75 0,45 1,45 1,35 Seating Plane 0,08 1,60 MAX 4040152 / C 11/96 NOTES: A. B. C. D. All linear dimensions are in millimeters. This drawing is subject to change without notice. Falls within JEDEC MS-026 May also be thermally enhanced plastic with leads connected to the die pads. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. 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