TI TPS56300PWP

TPS56300
DUAL-OUTPUT LOW-INPUT-VOLTAGE
DSP POWER SUPPLY CONTROLLER WITH SEQUENCING
SLVS261A – DECEMBER 1999 – JANUARY 2000
D
D
D
D
D
D
D
D
D
D
2.8 V – 5.5 V Input Voltage Range
Programmable Dual Output Controller
Supports Popular DSP and Microcontroller
VID0
Core and I/O Voltages
VID1
– Switching Regulator Controls Core
SLOWST
Voltage
VHYST
– Low Dropout Controller Regulates I/O
VREFB
Voltage
VSEN–RR
ANAGND
Programmable Slow-Start Ensures
BIAS
Simultaneous Powerup of Both Outputs
VLDODRV
Power Good Output Monitors Both Outputs
CPC1
Fast Ripple Regulator Reduces Bulk
VCC
Capacitance for Lower System Costs
CPC2
VDRV
±1.5% Reference Voltage Tolerance
DRVGND
Efficiencies Greater than 90%
Overvoltage, Undervoltage, and Adjustable
Overcurrent Protection
Drives Low-Cost Logic Level N-Channel
MOSFETs Through Entire Input Voltage
Range
Evaluation Module TPS56300EVM–139
Available
PWP PACKAGE
(TOP VIEW)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
Thermal
Pad
28
27
26
25
24
23
22
21
20
19
18
17
16
15
DROOP
OCP
IOUT
PWRGD
VSEN–LDO
NGATE–LDO
INHIBIT
IOUTLO
HISENSE
LOSENSE/LOHIB
HIGHDR
BOOT
BOOTLO
LDWDR
PowerPAD Package
description
The high performance TPS56300 synchronous-buck regulator provides two supply voltages to power the core
and I/O of digital signal processors, such as the ‘C6000 family. The ripple regulator, using hysteretic control with
droop compensation, is configured for the core voltage and features fast transient response time reducing
output bulk capacitance (continued).
typical design
+
+
See Note A
See Note A
+
NOTE A: See Table 1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PowerPAD is a trademark of Texas Instruments Incorporated.
Copyright  2000, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
1
TPS56300
DUAL-OUTPUT LOW-INPUT-VOLTAGE
DSP POWER SUPPLY CONTROLLER WITH SEQUENCING
SLVS261A – DECEMBER 1999 – JANUARY 2000
description (continued)
The LDO controller drives an external N-channel power MOSFET and functions as an LDO regulator, suitable
for powering the I/O or as a power distribution switch. To promote better system reliability during power up,
voltage sequencing and protection are controlled such that the core and I/O power up together with the same
slow-start voltage. At power down, the LDO and ripple regulator are discharged towards ground for added
protection. The TPS56300 also includes inhibit, slowstart, and under-voltage lockout features to aide in
controlling power sequencing. A tri-level voltage identification network (VID) sets both regulated voltages to any
of 9 preset voltage pairs from 1.3 V to 3.3 V. Other voltages are possible by implementing an external voltage
divider. Strong MOSFET drivers, with a typical peak current rating of 2-A sink and source are included on chip,
enabling high system currents beyond 30 A. The high-side driver features a floating bootstrap driver with the
internal bootstrap synchronous rectifier. Many protection features are incorporated within the device to ensure
better system integrity. An open-drain output POWER GOOD status circuit monitors both output voltages, and
is pulled low if either output fall below the threshold. An over current shutdown circuit protects the high-side
power MOSFET against short-to-ground faults at load or the phase node, while over voltage protection turns
off the output drivers and LDO controller if either output exceeds its threshold. Under voltage protection turns
off the high-side and low-side MOSFET drivers and the LDO controller if either output is 25% below VREF.
Lossless current-sensing is done by detecting the drain-source voltage drop across the high-side power
MOSFET while it is conducting. The TPS56300 is fully compliant with TI DSP power requirements such as the
‘C6000 family.
AVAILABLE OPTIONS
PACKAGES
TJ
TSSOP†
(PWP)
EVALUATION MODULE
–40°C to 125°C
TPS56300PWP
TPS56300EVM–139 (SLVP139)
† The PWP package is also available taped and reel. To order, add an R to the end of
the part number (e.g., TPS56300PWPR).
2
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
TPS56300
DUAL-OUTPUT LOW-INPUT-VOLTAGE
DSP POWER SUPPLY CONTROLLER WITH SEQUENCING
SLVS261A – DECEMBER 1999 – JANUARY 2000
functional block diagram
Bias
PWRGD
LOSENSE/
LOHIB
25
19
Vcc
21
20
IOUT
26
+
8
Reg.
VLDODRV
IOUTLO HISENSE
>0.93xVSEN–RR
VDRV
–
>0.93xVSEN–LDO
9
SHUTDOWN
Delay
HIGHDR
INHIBIT
11
22
INHIBIT
VDRV UVLO
Vcc UVLO
RR_OVP
CPC1
Fault
Latch
10
LDO_OVP
Q
S
RR_UVP *
R
LDO_UVP *
CPC2
BOOT
12
SHUTDOWN
+
–
VDRV
VDRV
13
E/A
1
VID1
Ivrefb/5
24
VSEN–LDO
23
NGATE–LDO
17
BOOT
18
HIGHDR
16
BOOTLO
15
LOWDR
VLDODRV
–
+
SHUTDOWN
See table 1
2
Vbias
SLOWST
SLOWST
Vref_LDO
VID
OCP
125 mV
5V
SHUTDOWN
VID0
27
SLOWST
Hysteresis
Comparator
Vref_RR
3
+
Adaptive
Deadtime
–
SHUTDOWN
Hysteresis
Setting
VDRV
SHUTDOWN
7
ANAGND
RR–Ripple Regulator
5
VREFB
4
28
6
VHYST DROOP
Synchronous
FET
POST OFFICE BOX 655303
14
VSEN–RR
DRVGND
* UVP is disabled during
slowstart
• DALLAS, TEXAS 75265
3
TPS56300
DUAL-OUTPUT LOW-INPUT-VOLTAGE
DSP POWER SUPPLY CONTROLLER WITH SEQUENCING
SLVS261A – DECEMBER 1999 – JANUARY 2000
Terminal Functions
TERMINAL
NAME
DESCRIPTION
NO.
VID0
1
Voltage Identification input 0. VID pins are tri-level programming pins that set the output voltages for both converters. The code pattern for setting the output voltage is located in table 1. The VID pins are internally pulled to
Vbias/2, allowing floating voltage set to logic 1 (see table 1).
VID1
2
Voltage Identification input 1 (see VID0 above and table 1).
SLOWST
3
Slow start (soft start). A capacitor from pin 3 to GND sets the slowstart time for VOUT-RR and VOUT-LDO. Both
supplies will ramp-up together while tracking the slow-start voltage.
VHYST
4
Hysteresis set pin. The hysteresis is set by 2 × (VREFB – Vhyst).
VREFB
5
Buffered ripple regulator reference voltage from VID network.
VSEN-RR
6
Ripple regulator VOLTAGE SENSE input. This pin is connected to the ripple regulator output. It is used to sense
the ripple regulator voltage for regulation, OVP, UVP, and Powergood functions.. It is recommended that an RC
low pass filter be connected at this pin to filter high frequency noise.
ANAGND
7
Analog ground
BIAS
8
Analog BIAS pin. Recommended that a 1-µF capacitor be connected to ANAGND.
VLDODRV
9
Output of charge pump generated through bootstrap diode. Approximately equal to VDRV + VIN – 300mV. Used
as supply for LDO driver and Bias regulator. Recommended that a 1-µF capacitor be connected to DRVGND.
CPC1
10
Connect one end of Charge pump capacitor. Recommended that a 1-µF capacitor be connected from CPC1 to
CPC2.
VCC
11
3.3 V or 5 V supply (2.8 V – 5.5 V). Recommended that a low ESR capacitor be connected directly from VCC to
DRVGND. (Bulk capacitors supplied at power stage input).
CPC2
12
Other end of charge pump capacitor from CPC1.
VDRV
13
Regulated output of internal charge pump. Supplies DRIVE charge for the low-side MOSFET driver (5V). Recommended that a 10-µF capacitor be connected to DRVGND.
DRVGND
14
Drive ground. Ground for FET drivers. Connect to source of low-side FET.
LOWDR
15
Low drive. Output drive to synchronous rectifier low-side FET.
BOOTLO
16
Bootstrap low. This pin connects to the junction of the high-side and low-side FETs.
BOOT
17
Bootstrap pin. Connect a 1-µF low ESR capacitor to BOOTLO to generate floating drive for the high-side FET
driver.
HIGHDR
18
High drive. Output drive to high-side power switching FETs
LOSENSE/
LOHIB
19
Low sense/low-side inhibit. This pin is connected to the junction of the high and low-side FETs and is used in current sensing and the anti-cross-conduction to eliminate shoot-through current.
HISENSE
20
High current sense. For current sensing across high-side FETs, connect to the drain of the high-side FETs.
IOUTLO
21
Current sense low output. Voltage on this pin is the voltage on the LOSENSE pin when the high-side FETs are on.
INHIBIT
22
Inhibits the drive signals to the MOSFET drivers. IC is in low Iq state if INHIBIT is grounded. It is recommended
that an external pullup resistor be connected to 5 V.
NGATE-LDO
23
Drives external N-channel power MOSFET to regulate LDO voltage to VREF-LDO.
VSEN–LDO
24
LDO voltage sense. This pin is connected to the LDO output. It is used to sense the LDO voltage for regulation,
OVP, UVP, and power good functions.
PWRGD
25
Power good. Power good signal goes high when output voltage is about 93% of VREF for both ripple regulator and
LDO. This is an open-drain output.
4
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
TPS56300
DUAL-OUTPUT LOW-INPUT-VOLTAGE
DSP POWER SUPPLY CONTROLLER WITH SEQUENCING
SLVS261A – DECEMBER 1999 – JANUARY 2000
Terminal Functions (continued)
TERMINAL
NAME
NO.
I/O
DESCRIPTION
IOUT
26
Current signal output. Output voltage on this pin is proportional to the load current as measured across
the high-side FETs on-resistance. The voltage on this pin equals 2 × RON × IOUT, where Ron is the
equivalent on-resistance of the high-side FETs
OCP
27
Over current protection. Current limit trip point for ripple regulator is set with a resistor divider between
IOUT pin and ANAGND.
DROOP
28
Droop voltage. Voltage input used to set the amount of output voltage droop as a function of load current.
The amount of droop compensation is set with a resistor divider between the IOUT pin and ANAGND.
Table 1. Voltage Identification Code§¶
VID Terminals†
VID1
VID0
VREF–RR‡
(Vdc)
VREF–LDO‡
(Vdc)
0
0
1.30
1.5
0
1
1.50
1.80
0
2
1.30
1.80
1
0
1.80
3.30
1
1
1.30
1.30
1
2
2.50
3.30
2
0
1.30
2.50
2
1
1.50
3.30
2
2
1.80
2.50
† 0 = ground (GND), 1 = floating(Vbias/2), 2 = (Vbias)
‡ RR = Ripple Regulator, LDO = Low Drop-Out Regulator
§ Vbias/2 is internal, leave VID pin floating. Adding an external 0.1-µF capacitor to ANAGND may be used to
avoid erroneous level.
¶ External resistors may be used as a voltage divider (from VOUT to VSEN–xx to Gnd) to program output
voltages to other values.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
5
TPS56300
DUAL-OUTPUT LOW-INPUT-VOLTAGE
DSP POWER SUPPLY CONTROLLER WITH SEQUENCING
SLVS261A – DECEMBER 1999 – JANUARY 2000
absolute maximum ratings over operating virtual junction temperature (unless otherwise noted)†
Supply voltage range, VCC (see Note1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to 6 V
Input voltage range: VDRV . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to 7 V
BOOT to DRVGND (High-side Driver ON) . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to 15 V
BOOT to BOOTLO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to 7 V
BOOT to HIGHDRV . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to 7 V
BOOTLO to DRVGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 15 V
DRV to DRVGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to 7 V
BIAS to ANAGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to 7 V
INHIBIT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to 7 V
DROOP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to VCC + 0.3 V
OCP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to 7 V
VID0, VID1 (tri-level terminals) . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to VBIAS + 0.3 V
PWRGD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to 6 V
LOSENSE, LOHIB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 14 V
IOUTLO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to 14 V
HISENSE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to 7 V
VSEN–LDO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to 6 V
VSEN–RR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to 6 V
Voltage difference between ANAGND and DRVGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±300 mV
Continuous total power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Dissipation Rating Table
Operating virtual junction temperature range, TJ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –40°C to 125°C
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
Lead temperature soldering 1,6 mm (1/16 inch) from case for 10 seconds . . . . . . . . . . . . . . . . . . . . . . . 300°C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 1: Unless otherwise specified, all voltages are with respect to ANAGND.
PWP
PowerPAD mounted
PowerPAD unmounted
TA < 25°C
3.58 W
DISSIPATION RATING TABLE
Derating Factor‡
TA = 70°C
1.78 W
0.0358 W/°C
1.96 W
TA = 85°C
1.43 W
0.0178 W/°C
0.98 W
0.71 W
JUNCTION-CASE THERMAL RESISTANCE TABLE
0.72 °C/W
Junction-case thermal resistance
‡ Test Board Conditions:
1. Thickness: 0.062”
2. 3”x 3” (for packages < 27 mm long)
3. 4” x 4” (for packages > 27 mm long)
4. 2 oz. Copper traces located on the top of the board (0.071 mm thick )
5. Copper areas located on the top and bottom of the PCB for soldering
6. Power and ground planes, 1oz. Copper (0.036 mm thick)
7. Thermal vias, 0.33 mm diameter, 1.5 mm pitch
8. Thermal isolation of power plane
For more information, refer to TI technical brief SLMA002.
6
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
TPS56300
DUAL-OUTPUT LOW-INPUT-VOLTAGE
DSP POWER SUPPLY CONTROLLER WITH SEQUENCING
SLVS261A – DECEMBER 1999 – JANUARY 2000
electrical characteristics TJ = 0° to 125°C, VCC = 2.8 V to 5.5 V (unless otherwise noted)
input
PARAMETER
CONDITIONS
VCC Supply voltage range
MIN
TYP
MAX
UNITS
2.8
3.3
5.5
V
INHIBIT = 0 V,
ICC Quiescent current
VCC = 5 V
NOTE 2. Ensured by design, not production tested.
15
mA
reference/voltage identification
PARAMETER
CONDITIONS
MIN
D0–D1 High level input voltage (2)
TYP
MAX
UNITS
Vbias – 0.3 V
V
D0–D1 Mid level floating voltage (1)
bias
2
V
*1
V
D0–D1 Low level input voltage (0)
Input pull-to-mid resistance
36.5
)1
bias
2
0.3
73
V
V
95
KΩ
cumulative reference
PARAMETER
Cumulative accuracy ripple regulator
Cumulative accuracy LDO
CONDITIONS
VREF = 1.3 V,
TJ = 25°C
Hysteresis window = 30 mV,
VREF = 1.3 V,
TJ = –40°C,
VREF = full range,
Droop = 0,
Hysteresis window = 30 mV,
See Note 2
Hysteresis window = 30 mV,
See Note 2
VREF = 1.3 V,
Closed Loop,
TJ = 25°C,
IO=0.1 A,
Pass device = IRFZ24N,
See Note 2
VREF = full range,
Closed Loop,
See Note 2
IO=0.1 A,
Pass device = IRFZ24N,
MIN
TYP
MAX
–1.3
0.25
1.3
UNITS
%
–0.2
–1.5
1.5
–2
2
%
–2.5
2.5
NOTE 2. Ensured by design, not production tested.
hysteretic comparator(ripreg)
PARAMETER
CONDITIONS
Input bias current
See Note 2
Hysteresis accuracy
VVREFB – VVHYST = 15 mV,
Hysteresis window = 30mV
Maximum hysteresis setting
VVREFB – VVHYST = 30 mV, See Note 2
Propagation delay time from VSENSE to
HIGHDR or LOWDR
(excluding deadtime)
10 mV overdrive,
See Note 2
1.3 V <= VREF <= 3.3 V
Prefilter pole frequency
See Note 2
NOTE 2. Ensured by design, not production tested.
POST OFFICE BOX 655303
MIN
TYP
–3.5
UNITS
500
nA
3.5
mV
60
mV
150
5
• DALLAS, TEXAS 75265
MAX
250
ns
MHz
7
TPS56300
DUAL-OUTPUT LOW-INPUT-VOLTAGE
DSP POWER SUPPLY CONTROLLER WITH SEQUENCING
SLVS261A – DECEMBER 1999 – JANUARY 2000
electrical characteristics TJ = 0° to 125°C, VCC = 2.8 V to 5.5 V (unless otherwise noted)
overvoltage protection
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
112
115
120
%VREF
OVP ripple regulator trip point (RR)
Upper threshold
Hysteresis (RR)
Upper threshold – lower threshold,
See Note 2
10
mV
Comparator propagation delay time (RR)
Voverdrive = 30mV,
See Note 2
1
µs
Deglitch time (includes comparator
propagation delay time) (RR)
Voverdrive = 30mV,
See Note 2
OVP LDO trip point (LDO)
Upper threshold
Hysteresis (LDO)
Upper threshold – lower threshold,
See Note 2
10
mV
Comparator propagation delay time (LDO)
Voverdrive = 50mV,
1
µs
2.25
112
See Note 2
Deglitch time (includes comparator
Voverdrive = 50mV,
propagation delay time) (LDO)
NOTE 2. Ensured by design, not production tested.
See Note 2
115
2.25
11
µs
120
%VREF
11
µs
undervoltage protection
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
70
75
80
%VREF
UVP ripple regulator trip point (RR)
Lower threshold
Hysteresis (RR)
Upper threshold – lower threshold,
See Note 2
10
mV
Comparator propagation delay time (RR)
Voverdrive = 50mV,
See Note 2
1
µs
Deglitch time (includes comparator
propagation delay time) (RR)
Voverdrive = 50mV,
See Note 2
UVP LDO trip point (LDO)
Lower threshold
Hysteresis (LDO)
Upper threshold – lower threshold,
See Note 2
0.1
70
Comparator propagation delay time (LDO)
Voverdrive = 50mV,
Deglitch time (includes comparator
Voverdrive = 50mV,
propagation delay time) (LDO)
NOTE 2. Ensured by design, not production tested.
See Note 2
See Note 2
75
1
ms
80
%VREF
10
mV
1
µs
0.1
1
ms
TYP
MAX
UNITS
2.1
2.35
inhibit comparator
PARAMETER
Start threshold
CONDITIONS
TJ = –40°C,
MIN
See Note 2
Stop threshold
NOTE 2. Ensured by design, not production tested.
2.1
1.79
V
V
VDRV UVLO
PARAMETER
CONDITIONS
MIN
Start threshold
See Note 2
Hysteresis
See Note 2
0.3
Stop threshold
See Note 2
NOTE 2. Ensured by design, not production tested.
4.4
8
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
TYP
0.35
MAX
UNITS
4.9
V
V
V
TPS56300
DUAL-OUTPUT LOW-INPUT-VOLTAGE
DSP POWER SUPPLY CONTROLLER WITH SEQUENCING
SLVS261A – DECEMBER 1999 – JANUARY 2000
electrical characteristics TJ = 0° to 125°C, VCC = 2.8 V to 5.5 V (unless otherwise noted)
slowstart
PARAMETER
CONDITIONS
Charge current
V(S/S) = 0.5V,
Resistance from VREFB pin to ANAGND = 20 kΩ
VREFB = 1.3 V,
Ichg = (IVREFB/5)
Discharge current
V(S/S) = 1.3 V
MIN
TYP
MAX
UNITS
10.4
13
15.6
µA
3
mA
Comparator input offset voltage
Comparator input bias current
10
See Note 2
10
Hysteresis accuracy
nA
7.5
mV
560
1000
ns
TYP
MAX
UNITS
2.72
2.80
–7.5
Comparator propagation delay
Overdrive = 10 mV,
NOTE 2. Ensured by design, not production tested.
See Note 2
mV
100
VCC UVLO
PARAMETER
Start threshold
CONDITIONS
MIN
See Note 2
TJ = –40°C,
Stop threshold
See Note 2
NOTE 2. Ensured by design, not production tested.
See Note 2
2.71
2.48
V
V
power good
PARAMETER
CONDITIONS
MIN
TYP
MAX
93
95
Undervoltage
g trip point ripple regulator
g
(VSENSE–RR)
VIN and VDRV above UVLO thresholds
TJ = –40°C,
See Note 2
90
Undervoltage
g trip point LDO
(VSENSE–LDO)
VIN and VDRV above UVLO thresholds
TJ = –40°C,
See Note 2
90
Output saturation voltage
IO=5 mA
VPGD = 4.5V
0.5
Hysteresis
VREF = 1.3V, 1.5V, or 1.8V
VREF = 2.5V, or 3.3V
Comparator high–low transition time
(propagation delay only)
See Note 2
Leakage current
93
93
95
93
%V
%
VREF
%V
%
VREF
0.75
V
50
75
mV
100
125
mV
µA
1
µs
1
Comparator low–high transition time
See Note 2
(propagation delay + deglitch)
NOTE 2. Ensured by design, not production tested.
UNITS
0.2
1
2
ms
MIN
TYP
MAX
UNITS
54
mV
droop compensation
PARAMETER
Initial accuracy
CONDITIONS
VDROOP = 50 mV
46
overcurrent protection (RR)
PARAMETER
CONDITIONS
OCP trip point
MIN
TYP
MAX
UNITS
118
130
142
mV
300
nA
Input bias current
Comparator propagation delay time
Voverdrive = 30mV,
Deglitch time (includes comparator
Voverdrive = 30mV,
propagation delay time)
NOTE 2. Ensured by design, not production tested.
POST OFFICE BOX 655303
See Note 2
See Note 2
• DALLAS, TEXAS 75265
µs
1
2.25
11
µs
9
TPS56300
DUAL-OUTPUT LOW-INPUT-VOLTAGE
DSP POWER SUPPLY CONTROLLER WITH SEQUENCING
SLVS261A – DECEMBER 1999 – JANUARY 2000
electrical characteristics TJ = 0° to 125°C, VCC = 2.8 V to 5.5 V (unless otherwise noted)
high-side VDS sensing
PARAMETER
CONDITIONS
MIN
Gain
Initial accuracy
Common-mode rejection ratio
Sink current (IOUTLO)
TYP
MAX
2
VHISENSE = 3.3 V,
VIOUTLO = 3.2 V,
Differential input to Vds sensing amp = 100 mV
VHISENSE=2.8 V to 5.5 V,
VHISENSE– VIOUTLO=100 mV
2.8 V < VIOUTLO < 5.5 V
194
69
UNITS
V/V
208
75
mV
dB
250
nA
VIOUT = 0.5 V,
VIOUTLO=2.8 V
VIOUT = 0.05 V,
VIOUTLO=3.3 V
VHISENSE=5.5 V,
VHISENSE=3.3 V,
500
µA
VHISENSE=3.35 V,
50
µA
RIOUT = 10 kΩ
0
1.75
Output voltage swing
VHISENSE=4.5 V,
VHISENSE=3 V,
RIOUT = 10 kΩ
0
1.5
0
0.75
LOSENSE high level input voltage
VHISENSE=2.8 V,
VHISENSE=2.8 V,
See Note 2
VHISENSE=4.5 V,
VHISENSE=4.5 V,
See Note 2
VHISENSE=5.5 V,
VHISENSE=5.5 V,
See Note 2
VHISENSE = 6 V,
VHISENSE = 4.5 V,
See Note 2
70
90
See Note 2
80
100
See Note 2
90
120
See Note 2
120
180
Source current (IOUT)
Sink current (IOUT)
LOSENSE low level input voltage
LOSENSE high level input voltage
LOSENSE low level input voltage
LOSENSE high level input voltage
LOSENSE low level input voltage
Sample/hold resistance
Response time ((measured from 90% of
VIOUTLO to 90% of VIOUT)
Short circuit protection rising edge delay
RIOUT = 10 kΩ
See Note 2
V
1.49
2.85
See Note 2
3.80
4
VHISENSE = 2.8 V,
VIOUTLO pulsed from 2.8 V to 2.7 V,
100 ns rise and fall times,
See Note 2
3.5
VHISENSE = 4.5 V,
VIOUTLO pulsed from 4.5V to 4.4V,
100 ns rise and fall times,
See Note 2
3
VHISENSE = 5.5 V,
VIOUTLO pulsed from 5.5 V to 5.9 V,
100 ns rise and fall times,
See Note 2
3
See Note 2
2.8V < VHISENSE < 5.5V,
VLOSENSE = VHISENSE,
NOTE 2. Ensured by design, not production tested.
POST OFFICE BOX 655303
See Note 2
• DALLAS, TEXAS 75265
V
V
3.2
VHISENSE = 2.55 V,
VIOUTLO pulsed from 2.55 V to 2.45 V,
100 ns rise and fall times,
See Note 2
LOSENSE grounded,
V
V
2.4
See Note 2
VHISENSE = 3.6 V,
VHISENSE = 2.8 V,
Sample/hold switch turnon/turnoff delay
10
1.77
V
V
Ω
µs
300
30
500
100
ns
ns
TPS56300
DUAL-OUTPUT LOW-INPUT-VOLTAGE
DSP POWER SUPPLY CONTROLLER WITH SEQUENCING
SLVS261A – DECEMBER 1999 – JANUARY 2000
electrical characteristics TJ = 0° to 125°C, VCC = 2.8 V to 5.5 V (unless otherwise noted)
buffered reference
PARAMETER
CONDITIONS
IREFB=50 µA,
MIN
Accuracy from VREF nominal
VREFB output voltage
VREF
–1.5%
IREFB=50 µA,
Accuracy from VREF nominal
TJ = –40°C,
See Note 2
VREFB load regulation
10 µA < IREFB < 500 µA
NOTE 2. Ensured by design, not production tested.
TYP
MAX
VREF
VREF
+1.5%
UNITS
V
VREF–0.6%
2
mV
thermal shutdown
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
See Note 2
145
°C
Hysteresis
See Note 2
NOTE 2. Ensured by design, not production tested.
10
°C
Over temperature trip point
synch charge pump regulator
PARAMETER
Internal oscillator frequency
CONDITIONS
2.8 V < VIN < 5.5 V, IDRV = 50 mA,
Internal oscillator turnon threshold
VCC above UVLO threshold,
Internal oscillator turnon hysteresis
VCC above UVLO threshold,
NOTE 2. Ensured by design, not production tested.
MIN
TYP
MAX
UNITS
VDRV=5 V
200
300
400
kHz
See Note 2
5.05
5.2
20
mV
MAX
UNITS
20
mV
MAX
UNITS
See Note 2
V
hysteretic comparator (charge pump)
PARAMETER
CONDITIONS
Threshold
VIN above UVLO threshold,
Hysteresis
VIN above UVLO threshold,
NOTE 2. Ensured by design, not production tested.
See Note 2
MIN
TYP
5.05
5.2
See Note 2
V
bias regulator
PARAMETER
CONDITIONS
MIN
TYP
Output voltage
2.8V < VIN < 5.5 V, Rip reg operating See Note 3
6.1
V
NOTE 3. The BIAS regulator is designed to provide a quiet bias supply for TPS56300 controller. External loads should not be driven by the BIAS
Regulator.
deadtime circuit
PARAMETER
LOSENSE/LOHIB high level input voltage
LOSENSE/LOHIB low level input voltage
LOWDR high level input voltage
LOWDR low level input voltage
CONDITIONS
VHISENSE=2.55 V – 5.5 V,
VHISENSE=2.55 V – 5.5 V,
See Note 2
VHISENSE=2.55 V–5.5 V,
VHISENSE=2.55 V–5.5 V,
See Note 2
MAX
3
40
UNITS
V
1.33
See Note 2
• DALLAS, TEXAS 75265
TYP
2.4
See Note 2
Driver nonoverlap time
Clowdr = 9 nF, 10% threshold on LOWDR, VDRV=5 V
NOTE 2. Ensured by design, not production tested.
POST OFFICE BOX 655303
MIN
V
V
1.7
V
170
ns
11
TPS56300
DUAL-OUTPUT LOW-INPUT-VOLTAGE
DSP POWER SUPPLY CONTROLLER WITH SEQUENCING
SLVS261A – DECEMBER 1999 – JANUARY 2000
electrical characteristics TJ = 0° to 125°C, VCC = 2.8 V to 5.5 V (unless otherwise noted)
output drivers (see Note 5)
PARAMETER
Peak output current
Output resistance
MIN
TYP
Duty cycle < 2%,
tpw < 100 us,
VBOOT – VBOOTLO = 4.5V,
VHIGHDR = 4V (sink),
See Note 2 and Figure 15
CONDITIONS
0.7
2
Duty cycle < 2%,
tpw < 100 us,
VBOOT – VBOOTLO = 4.5V,
VHIGHDR = 0.5V (src),
See Note 2 and Figure 15
1.2
2
Duty cycle < 2%,
tpw < 100 µs,
VDRV = 4.5 V,
VLOWDR = 4 V (sink)
See Note 2 and Figure 15
1.3
2
Duty cycle < 2%,
tpw < 100 us,
VDRV = 4.5 V,
VLOWDR = 0.5 V (src),
See Note 2 and Figure 15
1.4
2
5
VBOOT – VBOOTLO = 4.5V, VHIGHDR = 4 V,
See Note 2
45
LOWDR rise/fall time (see Note 7)
VLOWDR = 0.5V,
VLOWDR = 4V,
UNITS
A
VBOOT – VBOOTLO = 4.5 V, VHIGHDR = 0.5 V
See Note 2
VDRV = 4.5V,
VDRV = 4.5V,
HIGHDR rise/fall time (see Note 7)
MAX
See Note 2
9
See Note 2
45
Cl = 3.3 nF,
VBOOT= 4.5V,
VBOOTLO=grounded
Cl = 3.3 nF,
VDRV= 4.5V
INHIBIT grounded,
VIN < UVLO; VBOOT=6V,
BOOTLO grounded
Ω
60
ns
40
ns
10
µA
High-side driver quiescent current
INHIBIT connected to +5 V, VIN > UVLO
Fswx = 200KHz,
VBOOT = 5.5 V,
2
mA
BOOTLO = 0
CHIGHDR = 50 pF
See Note 2
NOTES: 2. Ensured by design, not production tested.
5. The pullup/pulldown circuits of the drivers are bipolar and MOSFET transistors in parallel. The peak output current rating is the
combined current from the bipolar and MOSFET transistors. The output resistance is the Rds(on) of the MOSFET transistor when
the voltage on the driver output is less than the saturation voltage of the bipolar transistor.
LDO N-channel output driver
PARAMETER
Peak output current
Open loop voltage gain
( VNGATE–LDO / VSENSE–LDO )
CONDITIONS
VLDODRV = 7.5V,
VN–DRV=3 V(src),
VIOSENSE = 0.9 × VLDOREF,
See Note 2
VLDODRV = 7.5V,
VN–DRV=0 V(snk),
VIOSENSE = 1.1 × VLDOREF,
See Note 2
VIN = 5.5 V,
7.5 V ≥ VNGATE–LDO ≥ 0.5 V,
See Note 2
f=1 kHz,
5.5 V ≥ VIN ≥ 2.55 V,
NOTE 2. Ensured by design, not production tested.
Power supply ripple rejection
12
CO=10 µF,
See Note 2
POST OFFICE BOX 655303
TJ=125 °C,
• DALLAS, TEXAS 75265
MIN
TYP
190
200
MAX
UNITS
µA
1.5
mA
3000
(70)
V/V
(dB)
60
dB
TPS56300
DUAL-OUTPUT LOW-INPUT-VOLTAGE
DSP POWER SUPPLY CONTROLLER WITH SEQUENCING
SLVS261A – DECEMBER 1999 – JANUARY 2000
electrical characteristics TJ = 0° to 125°C, VCC = 2.8 V to 5.5 V (unless otherwise noted)
VSENSE–RR and VSENSE–LDO discharge
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
VSENSE–RRdischargeFETcurrentsaturaVSENSE–RR = 1.5 V,
See Note 2
tion
5
mA
VSENSE–RR discharge series resistance
(limits current)
INHIBIT = 0 V,
1
kΩ
VSENSE–RR discharge FET propagation
delay time
See Note 2
VIN = 5.5 V
100
ns
VSENSE–LDO discharge FET current satuVSENSE–LDO = 3.3 V,
ration
See Note 2
5
mA
VSENSE–LDO discharge series
resistance (limits current)
VIN = 5.5 V,
1
kΩ
INHIBIT = 0 V,
VSENSE–LDO discharge FET
See Note 2
propagation delay time
NOTE 2. Ensured by design, not production tested.
100
ns
detailed description
reference/voltage identification
The reference/voltage identification (VID) section consists of a temperature compensated bandgap reference
and a 2-pin voltage selection network. Both ripple regulator and LDO reference voltages are programmed with
each VID setting. The 2 VID pins are inputs to the VID selection network and are tri-level inputs that may be
set to GND, floating (internally 2.5V), or VDRV. The VID codes allow the controller to power both current and
future DSP products. The output voltages may also be programmed by external resistor voltage dividers for any
values not included in the VID code settings. Refer to Table 1 for the VID code settings. The output voltages
of the VID network, VREF–RR & VREF–LDO, are within 1.5% of the nominal setting for all the VID range of 1.3V
to 3.3V. The reference tolerance conditions include a junction temperature range of –40°C to +125°C and a VCC
supply voltage range of 2.8 V to 5.5 V. The VREF–RR output of the reference/VID network is indirectly brought
out through a buffer to the VREFB pin. The voltage on this pin will be within 1.5% of VREF–RR. It is not
recommended to drive loads with VREFB, other than setting the hysteresis of the hysteretic comparator,
because the current drawn from VREFB sets the charging current for the slowstart capacitor. Refer to the
Slowstart section for additional information.
hysteretic comparator
The hysteretic comparator regulates the output voltage of the synchronous-buck converter. The hysteresis is
set by 2 external resistors and is centered around VREF. The 2 external resistors form a resistor divider from
VREFB to ANAGND, and the divided down voltage connects to the VHYST pin. The hysteresis of the
comparator will be equal to twice the voltage difference that is across the VREFB and VHYST pins. The
propagation delay from the comparator inputs to the driver outputs is 250 ns maximum. The maximum
hysteresis setting is 60 mv.
low-side driver
The low-side driver is designed to drive low Rds(on) logic-level N-channel MOSFETs. The current rating of the
driver is 2 amps typical, source and sink. The bias to the low-side driver is internally connected to the regulated
synchronous charge pump output.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
13
TPS56300
DUAL-OUTPUT LOW-INPUT-VOLTAGE
DSP POWER SUPPLY CONTROLLER WITH SEQUENCING
SLVS261A – DECEMBER 1999 – JANUARY 2000
detailed description (continued)
high-side driver
The high-side driver is designed to drive low Rds(on) logic-level N-channel MOSFETs. The current rating of the
driver is 2 amps typical, source and sink. The high-side driver can be configured either as a floating bootstrap
driver or as a ground-reference driver. When configured as a floating driver, the bias voltage to the driver is
developed from the charge pump VDRV voltage. The internal synchronous bootstrap rectifier, connected
between the VDRV and BOOT pins, is a synchronously-rectified MOSFET for improved drive efficiency. The
maximum voltage that can be applied between the BOOT pin and ground is 14 V. The driver can be referenced
to ground by connecting BOOTLO to DRVGND, and connecting a voltage ≥ (4.5 V + VCC ) to the BOOT pin.
deadtime control
Deadtime control prevents shoot-through current from flowing through the main power FETs during switching
transitions by actively controlling the turn-on time of the MOSFET drivers. The high-side driver is not allowed
to turn on until the gate drive voltage to the low-side FET is below 1 V, and the low-side driver is not allowed
to turn on until the voltage at the junction of the 2 FETs (Vphase) is below 2 V.
current sensing
Current sensing is achieved by sampling and holding the voltage across the high-side power FET while the
high-side FET is on. The sampling network consists of an internal 60-Ω switch and an external hold capacitor.
Internal logic controls the turnon and turnoff of the sample/hold switch such that the switch does not turn on until
the Vphase voltage transitions high, and the switch turns off when the input to the high-side driver goes low.
Thus sampling will occur only when the high-side FET is conducting current. The voltage on the IOUT pin equals
2 times the sensed high-side voltage.
droop compensation
The droop compensation network reduces the load transient overshoot / undershoot on VOUT, relative to VREF
(see application information for more details). VOUT is programmed to a voltage greater than VREF by an external
resistor divider from VOUT to the VSENSE pin to reduce the undershoot on VOUT during a low to high load
transient. The overshoot during a high to low load transient is reduced by subtracting the voltage that is on the
DROOP pin from VREF. The voltage on the IOUT pin is divided down with an external resistor divider, and
connected to the DROOP pin.
inhibit
INHIBIT is a TTL compatible comparator pin that is used to enable the controller. When INHIBIT is lower than
the threshold, the output drivers are low and the slowstart capacitor is discharged. When INHIBIT goes high
(above 2.1 V), the short across the slowstart capacitor is released and normal converter operation begins. When
another system logic supply is connected to the INHIBIT pin, this pin controls power sequencing by locking out
controller operation until the system logic supply exceeds the input threshold voltage of the inhibit circuit; thus
the +3.3-V supply and another system logic supply (either +5 V or +12 V) must be above UVLO thresholds
before the controller is allowed to start up. Toggling the INHIBIT pin down clears the fault latch.
VCC & VDRV undervoltage lockout
The VCC undervoltage lockout circuit disables the controller while the VCC supply is below the 2.8-V start
threshold. The VDRV undervoltage lockout circuit disables the controller while the VDRV supply is below the
4.9 V start threshold during powerup. While the controller is disabled, the output drivers will be low, the LDO
drive is off, and the slowstart capacitor will be shorted. When VCC and VDRV exceed the start threshold, the
short across the slowstart capacitor is released and normal converter operation begins.
14
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
TPS56300
DUAL-OUTPUT LOW-INPUT-VOLTAGE
DSP POWER SUPPLY CONTROLLER WITH SEQUENCING
SLVS261A – DECEMBER 1999 – JANUARY 2000
detailed description (continued)
slowstart
The slowstart circuit controls the rate at which VOUT–RR and VOUT–LDO power up (at same time). A capacitor
is connected between the SLOWST and ANAGND pins and is charged by an internal current source. The value
of the current source is proportional to the reference voltage, so that the charging rate of Cslowst is proportional
to the ripple regulator reference voltage. The slowstart charging current is determined by the following equation:
I
I
VREFB
+
SLOWSTART
5
Where IVREFB is the current flowing out of the VREFB pin. It is recommended that no additional loads be
connected to VREFB, other than the resistor divider for setting the hysteresis voltage. Thus these resistor values
will determine the slowstart charging current. The maximum current that can be sourced by the VREFB circuit
is 500 µA. The equation for the slowstart time is:
T
SLOWSTART
+5
C
SLOWSTART
R
VREFB
Where RVREFB is the total external resistance from VREFB to ANAGND.
power good
The power good circuit monitors for an undervoltage condition on VOUT–RR and VOUT–LDO. The powergood
(PWRGD) pin is pulled low if either VOUT–RR is 7% below VREF–RR, or VOUT–LDO is 7% below VREF–LDO.
PWRGD is an open drain output. The powergood pin is also pulled down, if either VCC or VDRV are below their
UVLO thresholds.
overvoltage protection
The overvoltage protection circuit monitors VOUT–RR and VOUT–LDO for an overvoltage condition. If
VOUT–RR or VOUT–LDO are 15% above their reference voltage, then a fault latch is set and both output drivers
and LDO are turned off. The latch will remain set until the VCC or inhibit voltages go below their undervoltage
lockout values. A 1-µs to 5 µs deglitch timer is included for noise immunity.
overcurrent protection
The overcurrent protection circuit monitors the current through the high-side FET. The overcurrent threshold
is adjustable with an external resistor divider between IOUT and ANAGND pins, with the divider voltage
connected to the OCP pin. If the voltage on the OCP pin exceeds 125 mV, then a fault latch is set and the output
drivers are turned off. The latch will remain set until the VCC or inhibit voltages go below their undervoltage
lockout values. A 1-µs to 5-µs deglitch timer is included for noise immunity. The OCP circuit is also designed
to protect the high-side power FET against a short-to-ground fault on the terminal common to both power FETs.
undervoltage protection
The undervoltage protection circuit monitors VOUT–RR and VOUT–LDO for an undervoltage condition. If
VOUT–RR or VOUT–LDO is 15% below their reference voltage, then a fault latch is set and both output drivers
and LDO are turned off. The latch will remain set until the VCC or inhibit voltages go below their undervoltage
lockout values. A 100-µs to 1-ms deglitch timer is included for noise immunity.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
15
TPS56300
DUAL-OUTPUT LOW-INPUT-VOLTAGE
DSP POWER SUPPLY CONTROLLER WITH SEQUENCING
SLVS261A – DECEMBER 1999 – JANUARY 2000
detailed description (continued)
synchronous charge pump
The regulated synchronous charge pump provides drive voltage to the low-side driver at VDRV (5V), and to the
high-side driver when the high-side driver is configured as a floating driver. The minimum drive voltage is 4.5V,
(typical 5V). The minimum short circuit current is 80 mA. The bootstrap capacitor is used to provide Vdrive for
the high-side FET, the power for VLDODRV, and the bias regulator. Instead of diodes, synchronous rectified
MOSFETs are used to reduce voltage drop losses and allow a lower input voltage threshold. The charge pump
oscillator operates at 300 kHz until the UVLO VDRV is set; after which it is synchronized to the converter
switching frequency and is turned on and off to regulate VDRV at 5 V.
The charge pump is designed to operate at a switching frequency of 200 kHz to 400 kHz. Operation at low
frequency may require larger capacitors on CPC and VDRV pin. High frequency (> 400 kHz) may not be
possible.
power sequence
The VOUT–LDO voltage is powered up with respect to the same slowstart reference voltage as the VOUT–RR.
Also, at power down, the VOUT–RR and VOUT–LDO are discharged to ground through P-channel MOSFETs
in series with 1-kΩ resistors.
TYPICAL CHARACTERISTICS
QUIESCENT CURRENT
vs
JUNCTION TEMPERATURE
VCC UVLO HYSTERESIS
vs
JUNCTION TEMPERATURE
13
180
VCC = 3.3 V
Inhibit = 0 V
V CCUVLO Hysteresis – mV
Quiescent Current – mA
175
12
11
170
165
160
155
10
150
0
25
50
75
100
TJ – Junction Temperature – °C
125
0
Figure 1
16
25
50
75
100
TJ – Junction Temperature – °C
Figure 2
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
125
TPS56300
DUAL-OUTPUT LOW-INPUT-VOLTAGE
DSP POWER SUPPLY CONTROLLER WITH SEQUENCING
SLVS261A – DECEMBER 1999 – JANUARY 2000
TYPICAL CHARACTERISTICS
VCC UVLO START THRESHOLD VOLTAGE
vs
JUNCTION TEMPERATURE
SLOWSTART CHARGE CURRENT
vs
JUNCTION TEMPERATURE
15
Slow Start Charge Current – µ A
V CCUVLO Start Threshold Voltage – V
2.750
2.725
2.700
2.675
14
13
12
11
10
2.65
0
25
50
75
100
TJ – Junction Temperature – °C
0
125
50
25
Figure 3
100
VCC = 3.3 V
V(VREFB) = 1.3 V
CS = 0.1 µF
TJ = 27°C
VCC = 3.3 V
V(VREFB) = 1.3 V
I(VREFB) = 65 µA
TJ = 25°C
Slowstart Time – ms
Slowstart Time – ms
125
SLOWSTART TIME†
vs
SLOWSTART CAPACITANCE
1000
100
10
1
10
100
Figure 4
SLOWSTART TIME
vs
SUPPLY CURRENT (VREFB)
1
75
TJ – Junction Temperature – °C
100
1000
10
1
0.1
0.0001
ICC – Supply Current (VREFB) – µA
0.0010
0.0100
0.1000
1
Slowstart Capacitance – µF
Figure 5
Figure 6
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
17
TPS56300
DUAL-OUTPUT LOW-INPUT-VOLTAGE
DSP POWER SUPPLY CONTROLLER WITH SEQUENCING
SLVS261A – DECEMBER 1999 – JANUARY 2000
TYPICAL CHARACTERISTICS
DRIVER
DRIVER
RISE TIME
vs
LOAD CAPACITANCE
FALL TIME
vs
LOAD CAPACITANCE
1000
1000
TJ = 27°C
100
t f – Fall Time – ns
t r – Rise Time – ns
TJ = 27°C
High Side
Low Side
10
1
0.1
1
10
100
High Side
Low Side
10
1
0.1
100
1
CL – Load Capacitance – nF
100
Figure 8
DRIVER
DRIVER
HIGH-SIDE OUTPUT RESISTANCE
vs
JUNCTION TEMPERATURE
LOW-SIDE OUTPUT RESISTANCE
vs
JUNCTION TEMPERATURE
5.0
8
4.5
7
R O – Low-Side Output Resistance – Ω
R O – High-Side Output Resistance – Ω
Figure 7
4.0
3.5
3.0
2.5
2.0
1.5
1.0
6
5
4
3
2
1
0
0
25
50
75
100
TJ – Junction Temperature – °C
125
0
Figure 9
18
10
CL – Load Capacitance – nF
25
50
75
100
TJ – Junction Temperature – °C
Figure 10
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
125
TPS56300
DUAL-OUTPUT LOW-INPUT-VOLTAGE
DSP POWER SUPPLY CONTROLLER WITH SEQUENCING
SLVS261A – DECEMBER 1999 – JANUARY 2000
TYPICAL CHARACTERISTICS
DRIVER
VDRV UVLO START THRESHOLD VOLTAGE
vs
JUNCTION TEMPERATURE
INPUT CURRENT
vs
OUTPUT VOLTAGE
5
4.70
VDRV UVLO Start Threshold Voltage – V
4.5
4
Input Current – A
3.5
3
2 A Typical
2.5
2
1.5
1
4.5 V
0.5
0
4.69
4.68
4.67
4.66
4.65
0
1
2
3
4
5
6
7
8
9
0
25
50
75
100
TJ – Junction Temperature – °C
VO – Output Voltage – V
Figure 11
Figure 12
RIPPLE REGULATOR
POWERGOOD THRESHOLD
vs
JUNCTION TEMPERATURE
VDRV UVLO HYSTERESIS
vs
JUNCTION TEMPERATURE
94.00
Ripple Regulator Powergood Threshold – %
300
280
VDRV UVLO Hysteresis – mV
125
260
240
220
200
180
160
140
120
93.75
93.50
93.25
93.00
92.75
92.50
92.25
92
100
0
25
50
75
100
TJ – Junction Temperature – °C
125
0
Figure 13
25
50
75
100
TJ – Junction Temperature – °C
125
Figure 14
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TPS56300
DUAL-OUTPUT LOW-INPUT-VOLTAGE
DSP POWER SUPPLY CONTROLLER WITH SEQUENCING
SLVS261A – DECEMBER 1999 – JANUARY 2000
TYPICAL CHARACTERISTICS
INHIBIT START THRESHOLD VOLTAGE
vs
JUNCTION TEMPERATURE
INHIBIT HYSTERESIS VOLTAGE
vs
JUNCTION TEMPERATURE
140
Inhibit Hysteresis Voltage – mV
Inhibit Start Threshold Voltage – V
2.100
2.075
2.050
2.025
2.000
130
120
110
100
90
0
25
50
75
100
TJ – Junction Temperature – °C
125
0
25
50
75
100
TJ – Junction Temperature – °C
Figure 15
Figure 16
RIPPLE REGULATOR OVP THRESHOLD
vs
JUNCTION TEMPERATURE
RIPPLE REGULATOR UVP THRESHOLD
vs
JUNCTION TEMPERATURE
77
Ripple Regulator UVP Threshold – %
Ripple Regulator OVP Threshold – %
118
117
116
115
114
113
112
0
25
50
75
100
125
76
75
74
73
72
71
0
TJ – Junction Temperature – °C
25
50
Figure 18
POST OFFICE BOX 655303
75
100
TJ – Junction Temperature – °C
Figure 17
20
125
• DALLAS, TEXAS 75265
125
TPS56300
DUAL-OUTPUT LOW-INPUT-VOLTAGE
DSP POWER SUPPLY CONTROLLER WITH SEQUENCING
SLVS261A – DECEMBER 1999 – JANUARY 2000
TYPICAL CHARACTERISTICS
LDO OVP THRESHOLD
vs
JUNCTION TEMPERATURE
OCP THRESHOLD VOLTAGE
vs
JUNCTION TEMPERATURE
118
135
LDO OVP Threshold – %
133
131
116
115
114
113
129
112
0
25
50
75
100
125
0
25
50
75
100
TJ – Junction Temperature – °C
TJ – Junction Temperature – °C
Figure 19
125
Figure 20
LDO UVP THRESHOLD
vs
JUNCTION TEMPERATURE
77
76
LDO UVP Threshold – %
OCP Treshhold Voltage – mV
117
75
74
73
72
71
0
25
50
75
100
125
TJ – Junction Temperature – °C
Figure 21
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TPS56300
DUAL-OUTPUT LOW-INPUT-VOLTAGE
DSP POWER SUPPLY CONTROLLER WITH SEQUENCING
SLVS261A – DECEMBER 1999 – JANUARY 2000
APPLICATION INFORMATION
The design shown in this datasheet is a reference design for a DSP application. An evaluation module (EVM),
TPS56300EVM–139 (SLVP139), is available for customer testing and evaluation. The following figure is an
application schematic for reference. The circuit can be divided into the power-stage section and the
control-circuit section. The power stage must be tailored to the input/output requirements of the application. The
control circuit is basically the same for all applications with some minor tweaking of specific values. Table 2
shows the values of the power stage components for various output-current options.
LDO
POWER
STAGE
TP6
FB2
+
J2
TP5
+
JP3
L1
3.3 uH
TP8
+
Q1:A
J1
Q4
TP7
TP1
+
TP11
PwrPad
+
TP9
TP3
TP4
CC
U1
TPS56300PWP
TP2 Q1:B
+
Q5
+
+
+
TP10
FB1
JP1
JP2
RIPPLE REGULATOR POWER STAGE
CONTROL SECTION
Figure 22. EVM Schematic
Table 2. EVM Input and Outputs
VIN
5V
22
IIN
4A
VRR
1.8 V
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3.3 V
ILDO
0.5 A
TPS56300
DUAL-OUTPUT LOW-INPUT-VOLTAGE
DSP POWER SUPPLY CONTROLLER WITH SEQUENCING
SLVS261A – DECEMBER 1999 – JANUARY 2000
APPLICATION INFORMATION
Table 3. Ripple Regulator Power Stage Components
Ripple Regulator Section
Ref Des
Function
4A (EVM Design)
8A
12A
20A
C3, C6
Input Bulk Capacitor
C3: open
C6: 150 µF
(Sanyo,
6TPB150M)
C3: 150 µF
C6: 150 µF
(Sanyo,
6TPB150M)
C3: 150 µF
C6: 150 µF
(Sanyo,
6TPB150M)
C3: 150 µF
C6: 2x150 µF
(Sanyo,
6TPB150M)
C11, C2
Input high–freq
Capacitor
C2: 0.1 µF
C11: 0.1 µF
(muRata
GRM39X7R104K016A,
0.1 µF, 16–V, X7R)
C2: 0.1 µF
C11: 0.1 µF
(muRata
GRM39X7R104K016A,
0.1 µF, 16–V, X7R)
C2: 0.1 µF
C11: 0.1 µF
(muRata
GRM39X7R104K016A, 0.1
µF, 16–V, X7R)
C2: 0.33 µF
C11: 0.33 µF
(muRata
GRM39X7R334K016A,
0.33 µF, 16–V, X7R)
C13, C14
Output Bulk Capacitor
C13: 150 µF
(Sanyo, 6TPB150M)
C14: open
C13: 150 µF
(Sanyo, 6TPB150M)
C14: open
C13: 150 µF
C14: 150 µF
(Sanyo, 6TPB150M)
C13: 150 µF
C14: 150 µF
(Sanyo, 6TPB150M)
C15,C30,
C31
Output Mid–freq
Capacitor
C15: open
C30: 10 µF
C31: 10 µF
(muRata
GRM39X7R106K016A,
10 µF, 16–V, X7R)
C15: open
C30: 10 µF
C31: 10 µF
(muRata
GRM39X7R106K016A,
10 µF, 16–V, X7R)
C15: 10 µF
C30: 10 µF
C31: 10 µF
(muRata
GRM39X7R106K016A, 10
µF, 16–V, X7R)
C15: 10 µF
C30: 10 µF
C31: 10 µF
(muRata
GRM39X7R106K016A,
10 µF, 16–V, X7R)
C16
Output High–freq
Capacitor
open
0.1 µF
(muRata
GRM39X7R104K016A,
0.1 µF, 16–V, X7R)
0.1 µF
(muRata
GRM39X7R104K016A, 0.1
µF, 16–V, X7R)
0.1 µF
(muRata
GRM39X7R104K016A,
0.1 µF, 16–V, X7R)
L1
Input filter
3.3 µH
Coilcraft
DO3316P–332, 5.4 A
3.3 µH
Coilcraft
DO3316P–332,5.4 A
1.5 µH
Coilcraft
DO3316P–152,6.4 A
1 µH
Coiltronics
UP3B–1R0, 12.5–A
L2
Output filter
3.3 µH
Coilcraft
DO3316P–332, 5.4 A
3.3 µH
Coilcraft
DO5022P–332HC, 10 A
1.5 µH
Coilcraft
DO5022P–152HC,
15 A
3.3 µH
Micrometals,
T68–8/90 Core w/7T, #16,
25 A
R8
Low Side Gate
Resistor
10 Ω
10 Ω
5.1 Ω
5.1 Ω
Q1A,Q4
Power Switch
Q1A: Dual FET
IRF7311
Q4: IRF7811
Q4: 2xIRF7811
Q4: 2xIRF7811
Q1B,Q5
Synchronous
Switch
Q1B: Dual FET
IRF7311
Q5: IRF7811
Q5: 2xIRF7811
Q5:
2xIRF7811
The values listed in Table 3 are recommendations based on actual test circuits. Many variations of the above
are possible based upon the desires and/or requirements of the user. Performance of the circuit is equally, if
not more, dependent upon the layout than on the specific components, as long as the device parameters are
not exceeded. Fast-response, low-noise circuits require circuits require critical attention to the layout details.
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TPS56300
DUAL-OUTPUT LOW-INPUT-VOLTAGE
DSP POWER SUPPLY CONTROLLER WITH SEQUENCING
SLVS261A – DECEMBER 1999 – JANUARY 2000
APPLICATION INFORMATION
Table 4. LDO Power Stage Components
LDO Section
Ref. Des
Part
VIN
VOUT
VIN
VIN– VDROPOUT
Description
†
Q2:A
IRF7811(EVM)
or
Si4410, IRF7413
FDS6680
Used as a power distribution switch for LDO
output control
Q2:A
IRF9410, Si9410
Low cost solution for low LDO output current (VIN–VOUT)*IOUT < 1 W
Q2:A
IRF7811
Higher current and still surface mount
1 W < (VIN–VOUT)*IOUT) < 2 W
Q2: B
IRLZ24N
High output current requiring heat sink. Low
cost but through–hole package.
(VIN–VOUT)*IOUT > 2 W
† VDROPOUT = IOUT × Rdson. It should be as small as possible.
frequency calculation
With hysteretic control, the switching frequency is a function of the input voltage, the output voltage, the
hysteresis window, the delay of the hysteresis comparator and the driver, the output inductance, the resistance
in the output inductor, the output capacitance, the ESR and ESL in the output capacitor, the output current, and
the turnon resistance of high-side and low-side MOSFET. It is a very complex equation if everything is included.
To make it more useful to designers, a simplified equation is developed that considers only the most influential
factors. The tolerance of the result for this equation is about 30%:
fs
+
V
IN
ǒ
V
V
OUT
IN
ESR
ǒ
V
* VOUT
IN
ǒ
250
Ǔ ȡȧȢ *ǒ
) Ǔ)
10 –9
ESR
T
d
)
250 10 –9 T
V
C
hys
out
L
OUT
Ǔȣȧ
d
Ȥ
* ESL
V
Ǔ
IN
Where fs is the switching frequency (Hz); VOUT is the output voltage (V); VIN is the input voltage (V); COUT is
the output capacitance; ESR is the equivalent series resistance in the output capacitor (Ω); ESL is the equivalent
series inductance in the output capacitor (H); LOUT is the output inductance (H); Td is output feedback RC filter
time constant (S); Vhys is the hysteresis window (V).
hysteresis window
The changeable hysteresis window in TPS56300 is used for switching frequency and output voltage ripple
adjustment. The hysteresis window setup is decided by a two-resistor voltage divider on VREFB and VHYST
pin. Two times of the voltage drop on the top resistor is the hysteresis window. The formula is shown in the
following:
Vhyswindow
R 13
= 2 × VREFB × ( 1 –
)
R 11 + R 13
Where Vhyswindow is the hysteresis window (V); VREFB is the regulated voltage from VREVB (pin 5); R11 is
the top resistor in the voltage divider; R13 is the bottom resistor in the voltage divider. The maximum hysteresis
window is 60 mV.
24
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TPS56300
DUAL-OUTPUT LOW-INPUT-VOLTAGE
DSP POWER SUPPLY CONTROLLER WITH SEQUENCING
SLVS261A – DECEMBER 1999 – JANUARY 2000
APPLICATION INFORMATION
slowstart
Slowstart reduces the start-up stresses on the power-stage components and reduces the input current surge.
The minimum slowstart time is limited to 1 ms due to the power good function deglitch time. Slowstart timing
is dependent of the timing capacitor value on the slowstart pin. The following formula can be used for setting
the slowstart timing:
T
+5
SLOWSTART
C
SLOWSTART
R
VREFB
TSLOWSTART is the slowstart time; CSLOWSTART is the capacitor value on SLOWST (pin 3). RVREFB is the total
resistance on VREFB (pin 5).
current limit
Current limit can be implemented using the on-resistance of the upper FETs as the sensing elements. The IOUT
signal is used for the current limit and the droop function. The voltage at IOUT at the output current trip point
will be:
V
IOUT
+ RON
ǒǒ
I
2
O
Ǔ
RON is the high-side on-time resistance; IO is the output current. The current limit is calculated by using the
formula:
R5
+
R4
I
Ǔ
O MAX
2
R
ON
* 0.125
0.125
Where R4 is the bottom resistor in the voltage divider on OCP pin, and R5 is the top resistor; IO(MAX) is the
maximum current allowed; RON is the high-side FET on-time resistance.
Since the FET on-time resistance varies according to temperature, the current limit is basically for catastrophic
failure.
droop compensation
Droop compensation with the offset resistor divider from VOUT to the VSENSE is used to keep the output voltage
in range during load transients by increasing the output voltage setpoint toward the upper tolerance limit during
light loads and decreasing the voltage setpoint toward the lower tolerance limit during heavy loads. This allows
the output voltage to swing a greater amount and still remain within the tolerance window. The maximum droop
voltage is set with R6 and R7:
V
DROOPǒmaxǓ
+ VIOUTǒmaxǓ
) R7
R6
R6
Where VDROOP(max) is the maximum droop voltage; VIOUT(max) is the maximum VIOUT that reflects the maximum
output current (full load); R6 is the bottom resistor of the divider connected to the DROOP pin, R7 is the top
resistor.
The offset voltage is set to be half of the maximum droop voltage higher than the nominal output voltage, so
the whole droop voltage range is symmetrical to the nominal output voltage. The formula for setting the offset
voltage is:
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TPS56300
DUAL-OUTPUT LOW-INPUT-VOLTAGE
DSP POWER SUPPLY CONTROLLER WITH SEQUENCING
SLVS261A – DECEMBER 1999 – JANUARY 2000
ǒ
Ǔ
APPLICATION INFORMATION
V
OFFSET
+ 12
V
DROOPǒmaxǓ
+ VO
)
R12
R10 R12
Where VOFFSET is the desired offset voltage; VDROOP(max) is the droop voltage at full load; Vo is the nominal
output voltage; R10 is the top resistor of the offset resistor divider, and R12 is the bottom one.
Therefore, with the setup above, at light load, the output voltage is:
V
Ǔ + VOǒnomǓ ) VOFFSET + VOǒnomǓ ) 12
ǒ
O NO LOAD
V
DROOP
And, at full load, the output voltage is:
V
Ǔ + VOǒnomǓ * VOFFSET + VOǒnomǓ * 12
ǒ
V
O FULL LOAD
DROOP
output inductor ripple current
The output inductor current ripple can affect not only the efficiency, but also the output voltage ripple. The
equation for calculating the inductor current ripple is exhibited in the following:
I
+
ripple
V
IN
* VOUT * Iout
L
ǒ
Rdson
Ǔ
) RL
D
Ts
OUT
Where Iripple is the peak-to-peak ripple current (A) through the inductor; VIN is the input voltage (V); VOUT is the
output voltage (V); IOUT is the output current; Rdson is the on-time resistance of MOSFET (Ω); RL is the output
inductor equivalent series resistance; D is the duty cycle; and Ts is the switch cycle (S). From the equation, it
can be seen that the current ripple can be adjusted by changing the output inductor value.
Example:
VIN = 5 V; VOUT = 1.8 V; IOUT = 5 A; Rdson = 10 mΩ; RL = 5 mΩ; D = 0.36; Ts = 5 µs; LOUT = 6 µH
Then, the ripple Iripple = 1 A.
output capacitor RMS current
Assuming the inductor ripple current totally goes through the output capacitor to the ground, the RMS current
in the output capacitor can be calculated as:
IO(rms) =
∆I
12
Where IO(rms) is the maximum RMS current in the output capacitor (A); ∆I is the peak-to-peak inductor ripple
current (A).
Example:
∆I = 1 A, so IO(rms) = 0.29 A
input capacitor RMS current
The input capacitor RMS current is important for input capacitor design. Assuming the input ripple current totally
goes into the input capacitor to the power ground, the RMS current in the input capacitor can be calculated as:
26
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TPS56300
DUAL-OUTPUT LOW-INPUT-VOLTAGE
DSP POWER SUPPLY CONTROLLER WITH SEQUENCING
SLVS261A – DECEMBER 1999 – JANUARY 2000
I
I(rms)
+
Ǹ
I
APPLICATION INFORMATION
2
D
O
(1
* D) ) 121
D
I
2
ripple
Where II(rms) is the input RMS current in the input capacitor (A); IO is the output current (A); Iripple is the
peak-to-peak output inductor ripple current; D is the duty cycle. From the equation, it can be seen that the
highest input RMS current usually occurs at the lowest input voltage, so it is the worst case design for input
capacitor ripple current.
Example:
IO = 5 A; D = 0.36; Iripple = 1 A,
Then, II(rms) = 2.46 A
layout and component value consideration
Good power supply results will only occur when care is given to proper design and layout. Layout and
component value will affect noise pickup and generation and can cause a good design to perform with less than
expected results. With a range of current from milliamps to tens or even hundreds of amps, good power supply
layout and component selection, especially for a fast ripple controller, is much more difficult than most general
PCB design. The general design should proceed from the switching node to the output, then back to the driver
section, and, finally, to placing the low-level components. In the following list are several specific points to
consider before layout and component selection for TPS56300:
1. All sensitive analog components should be referenced to ANAGND. These include components connected
to SLOWST, DROOP, IOUT, OCP, VSENSE, VREFB, VHYST, BIAS, and LOSENSE/LOHIB.
2. The input voltage range for TPS56300 is low from 2.8-V to 5.5-V, so it has a voltage tripler (charge pump)
inside to deliver proper voltage for internal circuitry. To avoid any possible noise coupling, a low ESR
capacitor on VCC is recommended.
3. For the same reason in Item 2, the ANAGND and DRVGND should be connected as close as possible to
the IC.
4. The bypass capacitor should be placed close to the TPS56300.
5. When configuring the high-side driver as a boot-strap driver, the connection from BOOTLO to the power
FETs should be as short and as wide as possible. LOSENSE/LOHIB should have a separate connection
to the FETs since BOOTLO will have large peak current flowing through it.
6. The bulk storage capacitors across VIN should be placed close to the power FETs. High-frequency bypass
capacitors should be placed in parallel with the bulk capacitors and connected close to the drain of the
high-side FET and to the source of the low-side FET.
7. HISENSE and LOSENSE should be connected very close to the drain and source, respectively, of the
high-side FET. HISENSE and LOSENSE should be routed very close to each other to minimize
differential-mode noise coupling to these traces. Ceramic decoupling capacitors should be placed close to
where HISENSE connects to VIN, to reduce high-frequency noise coupling on HISENSE.
The EVM board (SLVP-139) is used in the test. The test results are shown in the following.
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TPS56300
DUAL-OUTPUT LOW-INPUT-VOLTAGE
DSP POWER SUPPLY CONTROLLER WITH SEQUENCING
SLVS261A – DECEMBER 1999 – JANUARY 2000
APPLICATION INFORMATION
RIPPLE OUTPUT
LOAD REGULATION (1.8 V)
RIPPLE OUTPUT EFFICIENCY (1.8 V)
100
1.83
VIN = 3.3 V
1.825
80
VO – Output Voltage – V
Efficiency – %
VIN = 5 V
60
40
VIN = 5 V
1.82
1.815
VIN = 3.3 V
1.81
20
1.805
0
0
1
2
3
4
1.8
5
0
1
2
IO – Output Current – A
5
Figure 24
RIPPLE OUTPUT
LINE REGULATION (1.8 V)
LDO OUTPUT
LOAD REGULATION (3.3 V)
1.83
3.32
3.315
VO – Output Voltage – V
1.825
VO – Output Voltage – V
4
IO – Output Current – A
Figure 23
1.82
1.815
1.81
1.805
3.31
3.305
3.3
3.295
1.8
2
3
4
5
6
7
3.29
2
VIN – Input Voltage – V
3
4
Figure 26
POST OFFICE BOX 655303
5
VIN – Input Voltage – V
Figure 25
28
3
• DALLAS, TEXAS 75265
6
7
TPS56300
DUAL-OUTPUT LOW-INPUT-VOLTAGE
DSP POWER SUPPLY CONTROLLER WITH SEQUENCING
SLVS261A – DECEMBER 1999 – JANUARY 2000
APPLICATION INFORMATION
DROOP COMPENSATION EFFECT
Load Current
4
400 A/µs
4A
2
0
VO – Output Voltage – mV
Recovery Time
100
0
Output Voltage
–100
–200
0
5
10
15
20 25 30
t – Time – µs
35
10
I L – Load Current – A
6
40
45
5
0
–5
No Droop
280 mV
Output Voltage
200
100
220 mV
0
With Droop
–100
50
0
0.5
1
Figure 27
1.5
2 2.5 3
t – Time – ms
3.5
4
4.5
5
Figure 28
SLOWSTART
6
5
VO – Output Voltage – mV
VO – Output Voltage – mV
I L – Load Current – A
HYSTERESIS CONTROL
TRANSIENT RESPONSE
4
3.3 V
3
2
1
1.8 V
0
–1
–2
0
4
8
12
16 20 24
t – Time – ms
28
32
36
40
Figure 29
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TPS56300
DUAL-OUTPUT LOW-INPUT-VOLTAGE
DSP POWER SUPPLY CONTROLLER WITH SEQUENCING
SLVS261A – DECEMBER 1999 – JANUARY 2000
APPLICATION INFORMATION
layouts
Figure 30. Top Layer
Figure 31. Bottom Layer (Top View)
30
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TPS56300
DUAL-OUTPUT LOW-INPUT-VOLTAGE
DSP POWER SUPPLY CONTROLLER WITH SEQUENCING
SLVS261A – DECEMBER 1999 – JANUARY 2000
APPLICATION INFORMATION
bill of materials
REF
PN
Description
MFG
Size
C1
10TPA33M
Capacitor, POSCAP, 33 µF, 10 V
Sanyo
C
C2, C20, C21, C30, C31
Std
Capacitor, Ceramic, 10 µF, 16 V
Sanyo
1210
C3. C6, C8, C13, C25
6TPB150M
Capacitor, POSCAP, 150 µF, 6 V
Sanyo
D
C4, C5, C11, C12, C23, C26,
C27,
Std
Capacitor, Ceramic, 0.1 µF, 16 V
Sanyo
603
C7, C22
Std
Capacitor, Ceramic, 1 µF, 16 V
Sanyo
805
C9
Std
Open
1210
C10, C16
Std
Open
603
C14, C15
Std
Open
C17, C24
Std
Capacitor, Ceramic, 1000 pF, 16
V
Sanyo
603
C18, C19
Std
Capacitor, Ceramic, 1 µF, 16 V
Sanyo
805
D1
SML-LX2832G
Diode, LED, Green, 2.1 V SM
Lumwx
1210
L1, L2
DO3316P-332
Inductor, 3.3 µH, 5.4 A
Coilcraft
0.5 × 0.37 in
J1
ED2227
Terminal Block, 4-pin, 15 A, 5.08
mm
OST
5.08 mm
J2
ED1515
Terminal Block, 3-pin, 6 A, 3.5
mm
OST
n, 6 A,
JP1, JP2
S1132-3-ND
Header, Right straight, 3-pin, 0.1
ctrs, 0.3” pins
Sullins
#S1132-3-ND
JP1shunt
929950-00-ND
Shunt jumper, 0.1” (for JP1)
3M
0.1”
J3
S1132-2-ND
Header, Right straight, 2-pin, 0.1
ctrs, 0.3” pins
Sullins
#S1132-2-ND
Q1
Q2:A, Q4, Q5
IRF7811
Q2:B
D
Open
SO-8
MOSFET, N-ch, 30 V, 10 mΩ
SO-8
Open
?
Q3
2N7002DICT-N
MOSFET, N-ch, 115 mA, 1.2 Ω
R3
std
Resistor, 10 kohms, 5 %
603
R4
std
Resistor, 1 kohms, 1%
603
R5
std
Resistor, 0 ohms, 1%
603
R6
std
Resistor, 1 kohms, 1%
603
R7
std
Resistor, 3.32 kohms, 1%
603
R8
std
Resistor, 10 ohms, 5 %
603
R9
std
Resistor, 2.7 ohms, 5 %
1206
R10
std
Resistor, 150 ohms, 5 %
603
R11
std
Resistor, 100 ohms, 1 %
603
R12
std
Resistor, 10 kohms, 5 %
603
R13
std
Resistor, 20.0 kohms, 1 %
603
TP1–TP10
240–345
Test Point, Red
Farnell
TP11
131–4244–00
Adaptor, 3.5-mm probe clip ( or
131–5031–00)
Tektronix
U1
TPS56300PWP
Dual controller
POST OFFICE BOX 655303
Diodes, Inc.
TO-236
TSSOP–28pin
• DALLAS, TEXAS 75265
31
TPS56300
DUAL-OUTPUT LOW-INPUT-VOLTAGE
DSP POWER SUPPLY CONTROLLER WITH SEQUENCING
SLVS261A – DECEMBER 1999 – JANUARY 2000
APPLICATION INFORMATION
Power Supply
5–V, 5–A Supply
– +
Load
+
0–4A
–
6.8 Ohms
2W
Note: All wire pairs should be twisted.
Figure 32. Test Setup
32
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
TPS56300
DUAL-OUTPUT LOW-INPUT-VOLTAGE
DSP POWER SUPPLY CONTROLLER WITH SEQUENCING
SLVS261A – DECEMBER 1999 – JANUARY 2000
MECHANICAL DATA
PWP (R-PDSO-G**)
PowerPAD PLASTIC SMALL-OUTLINE PACKAGE
20-PIN SHOWN
0,30
0,19
0,65
20
0,10 M
11
Thermal Pad
(See Note D)
4,50
4,30
0,15 NOM
6,60
6,20
Gage Plane
1
10
0,25
A
0°– 8°
0,75
0,50
Seating Plane
0,15
0,05
1,20 MAX
PINS **
0,10
14
16
20
24
28
A MAX
5,10
5,10
6,60
7,90
9,80
A MIN
4,90
4,90
6,40
7,70
9,60
DIM
4073225/E 03/97
NOTES: B.
C.
D.
E.
All linear dimensions are in millimeters.
This drawing is subject to change without notice.
Body dimensions do not include mold flash or protrusions.
The package thermal performance may be enhanced by bonding the thermal pad to an external thermal plane. This pad is electrically
and thermally connected to the backside of the die and possibly selected leads.
F. Falls within JEDEC MO-153
PowerPAD is a trademark of Texas Instruments Incorporated.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
33
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