CSP-12 TPS61050 TPS61052 QFN-10 www.ti.com SLUS525 – MARCH 2007 1.2-A HIGH POWER WHITE LED DRIVER 2-MHz SYNCHRONOUS BOOST CONVERTER WITH I2C COMPATIBLE INTERFACE FEATURES • • • • • • • • • • • • • DESCRIPTION Four Operational Modes – Torch and Flash up to ILED = 1200 mA – Voltage-Regulated Boost Converter: 4.5/5.0/5.25 V – Shutdown: 0.3 µA (typ) Total Solution Circuit Area < 25 mm2 Up to 96% Efficiency I2C-Compatible Interface up to 400 kbps Integrated LED Turn-On Safety Timer Zero Latency TX-Masking Input (TPS61050) Hardware Voltage Mode Selection Input (TPS61052) Integrated ADC for LED VF Monitoring Integrated Low Light Dimming Mode LED Disconnect During Shutdown Open/Shorted LED Protection Over-Temperature Protection Available in a 12-Pin NanoFree™ (CSP) and 10-Pin QFN Packaging APPLICATIONS • • Camera White LED Torch/Flash for Cell Phones, Smart-Phones and PDAs Audio Amplifier Power Supply The TPS6105x device is based on a high-frequency synchronous-boost topology with constant current sink to drive single white LEDs. The device uses an inductive fixed-frequency PWM control scheme using small external components, minimizing input ripple current. The 2-MHz switching frequency allows the use of small and low profile 2.2-µH inductors. To optimize overall efficiency, the device operates with only a 250 mV LED feedback voltage. The TPS6105x device not only operates as a regulated current source, but also as a standard voltage-boost regulator. This additional operating mode can be useful to supply other high-power devices in the system, such as a hands-free audio power amplifier, or any other component requiring a supply voltage higher than the battery voltage (refer to TPS61052). For highest flexibility, the LED current or the desired output voltage can be programmed via an I2C compatible interface. To simplify flash synchronization with the camera module, the device offers a trigger pin (FLASH_SYNC) for fast LED turn-on time. When the TPS6105x is not in use, it can be put into shutdown mode via the I2C-compatible interface, reducing the input current to 0.3 µA (typ). During shutdown, the LED pin is high impedance to avoid leakage current through the LED. 4.7 mm TPS61050 VOUT CIN P LED I 2C I/F SCL SDA L1 LED SENSE 4.7 mm P INDUCTOR C1 COUT 10 mF P AVIN AGND SW SW INPUT CAP 2.2 mH + BATTERY PGND DIGITAL I/O L GPIO AGND PGND PGND P PGND OUTPUT CAP FLASH_SYNC C2 LED ANODE Figure 1. Typical Application Figure 2. Typical PC-Board Layout Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. NanoFree, PowerPAD are trademarks of Texas Instruments. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2007, Texas Instruments Incorporated TPS61050 TPS61052 www.ti.com SLUS525 – MARCH 2007 These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. AVAILABLE OPTIONS TA PART –40°C to 85°C (1) NUMBER (1) SAFETY TIMER MAXIMUM DURATION PACKAGE MARKING PACKAGE TPS61050YZG 1.02 s 61050 CSP-12 TPS61050DRC 1.02 s BRV QFN-10 TPS61052YZG 1.02 s 61052 CSP-12 TPS61052DRC 1.02 s BRW QFN-10 The YZG package is available in tape and reel. Add R suffix (TPS6105xYZGR, TPS6105xDRCR) to order quantities of 3000 parts. Add T suffix (TPS6105xYZGT, TPS6105xDRCT) to order quantities of 250 parts. ABSOLUTE MAXIMUM RATINGS over operating free-air temperature range (unless otherwise noted) (1) Voltage range on AVIN, VOUT, SW, LED (2) Voltage range on SCL, SDA, FLASH_SYNC, GPIO, ENVM (2) Input current on GPIO (3) TA Operating ambient temperature range TJ (MAX) Maximum operating junction temperature Tstg Storage temperature range Human body model ESD rating (4) Charge device model Machine model (1) (2) (3) (4) TPS6105X UNIT –0.3 to 7 V –0.3 to 7 V 25 mA –40 to 85 °C 150 °C –65 to 150 °C 2 kV 1 kV 200 V Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute–maximum–rated conditions for extended periods may affect device reliability. All voltage values are with respect to network ground terminal. In applications where high power dissipation and/or poor package thermal resistance is present, the maximum ambient temperature may have to be derated. Maximum ambient temperature (TA(max)) is dependent on the maximum operating junction temperature (TJ(max)), the maximum power dissipation of the device in the application (PD(max)), and the junction-to-ambient thermal resistance of the part/package in the application (θJA), as given by the following equation: TA(max)= TJ(max)–(θJA X PD(max)). The human body model is a 100-pF capacitor discharged through a 1.5-kΩ resistor into each pin. The machine model is a 200-pF capacitor discharged directly into each pin. DISSIPATION RATINGS PACKAGE (1) (2) 2 THERMAL RESISTANCE (1) (2) POWER RATING TA = 25°C DERATING FACTOR ABOVE (1) (2) TA = 25°C YZG θJA= 89°C/W θJB= 35°C/W 1.1 W 12 mW/°C DRC θJA= 49°C/W θJC= 3.2°C/W 2.4 W 20 mW/°C Measured with high-K board. Maximum power dissipation is a function of TJ(max), θJA and TA. The maximum allowable power dissipation at any allowable ambient temperature is PD = (TJ(max)–TA)/ θJA. Submit Documentation Feedback TPS61050 TPS61052 www.ti.com SLUS525 – MARCH 2007 ELECTRICAL CHARACTERISTICS Unless otherwise noted the specification applies for VIN = 3.6 V over an operating junction temp. of –40°C ≤ TJ ≤ 125°C. Typical values are for TA = 25°C. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT SUPPLY CURRENT Input voltage range VIN IQ ISD 2.5 Minimum input voltage for start-up MODE_CTRL[1:0] = 11, OV[1:0] = 01, RL = 10 Ω Operating quiescent current into AVIN MODE_CTRL[1:0] = 01, ILED = 0 mA 8.5 MODE_CTRL[1:0] = 00, OV[1:0] ≠ 11 – 40°C ≤ TJ ≤ 85°C 0.3 MODE_CTRL[1:0] = 00, OV[1:0] = 11 – 40°C ≤ TJ ≤ 85°C 140 VIN falling 2.3 Shutdown current into AVIN VUVLO Undervoltage lockout threshold 6.0 V 2.5 V mA 3.0 µA µA 2.4 V OUTPUT VOUT Output voltage range OVP Output overvoltage protection OVP Current regulator mode VIN 5.5 Voltage regulator mode 4.5 5.25 VOUT rising 5.7 Output overvoltage protection hysterisis D Minimum duty cycle LED current 6.25 V V 7.5% accuracy (1) 0.25 V ≤ VLED ≤ 2.0 V, 50 mA ≤ ILED ≤ 250 mA, TJ = 50°C –15% 15% 0.25 V ≤ VLED ≤ 2.0 V, 200 mA ≤ ILED ≤ 1200 mA, TJ = 50°C –12% 12% LED current temperature coefficient VLED 6.0 0.15 V 0.08 DC output voltage accuracy 2.5 V ≤ VIN ≤ 0.9 VOUT, PWM operation LED sense voltage ILED = 1200 mA 250 LED input leakage current VLED = VOUT = 5 V, –40°C ≤ TJ ≤ 85°C 0.1 –3% %/°C 3% mV 1 µA POWER SWITCH rDS(on) Ilkg(SW) Switch MOSFET on-resistance Rectifier MOSFET on-resistance Switch MOSFET leakage Rectifier MOSFET leakage Switch current limit 0.1 1 0.1 1 µA 850 1000 1150 2.5 V ≤ VIN ≤ 6.0 V, ILIM bits = 01, 10 (1) 1275 1500 1725 2.5 V ≤ VIN ≤ 6.0 V, ILIM bits = 11 (1) 1700 2000 2300 140 160 °C 20 °C Thermal shutdown (1) Thermal shutdown hysteresis mΩ 80 VDS = 6.0 V, –40°C ≤ TJ ≤ 85°C 2.5 V ≤ VIN ≤ 6.0 V, ILIM bits = 00 Ilim 80 VOUT = VGS = 3.6 V (1) mA OSCILLATOR fSW Oscillator frequency 1.8 2.0 2.2 MHz ±0.25 ±1 LSB ADC Resolution Total error (1) 3 VLED = 0.25 V, assured monotonic by design Bits SDA, SCL, GPIO, ENVM, FLASH_SYNC V(IH) High-level input voltage V(IL) Low-level input voltage V(OL) I(LKG) (1) 1.2 V 0.4 V Low-level output voltage (SDA) IOL = 8 mA 0.3 Low-level output voltage (GPIO) DIR = 1, IOL = 8 mA 0.3 Logic input leakage current Input connected to VIN or GND, –40°C ≤ TJ ≤ 85°C 0.01 GPIO pull-down resistance DIR = 0, GPIO ≤ 0.4 V (TPS61050) 400 kΩ ENVM pull-down resitance ENVM ≤ 0.4 V (TPS61052) 400 kΩ FLASH_SYNC pull-down resistance FLASH_SYNC ≤ 0.4 V 400 kΩ 0.1 V µA Assured by design. Not tested in production. Submit Documentation Feedback 3 TPS61050 TPS61052 www.ti.com SLUS525 – MARCH 2007 ELECTRICAL CHARACTERISTICS (continued) Unless otherwise noted the specification applies for VIN = 3.6 V over an operating junction temp. of –40°C ≤ TJ ≤ 125°C. Typical values are for TA = 25°C. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT TIMING Start-up time time (2) LED current settling triggered by rising edge on FLASH_SYNC LED current settling TX mask (2) time (2) triggered by From shutdown into torch mode ILED = 75 mA 1.2 ms From shutdown into voltage mode via ENVM IOUT = 0 mA 650 µs MODE_CTRL[1:0] = 10, ILED = from 0 mA to 900 mA 400 µs 20 µs MODE_CTRL[1:0] = 10, ILED = 900 mA to 150 mA Settling time to ±15% of the target value I2C INTERFACE TIMING CHARACTERISTICS (1) PARAMETER fSCL SCL clock frequency tBUF Bus free time between a STOP and START condition tHD; tSTA Hold time (repeated) START condition tLOW LOW period of the SCL clock tHIGH HIGH period of the SCL clock tSU; tSTA Setup time for a repeated START condition tSU; tDAT Data setup time tHD; tDAT Data hold time tRCL Rise time of SCL signal tRCL1 Rise time of SCL signal after a repeated START condition and after an acknowledge bit tFCL Fall time of SCL signal tRDA Rise time of SDA signal tFDA Fall time of SDA signal tSU; tSTO Setup time for STOP condition CB Capacitive load for SDA and SCL (1) 4 TEST CONDITIONS MIN TYP MAX Standard mode 100 Fast mode 400 UNIT kHz Standard mode 4.7 Fast mode 1.3 Standard mode 4.0 µs Fast mode 600 ns Standard mode 4.7 Fast mode 1.3 Standard mode 4.0 Fast mode 600 ns Standard mode 4.7 µs Fast mode 600 ns Standard mode 250 Fast mode 100 µs µs µs ns Standard mode 0 3.45 Fast mode 0 0.9 Standard mode 20 + 0.1CB 1000 Fast mode 20 + 0.1CB 300 Standard mode 20 + 0.1CB 1000 Fast mode 20 + 0.1CB 1000 Standard mode 20 + 0.1CB 300 Fast mode 20 + 0.1CB 300 Standard mode 20 + 0.1CB 1000 Fast mode 20 + 0.1CB 300 Standard mode 20 + 0.1CB 300 Fast mode 20 + 0.1CB 300 Standard mode 4.0 Fast mode 600 Submit Documentation Feedback ns ns ns ns ns µs ns 400 Assured by design. Not tested in production. µs pF TPS61050 TPS61052 www.ti.com SLUS525 – MARCH 2007 DEVICE INFORMATION I2C TIMING DIAGRAMS SDA tf tLOW tf tsu;DAT tr tBUF tr thd;STA SCL thd;STA thd;DAT S tsu;STA HIGH tsu;STO Sr P S Figure 3. Serial Interface Timing for F/S-Mode PIN ASSIGMENTS TERMINAL FUNCTIONS TERMINAL NO. (QFN) NO. (CSP) I/O AVIN 5 D3 I This is the input voltage pin of the device. Connect directly to the input bypass capacitor. VOUT 9 A2 O Boost converter output. LED 6 D2 I LED return input. This feedback pin regulates the LED current through the internal sense resistor by regulating the voltage across it. The regulation operates with typically 250 mV dropout voltage. Connect to the cathode of the LED. FLASH_SYNC 10 A1 I Flash strobe pulse synchronization input. NAME DESCRIPTION FLASH_SYNC = LOW (GND): The device is operating and regulating the LED current to the torch current level (TC). FLASH_SYNC = HIGH (VIN): The device is operating and regulating the LED current to the flash current level (FC). SCL 2 B3 I SDA 1 A3 I/O Serial interface address/data line. This pin must not be left floating and must be terminated. GPIO 3 C3 I/O General purpose input/output (refer to REGISTER2). This pin can either be configured as a logic input or as an open-drain output (TPS61050). ENVM 3 C3 I SW 8 B1, B2 I/O PGND 7 C1, C2 AGND 4 D1 Analog ground. N/A Internally connected to PGND. PowerPAD™ Serial interface clock line. This pin must not be left floating and must be terminated. Enable pin for voltage mode boost converter (TPS61052). Inductor connection. Drain of the internal power MOSFET. Connect to the switched side of the inductor. SW is high impedance during shutdown. Power ground. Connect to AGND underneath IC. Submit Documentation Feedback 5 TPS61050 TPS61052 www.ti.com SLUS525 – MARCH 2007 FUNCTIONAL BLOCK DIAGRAM AVIN SW Undervoltage Lockout Bias Supply VREF = 1.22 V Ramp Compensation Bandgap REF OVP COMPARATOR VOUT S ERROR AMPLIFIER Control Logic VREF P COMPARATOR CURRENT REGULATION VOLTAGE REGULATION 2 MHz Oscillator D = k*(VOUT-LED) 3-bit + ADC - SENSE FB SCL SDA FLASH_SYNC Max tON Timer I2C I/F Control Logic LED ON/OFF CURRENT CONTROL DAC P LED Current Regulator GPIO or ENVM P AGND 6 Submit Documentation Feedback PGND TPS61050 TPS61052 www.ti.com SLUS525 – MARCH 2007 TIMER BLOCK DIAGRAM (TPS61050) LED CURRENT CONTROL TX -OFF ILED 0 0 Torch Current 0 1 Torch Current 1 0 Flash Current 1 1 Torch Current (GPIO Bit) 0: Input 1: Output Port Direction (DIR) GPIO 400 kW (GPIO Bit) CURRENT REGULATOR MODE - TORCH/FLASH ACTIVE MODE 0 = LOW MODE 1 = HIGH 0 1 0 TX -OFF Flash Blanking (Tx-MASK) MODE 0 MODE 1 FLASH_SYNC 1 0 1 400 kW Safety Timer Trigger (STT) Edge Detect LED CURRENT CONTROL 0: TORCH CURRENT LEVEL 1: FLASH CURRENT LEVEL Start Flash/Timer (SFT) Start tSTIM 30.5 Hz 2 MHz CLOCK 16-bit Prescaler Safety Timer Time-Out (TO) Dimming (DIM) 122 Hz Timer Value (STIM) Timer Value (DCTIM LED ON/OFF CONTROL Duty-Cycle Generator (0.8% . . . 8.6%) 0: LED OFF 1: TORCH CURRENT LEVEL Submit Documentation Feedback 7 TPS61050 TPS61052 www.ti.com SLUS525 – MARCH 2007 TIMER BLOCK DIAGRAM (TPS61052) Enable Voltage Mode CURRENT REGULATOR MODE - TORCH/FLASH ACTIVE MODE 0 = LOW MODE 1 = HIGH ENVM 400 kW MODE 0 MODE 1 FLASH_SYNC 1 400 kW 0 1 Safety Timer Trigger (STT) Edge Detect LED CURRENT CONTROL 0: TORCH CURRENT LEVEL 1: FLASH CURRENT LEVEL Start FLASH/Timer (SFT) Start tSTIM 2 MHz CLOCK 16-bit Prescaler 30.5 Hz Safety Timer Time-Out (TO) Dimming (DIM) 122 Hz Timer Value (STIM) Timer Value (DCTIM) LED ON/OFF CONTROL Duty-Cycle Generator (0.8% . . . 8.6%) 0: LED OFF 1: TORCH CURRENT LEVEL PARAMETER MEASUREMENT INFORMATION TPS6105X L 2.2µH VIN SW SW VOUT C OUT 10 µF P AVIN CIN P P LED I2 C I/F SCL SDA GPIO FLASH_SYNC AGND PGND PGND List Of Components: - L = Wuerth Elektronik WE-PD S Series - CIN = COUT = TDK C1605X5R0J106MT 8 Submit Documentation Feedback P TPS61050 TPS61052 www.ti.com SLUS525 – MARCH 2007 TYPICAL CHARACTERISTICS Table 1. Table of Graphs FIGURE LED Power Efficiency vs. Input Voltage Figure 4, Figure 5 DC Input Current vs. Input Voltage Figure 6 LED Current vs. LED Pin Headroom Voltage Figure 7 LED Current vs. LED Current Digital Code Figure 8, Figure 9, Figure 10 Voltage Mode Efficiency vs. Output Current Figure 11 DC Output Voltage vs. Load Current Figure 12 DC Output Voltage vs. Input Voltage Figure 13 Quiescent Current vs. Input Voltage Figure 14 Shutdown Current vs. Input Voltage Figure 15 Junction Temperature vs. GPIO Voltage Figure 16 PWM Operation Figure 17 Down-Mode Operation Figure 18 Voltage Mode Load Transient Response Figure 19 Down-Mode Line Transient Response Figure 20 Duty Cycle Jitter Figure 21 Input Ripple Voltage Figure 22 Low-Light Dimming Mode Operation Figure 23 Torch/Flash Sequence Figure 24 TX-Masking Operation Figure 25, Figure 26, Figure 27 Junction Temperature Monitoring Figure 28 Start-up Into Torch Operation Figure 29, Figure 30 LED POWER EFFICIENCY vs INPUT VOLTAGE LED POWER EFFICIENCY vs INPUT VOLTAGE 100 ILED = 250 mA 90 ILED = 150 mA 80 ILED = 100 mA 70 60 ILED = 50 mA 50 40 30 20 ILIM = 2000 mA 10 0 2.5 2.9 3.3 3.7 4.1 4.5 VI - Input Voltage - V 4.9 LED Power Efficiency (PLED/PIN) - % LED Power Efficiency (PLED/PIN) - % 100 ILED = 1200 mA 90 80 70 ILED = 300 mA ILED = 500 mA 60 ILED = 700 mA 50 ILED = 900 mA 40 30 20 ILIM =2000 mA 10 5.3 5.5 0 2.5 Figure 4. 2.9 3.3 3.7 4.1 4.5 VI - Input Voltage - V 4.9 5.3 5.5 Figure 5. Submit Documentation Feedback 9 TPS61050 TPS61052 www.ti.com SLUS525 – MARCH 2007 DC INPUT CURRENT vs INPUT VOLTAGE 2500 1400 ILIM = 2000 mA 2250 ILED = 700 mA 2000 ILIM = 2000 mA ILED = 900 mA 1750 ILED = 1200 mA 1500 1250 1000 750 1000 ILED = 900 mA 800 ILED = 700 mA 600 ILED = 500 mA 400 ILED = 150 mA 500 ILED = 500 mA 2.9 3.3 ILED = 300 mA 3.7 4.1 4.5 VI - Input Voltage - V 4.9 0 250 5.3 5.5 650 750 850 Figure 7. LED CURRENT vs LED CURRENT DIGITAL CODE LED CURRENT vs LED CURRENT DIGITAL CODE ILIM = 2000 mA 1200 VIN = 4.5 V 1100 VIN = 3.6 V 950 1050 VIN = 2.5 V 140 120 100 LED Current - mA 200 180 160 VIN = 4.5 V VIN = 3.6 V 1000 220 LED Current - mA 550 1300 240 900 VIN = 2.5 V 800 700 600 500 400 80 300 60 200 40 100 0 40 80 120 160 200 240 LED Current Digital Code - mA 280 300 0 Figure 8. 10 450 Figure 6. ILIM = 2000 mA 260 20 0 0 350 LED Pin Headroom Voltage - mV 300 280 ILED = 75 mA 200 250 0 2.5 ILED = 1200 mA 1200 LED Current - mA DC Input Current - mA LED CURRENT vs LED PIN HEADROOM VOLTAGE 200 400 600 800 Figure 9. Submit Documentation Feedback 1000 LED Current Digital Code - mA 1200 1300 TPS61050 TPS61052 www.ti.com SLUS525 – MARCH 2007 LED CURRENT vs LED CURRENT DIGITAL CODE 1300 ILIM = 2000 mA 1200 VOLTAGE MODE EFFICIENCY vs LOAD CURRENT 100 TA = 85°C VIN = 4.2 V 90 1100 80 1000 70 TA = 25°C 800 700 TA = -40°C 600 500 Efficiency - % 900 LED Current - mA VIN = 3.6 V 400 VIN = 3 V VIN = 2.5 V 60 50 40 30 300 20 200 VOUT = 5 V, ILIM = 2000 mA 10 100 0 0 0 5.15 200 0 400 600 800 1000 1200 1300 LED Current Digital Code - mA Figure 11. DC OUTPUT VOLTAGE vs OUTPUT CURRENT DC OUTPUT VOLTAGE vs INPUT VOLTAGE 5.60 5.50 5.05 VIN = 4.2 V 5 VIN = 3.6 V VIN = 3 V DC Output Voltage - V 5.10 DC Output Voltage - V 10 100 1000 IO - Output Current - mA Figure 10. VOUT = 5 V, ILIM = 2000 mA 4.95 1 VOUT = 5 V, ILIM = 2000 mA 10000 IOUT = 0 mA IOUT = 100 mA 5.40 5.30 IOUT = 1000 mA 5.20 5.10 5 VIN = 2.5 V 4.90 4.90 4.85 0.1 4.80 1 10 100 1000 IO - Output Current - mA 10000 2.5 Figure 12. 2.9 3.3 3.7 4.1 4.9 4.5 VI - Input Voltage - V 5.3 5.5 Figure 13. Submit Documentation Feedback 11 TPS61050 TPS61052 www.ti.com SLUS525 – MARCH 2007 QUIESCENT CURRENT vs INPUT VOLTAGE SHUTDOWN CURRENT vs INPUT VOLTAGE 15 1.40 Voltage Mode Regulation, VO = 5 V 14 13 TA = 85°C 1.20 Shutdown Current - mA Quiescent Current - mA 12 11 10 9 8 7 6 5 1 0.80 0.60 TA = 25°C 0.40 4 3 2 1 0 2.5 TA = -40°C 0.20 2.9 3.3 3.7 4.1 4.5 VI - Input Voltage - V 4.9 5.3 5.5 0 2.5 2.9 3.3 3.7 4.1 4.5 4.9 VI - Input Voltage - V Figure 14. Figure 15. JUNCTION TEMPERATURE vs GPIO VOLTAGE PWM OPERATION 200 GPIO = Input, IGPIO = -100 mA SW (2V/div) 150 125 100 75 50 IL (200mA/div - 0.6 A Offset) 25 GPIO Input Buffer 0 VGPIO TJ - Junction Temperature - °C 175 -25 -50 -0.50 -0.45 -0.40 -0.35 -0.30 100 mA VOUT (50mV/div - 5 V Offset) -0.25 -0.20 t - Time = 125 ns/div GPIO Voltage - V Figure 16. 12 VI = 3.6 V, VO = 5 V, IO = 500 mA, ILIM = 2000 mA Figure 17. Submit Documentation Feedback 5.3 5.5 TPS61050 TPS61052 www.ti.com SLUS525 – MARCH 2007 DOWN-MODE OPERATION VOLTAGE MODE LOAD TRANSIENT RESPONSE VI = 3.6 V, VO = 5 V, ILIM = 2000 mA ILED (50mA/div) VOUT (500 mV/div - 5 V Offset) VOUT (500 mV/div - 3.5 V Offset) LED Headroom Voltage (1V/div) IL (500 mA/div) IL (50mA/div) VI = 4.2 V, ILED = 75 mA IOUT (500 mA/div) t - Time = 250 ns/div t - Time = 50 ms/div Figure 18. Figure 19. DOWN-MODE LINE TRANSIENT RESPONSE DUTY CYCLE JITTER VOUT (200 mV/div - 4 V Offset) Battery Voltage (200 mV/div - 4 V Offset) TRIGGERED ON RISING EDGE ILED (100 mA/div - 0.3 A Offset) SW (1 V/div) IL (200 mA/div - 0.3 A Offset) VI = 3.6 V to 3.9 V, ILED = 500 mA, ILIM = 2000 mA t - Time = 20 ms/div VI = 3.6 V, VO = 5 V, IO = 500 mA, ILIM = 2000 mA t - Time = 50 ns/div Figure 20. Figure 21. Submit Documentation Feedback 13 TPS61050 TPS61052 www.ti.com SLUS525 – MARCH 2007 INPUT RIPPLE VOLTAGE Battery Voltage (20 mV/div - 3.7 V Offset) LOW-LIGHT DIMMING MODE OPERATION Frequency = 121 Hz Duty Cycle = 6.25% VOUT (100 mV/div - 5 V Offset) ILED (20 mA/div) IL (500 mA/div - 0.5 A Offset) VOUT (200 mV/div - 3.5 V Offset) ILED (200 mA/div - 0.7 A Offset) Li-Polymer Battery at 3.7 V, ILED = 1200 mA, ILIM = 2000 mA VIN = 3.6 V, ITORCH = 75 mA, DCTIM[2:0] = 110 t - Time = 2 ms/div t - Time = 500 ns/div Figure 22. Figure 23. TORCH/FLASH SEQUENCE TX-MASKING OPERATION FLASH_SYNC (2 V/div) FLASH_SYNC (2 V/div) SAFETY TIMER LIMITATION GPIO (Tx-MASK) (2 V/div) ILED (500 mA/div) ILED (500 mA/div) VOUT (500 mV/div - 3.35 V Offset) LED Pin Headroom Voltage (200 mV/div) IL (500 mA/div) VI = 3.2 V, ILIM = 2000 mA, ILED = 75 mA (Torch) to 700 mA (Flash), STIM[5:0] = 1 0001 (558 ms) VI = 3.6 V, ILIM = 2000 mA, DIR bit = 0, Tx-MASK bit = 1, TC[2:0] = 111, FC[2:0] = 111 t - Time = 100 ms/div t - Time = 200 ms/div Figure 24. 14 Figure 25. Submit Documentation Feedback TPS61050 TPS61052 www.ti.com SLUS525 – MARCH 2007 TX-MASKING OPERATION TX-MASKING OPERATION VI = 3.6 V, ILIM = 2000 mA, DIR bit = 0, Tx-MASK bit = 1, Torch = 150 mA / Flash = 900 mA VI = 3.6 V, ILIM = 2000 mA, DIR bit = 0, Tx-MASK bit = 1, Torch = 150 mA / Flash = 900 mA GPIO (Tx-MASK) (2 V/div) GPIO (Tx-MASK) (2 V/div) ILED (500 mA/div) ILED (500 mA/div) IL (500 mA/div) IL (500 mA/div) t - Time = 50 ms/div VOUT (500 mV/div - 4.5 V Offset) FLASH_SYNC ILED (2 V/div) (1 A/div) t - Time = 10 ms/div Figure 26. Figure 27. JUNCTION TEMPERATURE MONITORING START-UP IN TORCH OPERATION SCL (2 V/div) VF(LED) = 3.3 V at 900 mA, ILED = 0 mA (Torch) to 900 mA (Flash) ACK ILED (50 mA/div) TJ = 65°C GPIO Voltage (20 mV/div - -0.41 V Offset) TJ = 25°C IL (50 mA/div) VI = 3.6 V, ILIM = 2000 mA, Torch = 75 mA VI = 4.2 V, ILIM = 2000 mA, IGPIO = -100 mA, TA = 25°C t - Time = 200 ms/div t - Time = 100 ms/div Figure 28. Figure 29. Submit Documentation Feedback 15 TPS61050 TPS61052 www.ti.com SLUS525 – MARCH 2007 START-UP IN TORCH OPERATION SCL (2 V/div) VOUT (2 V/div) ACK ILED (50 mA/div) IL (50 mA/div) VI = 3.60V, ILIM = 2000 mA, TC[2:0] = 000 t - Time = 100 ms/div Figure 30. 16 Submit Documentation Feedback TPS61050 TPS61052 www.ti.com SLUS525 – MARCH 2007 DETAILED DESCRIPTION OPERATION The TPS6105x family employs a 2-MHz constant-frequency, current-mode PWM converter to generate the output voltage required to drive high-power LEDs. The device integrates a power stage based on an NMOS switch and a synchronous NMOS rectifier. The device also implements a linear low-side current regulator to control the LED current when the battery voltage is higher than the diode forward voltage. In boost mode, the duty cycle of the converter is set by the error amplifier and the saw-tooth ramp applied to the comparator. Because the control architecture is based on a current-mode control, a compensation ramp is added to allow stable operation at duty cycles larger than 50%. The converter is a fully-integrated synchronous-boost converter, always operating in continuous-conduction mode. This allows low-noise operation, and avoids ringing on the switch pin, which would be seen on a converter when entering discontinuous-conduction mode. The TPS6105x device not only operates as a regulated current source but also as a standard voltage-boost regulator. In the TPS61052 device, the voltage-mode operation can be activated either by a software command or by means of a hardware signal (ENVM). This additional operating mode can be useful to properly synchronize the converter when supplying other high-power devices in the system, such as a hands-free audio power amplifier, or any other component requiring a supply voltage higher than the battery voltage. The TPS6105x integrates an I2C-compatible interface, allowing transfers up to 400 kbps. This communication interface can be used to • set the operating mode (shutdown, constant output current mode vs. constant output voltage mode), • control the brightness of the external LED (torch and flash modes), • adjust the output voltage (4.5/5/5.25 V) or to program the safety timer. For more details, refer to the I2C Register Description section. The torch and flash functions can be controlled by the I2C interface. To simplify flash synchronization with the camera module, the device offers a FLASH_SYNC strobe input pin to switch (with zero latency) the LED current from flash to torch light. The maximum duration of the flash pulse can be limited by means of an internal user-programmable safety timer (STIM). EFFICIENCY The sense voltage has a direct effect on the converter’s efficiency. Because the voltage across the low-side current regulator does not contribute to the output power (LED brightness), the lower the sense voltage, the higher the efficiency will be. When running in boost mode (VF(LED) > VIN), the voltage present at the LED pin of the low-side current regulator is typically 250 mV, which contributes to high power-conversion efficiency. When running in the linear down-ocnverter mode (VF(LED) < VIN), the low-side current regulator drops the voltage difference between the input voltage and the LED forward voltage. Depending on the input voltage and the LED forward voltage characteristic, the converter displays efficiency of approximately 80% to 90%. SOFT-START Since the output capacitor always remains biased to the input voltage, the TPS6105x can immediately start switching once it has been enabled via the I2C-compatible interface (refer to MODE_CTRL[1:0] bits). The device starts-up by smoothly ramping up it’s internal reference voltage, thus limiting the inrush current. Submit Documentation Feedback 17 TPS61050 TPS61052 www.ti.com SLUS525 – MARCH 2007 DETAILED DESCRIPTION (continued) SHUTDOWN The MODE_CTRL[1:0] bits are low, the device is forced into shutdown. Depending on the setting of OV[1:0] the device can enter different shutdown modes. In shutdown mode, the regulator stops switching and the LED pin is high impedance thus eliminating any DC conduction path. If OV[1:0] ≠ 11, the internal switch and rectifier MOSFET are turned off. VOUT is one body-diode drop below the input voltage and the device consumes only a shutdown current of 0.3 µA (typ). The output capacitor remains biased to the input voltage. If OV[1:0] = 11, the internal switch MOSFET is turned off and the rectifier MOSFET is turned on. In this shutdown mode there is almost no dropout voltage between the converter’s input and output. The shutdown current is 150 µA (typ). LED FAILURE MODES If the LED fails as a short circuit, the low-side current regulator limits the maximum output current and the LED FAILURE (LF) flag will be set. If the LED fails as an open circuit, the control loop initially attempts to regulate off of its low-side current regulator feedback signal. This drives VOUT higher. Because the open-circuited LED will never accept its programmed current, VOUT must be voltage-limited by means of a secondary control loop. In this failure mode, the TPS6105x limits VOUT to 6.0 V (typ.) and sets the LED FAILURE (LF) flag. UNDERVOLTAGE LOCKOUT The undervoltage lockout circuit prevents the device from misoperation at low input voltages. It prevents the converter from turning on the switch or rectifier MOSFET under undefined conditions. THERMAL SHUTDOWN As soon as the junction temperature, TJ, exceeds 160°C typical, the device goes into thermal shutdown. In this mode, the boost power stage and the low-side current regulator are turned off, the MODE_CTRL[1:0] bits are reset, the OVERTEMP bit is set and can only be reset by a readout. 18 Submit Documentation Feedback TPS61050 TPS61052 www.ti.com SLUS525 – MARCH 2007 DETAILED DESCRIPTION (continued) OPERATING MODES: TORCH AND FLASH The device operation is more easily understood by referring to the timer block diagram. Depending on the settings of MODE_CTRL[1:0] bits the device can enter 4 different operating modes: • MODE_CTRL[1:0] = 00: The device is in shutdown mode. • MODE_CTRL[1:0] = 01: The device is regulating the LED current to the torch current level (TC bits) regardless of the FLASH_SYNC input and START_FLASH/TIMER (SFT) bit. The safety timer is disabled in this operating mode. • MODE_CTRL[1:0] = 11: The device is regulating a constant output voltage according to OV[1:0] bits settings. The low-side LED current regulator is disabled and the LED is disconnected from the output. In this operating mode, the safety timer is disabled and the general purpose timer (DCTIM) can be used to generate a software timeout (TO) flag. DCTIM start is triggered on the rising edge of START_FLASH/TIMER (SFT). • MODE_CTRL[1:0] = 10: The flash pulse can be either trigger by a hardware signal (FLASH_SYNC) or by a software bit (SFT). Flash strobe is level sensitive (STT = 0): LED strobe pulse follows FLASH_SYNC • FLASH_SYNC and (SFT) = 0: LED operation is set to the torch current level and the safety timer is disabled. • FLASH_SYNC or (SFT) = 1: The LED is driven at the flash current level and the safety timer is running. The maximum duration of the flash pulse is defined in the STIM register. IFLASH LED Current FLASH_SYNC I2 C Bus DC/DC Turn-Off Command TC[2:0] = 000 MODE_CTRL[1:0] = 10 MODE_CTRL[1:0] = 00 Figure 32. Synchronized Flash Strobe FLASH_SYNC or (SFT) STIM TIMER IFLASH LED CONTROL Free DC/DC Turn-On Command Figure 31. Torch Mode Operation FLASH_SYNC or (SFT) Free TIME-OUT RESET (SF) TORCH Figure 33. Level Sensitive Safety Timer (Timeout) STIM TIMER FLASH LED CONTROL TIME-OUT RESET (SF) TORCH Figure 34. Level Sensitive Safety Timer (Normal Operation + Timeout) The safety timer is started by: • a rising edge of FLASH_SYNC signal. • a rising edge of START_FLASH/TIMER (SFT) bit. The safety timer is stopped by: • a low level of FLASH_SYNC signal or START_FLASH/TIMER (SFT) bit. • a timeout signal (TO). The START-FLASH/TIMER (SFT) bit is reset by the timeout (TO) signal. Submit Documentation Feedback 19 TPS61050 TPS61052 www.ti.com SLUS525 – MARCH 2007 DETAILED DESCRIPTION (continued) The Flash strobe is edge sensitive (STT = 1): The LED strobe pulse is triggered by a rising edge When FLASH_SYNC and START_FLASH/TIMER (SFT) are both low, the LED operation is set to the torch current level without timeout. The duration of the flash pulse is defined in the STIM register. The flash strobe is started by: • a rising edge of FLASH_SYNC signal. • a rising edge of START_FLASH/TIMER (SFT) bit. Once running, the timer ignores any triggering signal, and only stops after a timeout (TO). The START-FLASH/TIMER (SFT) bit is reset by the timeout (TO) signal. FLASH_SYNC or (SFT) FLASH_SYNC or (SFT) STIM TIMER IFLASH LED CONTROL STIM TIMER IFLASH RESET (SF) ITORCH LED CONTROL Figure 35. Edge Sensitive Timer (Single Trigger Event) RESET (SFT) ITORCH Figure 36. Edge Sensitive Timer (Single Trigger Event) FLASH_SYNC or (SFT) STIM TIMER IFLASH LED CONTROL RESET (SFT) ITORCH Figure 37. Edge Sensitive Timer (Multiple Trigger Events) MODE OF OPERATION: FLASH BLANKING (TPS61050) The TPS61050 device also integrates a general purpose I/O pin (GPIO) that can be configured either as a standard logic input/output or as a flash masking input (Tx-MASK). This blanking function turns the LED from flash to torch light, thereby reducing almost instantaneously the peak current loading from the battery. The Tx-MASK function has no influence on the safety timer duration. IFLASH LED Current ITORCH FLASH_SYNC GPIO (Tx-MASK) I 2C Bus Free LED Turn-On Command Free Free LED Turn-Off Command Figure 38. Synchronized Flash With Blanking Periods 20 Submit Documentation Feedback TPS61050 TPS61052 www.ti.com SLUS525 – MARCH 2007 DETAILED DESCRIPTION (continued) HARDWARE VOLTAGE MODE SELECTION (TPS61052) The TPS61052 device integrates a logic input (ENVM) that can be used to force the converter to run in voltage mode regulation. This additional operating mode can be useful to supply other high power consumption devices in the system (e.g. hands-free audio power amplifier...) or any other component requiring a supply voltage higher than the battery voltage. Table 2 gives an overview of the different mode of operation of TPS61052. Table 2. TPS61052 Operating Modes INTERNAL REGISTER SETTINGS MODE_CTRL[1:0] ENVM OPERATING MODES 00 0 Power stage is in shutdown. The output is either connected directly to the battery (OV[1:0]=11, rectifier is bypassed) or via the rectifer’s body diode (OV[1:0]=01). In both case the power stage LC filter is connected in series between the battery and the output. 01 0 LED is turned-on for DC light operation. The converter is operating in the current regulation mode (CM). The output voltage is controlled by the forward voltage characteristic of the LED. 10 0 LED is turned-on for flash operation. The converter is operating in the current regulation mode (CM). The output voltage is controlled by the forward voltage characteristic of the LED. 11 0 LED is turned-off and the converter is operating in the voltage regulation mode (VM). The output voltage is set via the register OV[1:0]. 00 1 LED is turned-off and the converter is operating in the voltage regulation mode (VM). The output voltage is set via the register OV[1:0]. 01 1 The converter is operating in the voltage regulation mode (VM) and it’s output voltage is set via the register OV[1:0]. The LED is turned-on for torch operation according to the register TC[2:0]. The LED current is regulated by the means of the low-side current sink. 10 1 The converter is operating in the voltage regulation mode (VM) and it’s output voltage is set via the register OV[1:0]. The LED is turned-on for flash operation according to the register FC[2:0]. The LED current is regulated by the means of the low-side current sink. 11 1 LED is turned-off and the converter is operating in the voltage regulation mode (VM). The output voltage is set via the register OV[1:0]. LOW LIGHT DIMMING MODE The TPS6105x device features white LED drive capability at very low light intensity. To generate a reduced LED average current, the device employs a 122 Hz fixed frequency PWM modulation scheme. Operation is understood best by referring to the timer block diagram. The torch current is modulated with a duty cycle defined by the DCTIM[2:0] bits. The low light dimming mode can only be activated in the torch only mode, MODE_CTRL[1:0] = 01. I TORCH 0 PWM Dimming Steps (DCTIM) 0.8%, 1.6%, 2.3%, 3.1%, 3.9%, 4.7%, 6.3%, 8.6% Torch Current Steps (TC) 50mA, 75mA, 100mA, 150mA, 200mA, 250mA I LED(DC) = I TORCH x DCTIM Figure 39. PWM Dimming Principle Submit Documentation Feedback 21 TPS61050 TPS61052 www.ti.com SLUS525 – MARCH 2007 White LED blinking can be achieved by turning on/off periodically the LED dimmer via the (DIM) bit, see Figure 40. LED OFF LED ON with Reduced Current ITORCH ITORCH PWM Dimming Steps = 0.8%, 1.6%, 2.3%, 3.1%, 3.9%, 4.7%, 6.3%, 8.6% I 2 C Bus FREE FREE TC[2:0] = ITORCH DIM = 1 FREE FREE FREE TC[2:0] = 000 DIM = 0 TC[2:0] = ITORCH DIM = 1 FREE TC[2:0] = 000 DIM = 0 Figure 40. White LED Blinking Control 3-BIT ADC The TPS6105x device integrates a 3 bit A/D converter to measure the differential voltage across the output and the low-side current regulator. In order to get a proper settling of the LED forward voltage, the data acquisition is done approximately 10 ms after the start of the flash sequence. When running in the linear down-mode (VF(LED) < VIN), the low-side current regulator drops the voltage difference between the input voltage and the LED forward voltage. This may result in thermal limitations (especially for CSP-12 packaging) when running high LED current under high battery conditions (VIN ≥ 4.5 V) with low forward voltage LEDs and/or high ambient temperature. The LED forward voltage measurement can be started either by a START FLASH event (FLASH_SYNC or SFT bit) or by setting ADC[2:0] bits (whilst MODE_CTRL[1:0]=01 or 10). L VOUT VBAT CIN P C OUT P P P ADC Digital Output Coding, ADC [2:0] VOUT-LED <1.5 V 3-Bit ADC 000: (VOUT-LED) <3.20 V 001: 3.20 V ≤ (VOUT-LED) <3.35 V 010: 3.35 V ≤ (VOUT-LED) <3.50 V 011: 3.50 V ≤ (VOUT-LED) <3.65 V 100: 3.65 V ≤ (VOUT-LED) <3.80 V 101: 3.80 V ≤ (VOUT-LED) <3.95 V 110: 3.95 V ≤ (VOUT-LED) <4.10 V 111: (VOUT-LED) ≥ 4.10 V LED FAILURE S/H ADC[2:0] START FLASH ADC + - 10 ms Delay WRITE REGISTER 2[5:3] = 111 Low-Side Current Regulator IREF LED Figure 41. LED VF Measurement Principle 22 Submit Documentation Feedback TPS61050 TPS61052 www.ti.com SLUS525 – MARCH 2007 SERIAL INTERFACE DESCRIPTION I2C is a 2-wire serial interface developed by Philips Semiconductor (see I2C-Bus Specification, Version 2.1, January 2000). The bus consists of a data line (SDA) and a clock line (SCL) with pull-up structures. When the bus is idle, both SDA and SCL lines are pulled high. All the I2C compatible devices connect to the I2C bus through open drain I/O pins, SDA and SCL. A master device, usually a microcontroller or a digital signal processor, controls the bus. The master is responsible for generating the SCL signal and device addresses. The master also generates specific conditions that indicate the START and STOP of data transfer. A slave device receives and/or transmits data on the bus under control of the master device. The TPS6105x device works as a slave and supports the following data transfer modes, as defined in the I2C-Bus Specification: standard mode (100 kbps) and fast mode (400 kbps). The interface adds flexibility to the power supply solution, enabling most functions to be programmed to new values depending on the instantaneous application requirements. Register contents remain intact as long as the supply voltage remains above approximately 2 V. The data transfer protocol for standard and fast modes is exactly the same, therefore they are referred to as F/S-mode in this document. The TPS6105x device supports 7-bit addressing; 10-bit addressing and general call address are not supported. The device 7-bit address is defined as 011 0011. F/S-MODE PROTOCOL The master initiates data transfer by generating a start condition. The start condition is when a high-to-low transition occurs on the SDA line while SCL is high, as shown in Figure 42 All I2C-compatible devices should recognize a start condition. DATA CLK S P STOP Condition START Condition Figure 42. START and STOP Conditions The master then generates the SCL pulses, and transmits the 7-bit address and the read/write direction bit R/W on the SDA line. During all transmissions, the master ensures that data is valid. A valid data condition requires the SDA line to be stable during the entire high period of the clock pulse (see Figure 43). All devices recognize the address sent by the master and compare it to their internal fixed addresses. Only the slave device with a matching address generates an acknowledge (see Figure 44) by pulling the SDA line low during the entire high period of the ninth SCL cycle. Upon detecting this acknowledge, the master knows that communication link with a slave has been established. DATA CLK Data Line Stable; Data Valid Change of Data Allowed Figure 43. Bit Transfer on the Serial Interface Submit Documentation Feedback 23 TPS61050 TPS61052 www.ti.com SLUS525 – MARCH 2007 The master generates further SCL cycles to either transmit data to the slave (R/W bit 1) or receive data from the slave (R/W bit 0). In either case, the receiver needs to acknowledge the data sent by the transmitter. So an acknowledge signal can either be generated by the master or by the slave, depending on which one is the receiver. 9-bit valid data sequences consisting of 8-bit data and 1-bit acknowledge can continue as long as necessary. To signal the end of the data transfer, the master generates a stop condition by pulling the SDA line from low to high while the SCL line is high (see Figure 42). This releases the bus and stops the communication link with the addressed slave. All I2C compatible devices must recognize the stop condition. Upon the receipt of a stop condition, all devices know that the bus is released, and they wait for a start condition followed by a matching address. Attempting to read data from register addresses not listed in this section will result in 00h being read out. Figure 44. Acknowledge on the I2C Bus Figure 45. Bus Protocol 24 Submit Documentation Feedback TPS61050 TPS61052 www.ti.com SLUS525 – MARCH 2007 TPS6105X I2C UPDATE SEQUENCE The TPS6105x requires a start condition, a valid I2C address, a register address byte, and a data byte for a single update. After the receipt of each byte, TPS6105x device acknowledges by pulling the SDA line low during the high period of a single clock pulse. A valid I2C address selects the TPS6105x. TPS6105x performs an update on the rising edge of the SCL clock that follows the ACK bit transmission. 1 7 1 1 8 1 S Slave Address R/W ACK Register Address ACK 8 Data 1 1 ACK P “0” Write ACK = Acknowledge S = START condition P = STOP condition From Master to TPS6105x From TPS6105x to Master Figure 46. Write Data Transfer Format in F/S-Mode 1 7 1 1 8 1 1 7 1 1 S Slave Address R/W ACK Register Address ACK Sr Slave Address R/W ACK “0” Write 8 Data 1 1 ACK P “1” Read ACK = Acknowledge S = START condition Sr = REPEATED START condition P = STOP condition From Master to TPS6105x From TPS6105x to Master Figure 47. Read Data Transfer Format in F/S-Mode SLAVE ADDRESS BYTE MSB X LSB 0 1 1 0 0 1 1 The slave address byte is the first byte received following the START condition from the master device. REGISTER ADDRESS BYTE MSB 0 LSB 0 0 0 0 0 D1 D0 Following the successful acknowledgement of the slave address, the bus master will send a byte to the TPS6105x, which will contain the address of the register to be accessed. The TPS6105x contains four 8-bit registers accessible via a bidirectional I2C-bus interface. All internal registers have read and write access. Submit Documentation Feedback 25 TPS61050 TPS61052 www.ti.com SLUS525 – MARCH 2007 REGISTER DESCRIPTION REGISTER0 (READ/WRITE) (TPS6105X) MSB 7 LSB 6 5 4 3 2 1 0 Memory location: 00 Reset state: 0001 0010 TORCH CURRENT, TC[2:0] 000: 0 mA (dc/dc switching, LED Off, VOUT set according to OV[1:0] 001: 50 mA 010: 75 mA (default) 011: 100 mA 100: 150 mA 101: 200 mA 110: 250 mA / 400 mA 111: 250 mA / 500 mA (1) (1) LED DIMMING, DIM This bit is only valid for MODE_CTRL[1:0] = 01 0: LED current is unchanged (default) 1: LED current is PWM dimmed (see DCTIM bits) OUTPUT VOLTAGE, OV[1:0] This bit is only valid for MODE_CTRL[1:0] = 11 00: 4.5 V constant output voltage 01: 5.0 V constant output voltage (2) (2) 10: 5.25 V constant output voltage 11: 5.0 V constant output voltage (default) (2) (3) MODE CONTROL,MODE_CTRL[1:0] 00: Device in shutdown mode (default) 01: Device operates in torch only mode 10: Device operates in torch and flash modes 11: Device operates as constant voltage source Writing to REGISTERS[7:6] automatically updates REGISTER[7:6]. 26 (1) 400 mA/500 mA current level can only be activated when DIR = 0, Tx-MASK = 1 and GPIO input is set high. This operating mode only applies to TPS61050. (2) MODE_CTRL[1:0] = 00, VOUT is one body diode below the input voltage, IQ = 0.3µA (typ). (3) MODE_CTRL[1:0] = 00, rectifier MOSFET is turned on shorting VOUT and SW, IQ = 150µA (typ). Submit Documentation Feedback TPS61050 TPS61052 www.ti.com SLUS525 – MARCH 2007 REGISTER1 (READ/WRITE) (TPS6105X) MSB 7 LSB 6 5 4 3 2 1 0 Memory location: 01 Reset state: 0000 0100 FLASH CURRENT, FC[2:0] 000: 150 mA 001: 200 mA 010: 300 mA 011: 400 mA 100: 500 mA (default) 101: 700 mA 110: 900 mA 111: 1200 mA START FLASH/TIMER,SFT This bit is reset by the time-out of the safety timer 0: No change in LED current (default) 1: LED current ramps to the flash current level SAFETY TIMER TRIGGER, STT This bit is only valid for MODE_CTRL[1:0] = 10 0: LED safety timer is level sensitive (default) 1: LED safety timer is rising edge sensitive TIME-OUT FLAG, TO (READ ONLY) Time-out flag is reset at re-start of the safety timer. 0: No time-out event (default) 1: Time-out occurred MODE CONTROL, MODE_CTRL[1:0] 00: Device in shutdown mode (default) 01: Device operates in torch only mode 10: Device operates in torch and flash modes 11: Device operates as constant voltage source Writing to REGISTER1[7:6] automatically updates REGISTER0[7:6] Submit Documentation Feedback 27 TPS61050 TPS61052 www.ti.com SLUS525 – MARCH 2007 REGISTER2 (READ/WRITE) (TPS61050) MSB 7 LSB 6 5 4 3 2 1 0 Memory location: 02 Reset state: 000X X000 GPIO DIRECTION, DIR 0: GPIO configured as input (default) 1: GPIO configured as open-drain output GPIO PORT BIT, GPIO This bit contains the GPIO port value FLASH BLANKING, Tx-MASK This bit is only valid for DIR = 0 In write mode, this bit enables/disables the flash blanking function. 0: Flash blanking is disabled (default) 1: LED current is reduced to torch current level when GPIO = 1 In read mode, this flag indicates whether or not the flashlight masking input has been activated. Tx-MASK flag is reset after readout of the flag. 0: No flash blanking event occured 1: Flash blanking triggered (1) ADC OUTPUT , ADC[2:0] (READ ONLY) Refer to 3-Bit ADC section for more details. CURRENT LIMIT (2) (3) , ILIM[1:0] (WRITE ONLY) ILIM[1:0] can only be written once whilst the device is in shutdown. 00: 1000 mA (typ) (default) 01: 1500 mA (typ) 10: 1500 mA (typ) 11: 2000 mA (typ) LED FAILURE (3) , LF (READ ONLY) LED failure flag is reset after readout of the flag. 0: Proper LED operation 1: LED failed (open or shorted) OVERTEMP (READ ONLY) Time-out flag is reset after readout of the flag. 0: Normal operation (default) 1: Thermal shutdown tripped 28 (1) Setting bits 3, 4 and 5 (whilst MODE_CTRL[1:0]=01 or 10) starts an LED forward voltage measurement. (2) A write operation on bit 5 and 6 points to the ILIM[1:0] bits. (3) A read operation on bit 5 and 6 points to the LF and ADC[2] bits. Submit Documentation Feedback TPS61050 TPS61052 www.ti.com SLUS525 – MARCH 2007 REGISTER2 (READ/WRITE) (TPS61052) MSB LSB 7 6 5 4 3 2 1 Memory location: 02 Reset state: 011X X000 0 RESERVED, DO NOT CARE (1) ADC OUTPUT , ADC[2:0] (READ ONLY) Refer to 3-Bit ADC section for more details. (2) (3) CURRENT LIMIT , ILIM[1:0] (WRITE ONLY) ILIM[1:0] can only be writen once whilst the device is in shutdown. 00: 1000 mA (typ) 01: 1500 mA (typ) 10: 1500 mA (typ) 11: 2000 mA (typ) (default) (3) LED FAILURE , LF (READ ONLY) LED failure flag is reset after readout of the flag. 0: Proper LED operation 1: LED failed (open or shorted) OVERTEMP (READ ONLY) Time-out flag is reset after readout of the flag. 0: Normal operation (default) 1: Thermal shutdown tripped (1) Setting bits 3, 4 and 5 (whilst MODE_CTRL[1:0]=01 or 10) starts an LED forward voltage measurement. (2) A write operation on bit 5 and 6 points to the ILIM[1:0] bits. (3) A read operation on bit 5 and 6 points to the LF and ADC[2] bits. REGISTER3 (READ/WRITE) (TPS6105X) MSB 7 LSB 6 5 4 3 2 1 0 Memory location: 03 Reset state: 1101 0001 SAFETY TIMER, STIM[4:0] 5-bit unsigned binary coding. STIM can only be Written once before the device has entered the flashlight mode. Timer = STIM x32.8 ms, default is 557.6 ms GENERAL PURPOSE TIMER, DCTIM[2:0] If MODE_CTRL = 01 and DIM = 1, DCTIM sets the average LED current 000: 0.8% x ITORCH 001: 1.6% x ITORCH 010: 2.3% x ITORCH 011: 3.1% x ITORCH 100: 3.9% x ITORCH 101: 4.7% x ITORCH 110: 6.3% x ITORCH (default) 111: 8.6% x ITORCH If MODE_CTRL = 11, DCTIM sets the duration of the timer till TO bit is set 3-bit unsigned binary coding Timer = DCTIM x 1.02 s Submit Documentation Feedback 29 TPS61050 TPS61052 www.ti.com SLUS525 – MARCH 2007 APPLICATION INFORMATION INDUCTOR SELECTON A boost converter requires two main passive components for storing energy during the conversion. A boost inductor and a storage capacitor at the output are required. The TPS6105x device integrates a current limit protection circuitry. The peak current of the NMOS switch is sensed to limit the maximum current flowing through the switch and the inductor. The typical peak current limit (1000 mA / 1500 mA / 2000 mA) is user selectable via the I2C interface. In order to optimize solution size the TPS6105x device has been designed to operate with inductance values between a minimum of 1.3 µH and maximum of 2.9 µH. In typical high-current white LED applications a 2.2 µH inductance is recommended. To select the boost inductor, it is recommended to keep the possible peak inductor current below the current limit threshold of the power switch in the chosen configuration. The highest peak current through the inductor and the power switch depends on the output load, the input and output voltages. Estimation of the maximum average inductor current and the maximum inductor peak current can be done using Equation 1 and Equation 2: V OUT I L [ I OUT + h VIN (1) I L(PEAK) + I OUT VIN D ) 2 f L (1 * D) h with D + V OUT * V IN VOUT (2) with: f = switching frequency (2 MHz) L = inductance value (2.2 µH) η = estimated efficiency (85%) For example, for an output current of 500 mA at 5 V, the TPS6105x device needs to be set for a 1000 mA current limit operation together with an inductor supporting this peak current. The losses in the inductor caused by magnetic hysteresis losses and copper losses are a major parameter for total circuit efficiency. Table 3. List of Inductors 30 MANUFACTURER SERIES DIMENSIONS TDK VLF3010AT 2,6 mm × 2,8 mm × 1,0 mm max. height TAIYO YUDEN NR3010 3,0 mm × 3,0 mm × 1,0 mm max. height TDK VLF3014AT 2,6 mm × 2,8 mm × 1,4 mm max. height COILCRAFT LPS3015 3,0 mm × 3,0 mm × 1,5 mm max. height MURATA LQH3NP 3,0 mm × 3,0 mm × 1,5 mm max. height TOKO FDSE0312 3,0 mm × 3,0 mm × 1,2 mm max. height Submit Documentation Feedback ILIM SETTINGS 1000 mA (typ.) 1500 mA (typ.) 2000 mA (typ.) TPS61050 TPS61052 www.ti.com SLUS525 – MARCH 2007 CAPACITOR SELECTION Input Capacitor For good input voltage filtering low ESR ceramic capacitors are recommended. A 10-µF input capacitor is recommended to improve transient behavior of the regulator and EMI behavior of the total power supply circuit. The input capacitor should be placed as close as possible to the input pin of the converter. Output Capacitor The primary parameter necessary to define the output capacitor is the maximum allowed output voltage ripple of the converter. This ripple is determined by two parameters of the capacitor, the capacitance and the ESR. It is possible to calculate the minimum capacitance needed for the defined ripple, supposing that the ESR is zero, by using Equation 3: C min [ I OUT f ǒVOUT * VINǓ DV V OUT (3) Parameter f is the switching frequency and ∆V is the maximum allowed ripple. With a chosen ripple voltage of 10mV, a minimum capacitance of 10 µF is needed. The total ripple is larger due to the ESR of the output capacitor. This additional component of the ripple can be calculated using Equation 4: ∆VESR = IOUT × RESR The total ripple is the sum of the ripple caused by the capacitance and the ripple caused by the ESR of the capacitor. Additional ripple is caused by load transients. This means that the output capacitor has to completely supply the load during the charging phase of the inductor. A reasonable value of the output capacitance depends on the speed of the load transients and the load current during the load change. For the high current white LED application, a minimum of 3 µF effective output capacitance is usually required when operating with 2.2 µH (typ) inductors. For solution size reasons, this is usually one or more X5R/X7R ceramic capacitors. For stable operation of the internally compensated control loop, a maximum of 50 µF effective output capacitance is tolerable. Depending on the material, size and margin to the rated voltage of the used output capacitor, degradation on the effective capacitance can be observed. This loss of capacitance is related to the DC bias voltage applied. It is therefore always recommended to check that the selected capacitors are showing enough effective capacitance under real operating conditions. CHECKING LOOP STABILITY The first step of circuit and stability evaluation is to look from a steady-state perspective at the following signals: • Switching node, SW • Inductor current, IL • Output ripple voltage, VOUT(AC) These are the basic signals that need to be measured when evaluating a switching converter. When the switching waveform shows large duty cycle jitter or the output voltage or inductor current shows oscillations the regulation loop may be unstable. This is often a result of board layout and/or L-C combination. The next step in regulation loop evaluation is to perform a load transient test. Output voltage settling time after the load transient event is a good estimate of the control loop bandwidth. The amount of overshoot and subsequent oscillations (ringing) indicates the stability of the control loop. Without any ringing, the loop has usually more than 45° of phase margin. Because the damping factor of the circuitry is directly related to several resistive parameters (e.g., MOSFET rDS(on)) that are temperature dependant, the loop stability analysis has to be done over the input voltage range, output current range, and temperature range. Submit Documentation Feedback 31 TPS61050 TPS61052 www.ti.com SLUS525 – MARCH 2007 LAYOUT CONSIDERATIONS As for all switching power supplies, the layout is an important step in the design, especially at high peak currents and high switching frequencies. If the layout is not carefully done, the regulator could show stability problems as well as EMI problems. Therefore, use wide and short traces for the main current path and for the power ground tracks. The input capacitor, output capacitor, and the inductor should be placed as close as possible to the IC. Use a common ground node for power ground and a different one for control ground to minimize the effects of ground noise. Connect these ground nodes at any place close to one of the ground pins of the IC. To lay out the control ground, it is recommended to use short traces as well, separated from the power ground traces. This avoids ground shift problems, which can occur due to superimposition of power ground current and control ground current. THERMAL INFORMATION Implementation of integrated circuits in low-profile and fine-pitch surface-mount packages typically requires special attention to power dissipation. Many system-dependant issues such as thermal coupling, airflow, added heat sinks and convection surfaces, and the presence of other heat-generating components affect the power-dissipation limits of a given component. Three basic approaches for enhancing thermal performance are listed below: • Improving the power dissipation capability of the PCB design • Improving the thermal coupling of the component to the PCB • Introducing airflow in the system Junction-to-ambient thermal resistance is highly application and board-layout dependent. In applications where high maximum power dissipation exists, special care must be paid to thermal dissipation issues in board design. The maximum junction temperature (TJ) of the TPS6105x is 150°C. The maximum power dissipation gets especially critical when the device operates in the linear down mode at high LED current. For single pulse power thermal analysis (e.g., flash strobe), the allowable power dissipation for the device is given by Figure 48. 4 No Airflow Single Pulse Power Disipation - W 3.5 3 2.5 2 1.5 tPCB = 85°C 1 0.5 0 0 Theta JB: 35°CW 100 200 300 400 500 600 700 800 900 1000 Pulse Width - ms Figure 48. Single Pulse Power Capability (CSP Package) 32 Submit Documentation Feedback TPS61050 TPS61052 www.ti.com SLUS525 – MARCH 2007 TYPICAL APPLICATIONS TPS61050 L SW SW VBAT 2.2 mH VOUT COUT 10 mF P AVIN Li-Ion CIN WHITE LED FLASH-LIGHT LED +2.8 V SCL SDA I2 C I/F CAMERA ENGINE R FLASH_SYNC GPIO PGND PGND AGND RED LED INDICATOR P Figure 49. High Power White LED Solution Featuring Privacy Indicator TPS61050 L SW SW VBAT 2.2 mH VOUT COUT 10 mF P AVIN Li-Ion CIN P WHITE LED FLASH-LIGHT P LED SCL SDA I2 C I/F CAMERA ENGINE FLASH_SYNC AGND GPIO PGND PGND P RF PA TX ACTIVE Figure 50. High Power White LED Solution Featuring No-Latency Turn-Down via PA TX Signal TPS61052 L VBAT 2.2 mH SW SW C OUT 10 mF P AVIN Li-Ior CIN P 5 V DC Power Rail for AF/ Zoom Motor Drive VOUT P LED I2C I/F Flash Synchronization Camera Engine SCL SDA FLASH_SYNC AGND ENVM PGND PGND P AF/Zoom Motor Drive Enable Camera Engine Engine Figure 51. High Power White LED Flash Driver and AF/Zoom Motor Drive Supply Submit Documentation Feedback 33 TPS61050 TPS61052 www.ti.com SLUS525 – MARCH 2007 TYPICAL APPLICATIONS (continued) TPS61052 L VBAT 2.2 mH SW SW VOUT COUT 10 mF AVIN Li-Ion C IN P CLASS-D APA Audio Input P Audio Input P EN_APA LED SCL SDA I2C I/F Flash Synchronization Camera Engine FLASH_SYNC ENVM PGND PGND AGND P 1G97 APA Enable Base-Band Engine Figure 52. White LED Flash Driver and Audio Amplifier Power Supply Exclusive Operation TPS61052 L VBAT 2.2 mH SW SW VOUT Li-Ion C IN P CLASS-D APA COUT 10 mF P AVIN Audio Input Audio Input P GAIN_SEL 0: Normal Gain 1: -6 dB LED EN _APA SCL SDA I2C I/F Flash Synchronization Camera Engine FLASH_SYNC ENVM P PGND PGND AGND APA Enable Base-Band Engine Figure 53. White LED Flash Driver and Audio Amplifier Power Supply Operating Simultaneously TPS61052 L VBAT 2.2 mH SW SW VOUT COUT 10 mF P AVIN Li-Ion C IN P Dx P LED I2 C I/F Flash Synchronization Camera Engine +1.8V TCA6507 VCC SCL SDA FLASH_SYNC AGND ENVM PGND PGND P I2C I/F SCL SDA EN P0 P1 Voltage Mode Enable Base-Band Engine GND P2 Figure 54. White LED Flash Driver and Auxiliary Lighting Zone Power Supply 34 Submit Documentation Feedback Dy Dz TPS61050 TPS61052 www.ti.com SLUS525 – MARCH 2007 TYPICAL APPLICATIONS (continued) TPS61050 L VBAT 2.2 mH SW SW VOUT COUT 10 mF AVIN Li-Ion C IN LED 1 P 1 .5 R P LED 2 1 .5 R P LED I 2C I /F SCL LED 1, LED 2 VF variation should be with 100 mV from each other SDA GPIO FLASH _SYNC PGND AGND P PGND Figure 55. 2 × 300 mA Dual LED Camera Flash Submit Documentation Feedback 35 TPS61050 TPS61052 www.ti.com SLUS525 – MARCH 2007 PACKAGE SUMMARY CHIP SCALE PACKAGE (BOTTOM VIEW) A3 A2 A1 B3 B2 B1 C3 C2 C1 D3 D2 D1 CHIP SCALE PACKAGE (TOP VIEW) YMLLLLS 6105x D A1 E Code: • Y — 2 digit date code • LLLL - lot trace code • S - assembly site code PACKAGE DIMENSIONS The dimensions for the YZG package are shown in Table 4. See the package drawing at the end of this data sheet. Table 4. YZG Package Dimensions 36 Packaged Devices D E TPS6105xYZG 1.96 ±0.05 mm 1.46 ±0.05 mm Submit Documentation Feedback PACKAGE OPTION ADDENDUM www.ti.com 7-May-2007 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Eco Plan (2) Qty TPS61050DRCR ACTIVE SON DRC 10 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR TPS61050DRCRG4 ACTIVE SON DRC 10 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR TPS61050DRCT ACTIVE SON DRC 10 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR TPS61050DRCTG4 ACTIVE SON DRC 10 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR TPS61050YZGR ACTIVE DSBGA YZG 12 3000 Green (RoHS & no Sb/Br) SNAGCU Level-1-260C-UNLIM TPS61050YZGT ACTIVE DSBGA YZG 12 250 Green (RoHS & no Sb/Br) SNAGCU Level-1-260C-UNLIM TPS61052YZGR ACTIVE DSBGA YZG 12 3000 Green (RoHS & no Sb/Br) SNAGCU Level-1-260C-UNLIM TPS61052YZGT ACTIVE DSBGA YZG 12 250 SNAGCU Level-1-260C-UNLIM Green (RoHS & no Sb/Br) Lead/Ball Finish MSL Peak Temp (3) (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 17-May-2007 TAPE AND REEL INFORMATION Pack Materials-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com Device 17-May-2007 Package Pins Site Reel Diameter (mm) Reel Width (mm) A0 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant TPS61050DRCR DRC 10 MLA 330 12 3.3 3.3 1.1 8 12 PKGORN T2TR-MS P TPS61050DRCT DRC 10 MLA 180 12 3.3 3.3 1.1 8 12 PKGORN T2TR-MS P TPS61050YZGR YZG 12 UNITIVE 177 8 1.65 1.65 0.71 4 8 PKGORN T1TR-MS P TPS61050YZGT YZG 12 UNITIVE 177 8 1.65 1.65 0.71 4 8 PKGORN T1TR-MS P TPS61052YZGR YZG 12 UNITIVE 177 8 1.65 1.65 0.71 4 8 PKGORN T1TR-MS P TPS61052YZGT YZG 12 UNITIVE 177 8 1.65 1.65 0.71 4 8 PKGORN T1TR-MS P TAPE AND REEL BOX INFORMATION Device Package Pins Site Length (mm) Width (mm) TPS61050DRCR DRC 10 MLA 346.0 346.0 29.0 TPS61050DRCT DRC 10 MLA 190.0 212.7 31.75 TPS61050YZGR YZG 12 UNITIVE 195.2 193.7 34.9 TPS61050YZGT YZG 12 UNITIVE 195.2 193.7 34.9 TPS61052YZGR YZG 12 UNITIVE 195.2 193.7 34.9 TPS61052YZGT YZG 12 UNITIVE 195.2 193.7 34.9 Pack Materials-Page 2 Height (mm) PACKAGE MATERIALS INFORMATION www.ti.com 17-May-2007 Pack Materials-Page 3 D: 1.96 mm + 30 µm E: 1.46 mm + 30 µm IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. 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