TUSB1105, TUSB1106 ADVANCED UNIVERSAL SERIAL BUS TRANSCEIVERS www.ti.com SCAS818C – MAY 2006 – REVISED DECEMBER 2006 FEATURES • • • • • • Comply With Universal Serial Bus Specification Rev. 2.0 Transmit and Receive Serial Data at Both Full-Speed (12-Mbit/s) and Low-Speed (1.5-Mbit/s) Data Rates Integrated Bypassable 5-V to 3.3-V Voltage Regulator for Powering Via USB VBUS VBUS Disconnection Indication Through VP and VM Used as USB Device Transceiver or USB Host Transceiver Stable RCV Output During SE0 Condition • • • • • Two Single-Ended Receivers With Hysteresis Low-Power Operation, Ideal for Portable Equipment Support I/O Voltage Range From 1.65 V to 3.6 V IEC-61000-4-2 ESD Compliant – ±9-kV Contact-Discharge Model (D+, D–, VCC(5.0)) – ±15-kV Human-Body Model (D+, D–, VCC(5.0)) Available in Small RTZ16, RGT16 (TUSB1105), and TSSOP16 (TUSB1106) Packages APPLICATIONS • • • • Mobile Phones Personal Digital Assistants (PDAs) Information Appliances (IAs) Digital Still Cameras (DSCs) DESCRIPTION/ORDERING INFORMATION The TUSB1105 and TUSB1106 universal serial bus (USB) transceivers are compliant with the Universal Serial Bus Specification Rev. 2.0. These devices can transmit and receive serial data at both full-speed (12-Mbit/s) and low-speed (1.5-Mbit/s) data rates. The TUSB1105 and TUSB1106 can be used as USB device transceivers or USB host transceivers. The devices allow USB application-specific ICs (ASICs) and programmable logic devices (PLDs), with power-supply voltages from 1.65 V to 3.6 V, to interface with the physical layer (PHY) of the universal serial bus. They have an integrated 5-V to 3.3-V voltage regulator for direct powering via the USB supply VBUS. The TUSB1105 allows single-ended and differential input modes selectable by a mode (MODE) input and is available in RGT16 and RTZ16 packages. The TUSB1106 allows only differential input mode and is available in TSSOP16 and RTZ16 packages. The TUSB1105 and TUSB1106 are ideal for portable electronic devices, such as mobile phones, personal digital assistants, information appliances, and digital still cameras. ORDERING INFORMATION PACKAGE (1) TA –40°C to 85°C (1) (2) TOP-SIDE MARKING (2) ORDERABLE PART NUMBER TUSB1105RGTR ZYB TUSB1106RGTR ZYC TUSB1105RTZR ZYB TUSB1106RTZR ZYC Reel of 2000 TUSB1106PWR Preview Reel of 3000 TUSB1106RSVR Preview RGT16 Reel of 3000 RTZ16 Reel of 1000 TSSOP16 – PW RSV16 Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/sc/package. The actual top-side marking has one additional character that designates the assembly/test site. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2006, Texas Instruments Incorporated TUSB1105, TUSB1106 ADVANCED UNIVERSAL SERIAL BUS TRANSCEIVERS www.ti.com SCAS818C – MAY 2006 – REVISED DECEMBER 2006 TUSB1105 PACKAGES VM 4 9 D− VP 3 10 D+ RCV 2 11 VPO/VO OE 1 15 14 13 V pu(3.3) V C C(5.0) V reg(3.3) 7 8 D− 4 10 D+ VP 3 11 VPO /VO R CV 2 12 V MO /F SE0 OE 1 13 V reg(3.3) 5 VM G ND (exposed die pad) VMO/FSE0 16 15 SO FTC O N 16 SO FT CO N 12 6 9 SU SPN D 14 V CC (5.0) GND (expo sed die pad) SPE ED 8 V CC (I/O ) 7 V pu(3.3) V C C (I/O ) 6 MO DE M O DE 5 RTZ16 PACKAGE (BOTTOM VIEW) SPE ED S USPND RGT16 PACKAGE (BOTTOM VIEW) TUSB1106 PACKAGES VP 3 11 VPO RC V 2 12 VM O 13 V reg(3.3) D− VP 3 10 D+ RCV 2 11 VPO 12 VMO No Connect V pu(3 .3) V CC (5.0) TSSOP16 PACKAGE (TOP VIEW) 2 1 16 15 14 13 RSV16 PACKAGE (BOTTOM VIEW) SPEED 14 SPE ED 9 VCC(I/O) 15 8 4 SO FT CO N 16 SO F TC O N 1 7 VM OE OE 6 V reg(3.3) D+ V C C (I/O ) 10 5 V C C(5.0) 4 VM GND 8 D− 5 V pu(3.3) S PEE D 7 9 SU SP ND S USPND V C C(I/O ) 6 RGT16 PACKAGE (BOTTOM VIEW) SUSPND GND RTZ16 PACKAGE (BOTTOM VIEW) 1 16 V C C (5 .0 ) SO FTCO N 2 15 V reg (3 .3 ) OE 3 14 V M O VM D- R CV 4 13 V PO VP D+ 6 11 D − S U S PN D 7 10 S PE E D GN D 8 9 V C C (I /O ) Submit Documentation Feedback OE VMO Vreg(3.3) VM VPO VCC(5.0) 12 D + VPU(3.3) 5 RCV SOFTCON VP GND V p u(3 .3) TUSB1105, TUSB1106 ADVANCED UNIVERSAL SERIAL BUS TRANSCEIVERS www.ti.com SCAS818C – MAY 2006 – REVISED DECEMBER 2006 FUNCTIONAL BLOCK DIAGRAM 3.3 V VCC(I/O) Voltage Regulator VCC(5.0) Vreg(3.3) Vpu(3.3) SOFTCON 1.5 kΩ(A) OE D+ SPEED VMO/FSE0(B) 33 (1%) D– VPO/VO(B) 33 (1%) MODE(C) + Level Shifter SUSPND RCV – TUSB1105 TUSB1106 VP VM M B L30 1 GND A. Connect to D– for low-speed operation and to D+ for high-speed operation. B. Pin function depends on device type. C. TUSB1105 only TERMINAL FUNCTIONS TERMINAL NAME (1) TUSB1105 NO. TUSB1106 NO. I/O DESCRIPTION RGT RTZ PW RTZ OE 1 1 3 1 I Output enable (CMOS level with respect to VCC(I/O), active LOW). Enables the transceiver to transmit data on the USB bus input pad. Push pull, CMOS. RCV 2 2 4 2 O Differential data receiver (CMOS level with respect to VCC(I/O)). Driven LOW when input SUSPND is HIGH. The output state of RCV is preserved and stable during an SE0 condition output pad. Push pull, 4-mA output drive, CMOS. VP 3 3 5 3 O Single-ended D+ receiver (CMOS level with respect to V). For external detection of single-ended zero (SE0), error conditions, speed of connected device. Driven HIGH when no supply voltage is connected to VCC(5.0) and Vreg(3.3) output pad. Push pull, 4-mA output drive, CMOS. VM 4 4 6 4 O Single-ended D– receiver (CMOS level with respect to VCC(I/O)). For external detection of single-ended zero (SE0), error conditions, speed of connected device. Driven HIGH when no supply voltage is connected to VCC(5.0) and Vreg(3.3) output pad. Push pull, 4-mA output drive, CMOS. SUSPND 5 5 7 5 I Suspend (CMOS level with respect to VCC(I/O)). A HIGH level enables low-power state while the USB bus is inactive and drives output RCV to a LOW-level input pad. Push pull, CMOS. MODE 6 6 I Mode (CMOS level with respect to VCC(I/O)). A HIGH level enables the differential input mode (VPO, VMO), whereas a LOW level enables a single-ended input mode (VO, FSE0). See Table 5 and Table 6 input pad. Push pull, CMOS. (1) Terminal names with an overscore (e.g., NAME) indicate active LOW signals. Submit Documentation Feedback 3 TUSB1105, TUSB1106 ADVANCED UNIVERSAL SERIAL BUS TRANSCEIVERS www.ti.com SCAS818C – MAY 2006 – REVISED DECEMBER 2006 TERMINAL FUNCTIONS (continued) TERMINAL NAME (1) TUSB1105 NO. RGT GND VCC(I/O) RTZ Die pad Die pad 7 7 I/O DESCRIPTION PW RTZ 8 6 Ground supply (2) 9 7 Supply voltage for digital I/O pins (1.65 to 3.6 V). When VCC(I/O) is not connected, the D+ and D– pins are in 3-state. This supply pin is independent of VCC(5.0) and Vreg(3.3) and must never exceed the Vreg(3.3) voltage. Speed selection (CMOS level with respect to VCC(I/O)). Adjusts the slew rate of differential data outputs D+ and D– according to the transmission speed. Input pad, push pull, CMOS. LOW – low speed (1.5 Mbit/s) HIGH – full speed (12 Mbit/s) SPEED 8 8 10 8 I D– 9 9 11 9 AI/O Negative USB data bus connection (analog, differential). For low-speed mode, connect to pin Vpu(3.3) via a 1.5-kΩ resistor. D+ 10 10 12 10 AI/O Positive USB data bus connection (analog, differential). For full-speed mode, connect to pin Vpu(3.3) via a 1.5-kΩ resistor. VPO/VO 11 11 VPO VMO/FSE0 13 12 I Driver data (CMOS level with respect to VCC(I/O), Schmitt trigger). See Driving Function Table (pin OE = L) using single-ended input data interface for TUSB1105 (pin MODE = L), and Driving Function Table (pin OE = L) using differential input data interface for TUSB1105 (pin MODE = H) and TUSB1106 input pad. Push pull, CMOS. I Driver data (CMOS level with respect to VCC(I/O), Schmitt trigger). See Driving Function Table (pin OE = L) using single-ended input data interface for TUSB1105 (pin MODE = L), and Driving Function Table (pin OE = L) using differential input data interface for TUSB1105 (pin MODE = H) and TUSB1106 input pad. Push pull, CMOS. 11 12 VMO 14 12 Vreg(3.3) 13 13 15 13 Internal regulator option. Regulated supply-voltage output (3 V to 3.6 V) during 5-V operation. A decoupling capacitor of at least 0.1 mF is required for the regulator bypass option. Used as a supply-voltage input for 3.3 V ± 10% operation. VCC(5.0) 14 14 16 14 Internal regulator option. Supply-voltage input (4 V to 5.5 V). Can be connected directly to USB supply VBUS regulator bypass option. Connect to Vreg(3.3). 15 Pullup supply voltage (3.3 V ± 10%). Connect an external 1.5-kΩ resistor on D+ (full speed) or D– (low speed). Pin function is controlled by input SOFTCON. SOFTCON = LOW – Vpu(3.3) floating (high impedance), ensures zero pullup current SOFTCON = HIGH – Vpu(3.3) = 3.3 V, internally connected to Vreg(3.3) 16 Software-controlled USB connection. A HIGH level applies 3.3 V to pin Vpu(3.3), which is connected to an external 1.5-kΩ pullup resistor. This allows USB connect/disconnect signaling to be controlled by software input pad. Push pull, CMOS. Vpu(3.3) SOFTCON (2) 4 TUSB1106 NO. 15 16 15 16 1 2 I TUSB1105 ground terminal is connected to the exposed die pad (heat sink). The package die pad is open on the TUSB1106. Submit Documentation Feedback TUSB1105, TUSB1106 ADVANCED UNIVERSAL SERIAL BUS TRANSCEIVERS www.ti.com SCAS818C – MAY 2006 – REVISED DECEMBER 2006 FUNCTIONAL DESCRIPTION Function Selection FUNCTION TABLE SUSPND OE D+, D– RCV VP, VM L L Driving and receiving Active Active Normal driving (differential receiver active) L H Receiving (1) Active Active Receiving L Driving Inactive (2) Active Driving during suspend (3) (differential receiver inactive) H High-Z (1) Inactive (2) Active Low-power state H H (1) (2) (3) FUNCTION Signal levels on D+ and D– are determined by other USB devices and external pullup/pulldown resistors. In suspend mode (SUSPND = HIGH) the differential receiver is inactive and output RCV is always LOW. Out of suspend (K), signaling is detected via the single-ended receivers VP and VM. During suspend, the slew-rate control circuit of low-speed operation is disabled. The D+ and D– lines are still driven to their intended states, without slew-rate control. This is permitted because driving during suspend is used to signal remote wakeup by driving a K signal (one transition from idle to K state) for a period of 1 ms to 15 ms. Operating Functions FUNCTION TABLES xxx Driving Function (Pin OE = L) Using Single-Ended Input Data Interface for TUSB1105 (Pin MODE = L) DATA STATE FSE0 VO DATA LOW SPEED FULL SPEED L L Differential logic 0 J K L H Differential logic 1 K J H L SE0 X X H H SE0 X X Driving Function (Pin OE = L) Using Differential Input Data Interface for TUSB1105 (Pin MODE = H) and TUSB1106 VMO VPO L L DATA DATA STATE LOW SPEED FULL SPEED SE0 J K L H Differential logic 0 K J H L Differential logic 1 X X H H Illegal state X X Submit Documentation Feedback 5 TUSB1105, TUSB1106 ADVANCED UNIVERSAL SERIAL BUS TRANSCEIVERS www.ti.com SCAS818C – MAY 2006 – REVISED DECEMBER 2006 Receiving Function (Pin OE = H) DATA STATE RCV VP (1) VM (1) LOW SPEED FULL SPEED Differential logic 0 L L H J K Differential logic 1 H H L K J L L X X D+, D– RCV* (2 SE0 (1) ) VP = VM = H indicates the sharing mode (VCC(5.0) and Vreg(3.3) are disconnected). RCV* denotes the signal level on output RCV just before SE0 state occurs. This level is stable during the SE0 period. (2) Power-Supply Configurations The TUSB1105/1106 can be used with different power-supply configurations, which can be dynamically changed. An overview is given in Table 2. • Normal mode – Both VCC(I/O) and VCC(5.0) or (VCC(5.0) and Vreg(3.3)) are connected. For 5-V operation, VCC(5.0) is connected to a 5-V source (4 V to 5.5 V). The internal voltage regulator then produces 3.3 V for the USB connections. For 3.3-V operation, both VCC(5.0) and Vreg(3.3) are connected to a 3.3-V source (3 V to 3.6 V). VCC(I/O) is independently connected to a voltage source (1.65 V to 3.6 V), depending on the supply voltage of the external circuit. • Disable mode – VCC(I/O) is not connected, VCC(5.0) or (VCC(5.0) and Vreg(3.3)) are connected. In this mode, the internal circuits of the TUSB1105 and TUSB1106 ensure that the D+ and D– pins are in 3-state and the power consumption drops to the low-power (suspended) state level. Some hysteresis is built into the detection of VCC(I/O) lost. • Sharing mode – VCC(I/O) is connected, (VCC(5.0) and Vreg(3.3)) are not connected. In this mode, the D+ and D– pins are made 3-state and the TUSB1105 and TUSB1106 allow external signals of up to 3.6 V to share the D+ and D– lines. The internal circuits of the TUSB1105 and TUSB1106 ensure that virtually no current (maximum 10 mA) is drawn via the D+ and D– lines. The power consumption through VCC(I/O) drops to the low-power (suspended) state level. Both the VP and VM pins are driven HIGH to indicate this mode. Pin RCV is made LOW. Some hysteresis is built into the detection of Vreg(3.3) lost. Table 1. Pin States in Disable or Sharing Mode PINS DISABLE-MODE STATE VCC(5.0)/Vreg(3.3) Not present VCC(I/O) Not present 1.65-V to 3.6-V input Vpu(3.3) High impedance (off) High impedance (off) D+, D– High impedance High impedance VP, VM Invalid (1) H RCV Invalid (1) L High impedance High impedance Inputs (VO/VPO, FSE0/VMO, SPEED, MODE (2), SUSPND, OE, SOFTCON) (1) (2) SHARING-MODE STATE 5-V input/3.3-V output, 3.3-V input/3.3-V input High impedance or driven LOW TUSB1105 only Table 2. Power-Supply Configuration Overview (1) 6 VCC(5.0) or Vreg(3.3) VCC(I/O) CONFIGURATION Connected Connected Normal mode SPECIAL CHARACTERISTICS Connected Not connected Disable mode D+, D–, and Vpu(3.3) are in high impedance. VP, VM, and RCV are invalid. (1) Not connected Connected Sharing mode D+, D–, and Vpu(3.3) are in high impedance. VP and VM are driven HIGH. RCV is driven LOW. High impedance or driven LOW Submit Documentation Feedback TUSB1105, TUSB1106 ADVANCED UNIVERSAL SERIAL BUS TRANSCEIVERS www.ti.com SCAS818C – MAY 2006 – REVISED DECEMBER 2006 Power-Supply Input Options The TUSB1105 and TUSB1106 have two power-supply input options. • Internal regulator – VCC(5.0) is connected to 4 V to 5.5 V. The internal regulator is used to supply the internal circuitry with 3.3 V (nominal). Vreg(3.3) becomes a 3.3-V output reference. • Regulator bypass – VCC(5.0) and Vreg(3.3) are connected to the same supply. The internal regulator is bypassed and the internal circuitry is supplied directly from the Vreg(3.3) power supply. The voltage range is 3 V to 3.6 V to comply with the USB specification. The supply-voltage range for each input option is specified in Table 3. Table 3. Power-Supply Input Options INPUT OPTION VCC(5.0) VREG(3.3) VCC(I/O) Internal regulator Supply input for internal regulator (4 V to 5.5 V) Voltage-reference output (3.3 V, 300 µA) Supply input for digital I/O pins (1.65 V to 3.6 V) Regulator bypass Connected to Vreg(3.3) with maximum voltage drop of 0.3 V (2.7 V to 3.6 V) Supply input (3 V to 3.6 V) Supply input for digital I/O pins (1.65 V to 3.6 V) Electrostatic Discharge (ESD) PARAMETER TEST CONDITIONS D+, D–, VCC(5.0), and GND All other pins TYP ±15 Human-Body Model ±8 IEC61000-4-2, Contact Discharge Human-Body Model 7 UNIT kV kV Absolute Maximum Ratings (1) over operating free-air temperature range (unless otherwise noted) MIN MAX VCC(5.0) Supply-voltage range –0.5 6 V VI(I/O) Supply-voltage range –0.5 4.6 V VCCreg(3.3) Regulated voltage range –0.5 4.6 V VI DC input voltage –0.5 VCC(I/O) + 0.5 IIK Input clamp current Tstg Storage temperature range (1) VI = –1.8 V to 5.4 V –40 UNIT V 100 mA 125 °C Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. Recommended Operating Conditions MIN NOM MAX VCC(5.0) Supply voltage, internal regulator option PARAMETER 5-V operation TEST CONDITIONS 4 5 5.5 V VCCreg(3.3) Supply voltage, regulator bypass option 3.3-V operation 3 3.3 3.6 V VCC(I/O) I/O supply voltage 1.65 3.6 V VI I/O supply voltage 0 VCC(I/O) V VI/O Input voltage on analog I/O pins (D+, D–) 0 3.6 V Tc Junction temperature –40 85 °C Submit Documentation Feedback UNIT 7 TUSB1105, TUSB1106 ADVANCED UNIVERSAL SERIAL BUS TRANSCEIVERS www.ti.com SCAS818C – MAY 2006 – REVISED DECEMBER 2006 Static Electrical Characteristics – Supply Pins over recommended ranges of operating free-air temperature and supply voltage (unless otherwise noted) PARAMETER Vreg(3.3) Internal regulator option, Iload ≤ 300 µA (1) (2) ICC Operating supply current Full-speed transmitting and receiving at 12 Mbit/s, CL = 50 pF on D+ and D– (3) ICC(I/O) Operating I/O supply current Full-speed transmitting and receiving at 12 Mbit/s (3) ICC(idle) Supply current during full-speed idle and SE0 Full-speed idle: VD+ > 2.7 V, VD– < 0.3 V SE0: VD+ < 0.3 V, VD– < 0.3 V (4) ICC(I/O)(static) Static I/O supply current Full-speed idle, SE0 or suspend ICC(susp) Suspend supply current SUSPND = HIGH (4) ICC(dis) Disable-mode supply current MIN UNIT 3.6 6 8 mA 2.3 2.5 mA 500 µA 10 22 µA 10 22 µA VCC(I/O) not connected (4) 10 22 µA ICC(I/O)(sharing) Sharing-mode I/O supply current VCC(5.0) or Vreg(3.3) not connected 10 22 µA IDx(sharing) Sharing-mode load current on D+ and D– VCC(5.0) or Vreg(3.3) not connected, SOFTCON = LOW, VDx = 3.6 V 10 µA Vreg(3.3)th Regulated supply-voltage detection threshold 1.65 V ≤ VCC(I/O) ≤ Vreg(3.3), 2.7 V ≤ Vreg(3.3) ≤ 3.6 V Vreg(3.3)hys Regulated supply-voltage detection hysteresis VCC(I/O) = 1.8 V VCC(I/O)th I/O supply-voltage detection threshold Vreg(3.3) = 2.7 V to 3.6 V I/O supply-voltage detection hysteresis Vreg(3.3) = 3.3 V (1) (2) (3) (4) (5) 3 TYP MAX 3.3 VCC(I/O)hys 8 TEST CONDITIONS Regulated supply-voltage output Supply lost during power down Supply detect during power up (5) 0.8 V 2.4 0.45 Supply lost during power down Supply detect during power up V 0.5 V 1.4 0.45 Iload includes the pullup resistor current via Vpu(3.3). In suspend mode, the typical voltage is 2.8 V (see XX). Maximum value is characterized only, not tested in production. Excluding any load current and Vpu(3.3)/Vsw source current to the 1.5-kΩ and 15-kΩ pullup and pulldown resistors (200 µA typ) When VCC(I/O) < 2.7 V, the minimum value for Vreg(3.3)th (present) is 2 V. Submit Documentation Feedback V V TUSB1105, TUSB1106 ADVANCED UNIVERSAL SERIAL BUS TRANSCEIVERS www.ti.com SCAS818C – MAY 2006 – REVISED DECEMBER 2006 Static Electrical Characteristics – Digital Pins over recommended ranges of operating free-air temperature and supply voltage (unless otherwise noted) PARAMETER TEST CONDITIONS VCC(I/O) VIL LOW-level input voltage 1.65 V to 3.6 V VIH HIGH-level input voltage 1.65 V to 3.6 V IOL = 100 µA IOL = 2 mA IOL = 100 µA VOL LOW-level output voltage IOL = 2 mA IOL = 100 µA IOL = 2 mA IOL = 100 µA IOL = 2 mA IOH = 100 µA IOH = 2 mA IOH = 100 µA VOH HIGH-level output voltage IOH = 2 mA IOH = 100 µA IOH = 2 mA IOH = 100 µA IOH = 2 mA ILI Input leakage current CIN Input capacitance MIN 0.6 VCC(I/O) 0.4 0.15 0.15 0.4 VCC(I/O) – 0.15 VCC(I/O) – 0.4 1.5 1.25 Submit Documentation Feedback V 2.15 1.9 2.85 2.6 –1 Pin to GND V 0.4 3.3 V ± 0.3 V 3.3 V ± 0.3 V V 0.4 2.5 V ± 0.2 V 2.5 V ± 0.2 V V 0.15 1.8 V ± 0.15 V 1.8 V ± 0.15 V UNIT 0.15 1.65 V to 3.6 V 1.65 V to 3.6 V MAX 0.3 VCC(I/O) 1 µA 3.5 pF 9 TUSB1105, TUSB1106 ADVANCED UNIVERSAL SERIAL BUS TRANSCEIVERS www.ti.com SCAS818C – MAY 2006 – REVISED DECEMBER 2006 Static Electrical Characteristics – Analog I/O Pins over recommended ranges of operating free-air temperature and supply voltage, VCC = 4 V to 5.5 V or Vreg(3.3) = 3 V to 3.6 V, VGND = 0 V, TA = –40°C to 85°C (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT VDI Differential input sensitivity |VI(D+) – VI(D–)| 0.2 VCM Differential common-mode voltage Includes VDI range 0.8 2.5 V VIL LOW-level input voltage, single-ended receiver 2 0.8 V VIH HIGH-level input voltage, single-ended receiver 0.4 Vhys Hysteresis voltage, single-ended receiver VOL LOW-level output voltage VOH HIGH-level output voltage ILZ OFF-state leakage current CIN Transceiver capacitance RL = 1.5 kΩ to GND 2.8 (1) Pin to GND Driver output impedance ZINP Input impedance RSW Internal switch resistance at Vpu(3.3) VTERM Termination voltage for upstream port pullup (RPU) 10 V RL = 1.5 kΩ to 3.6 V ZDRV (1) (2) (3) (4) V Steady-state drive 34 (2) 39 0.7 V 0.3 V 3.6 V 1 µA 25 pF 44 10 VOH(min) = Vreg(3.3) – 0.2 V Includes external resistors of 33 Ω ±1% on both D+ and D– This voltage is available at Vreg(3.3) and Vpu(3.3). In suspend mode, the minimum voltage is 2.7 V. Submit Documentation Feedback 3 (3) (4) Ω MΩ 13 Ω 3.6 V TUSB1105, TUSB1106 ADVANCED UNIVERSAL SERIAL BUS TRANSCEIVERS www.ti.com SCAS818C – MAY 2006 – REVISED DECEMBER 2006 Dynamic Electrical Characteristics – Analog I/O Pins (D+, D–) Driver Characteristics, Full-Speed Mode (1) (2) over recommended ranges of operating free-air temperature and supply voltage, VCC = 4 V to 5.5 V or Vreg(3.3) = 3 V to 3.6 V, VCC(I/O) = 1.65 V to 3.6 V, VGND = 0 V, see Table 10 for valid voltage level combinations, TA = –40°C to 85°C (unless otherwise noted) PARAMETER TEST CONDITIONS MIN MAX UNIT 4 20 ns tFR Rise time CL = 50 pF to 125 pF, 10% to 90% of |VOH – VOL| (see Figure 1) tFF Fall time CL = 50 pF to 125 pF, 90% to 10% of |VOH – VOL| (see Figure 1) 4 20 ns FRFM Differential rise/fall time matching (tFR/tFF) Excluding the first transition from idle state 90 111.1 % VCRS Output signal crossover voltage Excluding the first transition from idle state (see Figure 10) 1.3 2 V (1) (2) Test circuit, see Figure 13 Driver timing in low-speed mode is not specified. Low-speed delay timings are dominated by the slow rise/fall times tLR and tLF. Dynamic Electrical Characteristics – Analog I/O Pins (D+, D–) (1) (2) Driver Characteristics, Low-Speed Mode over recommended ranges of operating free-air temperature and supply voltage, VCC = 4 V to 5.5 V or Vreg(3.3) = 3 V to 3.6 V, VCC(I/O) = 1.65 V to 3.6 V, VGND = 0 V, see Table 10 for valid voltage level combinations, TA = –40°C to 85°C (unless otherwise noted) PARAMETER TEST CONDITIONS MIN MAX UNIT 75 300 ns tLR Rise time CL = 200 pF to 600 pF, 10% to 90% of |VOH – VOL| (see Figure 1) tLF Fall time CL = 200 pF to 600 pF, 90% to 10% of |VOH – VOL| (see Figure 1) 75 300 ns LRFM Differential rise/fall time matching (tLR/tLF) Excluding the first transition from idle state 80 125 % VCRS Output signal crossover voltage Excluding the first transition from idle state (see Figure 10) 1.3 2 V (1) (2) Test circuit, see Figure 13 Driver timing in low-speed mode is not specified. Low-speed delay timings are dominated by the slow rise/fall times tLR and tLF. Dynamic Electrical Characteristics – Analog I/O Pins (D+, D–) (1) (2) Driver Timing, Full-Speed Mode over recommended ranges of operating free-air temperature and supply voltage, VCC = 4 V to 5.5 V or Vreg(3.3) = 3 V to 3.6 V, VCC(I/O) = 1.65 V to 3.6 V, VGND = 0 V, see Table 10 for valid voltage level combinations, TA = –40°C to 85°C (unless otherwise noted) PARAMETER tPLH(drv) tPHL(drv) tPHZ tPLZ tPZH tPZL (1) (2) Driver propagation delay (VO/VPO, FSE0/VMO to D+, D–) Driver disable delay (OE to D+, D–) Driver enable delay (OE to D+, D–) TEST CONDITIONS MIN MAX LOW to HIGH (see Figure 4) 18 HIGH to LOW (see Figure 4) 18 HIGH to OFF (see Figure 2) 15 LOW to OFF (see Figure 2) 15 OFF to HIGH (see Figure 2) 15 OFF to LOW (see Figure 2) 15 UNIT ns ns ns Test circuit, see Figure 13 Driver timing in low-speed mode is not specified. Low-speed delay timings are dominated by the slow rise/fall times tLR and tLF. Submit Documentation Feedback 11 TUSB1105, TUSB1106 ADVANCED UNIVERSAL SERIAL BUS TRANSCEIVERS www.ti.com SCAS818C – MAY 2006 – REVISED DECEMBER 2006 Dynamic Electrical Characteristics for Analog I/O Pins (D+, D–) (1) Receiver Timing, Full-Speed and Low-Speed Mode, Differential Receiver over recommended ranges of operating free-air temperature and supply voltage, VCC = 4 V to 5.5 V or Vreg(3.3) = 3 V to 3.6 V, VCC(I/O) = 1.65 V to 3.6 V, VGND = 0 V, see Table 10 for valid voltage level combinations, TA = –40°C to 85°C (unless otherwise noted) PARAMETER tPLH(rcv) tPHL(rcv) (1) TEST CONDITIONS Propagation delay (D+, D– to RCV) MIN MAX LOW to HIGH (see Figure 3) 15 HIGH to LOW (see Figure 3) 15 UNIT ns Test circuit, see Figure 13 Dynamic Electrical Characteristics for Analog I/O Pins (D+, D–) (1) Receiver Timing, Full-Speed and Low-Speed Mode, Single-Ended Receiver over recommended ranges of operating free-air temperature and supply voltage, VCC = 4 V to 5.5 V or Vreg(3.3) = 3 V to 3.6 V, VCC(I/O) = 1.65 V to 3.6 V, VGND = 0 V, see Table 10 for valid voltage level combinations, TA = –40°C to 85°C (unless otherwise noted) PARAMETER tPLH(se) tPHL(se) (1) TEST CONDITIONS Propagation delay (D+, D– to VP, VM) MAX 18 HIGH to LOW (see Figure 3) 18 UNIT ns Test circuit, see Figure 13 tFR,tLR VOH 1.8 V tFF,tLF 90% Logic Input 0.9 V 90% 0V 10% VOL 10% MGS96 3 tPHZ tPLZ VOH − 0.3 V VCRS VOL + 0.3 V Figure 1. Rise and Fall Times 2.0 V Differential Data Lines 0.9 V tPZH tPZL VOH Differential Data Lines VOL MG S96 6 Figure 2. OE to D+, D– 1.8 V VCRS 0.8 V VOH Logic Output Logic Output 0.9 V VCRS tPLH(rcv) tPLH(se) tPLH(drv) VOH Differential Data Lines 0.9 V 0.9 V 0.9 V 0V tPHL(rcv) tPHL(se) VOL MGS965 VCRS tPHL(drv) VCRS VOL Figure 3. D+, D– to RCV, VP, VM 12 MIN LOW to HIGH (see Figure 3) Submit Documentation Feedback MGS9 64 Figure 4. VO/VPO, FSE0/VMO to D+, D– TUSB1105, TUSB1106 ADVANCED UNIVERSAL SERIAL BUS TRANSCEIVERS www.ti.com SCAS818C – MAY 2006 – REVISED DECEMBER 2006 APPLICATION INFORMATION Test Point 33 Ω 500 Ω D.U.T. + V 50 pF – MBL142 Figure 5. Load for Enable and Disable Times A. V = 0 V for tPZH, tPHZ B. V = Vreg(3.3) for tPZL, tPLZ Test Point 25 pF D.U.T. MGS968 Figure 6. Load for VM, VP, and RCV VPU(3.3) 1.5 kΩ D.U.T. D+/D– 33 Ω CL 15 kΩ Test Point Figure 7. Load for D+, D– A. Full-speed mode: connected to D+ B. Low-speed mode: Connected to D– C. Load capacitance: • CL = 50 pF or 125 pF (full-speed mode, minimum or maximum timing) • CL = 200 pF or 600 pF (low-speed mode, minimum or maximum timing) Submit Documentation Feedback 13 TUSB1105, TUSB1106 ADVANCED UNIVERSAL SERIAL BUS TRANSCEIVERS www.ti.com SCAS818C – MAY 2006 – REVISED DECEMBER 2006 APPLICATION INFORMATION (continued) 1.65 V to 3.6 V 3.3 V 0.1 µF GND V VCC(I/O) OE CC Vreg(3.3) SPEED 0.1 µF SOFTCON VCC(5.0) SUSPND Vpu(3.3) (A) MODE System ASIC GND V =5V BUS 1.5 kW 33 W RCV D+ VMO/FSE0 33 W D– VPO/VO VP TUSB1105/1106 VM GND GND A. Only for TUSB1105 Figure 8. Peripheral-Side (Full-Speed) Regulator Bypass Mode Peripheral-Side (Full-Speed) Regulator Bypass Mode While operating at full speed, the 1.5-kΩ resistor must be connected between the D+ line and VPU(3.3) or an externa 3.3V supply. When the VCC(5.0) and the Vreg(3.3) are connected together, the device operates at regulator bypass mode. This enables power savings since the regulator is turned off. However, there must be a 3.3-V supply available on board to implement this operation mode. 14 Submit Documentation Feedback TUSB1105, TUSB1106 ADVANCED UNIVERSAL SERIAL BUS TRANSCEIVERS www.ti.com SCAS818C – MAY 2006 – REVISED DECEMBER 2006 APPLICATION INFORMATION (continued) 1.65 V to 3.6 V 3.3 V 0.1 µF GND V VCC(I/O) OE CC Vreg(3.3) SPEED 0.1 µF SOFTCON VCC(5.0) SUSPND Vpu(3.3) (A) MODE System ASIC GND V =5V BUS 1.5 kW 33 W RCV D+ VMO/FSE0 33 W D– VPO/VO VP TUSB1105/1106 VM GND GND A. Only for TUSB1105 Figure 9. Peripheral-Side (Low-Speed) Regulator Bypass Mode Peripheral-Side (Low-Speed) Regulator Bypass Mode While operating at low speed, the 1.5-kΩ resistor must to be connected between the D– line and VPU(3.3) or an externa 3.3V supply. When the VCC(5.0) and the Vreg(3.3) are connected together, the device operates at regulator bypass mode. This enables power savings since the regulator is turned off. However, there must be a 3.3-V supply available on board to implement this operation mode. Submit Documentation Feedback 15 TUSB1105, TUSB1106 ADVANCED UNIVERSAL SERIAL BUS TRANSCEIVERS www.ti.com SCAS818C – MAY 2006 – REVISED DECEMBER 2006 APPLICATION INFORMATION (continued) 1.65 V to 3.6 V 5V 0.1 µF 0.1 µF GND V OE CC GND VCC(I/O) V reg(3.3) SPEED 0.1 µF SOFTCON GND SUSPND 1.5 kW VPU(3.3) (A) MODE System ASIC V =5V BUS VCC(5.0) 33 W RCV D+ VMO/FSE0 33 W D– VPO/VO VP TUSB1105/1106 VM GND GND Figure 10. Peripheral-Side (Full-Speed) Internal Regulator Mode A. Only for TUSB1105 Peripheral-Side (Full-Speed) Internal Regulator Mode While operating at full speed, the 1.5-kΩ resistor must be connected between the D+ line and the VPU(3.3) or an externa 3.3-V supply. If there is no 3.3-V supply on the board, the internal regulator can be used to provide the 3.3-V supply for the USB signaling. The VCC(5.0) is connected to a 5-V supply that generates the 3.3-V output at the Vreg(3.3) pin. In this mode, it is important that both VCC(5.0) and Vreg(3.3) pins have individual bypass capacitors in the range of 0.1 µF. 16 Submit Documentation Feedback TUSB1105, TUSB1106 ADVANCED UNIVERSAL SERIAL BUS TRANSCEIVERS www.ti.com SCAS818C – MAY 2006 – REVISED DECEMBER 2006 APPLICATION INFORMATION (continued) 1.65 V to 3.6 V 5V 0.1 µF 0.1 µF GND V OE CC GND VCC(I/O) V reg(3.3) 0.1 µF SPEED SOFTCON VCC(5.0) SUSPND 1.5 kW VPU(3.3) (A) MODE System ASIC V =5V BUS GND 33 W RCV D+ VMO/FSE0 33 W D– VPO/VO VP TUSB1105/1106 VM GND GND Figure 11. Peripheral-Side (Low-Speed) Internal Regulator Mode A. Only for TUSB1105 Peripheral-Side (Low-Speed) Internal Regulator Mode While operating at full speed, the 1.5-kΩ resistor must be connected between the D+ line and the VPU(3.3) or an external 3.3-V supply. If there is no 3.3-V supply on the board, the internal regulator can be used to provide the 3.3-V supply for the USB signaling. The VCC(5.0) is connected to a 5-V supply that generates the 3.3-V rail at the Vreg(3.3) pin. In this mode, it is important that both VCC(5.0) and Vreg(3.3) pins have individual bypass capacitors in the range of 0.1 µF. Submit Documentation Feedback 17 TUSB1105, TUSB1106 ADVANCED UNIVERSAL SERIAL BUS TRANSCEIVERS www.ti.com SCAS818C – MAY 2006 – REVISED DECEMBER 2006 APPLICATION INFORMATION (continued) 1.65 V to 3.6 V 0.1 µF GND V 0.1 µF V BUS =5V CC(I/O) V reg(3.3) OE VCC SPEED GND SOFTCON VCC(5.0) SUSPND 0.1 µF V pu(3.3) MODE GND 33 W (A) RCV D+ System ASIC VMO/FSE0 33 W D– VPO/VO 15 kW VP 15 kW TUSB1105/1106 VM GND GND GND GND A. Only for TUSB1105 Figure 12. Host-Side (VCC(5.0) Supplied From VBUS Pin) Host-Side (VCC(5.0) Supplied From VBUS Pin) If there is no 3.3-V supply on board, the VBUS supply can support the USB-side power needs. The on-chip regulator generates the 3.3-V internal supply rail, which is required for the USB signal levels. The logic-side I/Os can operate at any voltage range from 1.65 V to 3.6 V. Powering VCC(5.0) through the VBUS port of the USB connector realizes significant power saving for portable applications, such as cell phones, PDAs, etc. In this operating mode, the ICC(5.0) current is fed from the external source. The USB-side power consumption, ICC(5.0) is 4 mA, as opposed to logic-side ICC(IO) of 1 mA under full-speed operation. 18 Submit Documentation Feedback TUSB1105, TUSB1106 ADVANCED UNIVERSAL SERIAL BUS TRANSCEIVERS www.ti.com SCAS818C – MAY 2006 – REVISED DECEMBER 2006 APPLICATION INFORMATION (continued) 1.65 V to 3.6 V 0.1 µF 3.3 V GND V CC(I/O) V reg(3.3) V CC SPEED 0.1 µF SOFTCON VCC(5.0) SUSPND GND V BUS OE V pu(3.3) (A) MODE 33 W RCV D+ System ASIC VMO/FSE0 33 W D– VPO/VO 15 kW 15 kW VP TUSB1105/1106 VM GND GND GND GND A. Only for TUSB1105 Figure 13. Host-Side (3.3-V Supply Present) Internal Regulator Bypass Mode Host-Side (3.3-V Supply Present) Internal Regulator Bypass Mode If a 3.3-V supply supports the USB-side power, VCC(5.0) and Vreg(3.3) must to be tied together and connected to a 3.3-V supply. It also makes the regulator inactive. Submit Documentation Feedback 19 PACKAGE OPTION ADDENDUM www.ti.com 6-Feb-2007 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Eco Plan (2) Qty TUSB1105RGTR ACTIVE QFN RGT 16 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TUSB1105RTZR ACTIVE QFN RTZ 16 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TUSB1106PWR ACTIVE TSSOP PW 16 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TUSB1106RGTR ACTIVE QFN RGT 16 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TUSB1106RTZR ACTIVE QFN RTZ 16 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM Lead/Ball Finish MSL Peak Temp (3) (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. 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Addendum-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 24-Apr-2007 TAPE AND REEL INFORMATION Pack Materials-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com Device TUSB1106PWR 24-Apr-2007 Package Pins PW 16 Site Reel Diameter (mm) Reel Width (mm) A0 (mm) B0 (mm) K0 (mm) P1 (mm) MLA 330 12 7.0 5.6 1.6 8 TAPE AND REEL BOX INFORMATION Device Package Pins Site Length (mm) Width (mm) Height (mm) TUSB1106PWR PW 16 MLA 338.1 340.5 20.64 Pack Materials-Page 2 W Pin1 (mm) Quadrant 12 Q1 MECHANICAL DATA MTSS001C – JANUARY 1995 – REVISED FEBRUARY 1999 PW (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE 14 PINS SHOWN 0,30 0,19 0,65 14 0,10 M 8 0,15 NOM 4,50 4,30 6,60 6,20 Gage Plane 0,25 1 7 0°– 8° A 0,75 0,50 Seating Plane 0,15 0,05 1,20 MAX PINS ** 0,10 8 14 16 20 24 28 A MAX 3,10 5,10 5,10 6,60 7,90 9,80 A MIN 2,90 4,90 4,90 6,40 7,70 9,60 DIM 4040064/F 01/97 NOTES: A. B. C. D. All linear dimensions are in millimeters. This drawing is subject to change without notice. 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