Features • • • • • • • Single 3-V Supply Voltage High Power-added Efficient Power Amplifier (Pout typically 26.5 dBm) Ramp-controlled Output Power Low-noise Preamplifier (NF typically 1.8 dB) Biasing for External PIN Diode T/R Switch Current-saving Standby Mode Few External Components DECT SiGe Front End IC with High PAE Electrostatic sensitive device. Observe precautions for handling. U7006B Description The U7006B is a monolithic SiGe transmit/receive front end IC with power amplifier, 50-W internal matching, low-noise amplifier and T/R switch driver. It is especially designed for operation in TDMA systems like DECT. Due to the ramp-control feature and a very low quiescent current, an external switch transistor for VS is not required. Figure 1. Block Diagram VS_PA V1_PA PA PA_IN V2_PA_OUT RAMP LNA LNA_IN LNA_OUT RX_ON TX/RX Standby control T/R Switch driver PU R_SWITCH SWITCH_OUT 4714A–DECT–07/03 1 Pin Configuration Figure 2. Pinning PSSO16 R_SWITCH 1 16 PU SWITCH_OUT 2 15 RX_ON GND1 3 14 LNA_OUT LNA_IN 4 13 GND2 V1_PA 5 12 VS_LNA V2_PA_OUT 6 11 PA_IN V2_PA_OUT 7 10 RAMP V2_PA_OUT 8 9 VS_PA U7006B Pin Description 2 Pin Symbol 1 R_SWITCH Function 2 SWITCH_OUT 3 GND1 4 LNA_IN Low-noise amplifier input 5 V1_PA Inductor to power supply for power amplifier 6 7 8 V2_PA-OUT 9 VS_PA Supply voltage for power amplifier 10 RAMP Power-ramping control input 11 PA_IN Power amplifier input 12 VS_LNA 13 GND2 14 LNA_OUT 15 RX_ON 16 PU Resistor to GND sets the PIN diode current Switched current output for PIN diode Ground Inductor to power supply and matching network for power amplifier output Supply-voltage input for low-noise amplifier Ground Low-noise amplifier output RX active high Power-up active high U7006B 4714A–DECT–07/03 U7006B Absolute Maximum Ratings All voltages refer to GND (Pins 3 and slug), ESD protection according to ESD-S5.2-1994, Class M1. Parameters Symbol Value Unit Supply voltage; pins 6, 10, 13 and 16 (no RF) VS 5 V Junction temperature Tj 150 °C Storage temperature Tstg -40 to +125 °C Input power PA, Pin 11 PinPA +10 dBm Input power LNA, Pin 4 PinLNA -5 dBm Symbol Value Unit RthJA 30 K/W Thermal Resistance Parameters Junction ambient Operating Range All voltages refer to GND (Pins 3, 13 and slug). The following table represents the sum of all supply currents depending on the TX/RX mode. Power supply points are VS_LNA, VS_PA, V1_PA, V2_PA_OUT. Parameters Symbol Min. Supply voltage pins 5, 6, 7, 8 and 9 VS Supply voltage pin 12 VS Supply current TX RX IS IS Standby current PU = 0 Typ. Max. 2.7 3 4.6 V 2.7 3.6 4.6 V 350 8 IS Ambient temperature Tamb Unit mA mA 10 -25 µA +25 °C +70 Electrical Characteristics Test conditions (unless otherwise specified): VS = 3 V, Tamb = 25°C, CW mode Parameters Power Amplifier Test Conditions Symbol Min. Typ. Max. Unit VS 2.7 3 4.6 V (1) Supply voltage Pins 5, 6, 7, 8 and 9 Supply current TX IS_TX Supply current RX (PA off) IS_RX Standby current Standby Frequency range TX Power gain TX, pin 11 to pins 6, 7, 8 Gain-control range TX 350 10 IS_standby f 1.88 µA 10 µA 1.94 GHz Gp 28 dB DGp 48 dB Ramping voltage TX, power gain (max), pin 10 VRAMP max 2.1 Ramping current TX, power gain (max), pin 10 IRAMP 0.5 Power-added efficiency TX PAE 40 Notes: mA V 2.0 mA % 1. Power amplifier shall be unconditionally stable, maximum duty cycle 50%, maximum load mismatch and duration: TBD 2. With external matching network (see Figure 13 ) 3. Low-noise amplifier shall be unconditionally stable 3 4714A–DECT–07/03 Electrical Characteristics (Continued) Test conditions (unless otherwise specified): VS = 3 V, Tamb = 25°C, CW mode Parameters Test Conditions Saturated output power TX, referred to pins 6, 7, 8 VS = 3.6 V Input matching (2) TX, pin 11 Symbol Min. Typ. Max. Unit Psat 26.5 VSWRin < 2:1 TX, pins 6, 7, 8 VSWRout < 2:1 Harmonics at P 1dB TX, pins 6, 7, 8 2 fo 3 fo -30 dBc Maximum input power Pin 11 PinPA 10 dBm Stability (non harmonic emission) TX, pin 10 Pin = 2 dBm, VRAMP = 2 V VSWRout < 10:1 (all phases) -60 dBc Output matching (2) dBm T/R Switch Driver (Currently Programmed by External Resistor from R_SWITCH to GND) Standby, pin 2 Switch-out current output Low-noise Amplifier IS_O_standby 2 2 µA µA RX IS_O_RX TX at 100 W IS_O_100 1 mA TX at 1.2 kW IS_O_1k2 3 mA TX at 33 kW IS_O_33k 10 mA (3) Supply voltage All, pin 12 VS 2.7 3.6 Supply current RX IS 8 mA Supply current (LNA and control logic) TX (control logic active), pin 12 IS 300 µA 1 4.6 V Standby current Standby, pin 12 IS Frequency range RX f 1.88 10 µA 1.94 GHz Power gain RX, pin 4 to pin 14 Gp 17 Noise figure RX NF Gain compression RX, refer to pin 14 P1dB -7 dBm 3rd-order input interception point RX IIP3 -15 dBm Input matching RX VSWRin < 2:1 Output matching RX VSWRin < 2:1 19 1.8 dB 2.0 dB Logic Input Levels (RX_ON, PU) High input level = 1, pins 5 and 16 ViH 2.4 VS V Low input level =0 ViL 0 0.5 V High input current =1 IiH 40 µA Low input current =0 IiL 0 µA Notes: 4 1. Power amplifier shall be unconditionally stable, maximum duty cycle 50%, maximum load mismatch and duration: TBD 2. With external matching network (see Figure 13 ) 3. Low-noise amplifier shall be unconditionally stable U7006B 4714A–DECT–07/03 U7006B Control Logic Table 1. Control Logic for LNA and T/R Switch Driver Operation Mode PU RX_ON Standby 0 0 TX 1 0 RX 1 1 Figure 3. Output Power versus Ramp Voltage 30 Pout (dBM) 20 10 0 -10 -20 0.0 0.5 1.0 1.5 2.0 2.5 3.0 VRAMP (V) Input/Output Circuits Figure 4. Input Circuit PA_IN/VS_PA 9 VS_PA 11 PA_IN 13 GND 5 4714A–DECT–07/03 Figure 5. Input Circuit RAMP/VS_PA 9 VS_PA 10 RAMP Slug GND Figure 6. Input Circuit V1_PA 5 V1_PA Slug GND Figure 7. Input/Output Circuit V2_PA 6, 7, 8 V2_PA_OUT Slug GND 6 U7006B 4714A–DECT–07/03 U7006B Figure 8. Input Circuit LNA_IN/VS_LNA 12 VS_LNA 4 LNA_IN 3 GND Figure 9. Output Circuit LNA_OUT 12 VS_LNA 14 LNA_OUT Slug GND 7 4714A–DECT–07/03 Figure 10. Input Circuit SWITCH_OUT/R_SWITCH 9 VS_PA 2 SWITCH_OUT 1 R_SWITCH Slug GND Figure 11. Input Circuit RX_ON 12 VS_LNA 15 RX_ON Figure 12. Input Circuit PU 12 VS_LNA 16 PU 8 U7006B 4714A–DECT–07/03 U7006B Typical Application Circuit Figure 13. Typical Schematic LNA_OUT PA_IN RAMP PU RX_ON PCB 16 15 14 13 12 11 10 9 U7006B TX/RX standby control TX LNA PA 1 2 3 4 5 6 7 8 PCB diel. BPF Harmonic termination PCB VS PCB Microstripline l/4 Antenna 9 4714A–DECT–07/03 Figure 14. U7006B Application Board Schematic Figure 15. U7006B Application Board Layout 4.7 mF 0R 2.2 nH 56 pF 1 nF 22 nH 4.7 mF 1.1 pF 0.9 pF 0R 56 pF 0R LED 0R 18 nH 56 pF 1nF 1nF 1mF V1PA PA PU 56 pF 0R VS_LNA 56pF 0R SWITCH_OUT 2.7 pF RX_ON 0R 100pF RAMP LNA DECT Frontend 100 pF PA_IN GND LNA_OUT 56pF 0R 1 mF V2PA 0R VccPA 2k7 0R 390R 0R TMK9821 LNA_IN 10 PA_OUT U7006B 4714A–DECT–07/03 U7006B Ordering Information Extended Type Number Package Remarks U7006B-MLB PSSO16 Tube U7006B-MLBG3 PSSO16 Taped and reeled Package Information 11 4714A–DECT–07/03 Atmel Corporation 2325 Orchard Parkway San Jose, CA 95131 Tel: 1(408) 441-0311 Fax: 1(408) 487-2600 Regional Headquarters Europe Atmel Sarl Route des Arsenaux 41 Case Postale 80 CH-1705 Fribourg Switzerland Tel: (41) 26-426-5555 Fax: (41) 26-426-5500 Asia Room 1219 Chinachem Golden Plaza 77 Mody Road Tsimshatsui East Kowloon Hong Kong Tel: (852) 2721-9778 Fax: (852) 2722-1369 Japan 9F, Tonetsu Shinkawa Bldg. 1-24-8 Shinkawa Chuo-ku, Tokyo 104-0033 Japan Tel: (81) 3-3523-3551 Fax: (81) 3-3523-7581 Atmel Operations Memory 2325 Orchard Parkway San Jose, CA 95131 Tel: 1(408) 441-0311 Fax: 1(408) 436-4314 Microcontrollers 2325 Orchard Parkway San Jose, CA 95131 Tel: 1(408) 441-0311 Fax: 1(408) 436-4314 La Chantrerie BP 70602 44306 Nantes Cedex 3, France Tel: (33) 2-40-18-18-18 Fax: (33) 2-40-18-19-60 ASIC/ASSP/Smart Cards RF/Automotive Theresienstrasse 2 Postfach 3535 74025 Heilbronn, Germany Tel: (49) 71-31-67-0 Fax: (49) 71-31-67-2340 1150 East Cheyenne Mtn. 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