UC3172A Full Bridge Power Amplifier FEATURES DESCRIPTION • Plug-in Compatibility with the UC3173A The UC3172A power amplifier is pin-for-pin compatible with the UC3173A. Improvements have been made to allow more liberal application of the device. • 5V or 12V Operation • 13mA Quiescent Supply Current • 1.8mA Standby Current • Precision Current Control • ±1A Load Current • 1.65V Typical Total VSAT at 1A This full bridge power amplifier, rated for continuous output current of 1A, is intended for use in demanding servo applications such as head positioning for high-density disk drives. This device includes a precision current sense amplifier that senses load current with a single resistor in series with the load. The UC3172A is optimized to consume a minimum of supply current, and is designed to operate in both 5V and 12V systems. The power output stages have a low saturation voltage and are protected with current limiting and thermal shutdown. When inhibited the device will draw less than 1.8mA of total supply current. • Controlled Velocity Head Parking • Range Control for 4:1 Gain Change • Compensation Adjust Pin for Bandwidth Control • Inhibit Input and UVLO • PLCC, SOIC, and Low Profile Quad Flat Pack Packages BLOCK DIAGRAM Auxiliary functions on this device include a dual-input undervoltage comparator, which can monitor two independent supply voltages and activate the builtin head park function when either is below minimum. The park circuitry allows a programmable retract voltage to be applied to the load for limiting maximum head velocity. A separate low-side parking drive pin permits a series impedance to be inserted to control maximum retract current. The parking drive function can be configured to operate with supply voltages as low as 1.2V. The closed loop transconductance of the configured power amplifier can be switched between a high and low range with a logic input. The 4:1 change in gain can be used to extend the dynamic range of the servo loop. Bandwidth variations that would otherwise result with the gain change can be controlled with a compensation adjust pin. Note: Pin numbers refer to QP package. 9/96 UDG-94039 UC3172A ABSOLUTE MAXIMUM RATINGS (Note 1) Input Supply Voltage, (VIN, VC, VL) . . . . . . . . . . . . . . . . . . 18V UV Comparator Maximum Forced Voltage . . . . . . . . . . . . . . . . . −0.3V to 6V Maximum Forced Current . . . . . . . . . . . . . . . . . . . . . ±10mA Logic Inputs and REFIN Maximum Forced Voltage . . . . . . . . . . . . . . . . −0.3V to 10V Maximum Forced Current . . . . . . . . . . . . . . . . . . . . . ±10mA B Amplifier Inverting Input . . . . . . . . . . . . . . −0.3V to VIN + 1.0 A Amplifier Inverting Inputs, (Aux. and Normal) . . . . . . . . . . . . . . . . . −0.3V to VC + 1.0V Open Collector Output Voltages. . . . . . . . . . . . . . . . . . . . . . 20V A and B Output Currents (Continuous) Source . . . . . . . . . . . . . . . . . . . . . . . . . . . . Internally Limited Sink . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1A Parking Drive (PRKDRV) Output Current Continuous. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150mA Pulsed . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1A Output Diode Current (Pulsed) . . . . . . . . . . . . . . . . . . . . . . . 1A Power OK (PWROK) Output Current Continuous . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30mA Pulsed (Note 2). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150mA Operating Junction Temperature . . . . . . . . . − 55°C to +150°C Storage Temperature . . . . . . . . . . . . . . . . . . − 65°C to +150°C Lead Temperature (Soldering, 10 sec.) . . . . . . . . . . . . +300°C Note 1: Unless otherwise indicated, voltages are referenced to ground and currents are positive into, negative out of, the specified terminals, "Pulsed" is defined as a less than 10% duty cycle pulse with a maximum duration of 500µs. Note 2: The PWROK output will safely discharge a capacitive load of up to 30 nanojoules. Note 3: Consult Packaging Section of Unitrode Integrated Circuits databook for thermal specifications and limitations of packages. CONNECTION DIAGRAMS SOIC-28 (Top View) DWP Package TQFP-48 (Top View) FQ Package PLCC-28 (Top View) QP Package 2 UC3172A ELECTRICAL CHARACTERISTICS Unless otherwise stated, these specifications apply for TA = 0 to +70°C, VIN = 5V, VC = VIN = VL, REFIN = VIN/2, RANGE, PARK, and INH = 0V, and TA =TJ. PARAMETER TEST CONDITIONS MIN TYP MAX UNITS Input Supply VIN Supply Current VC Supply Current Low Range Mode 11 15 mA High Range Mode 17 23 mA mA IOUT = 0A, Low Range Mode 1.2 2.5 IOUT = 0A, High Range Mode 1.2 2.5 mA VL Supply Current Low Range Mode 0.75 1.1 mA High Range Mode 0.8 1.2 mA Total Supply Current Supplies = 5V, IOUT = 0A, Low Range Mode 13 17 mA Supplies = 12V, IOUT = 0A, Low Range Mode 14 20 mA Supplies = 5V, IOUT = 0A, High Range Mode 19 25 mA VL UVLO Threshold Supplies = 12V, IOUT = 0A, High Range Mode 21 29 mA Low to High 2.6 2.8 V UVLO Threshold Hysteresis Under Voltage (UV) Comparator Input Bias Current UV Thresholds 200 Max at Either UV Input Low to High, Other Input = 5V UV Threshold Hysteresis 1.28 19 PWROK Vsat IOUT = 5mA, UV Input Low PWROK Leakage VOUT = 20V mV −0.25 −1.0 µA 1.3 1.32 V 24 29 mV 0.15 0.45 5 V µA Power Amplifiers A and B Input Offset Voltage A Amplifier, VCM = 2.5V 4 mV B Amplifier, VCM = 2.5V 12 mV Input Bias Current VCM = 2.5V, Inverting Inputs Only −150 −500 nA Input Bias Current at Ref. Input (REFIN − CS+)/48kohms, TJ = 25°C 15 21 27 µA/V CMRR VCM = 1V to 10V, Supplies = 12V 70 90 dB PSRR VIN = 4V to 15V, Vcm = 1.5V 70 90 dB Large Signal Voltage Gain Supplies = 12V, VOUT = 1V, IOUT = 300mA to VOUT = 10V, IOUT = −300mA 3.0 20.0 V/mV Gain Bandwidth Product A Amplifier (Note 4) 3.5 MHz B Amplifier (Note 4) 1.0 MHz (Note 4) 1.0 V/µs Slew Rate High-Side Current Limit Output Saturation Voltage 1.6 A High-Side, IOUT = −100mA (Note 5) 1.1 0.75 V High-Side, IOUT = −300mA (Note 5) 0.85 V High-Side, IOUT = −550mA (Note 5) High-Side IOUT = −1A (Note 5) 0.95 1.15 V V Low-Side, IOUT = 100mA 0.15 V Low-Side, IOUT = 300mA 0.25 V Low-Side, IOUT = 550mA 0.3 V Low-Side, IOUT = 1A 0.5 Total Vsat, IOUT = 100mA 0.9 1.2 V Total Vsat, IOUT = 300mA 1.1 1.4 V V Total Vsat, IOUT = 550mA 1.25 1.6 V Total Vsat, IOUT = 1A 1.65 2.4 V 3 UC3172A ELECTRICAL CHARACTERISTICS Unless otherwise stated, these specifications apply for TA = 0 to +70°C, VIN = 5V, VC = VIN = VL, REFIN = VIN/2, RANGE, PARK, and INH = 0V, and TA =TJ. PARAMETER TEST CONDITIONS MIN TYP MAX UNITS 0.23 0.4 V Power Amplifiers A and B (cont.) VC to VIN Headroom Volts below VIN, delta High-Side, Vsat = 100mV, IOUT = −550mA (Note 5) High-Side Diode, VF Id = 1A 1.5 V Low-Side Diode, VF Id = 1A, INH Activated, B Amplifier Only 1.5 V Current Sense Amplifier −3 Common-mode Range Supplies = 12V (Note 4) 13 V Input Offset Voltage VCM = 2.5V, Low Range Mode 2.0 mV VCM = 2.5V, High Range Mode 4.0 mV Input Offset Change with Common Mode Input VCM = 0V to 13V, Supplies = 12V, Low Range Mode 2000 µV/V VCM = 0V to 13V, Supplies = 12V, High Range Mode 4000 Voltage Gain VDIFF = +1.0 to −1.0V, VCM = 2.5V, High Range Mode 0.485 0.50 0.515 µV/V V/V VDIFF = +1.0 to −1.0V, VCM = 2.5V, Low Range Mode 1.95 2.0 2.05 V/V Low-Side, IOUT = 1mA 0.1 0.3 V High-Side, IOUT = −1mA, Referenced to VIN 0.1 0.3 V 1.1 1.7 V 50 75 µA 0.15 0.35 V 50 µA Saturation Voltage Parking Function PARK Threshold Voltage 0.6 PARK Threshold Current Internal Pull-Up, PARK = 0.6V PRKDRV Saturation Voltage IOUT = 50mA PRKDRV Leakage VOUT = 20V Regulating Voltage at VPARK Input 1.275 1.30 1.325 V −300 −750 nA 0.8 0.95 V 1.4 1.7 V At VL, VC = VIN = 0V, Vsat < 0.5V, PRKDRV IOUT = 50mA, Rl = 30 ohms to 2V 1.1 1.4 V PWROK IOUT = 5mA, Rl = 300 ohms to 2V 1.2 1.6 V PARK Open, VL = 5V, VC = 1.6V, VIN = 0V, PWROK IOUT = 5mA, PRKDRV IOUT = 50mA 1.6 3.0 mA 1.1 1.7 V −0.5 −1.0 µA 1.1 1.7 V 50 100 µA 0.02 0.1 V 5 µA 1.8 mA Amplifier A Auxiliary Input Bias Current Amplifier A Parking High-Side Saturation Voltage Minimum Parking Supply Minimum Supply for Parking Drive and Power OK Operation VL Parking Supply Current IOUT = −50mA, VIN = 0V, VC = VL = 5V, PARK Open, VC to AOUT At VC and VL, VIN = 0V, AOUT - PRKDRV Vsat > 0.5V, IPARK = 50mA Auxiliary Functions INH Threshold INH Current 0.6 INH = 1.7V RANGE Threshold 0.6 RANGE Current RANGE = 1.7V COMPA Pin Saturation Voltage RANGE = 0V, Pin Current = ±500µA, Referenced to AOUT COMPA Leakage Current RANGE = 1.7V, Supplies = 12V, AOUT − VCOMPA = ±6V Total Supply Current when Inhibited VIN, VC, and VL currents 1.0 Thermal Shutdown Temperature (Note 4) 165 Note 4: Guaranteed by design. Not 100% tested in production. Note 5: The high -side saturation performance of the UC3172A is referenced to the VIN supply pin. The VC supply pin can operate about 400mV below the VIN supply input without affecting the performance. 4 °C UC3172A PIN DESCRIPTIONS AIN: Inverting input to the A amplifier. Used as the summing node to close the loop on the overall power amplifier. PGND: Current return for all high level circuitry, this pin should be connected to the same potential as GND. PRKDRV: A 100mA drive output that is active low during a park operation. This pin is normally used to supply the low-side drive to the load during parking, in place of the B amplifier. A series resistor can be added between this pin and the load to limit current during park. AOUT: Output for the A power amplifier, providing one end of the differential drive to the load during normal operation and during park. During a UVLO condition at the VL supply pin, this output is forced to a high, source only state. When the UC3172A is inhibited, this output will be set high, in a source only state. PWROK: Indicates with an active low condition that either of the UV inputs are low, or that the supply voltage at the VL input to the UC3172A has dropped below the UVLO threshold. This output will remain active low until the VL supply has dropped to below approximately 1.2V. BIN: Inverting input to the B amplifier. Used to program the gain of the B amplifier to guarantee maximum voltage swing to the load. BOUT: Output for the B power amplifier, providing one end of the differential drive to the load during normal operation. During park and while inhibited this pin is tristated. RANGE: When this pin is open or at a logic low potential, the current sense amplifier will be in its low range mode. In this mode the voltage gain of the current sense amplifier will be 2. If this pin is brought to a logic high, the gain of the current sense amplifier will change into its high range value of 0.5. This factor of four change in gain will vary the overall transconductance of the power amplifier by the same ratio, with the transconductance being the highest in the high mode. This feature allows improved dynamic range of load current control for a given control input range and resolution. COMPA: The compensation adjust pin allows the user to provide an auxiliary compensation network for the A amplifier that is only active when the current sense amplifier is in the low range. With this option, the user can control the change in bandwidth that would otherwise result from the gain change in the feedback loop. CS+: The non-inverting input to the current sense amplifier is typically tied to the connection between AOUT and the series current sense resistor. REFIN: Reference for input control signals to the power amplifier, as well as, the non-inverting inputs to the A and B amplifiers, and the output level shift for the CS amplifier. CS-: The inverting input to the current sense amplifier is typically tied to the load side of the current sense resistor connected in series with the load. This pin can be pulled below ground during an abrupt load current change with an inductive load. VC: High current supply to the collectors of the high-side NPN output devices on the A and B amplifiers. This supply should be powered whenever the A or B amplifiers are activated. This pin can operate approximately 400mV below the VIN supply without affecting the voltage available to the load. This supply pin provides drive to the power amplifiers during a parking operation. CSOUT: The output of the current sense amplifier has a 1.5mA current source pull-up and an active NPN pulldown. The output will pull to within 0.3V of either rail with a load current of less than 1mA. VIN: Provides bias supply to both the power amplifiers and the current sense amplifiers. The high-side drive to the power stages on both the A and B amplifiers is referenced to this pin. The high side saturation voltages are specified and measured with respect to this supply pin. The parking function of the device is fully operational independent of the voltage at this pin. GND: Reference point for the internal reference, UV comparator, and other low-level circuitry. INH: A high impedance logic input that disables the A and B power amplifiers, as well as the current sense amplifier. The UV comparators and logic functions of the UC3172A remain active. This input has an internal pullup that will inhibit the device if the input is left open. The INH function is overridden by any condition that forces the park function to be activated. VL: Logic portions of the UC3172A are powered by this supply pin, including the reference, UVLO, the UV comparators, and the PRKDRV and PWROK outputs. This pin is a low current supply that would normally be tied to the VC pin, or to a parking hold up capacitor for extended parking operation with very low recovered back EMF. PARK: Logic input that forces the park condition on the UC3172A. This input has an internal pull-up that will force the park condition if the pin is left open. 5 UC3172A PIN DESCRIPTIONS (cont.) VPARK: The auxiliary inverting input to the A amplifier, activated during park conditions on the UC3172A. An internal auxiliary non-inverting input is connected to the 1.3V reference. When the auxiliary inputs are activated, the A amplifier will force a programmed voltage at its output for a maximum back-EMF/velocity retract of the head. The park condition on the UC3172A is always activated by any one of the following four conditions, 1: a low condition on either of the UV inputs, 2: a high input level at the PARK input, 3: a UVLO condition at the VL supply pin, and 4: activation of the TSD (thermal shutdown) pro- tection circuit. During a UVLO condition at the VL pin the auxiliary inputs to the A amplifier are over-ridden, and the A amplifier output is forced to its high state. UV1 & 2: Inputs to the UV comparator, these inputs are high impedance sensing points used to monitor external supply conditions. Either of the inputs going low will force the device into a park condition, and force the PWROK output to an active low state. If either of these inputs is not used it should be connected to a voltage greater than 1.3V. APPLICATION INFORMATION A and B Amplifier Total Vsat A and B Amplifier High and Low Vsats 1.2 1.8 1.1 0°C HIGH-SIDE 1.0 1.6 0.9 25°C 125°C 25°C Vsat (Volts) 0.8 1.4 0.6 0.5 125°C 0.4 0°C 1.2 1.0 25°C LOW-SIDE 125°C 0.3 0.8 0°C 0.2 0.1 0.6 0 0 100 200 300 400 0 500 600 700 800 900 1000 100 200 300 400 Output Current (mA) 500 600 700 800 900 1000 Output Current (mA) PWROK Saturation Voltage VIN to VC Headroom 1 0.5 IOUT= 450mA 0.4 Power OK Vsat (Volts) 0.8 VIN - VC (Volts) Vsat (Volts) 0.7 0.6 0°C 25°C 0.4 0.3 125°C 0.2 125°C 25°C 0.1 0.2 0°C 0 0 0 50 100 150 0 200 5 10 15 Power OK Output Current (mA) A or B Amplifier High-Side Vsat Increase (mVolts) 6 20 UC3172A APPLICATION INFORMATION (cont.) A Amplifier High-Side Vsat in Park Mode 1.2 VIN = 0V VC = VL = 2V 1.1 0.6 Parking Drive Vsat (Volts) A Amp High-Side Sat (VC to AOUT) (Volts) PRKDRV Saturation Voltage 0.7 1.0 0°C 0.9 0.8 25°C 125°C 0.7 0.6 0.5 125°C 0.4 25°C 0.3 0°C 0.2 0.1 0.5 0 0.4 0 50 100 0 150 10 PRKDRV Current vs. VL Supply 150 PWROK vs. VL Supply 60 7.0 125°C 125°C 6.0 50 25°C Power OK Current (mA) Park Drive Current (mA) 100 Output Current (mA) Output Current (mA) 40 30 RL = 30Ωs to 2V VC = 0V VIN = 0V 20 10 5.0 25°C 4.0 RL = 300Ωs to 2V VC = 0V VIN = 0V 3.0 2.0 1.0 0 0 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 0 VL Supply Voltage (Volts) VL Supply Voltage (Volts) VL Current vs. PRKDRV Current 7 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 VL Current vs. PWROK Current 2.0 VL = 5V VC = 1.6V VL = 5V VC = 1.6V 6 VL Supply Current (mA) VL Supply Current (mA) 0°C 5 25°C 4 125°C 3 2 1.5 25°C 0°C 1.0 125°C 0.5 1 0 0 0 50 100 150 0 Parking Drive Output Current (mA) 5 10 15 Power OK Output Current (mA) 7 20 UC3172A APPLICATION INFORMATION (cont.) GM = IL Rfb I = • VS Rfa AVCS • RS AVCS = Current Sense Amplifier Gain = 2.0 Low Range, 0.5 High Range UDG-94040 Figure 1. Typical Application Design Procedure for Application of the UC3172A The following is a simple design flow that can be used to configure the UC3172A or UC3173A Full Bridge Power Amplifiers as shown in Figure 1. D. In order to assure that maximum voltage drive to the load is achievable, there are some precautions that should be taken. In a standard configuration, the B amplifier is slaved to the A amplifier. The bias point of the REFIN and the gain of the B amplifier, as well as the saturation voltages of the power output stages, will affect the voltage available to the load. Definitions: f3dB = the closed loop 3dB bandwidth AVB = B amplifier closed loop gain, = Rfd/Rfc AVCS = current sense amplifier gain, = 0.5 in high range, and 2.0 in low range fGBWA = gain bandwidth product of the A amplifier GmHR = closed loop transconductance in high range mode GmLR = closed loop transconductance in low range mode L = load inductance = load resistance RL There are two simple procedures to follow, either will insure that the capabilities of the device are fully utilized. The first is to set the REFIN voltage at the center of the available voltage swing at the output of the power amplifiers. This optimum reference is defined by equation (3). VIN − VHSsat + VLSsat (3) VREF (optimum) = 2 A. Choose RS to be as large as head room will tolerate, this is the series current sense resistor. where: VHSsat = high-side Vsat at maximum load VLSsat = low-side Vsat at maximum load. B. Choose a value of RFB to be less than the peak current sense amplifier swing divided by 1mA. A value in the range of 3k to 10k is suggested. A second approach is to raise the gain of the B amplifier to insure maximum swing. For a given REFIN voltage the gain of the B amplifier, set by the ratio of the feedback resistors, can be made greater than unity as given by: C. Calculate RFA according to: RFB (1) RFA = 0.5 • RS • GmHR (4) AVB = If the range change option is not going to be used, it is recommended that the device be set in the low range mode and RFA be calculated by: RFB (2) RFA = 2 • RS • GmLR VIN − VHSsat + VREF or, VREF − VLSsat VREF − VLSsat VIN − VHSsat − VREF 8 UC3172A APPLICATION INFORMATION (cont.) fier will change according to (6). In other words, the bandwidth would be four times larger during the low range mode when AVCS is equal to 2, than during the high range mode when AVCS is equal to 0.5, unless the value of RC is adjusted to compensate. The COMPA pin on the UC3172A can be used to do this. The COMPA pin acts as a simple switch that allows a parallel compensation network to be applied around the A amplifier during low range operation. A simple network as shown here will keep the loop response constant independent of the range condition. whichever is greater than unity. For a typical case, where VREF has been set at VIN/2, the required gain for a 5 volt system will be about 1.5, and for a 12 volt system, 1.2. It is worth noting that when using this method the B amplifier will saturate before the A amplifier on one polarity of the voltage swing. During the time when the B amplifier is saturated and the A amplifier is not, the small signal bandwidth of the loop will be reduced by a factor of (AVB + 1). E. The normal configuration for compensation of the power amplifier is shown in Figure 1. A simple RC network, RCCC, around the A amplifier is all that is required. To maintain the same 3dB bandwidth in both the high and low range modes set RCA and CCA to: In the closed loop transconductance amplifier, the A amplifier operates at the highest noise gain. Noise gain is a measure of the feedback ratio at which the amplifier is operating. For the configuration of the A amplifier in Figure 1, the noise gain is given by the impedance ratio of the RC-CC series network, to the parallel combination of RFA and RFB. For the A amplifier to operate at its expected closed loop gain, the noise gain at any frequency must not exceed its Gain Bandwidth Product (GBW) divided by that frequency. Applying this to the expression above will yield a result for the maximum 3dB bandwidth that can be achieved for a given configuration. fGBWA • (1+AVB) • AVCS • RS • RFA (5) f3dBmax = 2πL • (RFA+RFB) 1 2 UDG-94041 The COMPA pin switches in a parallel compensation network to stabilize the small signal bandwidth with range changes. In the UC3172A, to accommodate wider power amplifier bandwidths, the fGBWA has been extended to 3.5MHz. (8) RCA = The bandwidth of the closed loop amplifier can be set by choosing the value of RC. Calculate RC according to: (6) RC = Head Parking In Figure 2, the UC3172A is shown configured to force a programmed voltage at the A amplifier output upon the activation of a park condition. A pair of feedback resistors R1 and R2 set this voltage as defined by: 2πL • f3dB • RFB (1 + AVB)AVCS • RS Use AVCS = 0.5 if range changing is to be used, and AVCS = 2.0 if only the low range mode of operation is to be used. VPARK (9) R1 = R2 − 1 1.3 R2 is typically chosen in the range of 10kΩ to 100kΩ. The compensation zero is typically set to coincide with the L/R time constant of the load. CC can then be calculated by: (7) CC = F. RC , CCA = 3CC 3 The B amplifier output is tri-stated during park, this side of the load is driven low by the PRKDRV pin. A series resistor, RP in the figure, can be inserted in series with the load to limit the peak current if required. L RC(RS + RL) The UV thresholds for the supply monitors are set by picking R4 and R6 values in the 10kΩ to 100kΩ range and then calculating R3 and R5 according to: When the range change feature of the UC3172A is used, the closed loop bandwidth of the power ampli9 UC3172A APPLICATION INFORMATION (cont.) UV1 UV2 (10) R3 = R4 − 1, and R5 = R6 − 1 1.3 1.3 able to force approximately one volt across the load with a recovered back EMF voltage of 1.3V. During system commanded parking with the supplies present, the VPARK pin is still used to set the maximum voltage to the load. The logic function of the PWROK pin is still available since the external PNP will provide isolation to this output when it is high. During park, supply to the load, and the UC3172A, is typically recovered from the back EMF of the spindle motor. When the supply voltage at the VL supply pin drops below the UVLO voltage, (2.4V high-to-low), the output of the A amplifier is forced high, over-riding the programmed park voltage. The UC3172A will maintain drive to the load down to low supply levels. For example, with 1.5 volts of recovered back EMF, the UC3172A can still deliver 50mA of drive to a 10Ω load. Base drive to the PRKDRV and PWROK pins are provided by the VL supply pin. By using a hold up capacitor, CHOLD, the drive can be maintained to the load as the back EMF drops to below 1 volt. A variation on this approach is to add a connection between the VL pin and the recovered back EMF, this will eliminate the need for the holdup capacitor and provide operation down to about 1.2V of back EMF recovery. Care with this approach should be taken in case the 5V supply hangs at just below the programmed UV threshold. In this situation large currents could flow from this supply through the external PNP and into the A output which, until the supply Parking With Very Low Back EMF The UC3172A can also be configured to get parking drive to the load with very low recovered back EMF. Figure 3 illustrates how the PWROK pin can be used to drive an external PNP device to achieve very low parking drive Vsat losses. With this configuration, the UC3172A will be UDG-94042 Figure 2. Controlled Velocity Head Parking 10 UC3172A APPLICATION INFORMATION (cont.) UDG-94043 Figure 3. Head Parking with Low Back EMF UNITRODE INTEGRATED CIRCUITS 7 CONTINENTAL BLVD. • MERRIMACK, NH 03054 TEL. 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