NEC UPC1854AGT

DATA SHEET
BIPOLAR ANALOG INTEGRATED CIRCUIT
µPC1854A
I2C BUS-COMPATIBLE US MTS PROCESSING LSI
The µPC1854A is an integrated circuit for US MTS (Multichannel Television Sound) system with the addition of
the I2C bus interface. All functions required for US MTS system are incorporated on a single chip.
The µPC1854A allows users to switch modes and adjust filter and separation circuits through the I2C bus.
FEATURES
• Stereo demodulation, SAP (Sub Audio Program) demodulation, dbx noise reduction decoding, and I2C bus
interface incorporated on a single chip
• Mode switching and filter/separation adjustments through the I2C bus
• Power supply: 8 V to 10 V
• On-chip input attenuator for simple interface with intermediate frequency processing IC (I2C bus control)
• Output level: 1.4 Vp-p (with L+R signals, 100% modulation)
APPLICATIONS
• TV sets and VCRs for north America
ORDERING INFORMATION
Part Number
Package
µPC1854ACT
28-pin plastic SDIP (10.16 mm (400))
µPC1854AGT
28-pin plastic SOP (9.53 mm (375))
The µPC1854A is available only to licensees of THAT Corporation.
For information, please call: (508) 229-2500 (U.S.A.), or (03) 5790-5391 (Tokyo).
The information in this document is subject to change without notice. Before using this document, please
confirm that this is the latest version.
Not all devices/types available in every country. Please check with local NEC representative for availability
and additional information.
Document No. S12816EJ3V0DS00 (3rd edition)
Date Published June 2000 N CP(K)
Printed in Japan
The mark
shows major revised points.
©
1997
µPC1854A
SYSTEM BLOCK DIAGRAM
Tuner
IF processing
C, Y, and deflecting
signal processing
DTS interface
Chroma output
CRT
Vertical output
µ PC1854A
L
Surround signal
processing
US MTS
processing
R
Tuning
microcontroller
SDA
SCL
Remote
controller
receive amp.
PIN photodiode
2
Data Sheet S12816EJ3V0DS00
Power amplifier
µPC1854A
BLOCK DIAGRAM
9V
VCC
22 µF
VRE
1
2
Deemphasis
0.1 µF
27
PD2
φD1
1 kΩ
4.7 µF
+
+
φD2
Mode
Selector
Stereo
VCO
1/4
5
6
+
Stereo
LPF
D/A
Input
Attenuator
NDT
NOT
WideBand
VCA
ST/SAP
SW
LPF
24
+
23
Filter
WTI
WideBand
RMS
WideBand
RMS
Filter
1 µF
VOA
10 µF
+
22
STI
3.3 µF
+
Offset
Absorption
9
10
Noise
BPF
Noise
Detector
Timing
Current
SAP
BPF
ITI
1.6 kΩ 15 kΩ
20
Spectral
RMS
Filter
Phase
Detector
Spectral
RMS
19
0.1 µF
SI
Loop
Filter
11
12
408 Hz
LPF
1 µF
D/A
2fH
Trap
SAP
Detector
21
WRB
5.1 kΩ +
Variable
Emphasis
2.19 kHz
LPF
Offset
Absorption
SAP
LPF
18
3 kΩ
dO
+
1 µF
+
17
SAP
VCO
1 µF
SRB
68 kΩ
SOT
External
dbx NR
25
10 µF
+
fH Trap
8
+
0.047 µ F
SDT
+
10 µF
D/A
0.1 µF
SOA
0.47 µF
Offset
Absorption
ST VCO
SAP VCO
Filter
Stereo
Phase
Comparator
7
ROT
ST VCO
1/2
D/A
2.2 µF
COM
26
+
Pilot
Canceller
4
1 µF
LOT
+
Matrix
Pilot
Discrimination
Phase
Comparator
1 µF
10 µF
L+R
LPF
L–R
AM
Demodulator
3
MOA
+
1/2 VCC
+
PD1
28
Offset
Absorption
DGND
D/A
ESA
13
1/2
AGND
SAP VCO
16
Filter
Adjuster
D/A
14
I2C Bus
Interface
15
SCL
SDA
Remark Use the following for external parts.
Resistor : Metal film resistor (±1 %) for an ITI pin (pin 21). Unless otherwise specified; ±5 %
Capacitor : Tantalum capacitor (±10 %) for STI and WTI pins (pins 22 and 23). Unless otherwise
specified; ±20 %
Data Sheet S12816EJ3V0DS00
3
µPC1854A
PIN CONFIGURATION (Top View)
28-pin plastic SDIP (10.16 mm (400))
• µPC1854ACT
28-pin plastic SOP (9.53 mm (375))
• µPC1854AGT
4
Power (9 V)
1
VCC
MOA
28
Monaural Offset Absorption
1/2 VCC Filter
2
VRE
LOT
27
L-channel Output
Pilot Discrimination Filter 1
3
PD1
ROT
26
R-channel Output
Pilot Discrimination Filter 2
4
PD2
NOT
25
Normal Output
Phase Comparator Filter 1
5
φD1
VOA
24
VCA Offset Absorption
Phase Comparator Filter 2
6
φD2
WTI
23
Wide-Band RMS Timing
Composite Signal Input
7
COM
STI
22
Spectral RMS Timing
SAP Offset Absorption
8
SOA
ITI
21
Timing Current Setting
SAP Discrimination Filter
9
SDT
WRB
20
Wide-Band RMS Offset Absorption
Noise Detection Filter
10
NDT
SRB
19
Spectral RMS Offset Absorption
SAP Single Output
11
SOT
dO
18
Variable Emphasis Offset Absorption
SAP Single Input
12
SI
DGND
17
Digital GND (for I2C bus)
External SAP Input
13
ESA
SCL
16
SCL (for I2C bus)
Analog GND
14
AGND
SDA
15
SDA (for I2C bus)
Data Sheet S12816EJ3V0DS00
µPC1854A
CONTENTS
1.
PIN EQUIVALENT CIRCUITS .............................................................................................................................. 6
2.
BLOCK FUNCTIONS .......................................................................................................................................... 13
3.
4.
5.
6.
2.1
Stereo Demodulation Block ..................................................................................................................... 14
2.2
SAP Demodulation Block ........................................................................................................................ 15
2.3
dbx Noise Reduction Block ..................................................................................................................... 16
2.4
Matrix Block .............................................................................................................................................. 17
I2C BUS INTERFACE ......................................................................................................................................... 18
3.1
Data Transfer ........................................................................................................................................... 19
3.2
Data Transfer Format .............................................................................................................................. 20
I2C BUS COMMANDS ........................................................................................................................................ 22
4.1
Subaddress List ....................................................................................................................................... 22
4.2
Setting Procedure .................................................................................................................................... 23
4.3
Explanation of Write Register .................................................................................................................. 25
4.4
Explanation of Read Register ................................................................................................................. 28
MODE MATRIX ................................................................................................................................................... 30
5.1
L-, R-Channel Output (LOT, ROT pins) Matrix ....................................................................................... 30
5.2
Normal Output (NOT pin) Matrix ............................................................................................................. 31
USAGE CAUTIONS ............................................................................................................................................ 32
6.1
Caution on Shock Noise Reduction ........................................................................................................ 32
6.2
Supply Voltage ......................................................................................................................................... 32
6.3
Impedance of Input and Output Pins ...................................................................................................... 32
6.4
Drive Capability of Output Pins ............................................................................................................... 32
6.5
Caution on External Components ........................................................................................................... 33
6.6
Change of Electrical Characteristics by External Components ............................................................. 33
7.
ELECTRICAL SPECIFICATIONS ...................................................................................................................... 34
8.
MEASURING CIRCUIT ....................................................................................................................................... 44
9.
PACKAGE DRAWINGS ..................................................................................................................................... 45
10. RECOMMENDED SOLDERING CONDITIONS ................................................................................................ 47
Data Sheet S12816EJ3V0DS00
5
µPC1854A
1. PIN EQUIVALENT CIRCUITS
(1/7)
Pin No.
Pin Name
Symbol
1
Power (9 V)
VCC
2
1/2 VCC Filter
VRE
Internal Equivalent Circuit
VCC
10 kΩ
10 kΩ
5 kΩ
20 kΩ
20 kΩ
20 kΩ
10 kΩ
2
10 kΩ
20 kΩ
5 kΩ
GND
3
Pilot Discrimination Filter 1
PD1
VCC
3
15 kΩ
4
Pilot Discrimination Filter 2
15 kΩ
5 kΩ
1
V CC
2
PD2
VCC
4
6
Data Sheet S12816EJ3V0DS00
15 kΩ
15 kΩ
5 kΩ
µPC1854A
(2/7)
Pin No.
5
Pin Name
Phase Comparator Filter 1
Symbol
Internal Equivalent Circuit
φD1
VCC
5
15 kΩ
6
Phase Comparator Filter 2
5 kΩ
5 kΩ
1
V CC
2
φD2
VCC
15 kΩ
6
7
Composite Signal Input
5 kΩ
5 kΩ
COM
VCC
1
V CC
2
80 kΩ
7
3 kΩ
17 kΩ
5 kΩ
5 kΩ
GND
8
SAP Offset Absorption
SOA
VCC
10 kΩ
10 kΩ
5 pF
50 kΩ
3 kΩ
2.3 kΩ
10 kΩ
GND
8
Data Sheet S12816EJ3V0DS00
7
µPC1854A
(3/7)
Pin No.
9
Pin Name
SAP Discrimination Filter
Symbol
Internal Equivalent Circuit
SDT
9
VCC
20 kΩ
10 kΩ
20 kΩ
20 kΩ
10 kΩ
GND
10
Noise Detection Filter
NDT
10
VCC
20 kΩ
20 kΩ
20 kΩ
20 kΩ
20 kΩ
20 kΩ
20 kΩ
GND
8
Data Sheet S12816EJ3V0DS00
µPC1854A
(4/7)
Pin No.
11
Pin Name
SAP Single Output
Symbol
Internal Equivalent Circuit
SOT
VCC
2 kΩ
200 Ω
11
2 kΩ
GND
12
SAP Single Input
SI
1
V CC
2
VCC
10 kΩ
80 kΩ
5 kΩ
10 kΩ
5 pF
12
5 kΩ
GND
13
External SAP Input
ESA
1
V CC
2
VCC
10 kΩ
10 kΩ
80 kΩ
5 pF
3 kΩ
13
10 kΩ
GND
Data Sheet S12816EJ3V0DS00
9
µPC1854A
(5/7)
Pin No.
Pin Name
14
Analog GND
15
SDA (for I2C bus)
Symbol
Internal Equivalent Circuit
AGND
SDA
Note
VCC
10 kΩ
10 kΩ
10 kΩ
50 kΩ 5 kΩ
15
30 kΩ
30 kΩ
GND
16
SCL (for I2C bus)
SCL
Note
VCC
10 kΩ
10 kΩ
10 kΩ
5 kΩ
16
30 kΩ
30 kΩ
GND
17
Digital GND (for I2C bus)
18
Variable Emphasis
Offset Absorption
19
Spectral RMS Offset Absorption
DGND
dO
Same as Pin 8
SRB
5 kΩ
VCC
5 kΩ
5 kΩ
3 kΩ
3 kΩ
19
3 kΩ
5 kΩ
GND
Note No protection diode is provided on the VCC side so that the I2C bus line is not pulled to 0 V when the power
is OFF (VCC = 0 V).
10
Data Sheet S12816EJ3V0DS00
µPC1854A
(6/7)
Pin No.
Pin Name
20
Wide-Band RMS Offset Absorption
21
Timing Current Setting
Symbol
WRB
Internal Equivalent Circuit
Same as pin 19
ITI
VCC
10 kΩ
10 kΩ
5 kΩ
20 pF
10 kΩ
10 kΩ
10
kΩ
10
kΩ
21
30 kΩ
GND
22
Spectral RMS Timing
STI
VCC
5 kΩ
600 Ω
5 kΩ
5 kΩ
5 kΩ
22
5 kΩ
GND
23
Wide-Band RMS Timing
WTI
Same as pin 22
24
VCA Offset Absorption
VOA
Same as pin 8
Data Sheet S12816EJ3V0DS00
11
µPC1854A
(7/7)
Pin No.
25
Pin Name
Normal Output
Symbol
Internal Equivalent Circuit
NOT
VCC
1 kΩ
10 kΩ
200 Ω
25
200 Ω
5 kΩ
1 kΩ
5 kΩ
GND
12
26
R-channel Output
ROT
27
L-channel Output
LOT
28
Monaural Offset Absorption
MOA
Same as pin 25
Same as pin 8
Data Sheet S12816EJ3V0DS00
µPC1854A
2. BLOCK FUNCTIONS
In the US, TV audio signals are broadcast in FM modulation. The stereo (L–R), Sub Audio Program (SAP) and
telemetry signals are multiplexed in a higher frequency band than the monaural (L+R) signal (50 Hz to 15 kHz).
The US MTS system base-band spectrum is described before:
Figure 2-1. US MTS System Base-Band Spectrum
Stereo signal (L–R)
Audio carrier deviation (kHz)
50
Stereo pilot
signal
Monaural
signal (L+R)
25
Sub Audio Program (SAP) signal
15
Telemetry
signal
5
3
0
fH
(15.734 kHz)
3 fH
2 fH
4 fH
5 fH
6 fH
6.5 fH
Modulation frequency (Hz)
Table 2-1. US MTS System Base-Band Spectrum
Signal frequency band
Monaural signal (L+R)
Stereo pilot signal
Signal processing system
50 Hz to 15 kHz
15.734 kHz
Maximum audio
carrier deviation (kHz)
25
Only stereo broadcasting
5
Stereo signal (L–R)
50 Hz to 15 kHz
AM modulation (carrier frequency 2 fH),
dbx noise reduction processing
50
Sub Audio Program (SAP)
signal
50 Hz to 10 kHz
FM modulation (carrier frequency 5 fH),
maximum frequency deviation 10 kHz)
dbx noise reduction processing
15
Audio
0 to 3.4 kHz
3
Data
0 to 1.5 kHz
FM modulation (carrier frequency 6.5 fH
maximum frequency deviation 3 kHz)
Telemetry signal
Data Sheet S12816EJ3V0DS00
13
µPC1854A
2.1 Stereo Demodulation Block
(1) Stereo LPF
This filter eliminates signals in the vicinity of 5 fH to 6 fH, such as SAP (Sub Audio Program) (5 fH) and telemetry
signals (6.5 fH) . The µPC1854A’s internal L–R demodulator, which uses a double-balanced circuit, demodulates L–R signals by multiplication of the L–R signal with the signal at the L–R carrier frequency (2 fH). The L–
R signal tends to receive interference from the 6 fH signal because a square waveform is used as the switching
carrier in this method. To eliminate this interference, the µPC1854A incorporates traps at 5 fH and 6 fH. The
filter response is adjusted by setting the Filter setting bits (write register, subaddress 02H, bits D0 to D5).
(2) Stereo phase comparator
The 8 fH signal generated at the stereo VCO is divided by 8 (4 × 2) and then multiplied by the pilot signal
passed through the stereo LPF. The two signals differ from each other by 90 degrees in terms of phase.
The resistor and capacitor connected to Pins φD1 and φD2 form a filter that smooths the phase error signal
output from the stereo phase comparator, converting the error signal to the DC voltage. When the voltage
difference between pins φD1 and φD2 becomes 0 V (strictly speaking, not 0 V by the internal offset voltage),
the VCO runs at 8 fH.
The lag/lead filter externally connected to the pins φD1 and φD2 determines the capture range.
(3) Stereo VCO
The VCO runs at 8 fH with the internal capacitor. The frequency is adjusted by setting the Stereo VCO setting
bits (write register, subaddress 01H, bits D0 to D5).
(4) Divider (Flip-flop)
Produces two separate fH signals: the inphase fH signal, and the fH signal differing by 90 degrees from the input
pilot signal by dividing the 8 fH frequency from the stereo VCO by 8 (4 × 2).
(5) Pilot discrimination phase comparator (Level detector)
Multiplies the pilot signal from the COM pin with the inphase fH signal from the divider. The resulting signal is
smoothed by passing it through the external filter connected to the PD1 and PD2 pins and converted into DC
voltage value that is used to determine whether or not a stereo pilot signal (read register, bit D6) is present.
(6) Pilot canceler
The fH signal from the divider is added to the stereo signal in resistor matrix depending on the level of the input
pilot signal to cancel the pilot signal.
(7) L+R LPF
This LPF which has traps at fH and 24 kHz, allows only the monaural signal to pass through. The filter response is adjusted by setting the Filter setting bits (write register, subaddress 02H, bits D0 to D5).
(8) De-emphasis
The filter is a 75-µs de-emphasis filter for the monaural signal. The response is adjusted by setting the Filter
setting bits (write register, subaddress 02H, bits D0 to D5).
(9) L–R AM demodulator
Demodulates the L–R AM-DSB modulated signal by multiplying with the 2fH signal which is synchronized to the
pilot signal. The 2-fH square wave is used as the switching carrier.
14
Data Sheet S12816EJ3V0DS00
µPC1854A
2.2 SAP Demodulation Block
(1) SAP BPF
Picks up the SAP signal by the 50-kHz and 102-kHz traps and a response peak at 5 fH. The filter response is
adjusted by setting the Filter setting bits (write register, subaddress 02H, bits D0 to D5).
(2) Noise BPF
The µPC1854A monitors signals picked up by the noise band-pass filter (fO ≅ 180 kHz), and distinguishes noise
from signals. By this method, the µPC1854A prevents faulty SAP detection in a weak electric field. The filter
response is adjusted by setting the Filter setting bits (write register, subaddress 02H, bits D0 to D5).
(3) Noise detector
Performs full-wave rectification of noise from noise band-pass filter, changes it to the DC voltage, and inputs it
to the comparator. When the noise level exceeds the reference level, the detector recognizes noise, and the
noise detection bit (read register, bit D4) is set “1”.
The sensitivity and time constant of the circuit are adjusted by setting the values of the resistor and capacitor
connected to the NDT.
(4) SAP detector
Detects the signal from the SAP band-pass filter and smooths it through the SDT pin and inputs it to the
comparator. When the SAP signal is detected, the SAP signal bit (read register, bit D5) is set “1”.
(5) SAP demodulation circuit
The SAP demodulator consists of a phase detector, a loop filter and an SAP VCO (PLL detection circuit).
The SAP VCO oscillates at 10 fH, and performs phase comparison between the signal divided by 2 of the VCO
frequency and the SAP signal to make the PLL. The SAP VCO oscillating frequency is adjusted by setting the
SAP VCO setting bits (write register, subaddress 05H, bits D0 to D5).
(6) SAP LPF
Eliminates the SAP carrier and high-frequency buzz. The filter consists of a 2nd-order low-pass filter and fH
trap filter. The filter response is adjusted by setting the Filter setting bits (write register, subaddress 02H, bits
D0 to D5).
Data Sheet S12816EJ3V0DS00
15
µPC1854A
2.3 dbx Noise Reduction Block
All the filters required for TV-dbx noise reduction are incorporated. The response to these filters is adjusted by
setting all the Filter setting bits (write register, subaddress 02H, bits D0 to D5).
(1) LPF
This LPF has traps at fH and 24 kHz each. The fH trap filter minimizes interference by the fH signal which is not
synchronized with the pilot signal (for example, leakage of the synchronous idle and buzz from the video
signal).
(2) 408-Hz LPF
This filter is a de-emphasis filter. Its transfer function is as follows:
1+j
T(f) =
f
5.23k
f
1+j
408
(3) Variable emphasis
Also called the spectral VCA. It is controlled by the spectral RMS. The transfer function is as follows:
1+j
S–1 (f, b) =
1+j
f
20.1k
f
20.1k
×
1 + 51b
×
1 + 51
b+1
b+1
where “b” is the variable transferred from the spectral RMS for controlling.
(4) Wide-band VCA
A VCA whose operating frequency range is mainly low to mid frequencies and controlled by the wide-band
RMS. The transfer function is as follows:
W–1 (a) = a
where “a” is the variable transferred from the wide-band RMS for controlling.
(5) 2.19-kHz LPF
This filter is a de-emphasis filter. Its transfer function is as follows:
1+j
T(f) =
1+j
16
f
62.5k
f
2.19k
Data Sheet S12816EJ3V0DS00
µPC1854A
(6) Spectral RMS filter
A filter that limits the band width of the signal input to the RMS which controls the variable emphasis. The
transfer function is as follows:
(j
T (f) =
f
7.66k
f
1+j
7.31k
)2
+ (j
j
f
7.66k
×
)2
f
3.92k
1+j
f
3.92k
(7) Wide-band RMS filter
A filter that limits the band width of the signal input to the wide-band RMS which controls the wide-band VCA.
The transfer function is as follows:
1
T(f) =
1+j
f
2.09k
(8) Spectral RMS
Detects the RMS value of the signal passed through the spectral RMS filter, and converts the signal to the DC
voltage. The release time is set by adjusting the current IT of the µPC1854A and the capacitance of the
external capacitor connected to the STI pin. The current IT is set by the current value output from the ITI pin.
(9) Wide-band RMS
Detects the RMS value of the signal passed through the wide-band RMS filter, and converts the signal to the
DC voltage. The release time is set by adjusting the current IT of the µPC1854A and the capacitance of the
external capacitor connected to the WTI pin. The current IT is set by the current value output from the ITI pin.
2.4 Matrix Block
(1) Matrix
Adds L+R signal and L–R signal to output L signal, and subtracts L+R signal from L–R signal to output R
signal.
(2) Mode selector
Selects the user-selected mode among the monaural, stereo, SAP, external SAP input signals, and mute, then
outputs it from the NOT, ROT and LOT pins.
Data Sheet S12816EJ3V0DS00
17
µPC1854A
3. I2C BUS INTERFACE
The µPC1854A uses the I2C bus interface that is developed by Philips. The serial clock line (SCL) and serial
data line (SDA) employ the 2-wire configuration as shown in Figure 3-1.
The µPC1854A contains seven (1 byte 8 bits) write registers and one read register through the I2C bus interface
circuit.
Serial Clock Line (SCL)
The master CPU outputs a serial clock to achieve data synchronization. The µPC1854A receives serial data
based on this clock. The input level is CMOS-compatible. The clock frequency is from 0 to 100 kHz.
Serial Data Line (SDA)
The master CPU outputs data synchronously with the serial clock. The µPC1854A receives this data based on
the serial clock. The input level is CMOS-compatible.
Figure 3-1. Internal Equivalent Circuit of Interface Pins
RP
RP
SCL
SDA
µ PC1854A
No protection diode is provided on the VCC side for the SCL and SDA pins so that the I2C bus line is not pulled
to 0 V when the power is OFF (VCC = 0 V).
18
Data Sheet S12816EJ3V0DS00
µPC1854A
3.1 Data Transfer
(1) Start condition
The start condition is created when SDA changes from high to low while SCL is high, as shown in Figure 3-2.
When the µPC1854A receives this information, it captures data sent in synchronization with the clock.
(2) Stop condition
The stop condition is created when SDA changes from low to high while SCL is high, as shown in Figure 3-2.
When the µPC1854A receives this information, it stops receiving or outputting data.
Figure 3-2. Data Transfer Start/Stop Condition
3.5 V
SDA
1.5 V
4.0 µ s
MIN.
4.7 µs
MIN.
3.5 V
SCL
1.5 V
Stop
Start
(3) Data transfer
When transferring data, be sure to switch data only when SCL is low, as shown in Figure 3-3. When SCL is
high, the data must not be changed.
Figure 3-3. Data Transfer
SDA
Note 1
Note 2
SCL
Note 3
Note 4
Notes 1. Data hold time: 300 ns MIN.
2. Data setup time: 250 ns MIN.
3. Interval when data cannot be changed
4. Interval when data can be changed
Data Sheet S12816EJ3V0DS00
19
µPC1854A
3.2 Data Transfer Format
An example of data transfer in the write mode is shown in Figure 3-4.
Figure 3-4. Data Transfer Example in Write Mode
SDA
D6 D5 D4 D3 D2 D1 D0
SCL
1
Start
2
3
4
5
6
Slave address
7
Write
mode
8
9
D7 D6 D5 D4 D3 D2 D1 D0
1
Read/
Write Acknowledge
2
3
4
5
6
7
D7 D6 D5 D4 D3 D2 D1 D0
8
9
1
2
3
Acknowledge
Subaddress
4
5
6
data
7
8
9
Acknow- Stop
ledge
Data consists of 8-bit units. This 8-bit data must always be followed by an acknowledge bit. Data transfer must
be done on an MSB-first basis.
The first byte after a start condition specifies the slave address. The slave address consists of 7 bits.
Table 3-1 shows the slave addresses of the µPC1854A. These slave addresses are registered by Philips.
Table 3-1. Slave Addresses of µPC1854A
Slave address
D6
D5
D4
D3
D2
D1
D0
Read/Write
Write
1
0
0
0
1
1
1
0
Read
1
0
0
0
1
1
1
1
Mode
The bit following the slave address is the read/write bit specifying the direction of the data to be transferred.
During the read operation, data is transferred from the µPC1854A to the master CPU. During the write operation, data is transferred from the master CPU to the µPC1854A. “0” and “1” are written to the Read/Write bit during
the Write and Read modes, respectively.
The byte following the slave address is the subaddress of the µPC1854A in the write mode.
The µPC1854A has seven subaddresses, SA0 to SA6, which are made up of 8 bits. Following the subaddress
byte is the data to be set to the subaddress.
20
Data Sheet S12816EJ3V0DS00
µPC1854A
(1) 1-byte data transfer
The format for 1-byte data transfer is the following:
Start
Slave
address
Write Acknow
Acknow
Subaddress
mode -ledge
-ledge
Data
Acknow Stop
-ledge
(2) Continuous data transfer
The format when transferring multiple (7) bytes of data at one time is the following:
Start
Slave
address
Write Acknow
Acknow
Subaddress
mode -ledge
-ledge
Data1
Acknow
-ledge
Data2
Acknow
-ledge
Data7
Acknow
Stop
-ledge
The master CPU transfers “00H” as subaddress SA0 following the start condition and slave address. After the
subaddress SA0, the master CPU transfers the SA0 data, and continues with SA1, SA2, ..., SA6 data without
transferring stop conditions in between.
The subaddress is automatically incremented. Finally, the stop condition is transferred and the transfer is
completed.
(3) Data read
The µPC1854A has one read register. The contents of this register can be read by the master CPU.
The format when data is read is the following:
Start
Slave
address
Read
Acknow
-ledge
Data
Nonacknow Stop
-ledge
(4) Acknowledge
In the case of the I2C bus, an acknowledge bit is added to the data as the 9th bit to determine whether data
transfer was successful. The master determines the success or failure of data transfer based on whether this
acknowledge bit is a logical low or high.
If the acknowledge interval is a logical low, this indicates that data transfer was successful. If it is a logical
high, this indicates that data transfer was unsuccessful or that the slave side forcibly released the bus as a
non-acknowledge state.
Data Sheet S12816EJ3V0DS00
21
µPC1854A
4. I2C BUS COMMANDS
4.1 Subaddress List
(1) Write register (command list)
Subaddress
MSB
D7
00H
0
During noise
detection
Stereo/SAP
output stop
0: SAP OFF
1: Stereo,
SAP OFF
01H
0
fH monitor
ON/OFF
0: OFF
D6
D5
D4
D3
D2
D1
LSB
D0
Input level setting
Stereo VCO setting
1: ON
02H
0
Pilot canceler
ON/OFF
0: ON
1: OFF
Filter setting
03H
0
0
Low-band separation setting
04H
0
0
High-band separation setting
05H
0
06H
0
5 fH monitor
ON/OFF
0: OFF
1: ON
0
SAP VCO setting
Normal track
Normal track
SAP1/SAP2
output select 1 output select 2 switchNote
0: SAP
0: SAP
0: SAP1
1: External SAP 1: Monaural
1: SAP2
Stereo/SAP
switch
0: Stereo
1: SAP
Forced monaural Mute ON/OFF
ON/OFF
0: OFF
0: ON
1: ON
1: OFF
Note Output when SAP1 or SAP2 is selected is as follows:
LOT pin (L-channel output)
SAP1
ROT pin (R-channel output)
SAP
SAP2
Monaural (L+R)
SAP
Remark The initial value of write register after power-on reset
• Mute register (subaddress 06H, bit D0) = 0 (Mute: ON)
• Other registers = undefined (setting properly after power-on reset)
(2) Read register
MSB
D7
D6
D5
D4
D3
D2
Power-on reset
Broadcast status
Noise detection
Reception status
1: Detection
0: Not available Stereo broadcast SAP broadcast
Stereo pilot
SAP signal
0: Not available 0: Not available 1: Available
reception
reception
1: Available
1: Available
0: Not available 0: Not available
1: Available
1: Available
22
Data Sheet S12816EJ3V0DS00
D1
LSB
D0
1
1
µPC1854A
4.2 Setting Procedure
Precise adjustment of the dbx decoder is absolutely critical for optimum performance. Where possible, the
adjustment should be performed after the µPC1854A is mounted on the chassis and with the video system active.
Set the data of write register as follows before the adjustment, because the registers other than the Mute register
are defined.
Table 4-1. Default Setting of Write Register
Bit
D7
D6
D5
D4
D3
D2
D1
D0
0
0
1
0
0
0
0
0
01H
0
0
1
0
0
0
0
0
02H
0
0
1
1
1
1
1
1
03H
0
0
1
0
0
0
0
0
04H
0
0
1
0
0
0
0
0
05H
0
0
1
0
0
0
0
0
06H
0
0
0
0
0
0
0
1
Subaddress
00H
(1) Input level setting (write register, subaddress 00H, bits D5 to D0)
<1> Write “1” to bit D0 (Mute: OFF) of subaddress 06H.
<2> Input sine wave of 300 Hz, 150 mVrms to COM pin.
<3> Set bits D5 to D0 (Input level setting bits) of subaddress 00H so that the output level of ROT pin is 500
mVrms (±10 mVrms).
(2) Stereo VCO setting (write register, subaddress 01H, bits D6 to D0)
Perform this adjustment with no signal applied.
<1> Write “1” to bit D0 (Mute: OFF) of subaddress 06H.
<2> Write “1” to bit D6 (fH monitor: ON) of subaddress 01H.
<3> Connect frequency counter to ROT pin, and set bits D5 to D0 (Stereo VCO setting bits) of subaddress
01H so that frequency counter displays 15.73 kHz (±0.1 kHz).
<4> When setting is completed, write “0” to bit D6 (fH monitor: OFF) of subaddress 01H.
(3) Filter setting (write register, subaddress 02H, bits D6 to D0)
<1> Write “1” to bit D6 (Pilot canceler: OFF) of subaddress 02H.
<2> Input pilot signal (15.734 kHz, 30 mVrms or higherNote) to COM pin and set data of bits D5 to D0 (Filter
setting bits) of subaddress 02H so that the output level of the ROT pin becomes as small as possible
(Decrease the set data from 63 (decimal)).
<3> When setting is completed, write “0” to bit D6 (Pilot canceler: ON) of subaddress 02H.
Note 100 mVrms is recommended.
Data Sheet S12816EJ3V0DS00
23
µPC1854A
(4) Separation setting (write register, subaddresses 03H and 04H, bits D5 to D0)
<1> Write “1” to bit D0 (Mute: OFF) of subaddress 06H.
<2> Write “20H” to bits D5 to D0 (High-band separation setting bits) of subaddress 04H.
<3> Input composite signal to COM pin (300 Hz, 30% modulation, L-only, with noise reduction), and set bits
D5 to D0 (Low-band separation setting bits) of subaddress 03H so that the output level of the ROT pin is
as small as possible.
<4> Change the modulation frequency of the composite signal to 3 kHz, and set bits D5 to D0 of subaddress
04H so that the output level of the ROT pin is as small as possible.
<5> While bits D5 to D0 of subaddress 04H are set as in step <4> above, repeat the setting procedure of step
<3> for bits D5 to D0 of subaddress 03H.
(5) SAP VCO setting (write register, subaddress 05H, bits D6 to D0)
Perform this adjustment with no signal applied.
<1> Add a 1 MΩ resistor between the SOA pin and GND.
<2> Write “1” to bit D0 (Mute: OFF) of subaddress 06H.
<3> Write “1” to bit D6 (5 fH monitor: ON) of subaddress 05H.
<4> Connect a frequency counter to the ROT pin, and set bits D5 to D0 of subaddress 05H (SAP VCO setting
bits) so that 78.67 kHz (±0.5 kHz) is displayed on the frequency counter.
<5> When setting is completed, write “0” to bit D6 (5 fH monitor: OFF) of subaddress 05H.
<6> Delete the 1 MΩ resistor between the SOA pin and GND.
24
Data Sheet S12816EJ3V0DS00
µPC1854A
4.3 Explanation of Write Register
(1) Stereo/SAP output stop function during noise detection
Stereo/SAP output stop can be selected with the data of bit D6 of subaddress 00H during weak electrical field
conditions (noise level during recommended circuit use is 30 mVrms (TYP.) or more).
SAP output stop
: Only SAP output is stopped.
SAP and stereo output stop : SAP and stereo outputs are stopped, switch to monaural output.
Noise level detection is performed, when detected a noise about 11.5 fH (180 kHz), a frequency that is sufficiently apart from that of the high frequency signals such as the stereo, SAP, and telemetry signal. If noise is
detected, “1” is set to bit D4 of the read register (Refer to section 4.4 (4) Noise detection).
Figure 4-1. Stereo/SAP Output Stop Function during Noise Detection
D7
D6
0
During noise
detection
00H
D5
D4
D3
D2
D1
D0
Input level setting
Stereo/SAP output stop function during noise detection
0
SAP output stop
1
SAP and stereo output stop
(2) Mute
The mute function can be set ON/OFF with the data of bit D0 of subaddress 06H.
The mute on state is entered when bit D0 is set to 0 after power-on reset.
Figure 4-2. Mute
06H
D7
D6
D5
D4
D3
D2
D1
D0
0
0
Normal track
output select 1
Normal track
output select 2
SAP1/SAP2
switch
Stereo/SAP
switch
Forced monaural
ON/OFF
Mute
ON/OFF
Mute
0 Mute ON
1
Caution
Mute OFF
When switching the power ON/OFF, use the mute function (200 ms) outside the µPC1854A
in order to minimize shock noise.
Data Sheet S12816EJ3V0DS00
25
µPC1854A
(3) Mode switch (L-, R-channel output (LOT, ROT pins))
The signal to be output can be selected from the L- and R-channel outputs (LOT, ROT pins) with bits D3 to D1
of subaddress 06H. For the combinations of bit and output signal, refer to section 5.1 L-, R-Channel Output
(LOT, ROT pins) Matrix.
Forced monaural ON/OFF : When set to ON, a monaural signal is forcibly output regardless of the selection
of other bits.
Stereo/SAP switch
: When forced monaural is set to OFF, performs selection of stereo or SAP.
SAP1/SAP2 switch
: When SAP output is selected with the stereo/SAP switch, performs selection of
SAP1 or SAP2.
L-Channel Output (LOT pin)
SAP1
SAP2
R-Channel Output (ROT pin)
SAP output
Monaural (L+R) output
SAP output
Figure 4-3. Mode Switch (L-, R-Channel Output (LOT, ROT pins))
06H
D7
D6
D5
D4
D3
D2
0
0
Normal track
output select 1
Normal track
output select 2
SAP1/SAP2
switch
Stereo/SAP
switch
D1
D0
Forced monaural Mute ON/OFF
ON/OFF
Forced monaural
0 Forced monaural OFF
1
Forced monaural ON
Stereo/SAP switch
0
Stereo output
1
SAP output
SAP1/SAP2 switch
26
Data Sheet S12816EJ3V0DS00
0
SAP1 output
1
SAP2 output
µPC1854A
(4) Mode switch (normal signal output (NOT pin))
The signal output from the normal signal output (NOT pin) can be selected with bits D5 to D1 of subaddress
06H. For the combinations of bit and output signal, refer to section 5.2 Normal Output (NOT pin) Matrix.
Normal track output select 2 : Selects SAP or monaural signal.
Normal track output select 1 : Selects SAP signal or external SAP signal.
Forced monaural ON/OFF
: When ON is selected, monaural signal is forcibly output regardless of ste-
Stereo/SAP switch
: Selects SAP or stereo signal when other switches are selected as follows;
reo/SAP switch selection.
Normal track output select 1: SAP
Normal track output select 2: SAP
Forced monaural: OFF
Figure 4-4. Mode Switch (Normal Signal Output (NOT Pin))
06H
D7
D6
D5
D4
D3
D2
0
0
Normal track
output select 1
Normal track
output select 2
SAP1/SAP2
switch
Stereo/SAP
switch
D1
D0
Forced monaural Mute ON/OFF
ON/OFF
Forced monaural
0 Forced monaural OFF
1
Forced monaural ON
Stereo/SAP switch
0
Stereo output
1
SAP output
Normal track output select 2
0
SAP output
1
Monaural output
Normal track output select 1
Data Sheet S12816EJ3V0DS00
0
SAP output
1
External SAP output
27
µPC1854A
4.4 Explanation of Read Register
(1) Power-on reset detection
Whether a power-on reset was detected is detected with bit D7 of the read register.
Figure 4-5. Power-On Reset Detection
D7
D6
D5
D4
D3
reset
Stereo
pilot
SAP
signal
D1
D0
1
1
Reception status
Broadcast status
Power-on
D2
Noise
detection
Stereo
broadcast
reception
SAP
broadcast
reception
Power-on reset detection
1
Power-on reset detection
(2) Stereo, SAP broadcast (broadcast status) detection
Whether SAP or stereo broadcast from a broadcasting station is being broadcast is detected with bits D5 and
D6 of the read register.
When a SAP signal (5 fH) or stereo pilot signal is detected, the register data becomes “1”.
Figure 4-6. Stereo, SAP Broadcast (Broadcast Status) Detection
D7
D6
D5
D4
D3
reset
Stereo
pilot
SAP
signal
D1
D0
1
1
Reception status
Broadcast status
Power-on
D2
Noise
detection
Stereo
broadcast
reception
SAP
broadcast
reception
SAP signal
0
No SAP broadcast
1
SAP broadcast (SAP signal detected)
Stereo pilot
28
0
No Stereo broadcast
1
Stereo broadcast (stereo pilot signal detected)
Data Sheet S12816EJ3V0DS00
µPC1854A
(3) Stereo, SAP broadcast reception (reception status) detection
Whether SAP or stereo broadcast is being received and the µPC1854A outputs the audio signal can be detected with bits D2 and D3 of the read register. The register data become “1” only if the SAP signal (5 fH) is
detected when the SAP broadcast reception is selected, or if the stereo pilot signal is detected when the stereo
broadcast reception is selected.
Figure 4-7. Stereo, SAP Broadcast Reception (Reception Status) Detection
D7
D6
D5
D4
reset
Stereo
pilot
SAP
signal
D2
D1
D0
1
1
Reception status
Broadcast status
Power-on
D3
Noise
detection
Stereo
broadcast
reception
SAP
broadcast
reception
SAP broadcast reception
0
No outputting SAP broadcast
1
Outputting SAP broadcast
Stereo broadcast reception
0
No outputting stereo broadcast
1
Outputting stereo broadcast
(4) Noise detection
Noise can be detected with bit D4 of the read register. It is monitored in the vicinity of the 11.5 fH (180 kHz)
signal level and noise is detected.
During noise detection, the operation of the SAP demodulator block and the stereo demodulation block is
interrupted (Refer to section 4.3 (1) Stereo/SAP output stop function during noise detection).
Figure 4-8. Noise Detection
D7
D6
D5
D4
reset
Stereo
pilot
SAP
signal
D2
D1
D0
1
1
Reception status
Broadcast status
Power-on
D3
Noise
detection
Stereo
broadcast
reception
SAP
broadcast
reception
Noise detection
0
No noise
1
Noise
Data Sheet S12816EJ3V0DS00
29
µPC1854A
5. MODE MATRIX
5.1 L-, R-Channel Output (LOT, ROT pins) Matrix
Mute OFF (Write register, subaddress 06H, bit D0 : “1”)
(1) Read register, bit D4: 0
Broadcast
mode
Write Register
Output
Forced Stereo/SAP SAP1/SAP2
monaural
switch
switch
ON/OFF
Stereo/SAP
output stop
Subaddress 06H
Subaddress 00H
Bit D1
Bit D2
Bit D3
Bit D6
Monaural
—
—
—
—
Stereo
0
—
—
—
Monaural
+ SAP
0
0
—
—
1
0
L-ch
output
(LOT)
L+R
L
R
1
1
—
—
0
0
—
1
0
—
—
Reception status
Stereo
pilot
SAP
signal
Stereo
SAP
broadcast broadcast
reception reception
Bit D6
Bit D5
Bit D3
Bit D2
0
0
0
0
1
0
1
0
0
1
0
0
L+R
SAP
L+R
0
1
SAP
L+R
—
0
L
R
1
1
SAP
1
1
Broadcast status
L+R
1
Stereo + SAP
Read Register
R-ch
output
(ROT)
L+R
1
0
0
1
SAP
L+R
0
(2) Read register, bit D4: 1
Broadcast
mode
Write Register
Output
Forced Stereo/SAP SAP1/SAP2
monaural
switch
switch
ON/OFF
Stereo/SAP
output stop
Subaddress 06H
Subaddress 00H
Bit D1
Bit D2
Bit D3
Bit D6
Monaural
—
—
—
—
Stereo
0
—
—
0
Monaural
+ SAP
0
1
0
L-ch
output
(LOT)
Read Register
R-ch
output
(ROT)
L+R
L
R
Broadcast status
Reception status
Stereo
pilot
SAP
signal
Stereo
SAP
broadcast broadcast
reception reception
Bit D6
Bit D5
Bit D3
Bit D2
0
0
0
0
1
0
1
0
1
L+R
0
0
0
L+R
0
0
0
0
1
0
1
0
1
1
0
1
Stereo + SAP
0
0
—
0
1
0
0
1
L
R
L+R
0
0
1
1
0
1
Remarks 1. When the µPC1854A recognizes a weak electric field, bit D4 of the read register becomes “1”.
2. — : Don’t care.
30
Data Sheet S12816EJ3V0DS00
µPC1854A
5.2 Normal Output (NOT pin) Matrix
Mute OFF (Write register, subaddress 06H, bit D0 : “1”)
Broadcast
mode
Write Register
Normal track
output select 2
Normal track
output select 1
Forced monaural
ON/OFF
Output
Stereo /SAP
switch
SAP1/SAP2
switch
Normal output
(NOT pin)
Subaddress : 06H
Bit: D4
Bit: D5
Bit: D1
Bit: D2
Bit: D3
Monaural
—
—
—
—
—
L+R
Stereo
—
—
—
—
—
L+R
Monaural
+ SAP
0
0
0
0
—
L+R
1
SAP
1
—
L+R
—
—
External SAPNote
1
Stereo + SAP
1
—
0
0
L+R
0
1
1
1
—
—
0
—
L+R
1
SAP
—
L+R
External SAPNote
L+R
Note SAP signal input from ESA pin.
Remark — : Don’t care.
Caution
All normal outputs with weak electric field are L+R.
Data Sheet S12816EJ3V0DS00
31
µPC1854A
6. USAGE CAUTIONS
6.1 Caution on Shock Noise Reduction
When switching the power ON/OFF, use the mute function (approx. 200 ms) outside the µPC1854A in order to
minimize shock noise.
6.2 Supply Voltage
Pass data through the I2C bus only after stabilizing the supply voltage of the entire application system.
6.3 Impedance of Input and Output Pins
Table 6-1. Impedance of Input and Output Pins
Input pin
Output pin
Symbol
Description
Impedance
Symbol
Description
Impedance
COM
Composite signal input
80 kΩ
SI
SAP single input
SOT
SAP single output
360 Ω
NOT
Normal output
15 Ω
ESA
External SAP input
ROT
R-channel output
LOT
L-channel output
6.4 Drive Capability of Output Pins
Table 6-2. Drive Capability of Output Pins
Pin symbol
Pin description
Output pin-GND Connection Resistance
Drive capability
SOT
SAP single output
10 kΩ
3-kΩ load or less
NOT
Normal output
ROT
R-channel output
LOT
L-channel output
700-Ω load or less
Remark If the load capacitance of the output pins (SOT, NOT, ROT, LOT pins) exceeds 100 pF, parasitic
oscillation may occur. In this case, connect a resistor between the output pins and the load capacitance. Bear in mind that the load capacitance is changed by wiring pattern on the printed circuit
board.
32
Data Sheet S12816EJ3V0DS00
µPC1854A
6.5 Caution on External Components
According to the license contract with THAT Corporation, use the following for external components.
With regard to the use of other external components, please contact to THAT Corporation.
Table 6-3. External Components
Pin symbol
Pin description
External component
ITI
Timing current setting
Metal film resistor (±1 %)
STI
Spectral RMS timing
Tantalum capacitor (±10 %)
WTI
Wide-band RMS timing
6.6 Change of Electrical Characteristics by External Components
(1) SAP sensitivity can be lowered by inserting a resistor between the SDT pin and GND.
(2) Noise sensitivity can be changed by changing the value of the resistor between the NDT pin and GND.
(3) The capture range can be changed by changing the recommended 1 µF value of the capacitor between the φD1
and φD2 pins (Refer to BLOCK DIAGRAM).
Reducing the capacitor value increases the capture range, and increasing it reduces the capture range. However,
too small a capacitor value may cause the distortion rate to become worse during stereo output, or may cause
malfunction. In this case, please contact NEC.
Data Sheet S12816EJ3V0DS00
33
µPC1854A
7. ELECTRICAL SPECIFICATIONS
Absolute Maximum Ratings (Unless otherwise specified, TA = +25°C)
Parameter
Symbol
Power supply voltage
VCC
I 2C
Vcont
bus input pin voltage
Conditions
Ratings
Unit
11
V
To SDA, SCL pins
VCC
V
VCC
V
Composite signal input voltage
Vin
COM pin
Power dissipation
PD
TA = 75 °C
Operating ambient temperature
TA
Storage temperature
Tstg
Caution
µPC1854ACT (SDIP)
600
mW
µPC1854AGT (SOP)
340
mW
–20 to +75
°C
–40 to +125
°C
VCC = 9 V
If any of the parameters exceeds the absolute maximum ratings, even momentarily, the device
reliability may be impaired. The absolute maximum ratings are values that may physically
damage the product. Be sure to use the product within the ratings.
Recommended Operating Range (Unless otherwise specified, TA = +25°C)
Parameter
Symbol
Conditions
MIN.
TYP.
MAX.
Unit
8.0
9.0
10.0
V
Power supply voltage
VCC
Output load impedance 1
RL1
AC load impedance that can be driven
by outputs of NOT, ROT and LOT pins
(at 100% modulation)
2
kΩ
Output load impedance 2
RL2
AC load impedance that can be driven
by output of SOT pin
(at 100% modulation)
10
kΩ
Signal input voltage
Vin
Signal voltage
to COM pin
I2C bus input pin voltage (High)
VcontH
I 2C
VcontL
bus input pin voltage (Low)
Clock frequency
34
fSCL
L+R signal
(100% modulation)
0.424
Vp-p
L-R signal
(100% modulation)
0.848
Vp-p
Pilot signal
0.0848
Vp-p
SAP signal
0.254
Vp-p
SDA, SCL pins
SCL pin
Data Sheet S12816EJ3V0DS00
3.5
5.0
0.0
0.0
5.0
V
1.5
V
100
kHz
µPC1854A
Electrical Characteristics (unless otherwise specified, TA = 25°C, RH ≤ 70 %, VCC = 9.0 V)
(1/2)
Parameter
Symbol
Conditions
MIN.
TYP.
MAX.
Unit
Supply current
ICC
No signal
33
45
60
mA
Stereo detection input sensitivity
STSENCE
11
16
21
mVrms
Stereo detection hysteresis
STHY
15.734 kHz, sine wave
Only stereo pilot signal input
Stereo detection capture range
STCCL
STCCH
SAP detection input sensitivity
SAPSENCE
SAP detection hysteresis
SAPHY
Noise detection input sensitivity
NOSENCE
Noise detection hysteresis
Vin = 30 mVrms
Only stereo pilot signal input
78.67 kHz, 0% modulation
Only SAP carrier input
3.0
6.0
9.0
dB
–5.5
–4.0
–2.5
%
2.5
4.0
5.5
%
17
23
30
mVrms
3.3
4.8
6.3
dB
Sine wave input
f: Noise BPF peak
20
30
40
mVrms
NOHY
Sine wave input
f: Noise BPF peak
1.0
2.0
3.0
dB
Monaural total output voltage
VOMO
300 Hz, 100% modulation
450
500
550
mVrms
Stereo total output voltage
VOST
450
500
550
mVrms
SAP total output voltage
VOSAP1
400
500
600
mVrms
SAP single output voltage
VOSAP2
300 Hz, 100% modulation
Noise reduction: OFF
420
470
520
mVrms
Normal output voltage
VONO
300 Hz, 100% modulation
Monaural signal
450
500
550
mVrms
Difference between monaural L and R
output voltage
VOLR
300 Hz, 100% modulation
–0.5
0
+0.5
dB
Monaural total frequency characteristics 1 VOMO1
1 kHz, 30% modulation
(300 Hz: 0 dB)
–0.5
0
+0.5
dB
Monaural total frequency characteristics 2 VOMO2
3 kHz, 30% modulation
(300 Hz: 0 dB)
–1.0
–0.3
+0.5
dB
Monaural total frequency characteristics 3 VOMO3
8 kHz, 30% modulation
(300 Hz: 0 dB)
–1.5
–0.5
+1.0
dB
Monaural total frequency characteristics 4 VOMO4
12 kHz, 30% modulation
(300 Hz: 0 dB)
–6.5
–4.0
–1.5
dB
Stereo total frequency characteristics 1
VOST1
1 kHz, 30% modulation
(300 Hz: 0 dB)
–0.5
0
+0.5
dB
Stereo total frequency characteristics 2
VOST2
3 kHz, 30% modulation
(300 Hz: 0 dB)
–1.0
0
+0.5
dB
Stereo total frequency characteristics 3
VOST3
8 kHz, 30% modulation
(300 Hz: 0 dB)
–1.0
0
+1.0
dB
Stereo total frequency characteristics 4
VOST4
12 kHz, 30% modulation
(300 Hz: 0 dB)
–11.0
–7.0
–3.0
dB
SAP total frequency characteristics 1
VOSAP11
1 kHz, 30% modulation
(300 Hz: 0 dB)
–1.2
–0.1
+1.2
dB
SAP total frequency characteristics 2
VOSAP12
3 kHz, 30% modulation
(300 Hz: 0 dB)
–1.0
+0.4
+2.0
dB
SAP total frequency characteristics 3
VOSAP13
8 kHz, 30% modulation
(300 Hz: 0 dB)
–0.5
+1.7
+4.0
dB
Data Sheet S12816EJ3V0DS00
35
µPC1854A
(2/2)
Parameter
Symbol
Conditions
MIN.
TYP.
MAX.
Unit
SAP single frequency characteristics 1
VOSAP21
1 kHz, 30% modulation
(300 Hz: 0 dB)
Noise reduction: OFF
–0.5
0
+0.5
dB
SAP single frequency characteristics 2
VOSAP22
3 kHz, 30% modulation
(300 Hz: 0 dB)
Noise reduction: OFF
–0.5
0
+0.5
dB
SAP single frequency characteristics 3
VOSAP23
8 kHz, 30% modulation
(300 Hz: 0 dB)
Noise reduction: OFF
–1.0
0
+1.0
dB
Stereo channel separation 1
Sep1
300 Hz, 30% modulation
27
32
—
dB
Stereo channel separation 2
Sep2
1 kHz, 30% modulation
25
30
—
dB
Stereo channel separation 3
Sep3
3 kHz, 30% modulation
27
35
—
dB
Monaural total harmonic distortion
THDMO
1 kHz, 100% modulation
—
0.1
0.5
%
Stereo total harmonic distortion 1
THDST1
1 kHz, 100% modulation
—
0.3
1.5
%
Stereo total harmonic distortion 2
THDST2
8 kHz, 30% modulation with
DIN/AUDIO filter used
—
0.8
1.8
%
SAP total harmonic distortion
THDSAP1
1 kHz, 100% modulation
—
0.5
2.0
%
SAP single harmonic distortion
THDSAP2
1 kHz, 100% modulation
Noise reduction: OFF
—
0.7
2.0
%
Normal output harmonic distortion
THDNO
1 kHz, 100% modulation
Monaural signal
—
0.1
0.5
%
Crosstalk 1 (SAP → Stereo)
CT1
SAP: f = 3 kHz, 30% modulation
Stereo: L-only, f = 800 Hz,
30% modulation
—
–60
–50
dB
Crosstalk 2 (Stereo → SAP)
CT2
SAP: f = 800 Hz, 30% modulation
Stereo: L-only, f = 3 kHz,
30% modulation
—
–60
–50
dB
Monaural total S/N
S/NMO
300 Hz, 100% modulation
Pre-emphasis: ON
65
68
—
dB
Stereo total S/N
S/NST
65
68
—
dB
SAP total S/N
S/NSAP
300 Hz, 100% modulation
Noise reduction: ON
70
80
—
dB
Normal output S/N
S/N NO
Signal: 300 Hz, 100% modulation
Monaural signal
65
68
—
dB
Total muting level
Mute
1 kHz, 100% modulation
60
70
—
dB
dbx timing current
IT
STI- and WTI-pin current flow
7.1
7.5
7.9
µA
Inter-mode DC offset 1
VDOF1
Mute → Monaural, no signal
–50
0
+50
mV
Inter-mode DC offset 2
VDOF2
Mute → Stereo,
only pilot signal input
–50
0
+50
mV
Inter-mode DC offset 3
VDOF3
Mute → SAP1,
only 5 fH signal input
–50
0
+50
mV
Inter-mode DC offset 4
VDOF4
Mute → Monaural (Normal output)
–50
0
+50
mV
Inter-mode DC offset 5
VDOF5
Mute → External SAP
(Normal output)
–50
0
+50
mV
36
Data Sheet S12816EJ3V0DS00
µPC1854A
Test Condition Parameters for Electrical Characteristics
(Unless otherwise specified, TA = 25°C, RH ≤ 70 %, VCC = 9 V)
(1/7)
Parameter
Symbol
Test Conditions
User ModeNote
Supply current
ICC
ICC : Current sent to VCC pin when there is no signal
Monaural
Stereo detection input
sensitivity
STSENCE
STSENCE : Input signal level of COM pin (input signal: 15.734 kHz)
Read register D6 : when changed from 0 to 1
Stereo
Stereo detection hysteresis
STHY
STHY =20 log (STSENCE ÷ V)
STSENCE : Stereo detection input sensitivity
V : Input signal level of COM pin (Input signal: 15.734 kHz)
Read register D6 : First set to 1, then changed to 0 by gradually
lowering input signal level.
Stereo detection
capture range
STCCL
STCCL = ∆f ÷ 15.734 kHz
∆f : Difference between f and 15.734 kHz
f : With signal (14.5 kHz, 30 mVrms) input to COM pin;
The frequency, which is gradually raised and measured when
read register D6 becomes 1
STCCH
STCCH = ∆f ÷ 15.734 kHz
∆f : Difference between f and 15.734 kHz
f : With signal (17.0 kHz, 30 mVrms) input to COM pin;
The frequency, which is gradually lowered and measured when
read register D6 becomes 1
SAP detection input
sensitivity
SAPSENCE
SAPSENCE : Input signal level of COM pin (input signal: 78.67 kHz)
Read register D5 : when changed from 0 to 1
SAP detection hysteresis
SAPHY
SAPHY =20 log (SAPSENCE ÷ V)
SAPSENCE : SAP detection input sensitivity
V: Input signal level of COM pin (Input signal: 78.67 kHz)
Read register D5 : First set to 1, then changed to 0 by gradually
lowering input signal level.
Noise detection input
NOSENCE
NOSENCE : Input signal level of COM pin
Read register D4 : Changed to 0 by applying 6-V DC voltage to
SDT pin.
Read register D4 : With signal (160 kHz, 10 mVrms) input to
COM pin;
Changed to 1 by raising the frequency until
the DC voltage of the NDT pin reaches the
maximum level and, with maintaining this
frequency, gradually raising the input signal
level.
NOHY
NOHY = 20 log (NOSENCE ÷ V)
NOSENCE : Noise detection input sensitivity
V: Input signal level of NDT pin
COM pin : Signal (160 kHz, 90 mVrms) input
Read register D4 : First set to 1, then changed to 0 by raising
the frequency until the DC voltage of the
NDT pin reaches the maximum level and,
with maintaining this frequency, gradually
raising the input signal level.
sensitivity
Noise detection hysteresis
Monaural total output voltage VOMO
VOMO : Output voltage of ROT and LOT pins
COM pin: Monaural signal (300 Hz, 100% modulation) input
SAP
Monaural
Note For details about the User Mode, refer to chapter 5. MODE MATRIX.
Data Sheet S12816EJ3V0DS00
37
µPC1854A
(2/7)
Parameter
Symbol
Test Conditions
User ModeNote
Stereo total output voltage
VOST
L-channel
Stereo
VOST : Output voltage of LOT pin
COM pin : Stereo signal (L-only, 300 Hz, 100% modulation) input
R-channel
VOST : Output voltage of ROT pin
COM pin : Stereo signal (R-only, 300 Hz, 100% modulation) input
SAP total output voltage
VOSAP1
VOSAP1 : Output voltage of ROT and LOT pins
COM pin : SAP signal (300 Hz, 100% modulation) input
SAP1
SAP single output voltage
VOSAP2
VOSAP2 : Output voltage of SOT pin
COM pin : SAP signal (300 Hz, 100% modulation,
Noise reduction: OFF) input
SAP
Normal output voltage
VONO
VONO : Output voltage of NOT pin
COM pin : Monaural signal (300 Hz, 100% modulation) input
Monaural
Difference between
monaural L and R
output voltage
VOLR
VOLR = 20 log (VL ÷ VR)
VL : Output voltage of LOT pin
COM pin : Monaural signal (300 Hz, 100% modulation) input
VR : Output voltage of ROT pin
COM pin : Monaural signal (300 Hz, 100% modulation) input
Monaural total frequency
characteristics 1
VOMO1
VOMO1 = 20 log {V(1k) ÷ V(300)}
V(1k) : Output voltage of LOT pin
COM pin : Monaural signal (1 kHz, 30% modulation) input
V(300) : Output voltage of LOT pin
COM pin : Monaural signal (300 Hz, 30% modulation) input
Monaural total frequency
characteristics 2
VOMO2
VOMO2 = 20 log {V(3k) ÷ V(300)}
V(3k) : Output voltage of LOT pin
COM pin : Monaural signal (3 kHz, 30% modulation) input
V(300) : Output voltage of LOT pin
COM pin : Monaural signal (300 Hz, 30% modulation) input
Monaural total frequency
characteristics 3
VOMO3
VOMO3 = 20 log {V(8k) ÷ V(300)}
V(8k) : Output voltage of LOT pin
COM pin : Monaural signal (8 kHz, 30% modulation) input
V(300) : Output voltage of LOT pin
COM pin : Monaural signal (300 Hz, 30% modulation) input
Monaural total frequency
characteristics 4
VOMO4
VOMO4 = 20 log {V(12k) ÷ V(300)}
V(12k) : Output voltage of LOT pin
COM pin : Monaural signal (12 kHz, 30% modulation) input
V(300) : Output voltage of LOT pin
COM pin : Monaural signal (300 Hz, 30% modulation) input
Stereo total frequency
characteristics 1
VOST1
VOST1 = 20 log {V(1k) ÷ V(300)}
V(1k) : Output voltage of LOT pin
COM pin : Stereo signal (L-only, 1 kHz, 30% modulation) input
V(300) : Output voltage of LOT pin
COM pin : Stereo signal (L-only, 300 Hz, 30% modulation) input
Stereo total frequency
characteristics 2
VOST2
VOST2 = 20 log {V(3k) ÷ V(300)}
V(3k) : Output voltage of LOT pin
COM pin : Stereo signal (L-only, 3 kHz, 30% modulation) input
V(300) : Output voltage of LOT pin
COM pin : Stereo signal (L-only, 300 Hz, 30% modulation) input
Note For details about the User Mode, refer to chapter 5. MODE MATRIX.
38
Data Sheet S12816EJ3V0DS00
Stereo
µPC1854A
(3/7)
Parameter
Symbol
Test Conditions
Stereo total frequency
characteristics 3
VOST3
VOST3 = 20 log {V(8k) ÷ V(300)}
V(8k) : Output voltage of LOT pin
COM pin : Stereo signal (L-only, 8 kHz, 30% modulation) input
V(300) : Output voltage of LOT pin
COM pin : Stereo signal (L-only, 300 Hz, 30% modulation) input
Stereo total frequency
VOST4
VOST4 = 20 log {V(12k) ÷ V(300)}
V(12k) : Output voltage of LOT pin
COM pin : Stereo signal (L-only, 12 kHz, 30% modulation) input
V(300) : Output voltage of LOT pin
COM pin : Stereo signal (L-only, 300 Hz, 30% modulation) input
SAP total frequency
characteristics 1
VOSAP11
VOSAP11 = 20 log {V(1k) ÷ V(300)}
V(1k) : Output voltage of LOT pin
COM pin : SAP signal (1 kHz, 30% modulation) input
V(300) : Output voltage of LOT pin
COM pin : SAP signal (300 Hz, 30% modulation) input
SAP total frequency
characteristics 2
VOSAP12
VOSAP12 = 20 log {V(3k) ÷ V(300)}
V(3k) : Output voltage of LOT pin
COM pin : SAP signal (3 kHz, 30% modulation) input
V(300) : Output voltage of LOT pin
COM pin : SAP signal (300 Hz, 30% modulation) input
SAP total frequency
characteristics 3
VOSAP13
VOSAP13 = 20 log {V(8k) ÷ V(300)}
V(8k) : Output voltage of LOT pin
COM pin : SAP signal (8 kHz, 30% modulation) input
V(300) : Output voltage of LOT pin
COM pin : SAP signal (300 Hz, 30% modulation) input
SAP single frequency
characteristics 1
VOSAP21
VOSAP21 = 20 log {V(1k) ÷ V(300)}
V(1k) : Output voltage of SOT pin
COM pin : SAP signal (1 kHz, 30% modulation,
Noise reduction: OFF) input
V(300) : Output voltage of SOT pin
COM pin : SAP signal (300 Hz, 30% modulation,
Noise reduction: OFF) input
SAP single frequency
characteristics 2
VOSAP22
VOSAP22 = 20 log {V(3k) ÷ V(300)}
V(3k) : Output voltage of SOT pin
COM pin : SAP signal (3 kHz, 30% modulation,
Noise reduction: OFF) input
V(300) : Output voltage of SOT pin
COM pin : SAP signal (300 Hz, 30% modulation,
Noise reduction: OFF) input
SAP single frequency
characteristics 3
VOSAP23
VOSAP23 = 20 log {V(8k) ÷ V(300)}
V(8k) : Output voltage of SOT pin
COM pin : SAP signal (8 kHz, 30% modulation,
Noise reduction: OFF) input
V(300) : Output voltage of SOT pin
COM pin : SAP signal (300 Hz, 30% modulation,
Noise reduction: OFF) input
characteristics 4
User ModeNote
Stereo
SAP1
SAP
Note For details about the User Mode, refer to chapter 5. MODE MATRIX.
Data Sheet S12816EJ3V0DS00
39
µPC1854A
(4/7)
Parameter
Symbol
Test Conditions
Stereo channel separation 1
Sep1
L-channel
Sep1 = 20 log (VL ÷ VR)
VL : Output voltage of LOT pin
COM pin : Stereo signal (L-only, 300 Hz, 30% modulation) input
VR : Output voltage of ROT pin
COM pin : Stereo signal (L-only, 300 Hz, 30% modulation) input
R-channel
Sep1 = 20 log (VR ÷ VL)
VR : Output voltage of ROT pin
COM pin : Stereo signal (R-only, 300 Hz, 30% modulation) input
VL : Output voltage of LOT pin
COM pin : Stereo signal (R-only, 300 Hz, 30% modulation) input
(465Z manufactured by EIDEN Co., Ltd.)
Stereo channel separation 2
Sep2
L-channel
Sep2 = 20 log (VL ÷ VR)
VL : Output voltage of LOT pin
COM pin : Stereo signal (L-only, 1 kHz, 30% modulation) input
VR : Output voltage of ROT pin
COM pin : Stereo signal (L-only, 1 kHz, 30% modulation) input
R-channel
Sep2 = 20 log (VR ÷ VL)
VR : Output voltage of ROT pin
COM pin : Stereo signal (R-only, 1 kHz, 30% modulation) input
VL : Output voltage of LOT pin
COM pin : Stereo signal (R-only, 1 kHz, 30% modulation) input
(465Z manufactured by EIDEN Co., Ltd.)
Stereo channel separation 3
Sep3
L-channel
Sep3 = 20 log (VL ÷ VR)
VL : Output voltage of LOT pin
COM pin : Stereo signal (L-only, 3 kHz, 30% modulation) input
VR : Output voltage of ROT pin
COM pin : Stereo signal (L-only, 3 kHz, 30% modulation) input
R-channel
Sep3 = 20 log (VR ÷ VL)
VR : Output voltage of ROT pin
COM pin : Stereo signal (R-only, 3 kHz, 30% modulation) input
VL : Output voltage of LOT pin
COM pin : Stereo signal (R-only, 3 kHz, 30% modulation) input
User ModeNote
Stereo
(465Z manufactured by EIDEN Co., Ltd.)
Monaural total harmonic
distortion
THDMO
THDMO : Distortion rate of LOT and ROT pins
COM pin : Monaural signal (1 kHz, 100% modulation) input
Monaural
Stereo total harmonic
distortion 1
THDST1
L-channel
THDST1 : Distortion rate of LOT pin
COM pin : Stereo signal (L-only, 1 kHz, 100% modulation) input
R-channel
THDST1 : Distortion rate of ROT pin
COM pin : Stereo signal (R-only, 1 kHz, 100% modulation) input
Stereo
Note For details about the User Mode, refer to chapter 5. MODE MATRIX.
40
Data Sheet S12816EJ3V0DS00
µPC1854A
(5/7)
Parameter
Stereo total harmonic
distortion 2
Symbol
THDST2
Test Conditions
User ModeNote
L-channel
THDST2 : Distortion rate of LOT pin
COM pin : Stereo signal (L-only, 8 kHz, 30% modulation) input
R-channel
THDST2 : Distortion rate of ROT pin
COM pin : Stereo signal (R-only, 8 kHz, 30% modulation) input
Stereo
SAP total harmonic distortion THDSAP1
THDSAP1 : Distortion rate of LOT and ROT pins
COM pin : SAP signal (1 kHz, 100% modulation) input
SAP1
SAP single harmonic
distortion
THDSAP2
THDSAP2 : Distortion rate of SOT pin
COM pin : SAP signal (1 kHz, 100% modulation,
Noise reduction off) input
SAP
Normal output harmonic
distortion
THDNO
THDNO : Distortion rate of NOT pin
COM pin : Monaural signal (1 kHz, 100% modulation) input
Monaural
Crosstalk 1 (SAP → stereo)
CT1
CT1 = 20 log (VCT1 ÷ VL)
Stereo
VCT1 : VL after BPF (3 kHz)
VL : Output voltage of LOT pin
COM pin : Composite signal {Stereo signal (L-only, 800 Hz, 30%
modulation) and SAP signal (3 kHz, 30 % modulation) }
input
BPF : Attenuation of 0 dB at 3 kHz and 80 dB at 800 Hz, or more
Crosstalk 2 (stereo → SAP)
CT2
CT2 = 20 log (VCT2 ÷ VL)
SAP1
VCT2 : VL after BPF (3 kHz)
VL : Output voltage of LOT pin
COM pin : Composite signal {SAPsignal (800 Hz, 30% modulation)
and Stereo signal (L-only, 3 kHz, 30 % modulation) }
input
BPF : Attenuation of 0 dB at 3 kHz and 80 dB at 800 Hz, or more
Monaural total S/N
S/NMO
L-channel
S/NMO = 20 log (VOMOL ÷ VL)
VOMOL : Output voltage of LOT pin
COM pin : Monaural signal (300 Hz, 100% modulation) input
VL : Output voltage of LOT pin (no signal)
R-channel
S/NMO = 20 log (VOMOR ÷ VR)
VOMOR: Output voltage of ROT pin
COM pin : Monaural signal (300 Hz, 100% modulation) input
VR : Output voltage of ROT pin (no signal)
Stereo total S/N
S/NST
L-channel
Stereo
S/NST = 20 log (VOSTL ÷ VL)
VOSTL : Output voltage of LOT pin
COM pin : Stereo signal (L-only, 300 Hz, 100% modulation) input
VL : Output voltage of LOT pin
COM pin : Pilot signal input
R-channel
S/NST = 20 log (VOSTR ÷ VR)
VOSTR : Output voltage of ROT pin
COM pin : Stereo signal (R-only, 300 Hz, 100% modulation) input
VR : Output voltage of ROT pin
COM pin : Pilot signal input
Monaural
Note For details about the User Mode, refer to chapter 5. MODE MATRIX.
Data Sheet S12816EJ3V0DS00
41
µPC1854A
(6/7)
Parameter
Symbol
Test Conditions
User ModeNote
SAP total S/N
S/NSAP
L-channel
S/NSAP = 20 log (VOSAP1L ÷ VL)
VOSAP1L : Output voltage of LOT pin
COM pin : SAP signal (300 Hz, 100% modulation) input
VL : Output voltage of LOT pin
COM pin : SAP carrier (0 % modulation) input
R-channel
S/NSAP = 20 log (VOSAP1R ÷ VR)
VOSAP1R : Output voltage of ROT pin
COM pin : SAP signal (300 Hz, 100% modulation) input
VR : Output voltage of ROT pin
COM pin : SAP carrier (0 % modulation) input
SAP1
Normal output S/N
S/NNO
S/NNO = 20 log (VONO ÷ VM)
VONO : Output voltage of NOT pin
COM pin : Monaural signal (300 Hz, 100% modulation) input
VM : Output voltage of NOT pin (no signal)
Monaural
Total muting level
Mute
Mute = 20 log (VOMOL ÷ VM)
VOMOL : Output voltage of LOT pin
COM pin : Monaural signal (300 Hz, 100% modulation) input
VM : Output voltage of LOT pin
Write register 06H, D0 : 0
COM pin : Monaural signal (300 Hz, 100% modulation) input
Monaural
mute
dbx timing current
IT
IT : Current that flows from VCC to STI and WTI pins
STI and WTI pins : 6-V DC is applied.
Inter-mode DC offset 1
VDOF1
VDOF1 = VMONO – VMute
VMONO : DC voltage at LOT and ROT pins
User mode : Monaural
NDT pin : 6-V DC is applied.
VMute : DC voltage at LOT and ROT pins
User mode : Mute (write register 06H, D1 : 0)
NDT pin : 6-V DC is applied.
Mute
to
Monaural
Inter-mode DC offset 2
VDOF2
VDOF2 = VST – VMute
VST : DC voltage at LOT and ROT pins
User mode : Stereo
NDT pin : 6-V DC is applied.
VMute : DC voltage at LOT and ROT pins
User mode : Mute (write register 06H, D1 : 0)
NDT pin : 6-V DC is applied.
Mute
to
Stereo
Inter-mode DC offset 3
VDOF3
VDOF3 = VSAP – VMute
VSAP : DC voltage at LOT and ROT pins
User mode : SAP1
NDT pin : 6-V DC is applied.
VMute : DC voltage at LOT and ROT pins
User mode : Mute (write register 06H, D1 : 0)
NDT pin : 6-V DC is applied.
Mute
to
SAP1
Note For details about the User Mode, refer to chapter 5. MODE MATRIX.
42
Data Sheet S12816EJ3V0DS00
µPC1854A
(7/7)
Parameter
Symbol
Test Conditions
User ModeNote
Inter-mode DC offset 4
VDOF4
VDOF4 = VMONO – VMute
VMONO : DC voltage at NOT pin
User mode : Monaural
NDT pin : 6-V DC is applied.
VMute : DC voltage at NOT pin
User mode : Mute (write register 06H, D1: 0)
NDT pin : 6-V DC is applied.
Mute
to
Monaural
Inter-mode DC offset 5
VDOF5
VDOF5 = VEXT – VMute
VEXT : DC voltage at NOT pin
User mode : External SAP
NDT pin: 6-V DC is applied.
VMute : DC voltage at NOT pin
User mode : Mute (write register 06H, D1 : 0)
NDT pin: 6-V DC is applied.
Mute
to
External SAP
Note For details about the User Mode, refer to chapter 5. MODE MATRIX.
Data Sheet S12816EJ3V0DS00
43
µPC1854A
8. MEASURING CIRCUIT
µPC1854A
A
VCC
22 µF
+
9V
1
VCC
MOA 28
1 µF
+
2
VRE
LOT 27
10 µ F
+
3
PD1
ROT 26
10 µF
+
4
PD2
NOT 25
10 µF
+
5
φ D1
VOA 24
1 µF
+
0.1 µF
1 kΩ
4.7 µ F
Note 1
Multiple Audio Signal Generator
+
+
1 µF
6
φ D2
WTI 23
10 µF
+
2.2 µF
+
7
COM
STI 22
3.3 µF
+
0.1 µF
+
8
SOA
ITI 21
1.6 kΩ 15 kΩ
0.047 µF
9
SDT
WRB 20
+
6V
0.47 µ F
V
10 µ F
+
Buffer
10 NDT
SRB 19
Note 2
5.1 kΩ 1 µF
+
3 kΩ 1 µF
+
68 kΩ
11 SOT
dO 18
Filter
Measuring
Device
A
1 µF
+
6V
0.1 µ F
12 SI
DGND 17
13 ESA
DGND
SCL 16
I2C Bus Data
14 AGND
SDA 15
Notes 1. 465Z manufactured by EIDEN Co., Ltd.
2. 30 kHz LPF, DIN/AUDIO filter, or 3kHz BPF
Remark Use the following for external parts.
Resistor : Metal film resistor (±1 %) for an ITI pin. Unless otherwise specified; ±5 %
Capacitor : Tantalum capacitor (±10 %) for STI and WTI pins. Unless otherwise specified; ±20 %
44
Data Sheet S12816EJ3V0DS00
µPC1854A
9. PACKAGE DRAWINGS
28-PIN PLASTIC SDIP (10.16mm400))
28
15
1
14
A
K
J
I
L
F
D
N
M
C
H
R
M
B
G
NOTES
1. Each lead centerline is located within 0.17 mm
of its true position (T.P.) at maximum material condition.
2. Item "K" to center of leads when formed parallel.
ITEM
MILLIMETERS
A
28.46 MAX.
B
2.67 MAX.
C
1.778 (T.P.)
D
0.50±0.10
F
G
0.85 MIN.
3.2±0.3
H
0.51 MIN.
I
4.31 MAX.
J
5.08 MAX.
K
L
10.16 (T.P.)
8.6
M
0.25 +0.10
−0.05
N
0.17
R
0∼15°
S28C-70-400B-2
Data Sheet S12816EJ3V0DS00
45
µPC1854A
28-PIN PLASTIC SOP (9.53 mm (375))
28
15
detail of lead end
R
1
14
A
H
F
I
G
J
S
C
D
M
B
L
N
K
M
S
E
NOTE
Each lead centerline is located within 0.12 mm of
its true position (T.P.) at maximum material condition.
ITEM
A
MILLIMETERS
17.9±0.2
B
0.845 MAX.
C
1.27 (T.P.)
D
0.42 +0.08
−0.07
E
0.125±0.075
F
2.9 MAX.
G
2.50±0.2
H
10.3±0.2
I
7.2±0.2
J
1.6±0.2
K
0.17 +0.08
−0.07
L
0.8
M
0.12
N
0.10
R
3° +7°
−3°
P28GT-50-375B-3
46
Data Sheet S12816EJ3V0DS00
µPC1854A
10. RECOMMENDED SOLDERING CONDITIONS
The µPC1854A should be soldered and mounted under the conditions recommended in the table below.
For details of recommended soldering conditions, refer to the information document Semiconductor Device
Mounting Technology Manual (C10535E).
For soldering methods and conditions other than those recommended below, contact an NEC sales representative.
Table 10-1. Surface Mounting Type Soldering Conditions
µPC1854AGT : 28-pin plastic SOP (9.53 mm (400))
Soldering Method
Soldering Conditions
Symbol
Infrared reflow
Package peak temperature: 235°C, Duration: 30 sec. max. (at 210°C or above),
Number of times: Three times max.
IR35-00-3
VPS
Package peak temperature: 215°C, Duration: 40 sec. max. (at 200°C or above),
Number of times: Three times max.
VP15-00-3
Wave soldering
Solder bath temperature: 260°C max., Duration: 10 sec. max., Number of times: Once,
Preliminary heat temperature: 120°C max. (Package surface temperature)
WS60-00-1
Partial heating
Pin temperature: 300°C max., Duration: 3 sec. max. (per pin row)
Caution
—
Do not use different soldering methods together (except in the case of partial heating).
Table 10-2. Inserting Type Soldering Conditions
µPC1854ACT : 28-pin plastic SDIP (10.16 mm (400))
Soldering Method
Soldering Conditions
Wave soldering
(only pins)
Solder bath temperature: 260°C max., Duration: 10 sec. max.
Partial heating
Pin temperature: 300°C max., Duration: 3 sec. max. (per pin row)
Caution
Apply wave soldering only to the pins and be careful not to bring solder into direct contact
with the package.
Data Sheet S12816EJ3V0DS00
47
µPC1854A
Purchase of NEC I2C components conveys a license under the Philips I 2C Patent Rights to
use these components in an I2C system, provided that the system conforms to the I2C Standard
Specifications as defined by Philips.
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M8E 00. 4