NEC UPD178024

DATA SHEET
MOS INTEGRATED CIRCUIT
µPD178023,178024
8-BIT SINGLE-CHIP MICROCONTROLLER
DESCRIPTION
The µPD178023, 178024 are 8-bit single-chip CMOS microcontrollers containing hardware for digital tuning
systems.
These microcontrollers employ a 78K/0 series architecture CPU and allow easy access to internal memories at
high speed and easy control of peripheral hardware units. The high-speed 78K/0 series instructions are ideal for
system control.
As peripheral hardware, a prescaler, PLL frequency synthesizer, and frequency counter for digital tuning systems
are provided, as well as many I/O ports, timers, A/D converter, serial interface, and a power-ON clear circuit.
In addition, three serial interfaces, I2C bus (IIC0), three-wire (SIO3), and UART are provided.
Moreover, a flash memory model, the µPD178F124, that operates in the same supply voltage range as the mask
ROM models, and various development tools are also under development.
For the detailed functional description, refer to the following User’s Manuals:
µPD178024, 178124 Subseries User’s Manual : U13915E
78K/0 Series User’s Manual - Instruction
: U12326E
FEATURES
• High-capacity ROM and RAM
Item
Program Memory (ROM)
Part Number
Data Memory
Internal high-speed RAM
µPD178023
24K bytes
µPD178024
32K bytes
• Instruction cycle:
1024 bytes
0.45/0.89/1.78/3.56/7.11 µs (with crystal resonator of
fX = 4.5 MHz)
• Many internal hardware units
General-purpose I/O ports, A/D converter, serial
interface (I2C bus and UART mode), timers, frequency
counter, power-ON clear circuit
• Hardware for PLL frequency synthesizer
Dual modulus prescaler, programmable divider,
phase comparator, charge pump
• Vectored interrupt sources:
• Supply voltage
17
:VDD = 4.5 to 5.5 V (during PLL and CPU
operations)
:VDD = 3.5 to 5.5 V (during CPU operation)
The information in this document is subject to change without notice. Before using this document, please
confirm that this is the latest version.
Not all devices/types available in every country. Please check with local NEC representative for availability
and additional information.
Document No. U14126EJ1V0DS00 (1st edition)
Date Published September 1999 N CP(K)
Printed in Japan
©
1999
µPD178023, 178024
APPLICATION FIELD
Car stereos
ORDERING INFORMATION
Part Number
Package
µPD178023GF-×××-3B9
80-pin plastic QFP (14 × 20 mm, 0.8-mm pitch)
µPD178023GC-×××-8BT
80-pin plastic QFP (14 × 14 mm, 0.65-mm pitch)
µPD178024GF-×××-3B9
80-pin plastic QFP (14 × 20 mm, 0.8-mm pitch)
µPD178024GC-×××-8BT
80-pin plastic QFP (14 × 14 mm, 0.65-mm pitch)
Remark ××× indicates ROM code suffix, which is E×× when the I2C bus is used.
2
Data Sheet U14126EJ1V0DS00
µPD178023, 178024
DEVELOPMENT OF 8-BIT DTS SERIES
Models under mass production
Models under development
Flash memory model
or PROM model
64/80 pins
µ PD178F048
Mask ROM model
64/80 pins
Internal OSD controller
8-bit PWM × 4 channels
14-bit PWM × 1 channel
µ PD178048 subseries
Internal OSD controller
8-bit PWM × 4 channels
14-bit PWM × 1 channel
100 pins
µ PD178098 subseries
Internal IEBus controller
100 pins
µ PD178F098
Internal IEBusTM controller
and UART
100 pins
µ PD178078 subseries
Internal UART
80 pins
µ PD178F134
80 pins
Internal LCD and UART
Internal LCD and UART
80 pins
µ PD178F124
80 pins
Internal UART
80 pins
µ PD178034 subseries
µ PD178024 subseries
Internal UART
80 pins
µ PD178018A subseries
80 pins
µ PD178003 subseries
µ PD178P018A
Limits functions of µ PD178018A subseries
Data Sheet U14126EJ1V0DS00
3
µPD178023, 178024
FUNCTIONAL OUTLINE
(1/2)
µPD178023
Item
Internal
memory
ROM
24 Kbytes
(Mask ROM)
High-speed RAM
1024 bytes
µPD178024
32 Kbytes
(Mask ROM)
General-purpose register
8 bits × 32 registers (8 bits × 8 registers × 4 banks)
Minimum instruction execution time
0.45 µs/0.89 µs/1.78 µs/3.56 µs/7.11 µs (with crystal resonator of fX = 4.5 MHz)
Instruction set
•
•
•
•
I/O port
Total
: 62 pins
• CMOS I/O
• CMOS input
: 53 pins
: 6 pins
16-bit operation
Multiplication/division (8 bits × 8 bits, 16 bits ÷ 8 bits)
Bit manipulation (set, reset, test, Boolean operation)
BCD adjustment, etc.
• N-ch open-drain output : 3 pins
A/D converter
8-bit resolution × 6 channels (VDD = 4.5 to 5.5 V)
Serial interface
• I2C bus modeNote : 1 channel
• 3-wire mode
: 1 channel
• UART mode
: 1 channel
Timer
• Basic timer (timer carry FF (10 Hz)) : 1 channel
• 8-bit timer/event counter
: 2 channels
• Watchdog timer
Buzzer output
Vectored
interrupt
source
PLL
frequency
synthesizer
Note
1 channel (1 kHz, 1.5 kHz, 3 kHz, 4 kHz)
Maskable
Internal : 11
External: 5
Non-maskable
Internal: 1
Software
Internal: 1
Division mode
2 types
• Direct division mode (VCOL pin)
• Pulse swallow mode (VCOL and VCOH pins)
Reference frequency
Seven types selectable in software (1, 3, 9, 10, 12.5, 25, 50 kHz)
Charge pump
Error out output: 2 pins
Phase comparator
Unlock detectable in software
When the I2C bus mode is used (including when the mode is implemented in software without using the
peripheral hardware), consult NEC when ordering a mask.
4
: 1 channel
Data Sheet U14126EJ1V0DS00
µPD178023, 178024
(2/2)
Item
µPD178023
µPD178024
Frequency counter
Frequency measurement
• AMIFC pin: For 450-kHz counting
• FMIFC pin: For 450-kHz/10.7-MHz counting
Reset
• Reset by RESET pin
• Internal reset by watchdog timer
• Reset by power-ON clear circuit
• Detection of less than 4.5 VNote (Reset does not occur, however.)
• Detection of less than 3.5 VNote (during CPU operation)
• Detection of less than 2.3 VNote (in STOP mode)
Supply voltage
• VDD = 4.5 to 5.5 V (during CPU, PLL operation)
• VDD = 3.5 to 5.5 V (during CPU operation)
Package
• 80-pin plastic QFP (14 × 20 mm, 0.8-mm pitch)
• 80-pin plastic QFP (14 × 14 mm, 0.65-mm pitch)
Note
These voltages are the maximum values. In practice, the chip may be reset at voltages lower than these.
Data Sheet U14126EJ1V0DS00
5
µPD178023, 178024
PIN CONFIGURATION (Top View)
• 80-pin plastic QFP (14 × 20 mm, 0.8 pitch)
P122
P123
P124
P125
P00/INTP0
P01/INTP1
P02/INTP2
P03/INTP3
P04/INTP4
P05
P06
REGCPU
GND
X2
X1
REGOSC
µPD178023GF-×××-3B9, 178024GF-×××-3B9
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65
1
64
P121
RESET
2
63
P120
P10/ANI0
3
62
P37
P11/ANI1
4
61
P36/BEEP0
P12/ANI2
5
60
P35
P13/ANI3
6
59
P34/TI51
P14/ANI4
7
58
P33/TI50
P15/ANI5
8
57
P32
VDD
P70/SI3
9
56
P31
P71/SO3
10
55
P30
P72/SCK3
11
54
P67
P73
12
53
P66
P74/RXD0
13
52
P65
19
46
P57
P40
20
45
P56
P41
21
44
P55
P42
22
43
P54
GNDPORT
23
42
P53
24
41
25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40
P52
P43
VDDPORT
P51
P132
IC
P60
P50
47
EO1
18
EO0
P61
P131/TO51
VCOL
48
VCOH
17
GNDPLL
P62
P130/TO50
VDDPLL
49
FMIFC
16
AMIFC
P63
P77/SCL0
P47
P64
50
P46
51
15
P45
14
P44
P75/TXD0
P76/SDA0
Cautions 1. Directly connect the IC (Internally Connected) to GND.
2. Keep the voltage at VDD PORT and VDDPLL at the same voltage as VDD.
3. Keep the voltage at GNDPORT and GNDPLL at the same voltage as GND.
4. Connect each of the REGOSC and REGCPU pins to GND via 0.1-µF capacitor.
6
Data Sheet U14126EJ1V0DS00
µPD178023, 178024
• 80-pin plastic QFP (14 × 14 mm, 0.65 pitch)
P120
P121
P122
P123
P124
P125
P00/INTP0
P01/INTP1
P02/INTP2
P03/INTP3
P04/INTP4
P05
P06
REGCPU
GND
X2
X1
REGOSC
VDD
RESET
µPD178023GC-×××-8BT, 178024GC-×××-8BT
P10/ANI0
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61
60
1
P11/ANI1
2
59
P36/BEEP0
P12/ANI2
3
58
P35
P13/ANI3
4
57
P34/TI51
P14/ANI4
5
56
P33/TI50
P15/ANI5
6
55
P32
P70/SI3
7
54
P31
P71/SO3
8
53
P30
P72/SCK3
9
52
P67
P37
17
44
P57
P40
18
43
P56
P41
19
42
P55
P42
41
20
21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40
P54
P53
P132
P52
P60
P51
P61
45
P50
46
16
IC
15
P131/TO51
EO1
P130/TO50
EO0
P62
GNDPLL
P63
47
VCOL
48
14
VCOH
13
P77/SCL0
VDDPLL
P76/SDA0
FMIFC
P64
AMIFC
49
P47
12
P46
P75/TXD0
P45
P65
P44
P66
50
P43
51
11
VDDPORT
10
GNDPORT
P73
P74/RXD0
Cautions 1. Directly connect the IC (Internally Connected) to GND.
2. Keep the voltage at VDD PORT and VDDPLL at the same voltage as VDD.
3. Keep the voltage at GNDPORT and GNDPLL at the same voltage as GND.
4. Connect each of the REGOSC and REGCPU pins to GND via 0.1-µF capacitor.
Data Sheet U14126EJ1V0DS00
7
µPD178023, 178024
PIN NAME
AMIFC
: AM intermediate frequency counter input
P130-P132
: Port 13
ANI0-ANI5
: A/D converter input
REGCPU
: Regulator for CPU power supply
BEEP0
: Buzzer output
REGOSC
: Regulator for oscillator
EO0, EO1
: Error out output
RESET
: Reset input
FMIFC
: FM intermediate frequency counter input
RXD0
: Serial (UART0) data input
GND
: Ground
SCK3
: Serial (SIO3) clock input/output
GNDPLL
: PLL ground
SCL0
: Serial (IIC0) clock input/output
GNDPORT
: Port ground
SDA0
: Serial (IIC0) data input/output
IC
: Internally connected
SI3
: Serial (SIO3) data input
INTP0-INTP4 : Interrupt input
SO3
: Serial (SIO3) data output
P00-P06
: Port 0
TI50, TI51
: 8-bit timer clock input
P10-P15
: Port 1
TO50, TO51 : 8-bit timer output
P30-P37
: Port 3
TXD0
P40-P47
: Port 4
VCOL, VCOH: Local oscillation input
P50-P57
: Port 5
VDD
: Power supply
P60-P67
: Port 6
VDDPLL
: PLL power supply
P70-P77
: Port 7
VDDPORT
: Port power supply
P120-P125
: Port 12
X1, X2
: Crystal resonator
8
Data Sheet U14126EJ1V0DS00
: Serial (UART0) data output
µPD178023, 178024
BLOCK DIAGRAM
TI50/P33
TO50/P130
8-bit TIMER/
EVENT COUNTER50
PORT0
7
P00-P06
TI51/P34
TO51/P131
8-bit TIMER/
EVENT COUNTER51
PORT1
6
P10-P15
PORT3
8
P30-P37
PORT4
8
P40-P47
PORT5
8
P50-P57
PORT6
8
P60-P67
PORT7
8
P70-P77
PORT12
6
P120-P125
PORT13
3
P130-P132
A/D CONVERTER
6
ANI0/P10ANI5/P15
WATCHDOG TIMER
78K/0
CPU
CORE
BASIC TIMER
SI3/P70
SO3/P71
SCK3/P72
SERIAL
INTERFACE3
SDA0/P76
SCL0/P77
I2C BUS
(RXD0)/P74
(TXD0)/P75
INTP0/P00INTP4/P04
BEEP0/P36
RESET
X1
X2
VDDPORT
GNDPORT
VDD
REGOSC
REGCPU
GND
ROM
UART0
5
INTERRUPT
CONTROL
RAM
BUZZER OUTPUT
FREQUENCY
COUNTER
AMIFC
FMIFC
PLL
EO0
EO1
VCOL
VCOH
RESET
SYSTEM
CONTROL
CPU
PERIPHERAL
VOLTAGE
REGULATOR
PLL
VOLTAGE
REGULATOR
VOSC
VCPU
VDDPLL
GNDPLL
IC
Remark The internal ROM and RAM capacities differ depending on the product.
Data Sheet U14126EJ1V0DS00
9
µPD178023, 178024
CONTENTS
1. PIN
1.1
1.2
1.3
FUNCTION LIST ......................................................................................................................
Port Pins .................................................................................................................................
Pins Other Than Port Pins ...................................................................................................
I/O Circuits of Pins and Recommended Connections of Unused Pins .........................
11
11
12
13
2. MEMORY SPACE ............................................................................................................................ 16
2.1 Memory Size Select Register (IMS) .................................................................................... 17
2.2 Internal Extension RAM Size Select Register (IXS) ......................................................... 18
3. FEATURES OF PERIPHERAL HARDWARE FUNCTIONS ..........................................................
3.1 Ports ........................................................................................................................................
3.2 Clock Generation Circuit .....................................................................................................
3.3 Timers .....................................................................................................................................
3.4 Buzzer Output Control Circuit .............................................................................................
3.5 A/D Converter ........................................................................................................................
3.6 Serial Interface ......................................................................................................................
3.7 PLL Frequency Synthesizer ................................................................................................
3.8 Frequency Counter ...............................................................................................................
19
19
20
20
22
23
24
26
27
4. INTERRUPT FUNCTION ................................................................................................................. 28
5. STANDBY FUNCTION .................................................................................................................... 31
6. RESET FUNCTION ......................................................................................................................... 31
7. INSTRUCTION SET ........................................................................................................................ 32
8. ELECTRICAL SPECIFICATIONS ................................................................................................... 35
9. PACKAGE DRAWING ..................................................................................................................... 44
10. RECOMMENDED SOLDERING CONDITIONS ............................................................................. 46
APPENDIX A. DEVELOPMENT TOOLS ............................................................................................. 47
APPENDIX B. RELATED DOCUMENTS ............................................................................................ 49
10
Data Sheet U14126EJ1V0DS00
µPD178023, 178024
1. PIN FUNCTION LIST
1.1 Port Pins
Pin Name
P00-P04
I/O
I/O
P05, P06
Function
At Reset
Port 0.
7-bit I/O port.
Can be set in input or output mode in 1-bit units.
Input
INTP0-INTP4
—
P10-P15
Input
Port 1.
6-bit input port.
Input
P30-P32
I/O
Port 3.
8-bit I/O port.
Input
P33
Shared by:
ANI0-ANI5
—
TI50
Can be set in input or output mode in 1-bit units.
P34
TI51
P35
—
P36
BEEP0
P37
—
P40-47
I/O
Port 4.
8-bit I/O port.
Can be set in input or output mode in 1-bit units.
Internal pull-up resistors can be specified in software.
Interrupt function by key input is provided.
Input
—
P50-P57
I/O
Port 5.
8-bit I/O port.
Can be set in input or output mode in 1-bit units.
Input
—
P60-P67
I/O
Port 6.
8-bit I/O port.
Input
—
Can be set in input or output mode in 1-bit units.
P70
I/O
P71
Port 7.
8-bit I/O port.
Can be set in input or output mode in 1-bit units.
Input
SI3
SO3
P72
SCK3
P73
—
P74
RXD0
P75
TXD0
P76
SDA0
P77
SCL0
P120-P125
I/O
Port 12.
6-bit I/O port.
Can be set in input or output mode in 1-bit units.
Input
P130
Output
Port 13.
3-bit output port.
N-ch open-drain output port (12 V withstand)
Low-level
output
P131
P132
—
TO50
TO51
—
Data Sheet U14126EJ1V0DS00
11
µPD178023, 178024
1.2 Pins Other Than Port Pins
Pin Name
I/O
Function
At Reset
Shared by:
INTP0-INTP4
Input
External maskable interrupt input whose valid edge
(rising edge, falling edge, or both rising and falling edges)
can be specified.
Input
P00-P04
SI3
Input
Serial data input to serial interface.
Input
P70
SO3
Output
Serial data output from serial interface.
Input
P71
SDA0
I/O
Serial data input/output to/from
serial interface.
Input
P76
SCK3
I/O
Serial clock input/output to/from serial interface.
Input
P72
SCL0
N-ch open drain I/O
N-ch open drain I/O
RXD0
Input
Serial data input to asynchronous serial interface (UART0).
TXD0
Output
Serial data output from asynchronous serial interface (UART0).
TI50
Input
External count clock input to 8-bit timer (TM50).
TI51
P77
Input
P74
P75
Input
P33
External count clock input to 8-bit timer (TM51).
TO50
Output
TO51
8-bit timer (TM50) output.
8-bit timer (TM51) output.
P34
Low-level
output
P130
P131
BEEP0
Output
Buzzer output.
Input
P36
ANI0-ANI5
Input
Analog input to A/D converter.
Input
P10-P15
EO0, EO1
Output
Error out output from charge pump of PLL frequency
–
–
–
–
synthesizer.
VCOL
Input
VCOH
Inputs local oscillation frequency of PLL (in HF and MF modes).
Inputs local oscillation frequency of PLL (in VHF mode).
AMIFC
Input
FMIFC
Input to AM intermediate frequency counter.
Input
–
Input to FM or AM intermediate frequency counter.
RESET
Input
System reset input.
–
–
X1
Input
Connection of crystal resonator for system clock oscillation.
–
–
X2
–
–
–
REGOSC
–
Regulator for oscillator. Connect this pin to GND via 0.1-µF
capacitor.
–
–
REGCPU
–
Regulator for CPU power supply. Connect this pin to GND
via 0.1-µF capacitor.
–
–
VDD
–
Positive power supply.
–
–
GND
–
Ground.
–
–
VDDPORT
–
Port power supply.
–
–
GNDPORT
–
Port ground.
–
–
VDDPLLNote
–
PLL positive power supply.
–
–
GNDPLLNote
–
PLL ground.
–
–
IC
–
Internally connected. Directly connect this pin to GND.
–
–
Note
12
Connect a capacitor of about 1000 pF between the VDDPLL and GNDPLL pins.
Data Sheet U14126EJ1V0DS00
µPD178023, 178024
1.3 I/O Circuits of Pins and Recommended Connections of Unused Pins
Table 1-1 shows the types of the I/O circuits of the respective pins and the recommended connections of the pins
when they are not used. For the configuration of the I/O circuit of each pin, refer to Figure 1-1.
Table 1-1. I/O Circuit Type of Each Pin
Pin Name
P00/INTP0-P04/INTP4
I/O Circuit Type
I/O
Recommended Connection of Unused Pin
8
I/O
Set these pins in general-purpose input mode in software, and connect
each of them to VDD, VDDPORT, GND, or GNDPORT via resistor.
P10/ANI0-P15/ANI5
25
Input
Connect each of them to VDD, VDDPORT, GND, or GNDPORT via resistor.
P30-P32
5
I/O
P33/TI50
5-K
Set these pins in general-purpose input mode in software, and output
low-level signal. Leave unconnected.
P05, P06
P34/TI51
P35
5
P36/BEEP0
P37
P40-P47
5-A
Set these pins in general-purpose input mode in software, and connect each
of them to GND or GNDPORT via resistor.
P50-P57
5
Set these pins in general-purpose input mode in software, and connect each
of them to VDD, VDDPORT, GND, or GNDPORT via resistor.
P60-P67
5
Set these pins in general-purpose input mode in software, and output
low-level signal. Leave unconnected.
P70/SI3
5-K
P71/SO3
5
Set these pins in general-purpose input mode in software, and connect each
of them to VDD, VDDPORT, GND, or GNDPORT via resistor.
P72/SCK3
5-K
P73
5
P74/RXD0
5-K
P75/TXD0
5
P76/SDA0
10-D
P77/SCL0
P120-P125
5
P130/TO50
19
Output
Set these pins to low-level output in software and leave unconnected.
EO0, EO1
DTS-EO1
Output
Leave unconnected.
VCOL, VCOH
DTS-AMP
Input
Disable PLL in software and select pull-down.
P131/TO51
P132
AMIFC, FMIFC
Set these pins in general-purpose input port mode in software and connect
each of them to VDD, VDDPORT, GND, or GNDPORT via resistor.
REGOSC, REGCPU
RESET
VDDPLL
GNDPLL
–
2
–
Connect these pins to GND via 0.1-µF capacitor.
Input
–
–
–
Connect this pin to VDD.
Directly connect these pins to GND or GNDPORT.
IC
Data Sheet U14126EJ1V0DS00
13
µPD178023, 178024
Figure 1-1. I/O Circuits of Respective Pins (1/2)
Type 2
Type 5
VDD
Data
P-ch
IN/OUT
IN
Output
disable
Schmitt trigger input with hysteresis characteristics
Type 5-A
N-ch
Input
enable
Type 5-K
VDD
VDD
Pullup
enable
Data
Data
P-ch
IN/OUT
P-ch
IN/OUT
Output
disable
P-ch
VDD
Output
disable
N-ch
N-ch
Input
enable
Input
enable
Type 8
Type 10-D
VDD
VDD
Data
Data
P-ch
P-ch
IN/OUT
IN/OUT
Output
disable
N-ch
Open drain
output disable
N-ch
Input
enable
Remark VDD and GND are the positive power supply and ground pins for all port pins. Take VDD and GND as
VDDPORT and GNDPORT.
14
Data Sheet U14126EJ1V0DS00
µPD178023, 178024
Figure 1-1. I/O Circuits of Respective Pins (2/2)
Type 19
Type DTS-EO1
VDDPLL
OUT
P-ch
DW
N-ch
OUT
UP
N-ch
GNDPLL
Type DTS-AMP
Type 25
VDDPLL
P-ch
Comparator
+
–
N-ch
VREF (Threshold voltage)
IN
IN
Input
enable
Note
GNDPLL
Note
This switch is selectable in software only for the VCOL and VCOH pins.
Remark VDD and GND are the positive power supply and ground pins for all port pins. Take VDD and GND as
VDDPORT and GNDPORT.
Data Sheet U14126EJ1V0DS00
15
µPD178023, 178024
2. MEMORY SPACE
Figure 2-1 shows the memory map of the µPD178023, 178024.
Figure 2-1. Memory Map
FFFFH
Special function registers
(SFR)
256 × 8 bits
FF0 0H
FEFFH
FEE 0H
FEDFH
General-purpose
registers
32 × 8 bits
Internal high-speed RAMNote
nnn nH
mmm m H
mm mm H − 1
Program area
Data memory
space
100 0H
0FFFH
CALLF entry area
Cannot be used
080 0H
07FFH
Program area
008 0H
007 FH
n n n nH+1
nnn nH
Program
memory space
CALLT table area
004 0H
003 FH
Internal ROM
Note
Vector table area
000 0H
Note
000 0H
The internal ROM and internal high-speed RAM capacities differ depending on the model (refer to the
table below).
Target Model Name
16
Internal ROM End Address
nnnnH
Internal High-Speed RAM First Address
mmmmH
µPD178023
5FFFH
FB00H
µPD178024
7FFFH
FB00H
Data Sheet U14126EJ1V0DS00
µPD178023, 178024
2.1 Memory Size Select Register (IMS)
The memory size select register (IMS) sets the internal memory capacity.
Set the µPD178023, µPD178024 to C6H, C8H respectively.
Use an 8-bit memory manipulation instruction to set the IMS.
This register is set to CFH at reset.
Caution Be sure to set the IMS to C6H or C8H as the program initial setting. The IMS set value changes
to CFH when reset. Therefore, set C6H or C8H again after reset.
Figure 2-2. Format of Memory Size Select Register (IMS)
Symbol
7
6
5
4
IMS RAM2 RAM1 RAM0
0
3
2
1
ROM3 ROM2 ROM1 ROM0
RAM2 RAM1 RAM0
1
1
0
Others
0
At reset
R/W
FFF0H
CFH
R/W
Selects Internal High-speed RAM Capacity
1024 bytes
Setting prohibited
RAM3 RAM2 RAM1 RAM0
Selects Internal ROM Capacity
0
1
1
0
24K bytes
1
0
0
0
32K bytes
Others
Address
Setting prohibited
Table 2-1 indicates the setting of IMS.
Table 2-1. Set Value of Memory Size Select Register (IMS)
Targeted Model
Set Value of IMS
µPD178023
C6H
µPD178024
C8H
Data Sheet U14126EJ1V0DS00
17
µPD178023, 178024
2.2 Internal Extension RAM Size Select Register (IXS)
The internal extension RAM size select register (IXS) sets the internal extension RAM capacity.
Use the µPD178023, µPD178024 with the initial value (0CH).
Use an 8-bit memory manipulation instruction to set the IXS.
This register is set to 0CH at reset.
Caution Do not assign a value other than that the value at reset.
Figure 2-3. Format of Internal Extension RAM Size Select Register (IXS)
Symbol
7
6
5
IXS
0
0
0
4
3
2
1
IXRAM4 IXRAM3 IXRAM2 IXRAM1 IXRAM0
IXRAM4 IXRAM3 IXRAM2 IXRAM1 IXRAM0
0
1
0
1
0
0
Others
Address
At reset
R/W
FFF4H
0CH
R/W
Selects Internal Extension RAM Capacity
0 byte
Setting prohibited
Table 2-2 indicates the setting of IXS.
Table 2-2. Set Value of Internal Extension RAM Size Select Register
Targeted Model
µPD178023, 178024
18
Set Value of IXS
0CH
Data Sheet U14126EJ1V0DS00
µPD178023, 178024
3. FEATURES OF PERIPHERAL HARDWARE FUNCTIONS
3.1 Ports
The following three types of ports are available:
• CMOS input (port 1)
:
6 pins
• CMOS I/O (ports 0, 3 - 7, and 12) : 53 pins
• N-ch open-drain output (port 13)
Total
:
3 pins
: 62 pins
Table 3-1. Port Functions
Name
Pin Name
Function
Port 0
P00-P06
I/O port. Can be set in input or output mode in 1-bit units.
Port 1
P10-P15
Input-only port
Port 3
P30-P37
I/O port. Can be set in input or output mode in 1-bit units.
Port 4
P40-P47
I/O port. Can be set in input or output mode in 1-bit units.
Port 5
P50-P57
I/O port. Can be set in input or output mode in 1-bit units.
Port 6
P60-P67
I/O port. Can be set in input or output mode in 1-bit units.
Port 7
P70-P77
I/O port. Can be set in input or output mode in 1-bit units.
Port 12
P120-P125
I/O port. Can be set in input or output mode in 1-bit units.
Port 13
P130-P132
N-ch open-drain output port
Data Sheet U14126EJ1V0DS00
19
µPD178023, 178024
3.2 Clock Generation Circuit
The instruction execution time can be changed as follows:
• 0.45 µs/0.89 µs/1.78 µs/3.56 µs/7.11 µs (system clock: 4.5-MHz crystal resonator) Note
Figure 3-1. Block Diagram of Clock Generation Circuit
Prescaler
X2
System
clock
oscillator
Clock to other than
peripheral hardware
Prescaler
fX
fX
2
fX
fX
4
f X 23 2
2
2
Selector
X1
Standby
control
circuit
Wait
control
circuit
CPU clock
(fCPU)
3
STOP
0
0
0
0
0
PCC2 PCC1 PCC0
Processor clock control register (PCC)
Internal bus
3.3 Timers
Four timer channels are provided.
• Basic timer
: 1 channel
• 8-bit timer/event counter : 2 channels
• Watchdog timer
: 1 channel
Figure 3-2. Block Diagram of Basic Timer
4.5 MHz
20
Divider circuit
Data Sheet U14126EJ1V0DS00
INTBTM0
µPD178023, 178024
Figure 3-3. Block Diagram of 8-Bit Timer/Event Counter 50
Internal bus
Selector
Coincidence
Selector
INTTM50
S
Q
INV
8-bit counter 50 OVF
(TM50)
Selector
TI50/P33
fX/2
fX/23
fX/25
fX/27
fX/29
fX/211
Mask circuit
8-bit compare
register 50 (CR50)
R
TO50/P130
Clear
Output latch
(P130)
S
3
Level
inversion
R
Selector
TCE50 TMC506 TMC504 LVS50 LVR50 TMC501 TOE50
Timer mode control
register 50 (TMC50)
TCL502 TCL501 TCL500
Timer clock select
register 50 (TCL50)
Internal bus
Figure 3-4. Block Diagram of 8-Bit Timer/Event Counter 51
Coincidence
Selector
TI51/P34
fX/2
fX/23
fX/25
fX/27
fX/29
fX/211
Selector
S
Q
INV
8-bit counter 51 OVF
(TM51)
R
INTTM51
Selector
8-bit compare
register 51 (CR51)
Mask circuit
Internal bus
TO51/P131
Clear
S
3
R
Selector
TCL512 TCL511 TCL510
Timer clock select
register 51 (TCL51)
Output latch
(P131)
Level
inversion
TCE51 TMC516 TMC514 LVS51 LVR51 TMC511 TOE51
Timer mode control
register 51 (TMC51)
Internal bus
Data Sheet U14126EJ1V0DS00
21
µPD178023, 178024
Figure 3-5. Block Diagram of Watchdog Timer
fX/28
Clock input
control circuit
INTWDT
Divided clock
select circuit
Divider circuit
Output
control
circuit
RESET
RUN
Division mode
select circuit
3
WDT mode signal
OSTS2 OSTS1 OSTS0
Oscillation stabilization
time select register (OSTS)
WDCS2 WDCS1 WDCS0
Watchdog timer clock
select register (WDCS)
RUN
WDTM4 WDTM3
Watchdog timer mode
register (WDTM)
Internal bus
3.4 Buzzer Output Control Circuit
The buzzer output frequency is selected as follows.
• BEEP0 ... 1 kHz/1.5 kHz/3 kHz/4 kHz
Figure 3-6. Block Diagram of Buzzer Output Control Circuit (BEEP0)
1 kHz
1.5 kHz
3 kHz
Selector
4 kHz
BEEP0/P36
Output latch
(P36)
PM36
BEEP BEEP BEEP BEEP0 clock select
CL02 CL01 CL00 register (BEEPCL0)
Internal bus
22
Data Sheet U14126EJ1V0DS00
µPD178023, 178024
3.5 A/D Converter
An A/D converter with a resolution of 8 bits × 6 channels is provided.
Figure 3-7. Block Diagram of A/D Converter
ANI0/P10
Selector
ANI2/P12
ANI3/P13
Tap selector
Sample & hold circuit
ANI1/P11
Voltage comparator
ANI4/P14
ANI5/P15
VDD
ADCS3
Successive
approximation
register (SAR)
GND
INTAD3
Control
circuit
A/D conversion result
register 3 (ADCR3)
4
ADS33 ADS32 ADS31 ADS30
ADCS3
0
FR32 FR31 FR30
Analog input channel
specification register 3 (ADS3)
0
0
0
Control
circuit
Voltage
comparator Power-fail comparison threshold
value register 3 (PFT3)
PFEN3 PFCM3 PFHRM3
A/D converter mode
register 3 (ADM3)
Power-fail comparison mode
register 3 (PFM3)
Internal bus
Data Sheet U14126EJ1V0DS00
23
µPD178023, 178024
3.6 Serial Interface
The µPD178023 and 178024 have three serial interface channels.
• Serial interface (IIC0)
• Serial interface (SIO3)
• Serial interface (UART0)
Figure 3-8. Block Diagram of Serial Interface (IIC0)
Internal bus
IIC status register 0
(IICS0)
MSTS0 ALD0 EXC0 COI0 TRC0 ACKD0 STD0 SPD0
IIC control register 0
(IICC0)
Slave address
register 0 (SVA0)
SDA0/P76
Noise elimination
circuit
IICE0 LREL0 WREL0 SPIE0 WTIM0 ACKE0 STT0
SPT0
Coincidence
CLEAR
signal
SET
SO0 latch
IIC shift register 0
D Q
(IIC0)
CL01,
CL00
Data hold
time correction
circuit
N-ch opendrain output
ACK detection
circuit
Wake up control
circuit
ACK detection circuit
Start condition
detection circuit
Stop condition
detection circuit
SCL0/P77
Noise elimination
circuit
Interrupt request
signal generator
Serial clock counter
Serial clock wait
control circuit
Serial clock control circuit
fX
Prescaler
CLD0 DAD0 SMC0 DFC0 CL01 CL00
IIC transfer clock select
register 0 (IICCL0)
Internal bus
24
Data Sheet U14126EJ1V0DS00
INTIIC0
µPD178023, 178024
Figure 3-9. Block Diagram of Serial Interface (SIO3)
Internal bus
8
Serial I/O shift
registe 3 (SIO3)
SI3/P70
PM71
SO3/P71
P71 output latch
Interrupt request
signal generation
circuit
Serial clock
counter
SCK3/P72
Serial clock
control circuit
PM72
INTCSI3
4
fX/25
fX/2
fX/26
Selector
P72 output latch
Figure 3-10. Block Diagram of Serial Interface (UART0)
Internal bus
Asynchronous serial interface
mode register 0 (ASIM0)
Receive buffer
register 0
(RXB0)
TXE0 RXE0 PS01 PS00 CL0
SL0 ISRM0
0
Asynchronous serial interface
status register 0 (ASIS0)
RXD0/P74
TXD0/P75
Receive shift
register 0
(RX0)
Reception
control circuit
PM75
(parity check)
P75 output latch
PE0
FE0 OVE0
Transmit shift
register 0
(TXS0)
INTSER0
INTSR0
Transmission
control circuit
(parity append)
INTST0
Baud rate
generator
Data Sheet U14126EJ1V0DS00
fX/2-fX/28
25
µPD178023, 178024
3.7 PLL Frequency Synthesizer
Figure 3-11. Block Diagram of PLL Frequency Synthesizer
Internal Bus
PLL Mode
Select Register
(PLLMD)
VCOH VCOL PLL PLL
DMD DMD MD1 MD0
2
PLL
Data Transfer
Register (PLLNS)
PLL Data Register
(PLLRL, PLLRH, PLLR0)
2
fN
VCOH
Mixer
Input Select
Block
Programmable
Divider
VCOL
Voltage
Control
Generator
Note
PLL
NS0
4.5 MHz
fr
Phase
Comparator
( φ -DET)
Reference
Frequency
Generator
Unlock
F/F
4
Note
Lowpass
Filter
Note
26
PLL PLL PLL PLL
PLL
RF3 RF2 RF1 RF0
UL0
PLL Reference
PLL Unlock
F/F Judge Register
Mode Register
(PLLUL)
(PLLRF)
Internal Bus
External circuit.
Data Sheet U14126EJ1V0DS00
EO1
Charge
Pump
EO0
µPD178023, 178024
3.8 Frequency Counter
Figure 3-12. Block Diagram of Frequency Counter
2
Gate time
control block
FMIFC
IF counter
register
(IFC)
block
Start/stop
control
block
Input select
block
AMIFC
2
IFC IFC IFC IFC
MD1 MD0 CK1 CK0
IF counter
mode select
register (IFCMD)
IFC IFC
ST RES
IFC
JG0
IF counter
gate judge
register (IFCJG)
IF counter
control
register (IFCCR)
Internal bus
Data Sheet U14126EJ1V0DS00
27
µPD178023, 178024
4. INTERRUPT FUNCTION
The µPD178023 and 178024 have the following three types and 17 sources of interrupts:
• Non-maskable : 1Note
• Maskable
: 16Note
• Software
: 1
Note
Two types of watchdog interrupt sources (INTWDT), non-maskable and maskable, are available, and
either of them can be selected.
Table 4-1. Interrupt Sources
Interrupt Source
Name
Non-maskable
–
INTWDT
Overflow of watchdog timer
(when watchdog timer mode 1 is selected)
Maskable
0
INTWDT
Overflow of watchdog timer
(when interval timer mode is selected)
1
INTP0
Pin input edge detection
2
INTP1
0008H
3
INTP2
000AH
4
INTP3
000CH
5
INTP4
000EH
6
INTKY
Detection of key input of port 4
7
INTIIC0
End of transfer by serial interface IIC0
0012H
8
INTBTM0 Generation of basic timer match signal
0014H
9
INTAD3
0016H
10
–
11
INTCSI3
12
INTTM50
Trigger
Internal/
External
Vector
Table
Address
Default
PriorityNote 1
Interrupt Type
Internal
End of transfer by serial interface SIO3
(A)
(B)
External
Internal
End of conversion by A/D converter
–
0004H
Basic
Configuration
TypeNote 2
–
Internal
Generation of coincidence signal of 8-bit
0006H
0010H
(C)
(B)
0018HNote 3
001AH
–
(B)
001CH
timer/event counter 50
Software
13
INTTM51
Generation of coincidence signal of 8-bit
timer/event counter 51
001EH
14
INTSER0 Reception error of serial interface UART0
0020H
15
INTSR0
End of reception by serial interface UART0
0022H
16
INTST0
End of transmission by serial interface UART0
0024H
–
BRK
Execution of BRK instruction
–
003EH
(D)
Notes 1. If two or more maskable interrupts occur at the same time, they are acknowledged or kept pending
according to their default priorities. The default priority 0 is the highest, while 16 is the lowest.
2. (A) to (D) under the heading Basic Configuration Type corresponds to (A) to (D) in Figure 4-1.
3. There are no interrupt sources corresponding to vector addresses 0018H.
28
Data Sheet U14126EJ1V0DS00
µPD178023, 178024
Figure 4-1. Basic Configuration of Interrupt Function (1/2)
(A) Internal non-maskable interrupt
Internal bus
Interrupt
request
Vector table
address generation
circuit
Priority control
circuit
Standby release
signal
(B) Internal maskable interrupt
Internal bus
MK
Interrupt
request
IE
PR
ISP
Priority control
circuit
IF
Vector table
address generation
circuit
Standby release
signal
(C) External maskable interrupt
Internal bus
External interrupt rising/
falling edge enable
registers (EGP, EGN)
Interrupt
request
Edge detection
circuit
MK
IF
IE
PR
Priority control
circuit
ISP
Vector table
address generation
circuit
Standby release
signal
Data Sheet U14126EJ1V0DS00
29
µPD178023, 178024
Figure 4-1. Basic Configuration of Interrupt Function (2/2)
(D) Software interrupt
Internal bus
Interrupt
request
Remark IF
IE
Priority control
circuit
: Interrupt request flag
: Interrupt enable flag
ISP : In-service priority flag
MK : Interrupt mask flag
PR : Priority specification flag
30
Data Sheet U14126EJ1V0DS00
Vector table
address generation
circuit
µPD178023, 178024
5. STANDBY FUNCTION
There are the following two standby functions to reduce the system power consumption.
• HALT mode : The CPU operating clock is stopped.
The average consumption current can be reduced by intermittent operation in combination with
the normal operating mode.
• STOP mode : The system clock oscillation is stopped. All operations by the system clock are stopped and
current consumption can be considerably reduced.
Figure 5-1. Standby Function
System Clock Operation
Interrupt
Request
HALT
Instruction
STOP
Instruction
Interrupt
Request
STOP Mode
(System clock
oscillation stopped)
HALT Mode
(Clock supply to CPU is
stopped, oscillation
continued)
6. RESET FUNCTION
There are the following three reset methods.
• External reset input by RESET pin
• Internal reset by watchdog timer runaway time detection
• Internal reset by Power-On Clear (POC).
Data Sheet U14126EJ1V0DS00
31
µPD178023, 178024
7. INSTRUCTION SET
(1) 8-bit instructions
MOV, XCH, ADD ADDC, SUB, SUBC, AND, OR, XOR, CMP, MULU, DIVUW, INC, DEC, ROR,
ROL, RORC, ROLC, ROR4, ROL4, PUSH, POP, DBNZ
Second
Operand
First
Operand
[HL + byte]
#byte
A
r
Note
sfr
saddr
!addr16
PSW
[DE]
[HL + B]
$addr16
1
None
[HL + C]
A
ADD
ADDC
SUB
SUBC
AND
OR
XOR
CMP
r
MOV
MOV
XCH
ADD
ADDC
SUB
SUBC
AND
OR
XOR
CMP
MOV
XCH
MOV
XCH
ADD
ADDC
SUB
SUBC
AND
OR
XOR
CMP
MOV
XCH
ADD
ADDC
SUB
SUBC
AND
OR
XOR
CMP
MOV
MOV
XCH
MOV
XCH
ADD
ADDC
SUB
SUBC
AND
OR
XOR
CMP
MOV
XCH
ADD
ADDC
SUB
SUBC
AND
OR
XOR
CMP
ROR
ROL
RORC
ROLC
MOV
ADD
ADDC
SUB
SUBC
AND
OR
XOR
CMP
INC
DEC
DBNZ
B,C
sfr
MOV
MOV
saddr
MOV
ADD
ADDC
SUB
SUBC
AND
OR
XOR
CMP
MOV
!addr16
PSW
[HL]
DBNZ
INC
DEC
MOV
MOV
MOV
PUSH
POP
MOV
ROR4
ROL4
[DE]
[HL]
[HL + byte]
[HL + B]
[HL + C]
MOV
X
MULU
C
DIVUW
Note
32
Except r = A
Data Sheet U14126EJ1V0DS00
µPD178023, 178024
(2) 16-bit instructions
MOVW, XCHW, ADDW, SUBW, CMPW, PUSH, POP, INCW, DECW
Second Operand
First Operand
#word
AX
ADDW
SUBW
CMPW
rp
MOVW
AX
rp Note
MOVW
XCHW
sfrp
MOVW
MOVW Note
saddrp
!addr16
MOVW
MOVW
SP
None
MOVW
INCW
DECW
PUSH
POP
sfrp
MOVW
MOVW
saddrp
MOVW
MOVW
!addr16
SP
Note
MOVW
MOVW
MOVW
Only when rp = BC, DE or HL
Data Sheet U14126EJ1V0DS00
33
µPD178023, 178024
(3) Bit manipulation instructions
MOV1, AND1, OR1, XOR1, SET1, CLR1, NOT1, BT, BF, BTCLR
Second Operand
First Operand
A.bit
sfr.bit
saddr.bit
PSW.bit
[HL].bit
CY
$addr16
None
A.bit
MOV1
BT
BF
BTCLR
SET1
CLR1
sfr.bit
MOV1
BT
BF
BTCLR
SET1
CLR1
saddr.bit
MOV1
BT
BF
BTCLR
SET1
CLR1
PSW.bit
MOV1
BT
BF
BTCLR
SET1
CLR1
[HL].bit
MOV1
BT
BF
BTCLR
SET1
CLR1
CY
MOV1
AND1
OR1
XOR1
MOV1
AND1
OR1
XOR1
MOV1
AND1
OR1
XOR1
MOV1
AND1
OR1
XOR1
MOV1
AND1
OR1
XOR1
(4) Call instruction/branch instructions
CALL, CALLF, CALLT, BR, BC, BNC, BZ, BNZ, BT, BF, BTCLR, DBNZ
Second Operand
First Operand
Basic instruction
AX
BR
!addr16
CALL
BR
!addr11
CALLF
[addr5]
CALLT
$addr16
BR, BC, BNC
BZ, BNZ
Compound
BT, BF
instruction
BTCLR
DBNZ
(5) Other instructions
ADJBA, ADJBS, BRK, RET, RETI, RETB, SEL, NOP, EI, DI, HALT, STOP
34
Data Sheet U14126EJ1V0DS00
SET1
CLR1
NOT1
µPD178023, 178024
8. ELECTRICAL SPECIFICATIONS
Absolute Maximum Ratings (TA = 25 °C)
Parameter
Rating
Unit
VDD
–0.3 to +6.0
V
VDDPORT
–0.3 to VDD + 0.3
V
VDDPLL
–0.3 to VDD + 0.3
V
Input voltage
VI
–0.3 to +11.0
V
Output voltage
VO
–0.3 to VDD + 0.3
V
Supply voltage
Symbol
Conditions
Excluding P130 to P132
Output breakdown
voltage
VBDS
P130-P132
N-ch open drain
16
V
Analog input voltage
VAN
P10-P15
Analog input pin
–0.3 to VDD + 0.3
V
High-level output
IOH
1 pin
–8
mA
Total of P00-P06, P30-P37, P54-P57, P60-P67,
and P120-P125
–15
mA
Total of P40-P47, P50-P53, and P70-P77
–15
mA
1 pin
Peak value
16
mA
r.m.s
8
mA
Total of P00-P06, P30-P37, P40-P47,
Peak value
30
mA
P50-P57, P60-P67, P70-P77,
r.m.s
15
mA
current
Low-level output
IOL Note
current
P120-P125, and P130-P132
Operating temperature
TA
–40 to +85
°C
Storage temperature
Tstg
–55 to +125
°C
Note
Calculate the r.m.s as follows: [r.m.s] = [Peak value] x √Duty
Caution If the rated value of even one of the above parameters is exceeded even momentarily, the quality
of the product may be degraded. The absolute maximum ratings, therefore, are the values
exceeding which the product may be physically damaged. Be sure to use the product with these
ratings never being exceeded.
Remark Unless otherwise specified, the characteristics of a multiplexed pin are the same as those of the
corresponding port pin.
Recommended Supply Voltage Ranges (TA = –40 to +85 °C)
Parameter
Supply voltage
Symbol
Conditions
MIN.
TYP.
MAX.
Unit
VDD1
When CPU and PLL are operating
4.5
5.0
5.5
V
VDD2
When CPU is operating and PLL is stopped
3.5
5.0
5.5
V
Data retention voltage
VDDR
When crystal oscillation stops
2.3
5.5
V
Output breakdown
voltage
VBDS
P130-P132 (N-ch open drain)
15
V
Data Sheet U14126EJ1V0DS00
35
µPD178023, 178024
DC Characteristics (TA = –40 to +85 °C, VDD = 3.5 to 5.5 V) (1/2)
Parameter
High-level input
voltage
Low-level input
voltage
High-level output
voltage
Low-level output
Symbol
MIN.
TYP.
MAX.
Unit
VIH1
P10-P15, P30-P32, P35-P37, P40-P47, P50-P57,
P60-P67, P71, P73, P120-P125
0.7 VDD
VDD
V
VIH2
P00-P06, P33, P34, P70, P72, P74-P75, RESET
0.8 VDD
VDD
V
VIH3
P76, P77
(N-ch open-drain I/O)
4.5 V ≤ VDD ≤ 5.5 V
0.7 VDD
VDD
V
VIL1
P10-P15, P30-P32, P35-P37, P40-P47, P50-P57,
P60-P67, P71, P73, P120-P125
0
0.3 VDD
V
VIL2
P00-P06, P33, P34, P70, P72, P74-P75, RESET
0
0.2 VDD
V
VIL3
P76, P77
(N-ch open-drain I/O)
4.5 V ≤ VDD ≤ 5.5 V
0
0.3 VDD
V
VOH1
P00-P06, P30-P37,
P40-P47, P50-P57,
4.5 V ≤ VDD ≤ 5.5 V,
IOH = –1 mA
VDD – 1.0
V
P60-P67, P70-P77,
P120-P125
3.5 V ≤ VDD < 4.5 V,
IOH = –100 µA
VDD – 0.5
V
VOH2
EO0, EO1
VDD = 4.5 to 5.5 V,
IOH = –3 mA
VDD – 1.0
V
VOL1
P00-P06, P30-P37,
P40-47, P50-57, P60-P67,
4.5 V ≤ VDD ≤ 5.5 V,
IOL = 1 mA
1.0
V
P70-P75, P120-P125
3.5 V ≤ VDD < 4.5 V,
IOL = 100 µA
0.5
V
VOL2
EO0, EO1
VDD = 4.5 to 5.5 V,
IOL = 3 mA
1.0
VOL3
P76, P77
(N-ch open-drain I/O)
4.5 V ≤ VDD ≤ 5.5 V
IOL = 3 mA
0.4
V
4.5 V ≤ VDD ≤ 5.5 V
IOL = 6 mA
0.6
V
3
µA
voltage
High-level input
leakage current
Test Conditions
ILH
P00-P06,
P30-P37,
P50-P57,
P70-P77,
RESET
P10-P15,
P40-P47,
P60-P67,
P120-P125,
VIN = VDD
Remark Unless otherwise specified, the characteristics of a multiplexed pin are the same as those of the
corresponding port pin.
36
Data Sheet U14126EJ1V0DS00
µPD178023, 178024
DC Characteristics (TA = –40 to +85 °C, VDD = 3.5 to 5.5 V) (2/2)
Parameter
Symbol
Low-level input
leakage current
ILIL
Test Conditions
P00-P06,
P30-P37,
P50-P57,
P70-P77,
RESET
P10-P15,
P40-P47,
P60-P67,
P120-P125,
MIN.
TYP.
MAX.
Unit
VIN = 0 V
–3
µA
Output off
ILOH1
P130-P132
VOUT = 15 V
–3
µA
leakage current
ILOL1
P130-P132
VOUT = 0 V
3
µA
ILOH2
P76, P77
(at N-ch open drain I/O)
VOUT = VDD
–3
µA
ILOL2
P76, P77
(at N-ch open drain I/O)
VOUT = 0 V
3
µA
ILOH3
EO0, EO1
VOUT = VDD
–3
µA
ILOL3
EO0, EO1
VOUT = 0 V
3
µA
IDD1
When CPU is operating and PLL is stopped.
Sine wave input to X1 pin
At fX = 4.5 MHz
VIN = VDD
4.0
20
mA
IDD2
In HALT mode with PLL stopped.
Sine wave input to X1 pin
At fX = 4.5 MHz
VIN = VDD
0.35
0.70
mA
5.5
V
Supply
currentNote
Data retention
VDDR1
When crystal resonator is oscillating
3.5
voltage
VDDR2
When crystal oscillation is
stopped
Power-failure detection
function
2.2
V
Data memory retained
2.0
V
VDDR3
Data retention
IDDR1
current
When crystal oscillation is
stopped
TA = 25 °C,
VDD = 5 V
IDDR2
Note
2.0
4.0
µA
2.0
20
µA
Excluding AVDD current and VDDPLL current.
Remarks 1. fX: System clock oscillation frequency
2. Unless otherwise specified, the characteristics of a multiplexed pin are the same as those of the
corresponding port pin.
Data Sheet U14126EJ1V0DS00
37
µPD178023, 178024
Reference Characteristics (TA = –40 to +85 °C, VDD = 4.5 to 5.5 V)
Parameter
Supply current
Symbol
IDD3
Conditions
MIN.
When CPU and PLL are operating.
Sine wave input to VCOH pin
At fIN = 160 MHz
VIN = 0.15 VP-P
TYP.
MAX.
8
Unit
mA
AC Characteristics
(1) Basic operation (TA = –40 to +85 °C, VDD = 3.5 to 5.5 V)
Parameter
Symbol
Cycle time
(minimum instruction
execution time)
TCY
TI50, TI51 input
frequency
fTI5
TI50, TI51 input
high-/low-level widths
tTIH5
tTIL5
Interrupt input
high-/low-level widths
tINTH
tINTL
RESET pin
low-level width
tRSL
38
Conditions
fX = 4.5 MHz
MIN.
0.44
INTP0-INTP4
Data Sheet U14126EJ1V0DS00
TYP.
MAX.
Unit
7.11
µs
2
MHz
200
ns
1
µs
10
µs
µPD178023, 178024
(2) Serial interface (TA = –40 to +85 °C, VDD = 3.5 to 5.5 V)
(a) Serial interface (IIC0)
I2C bus mode
Parameter
Symbol
Standard Mode
High-speed Mode
MIN.
MAX.
MIN.
MAX.
Unit
SCL0 clock frequency
fCLK
0
100
0
400
kHz
Bus free time (between stop and start
conditions)
tBUF
4.7
–
1.3
–
µs
Hold timeNote 1
tHD : STA
4.0
–
0.6
–
µs
SCL0 clock low-level width
tLOW
4.7
–
1.3
–
µs
SCL0 clock high-level width
tHIGH
4.0
–
0.6
–
µs
Start/restart condition setup time
tSU : STA
4.7
–
0.6
–
µs
Data hold
CBUS compatible master
tHD : DAT
5.0
–
–
–
µs
time
I 2C
–
0Note 2
0.9Note 3
µs
–
100Note 4
–
ns
1000
20+0.1CbNote 5
300
ns
–
300
20+0.1CbNote 5
300
ns
4.0
–
0.6
–
µs
0Note 2
bus
Data setup time
tSU : DAT
SDA0 and SCL0 signal rise time
tR
250
–
SDA0 and SCL0 signal fall time
tF
Stop condition setup time
tSU : STO
Pulse width of spike restrained by input filter
tSP
–
–
0
50
ns
Each bus line capacitative load
Cb
–
400
–
400
pF
Notes 1. The first clock pulse is generated at the start condition after this period.
2. The device needs to internally supply a hold time of at least 300 ns for the SDA0 signal to fill the
undefined area at the falling edge of the SCL0 (VIHmin. of the SCL0 signal).
3. Unless the device extends the low hold time (tLOW) of the SCL0 signal, it is necessary to fill only the
maximum data hold time (tHD : DAT).
4. The high-speed mode I2C bus can be used in the standard mode I2C bus system. In this case, satisfy
the following conditions:
• When the device does not extend the low hold time of the SCL0 signal
tSU : DAT ≥ 250 ns
• When the device extends the low hold time of the SCL0 signal
Send the next data bit to the SDA line before releasing the SCL0 line (tRmax. + tSU:DAT = 1000 + 250
= 1250 ns : in the standard mode I2C bus specification)
5. Cb: Total capacitance of one bus line (unit: pF)
Data Sheet U14126EJ1V0DS00
39
µPD178023, 178024
(b) Serial interface (SIO3)
(i) 3-wire serial I/O mode (SCK3 ... internal clock output)
Parameter
Symbol
Test Conditions
MIN.
TYP.
MAX.
Unit
SCK3 cycle time
tKCY1
800
ns
SCK3 high/low-level width
tKH1,
tKL1
tKCY1/2 – 50
ns
SI3 setup time (to SCK3↑)
tSIK1
100
ns
SI3 hold time (from SCK3↑)
tKSI1
400
ns
SCK3↓→ SO3 output delay time
Note
tKSO1
C = 100 pF
Note
300
ns
MAX.
Unit
C is the load capacitance of SCK3 and SO3 output line.
(ii) 3-wire serial I/O mode (SCK3 ... external clock input)
Parameter
Symbol
Test Conditions
MIN.
TYP.
SCK3 cycle time
tKCY2
800
ns
SCK3 high/low-level width
tKH2,
tKL2
400
ns
SI3 setup time (to SCK3↑)
tSIK2
100
ns
SI3 hold time (from SCK3↑)
tKSI2
400
ns
SCK3↓→ SO3 output delay time
tKSO2
SCK3 at rising or falling edge time
Note
C = 100 pF Note
tR2, tF2
300
ns
1000
ns
MAX.
Unit
38400
bps
C is the load capacitance of SO3 output line.
(d) Serial interface (UART0: Dedicated baud rate generator output)
Parameter
Symbol
Test Conditions
Transfer rate
40
Data Sheet U14126EJ1V0DS00
MIN.
TYP.
µPD178023, 178024
AC Timing Test Point (Excluding X1 Input)
0.8 VDD
0.2 VDD
0.8 VDD
0.2 VDD
Test Points
TI Timing
1/fTI5
tTIL5
tTIH5
TI50,TI51
Interrupt Input Timing
tINTL
tINTH
INTP0 to INTP4
RESET Input Timing
tRSL
RESET
Data Sheet U14126EJ1V0DS00
41
µPD178023, 178024
Serial Transfer Timing
I2C bus mode:
tLOW
tR
SCL0
tHD : DAT
tHIGH
tSU : DAT
tHD : STA
tF
tSU : STA
tHD : STA
tSP
tSU : STO
SDA0
tBUF
Stop
condition
Start
condition
Restart
condition
Stop
condition
3-wire serial I/O mode:
tKCYm
tKLm
tKHm
tFn
tRn
SCK3
tSIKm
SI3
tKSIm
Input Data
tKSOm
SO3
Output Data
Remark m = 1, 2
n=2
42
Data Sheet U14126EJ1V0DS00
µPD178023, 178024
A/D Converter Characteristics (TA = –40 to +85 °C, VDD = 4.5 to 5.5 V)
Parameter
Symbol
Conditions
Resolution
MIN.
TYP.
MAX.
Unit
8
8
8
bit
0.8
%
Total conversion
errorNote
Conversion time
tCONV
15.2
45.7
µs
Analog input voltage
VIAN
0
VDD
V
MAX.
Unit
Note
Excluding quantization error (±1/2LSB)
PLL Characteristics (TA = –40 to +85 °C, VDD = 4.5 to 5.5 V)
Parameter
Symbol
Conditions
MIN.
TYP.
Operating frequency
fIN1
VCOL pin, MF mode, sine wave input, VIN = 0.15 VP-P
0.5
3.0
MHz
fIN2
VCOL pin, HF mode, sine wave input, VIN = 0.15 VP-P
10
40
MHz
fIN3
VCOH pin, VHF mode, sine wave input, VIN = 0.15 VP-P
60
130
MHz
fIN4
VCOH pin, VHF mode, sine wave input, VIN = 0.3 VP-P
40
160
MHz
MAX.
Unit
IFC Characteristics (TA = –40 to +85 °C, VDD = 4.5 to 5.5 V)
Parameter
Symbol
Test Conditions
Operating frequency
fIN5
AMIFC pin, AMIF count mode, sine wave input,
VIN = 0.15 VP-P
0.4
0.5
MHz
fIN6
FMIFC pin, FMIF count mode, sine wave input,
VIN = 0.15 VP-P
10
11
MHz
fIN7
FMIFC pin, AMIF count mode, sine wave input,
VIN = 0.15 VP-P
0.4
0.5
MHz
Data Sheet U14126EJ1V0DS00
MIN.
TYP.
43
µPD178023, 178024
9. PACKAGE DRAWING
80-PIN PLASTIC QFP (14x20)
A
B
41
40
64
65
detail of lead end
S
C D
R
Q
25
24
80
1
F
G
J
I
H
M
K
P
M
N
S
L
NOTE
S
ITEM
Each lead centerline is located within 0.15 mm of
its true position (T.P.) at maximum material condition.
MILLIMETERS
A
23.6±0.4
B
20.0±0.2
C
14.0±0.2
D
17.6±0.4
F
1.0
G
0.8
H
0.37 +0.08
−0.07
I
J
0.15
0.8 (T.P.)
K
1.8±0.2
L
0.8±0.2
M
0.17 +0.08
−0.07
N
0.10
P
2.7±0.1
Q
0.1±0.1
R
5°±5°
S
3.0 MAX.
P80GF-80-3B9-5
44
Data Sheet U14126EJ1V0DS00
µPD178023, 178024
80-PIN PLASTIC QFP (14x14)
A
B
60
61
41
40
detail of lead end
S
C
D
R
Q
80
1
21
20
F
J
G
H
I
M
P
K
S
N
S
L
M
NOTE
Each lead centerline is located within 0.13 mm of
its true position (T.P.) at maximum material condition.
ITEM
MILLIMETERS
A
17.20±0.20
B
14.00±0.20
C
14.00±0.20
D
17.20±0.20
F
0.825
G
0.825
H
I
0.32±0.06
0.13
J
0.65 (T.P.)
K
1.60±0.20
L
0.80±0.20
M
0.17 +0.03
−0.07
N
P
0.10
1.40±0.10
Q
0.125±0.075
R
3° +7°
−3°
S
1.70 MAX.
P80GC-65-8BT-1
Data Sheet U14126EJ1V0DS00
45
µPD178023, 178024
10. RECOMMENDED SOLDERING CONDITIONS
Solder this product under the following recommended conditions.
For details of the recommended soldering conditions, refer to information document Semiconductor Device
Mounting Technology Manual (C10535E).
For soldering methods and conditions other than those recommended, consult NEC.
Table 10-1. Soldering Conditions for Surface-Mount Type
µPD178023GF-XXX-3B9: 80-pin plastic QFP (14 × 20 mm, 0.8-mm pitch)
µPD178024GF-XXX-3B9: 80-pin plastic QFP (14 × 20 mm, 0.8-mm pitch)
Soldering Method
Soldering Conditions
Recommended
Conditions Symbol
Infrared reflow
Package peak temperature: 235 °C, Time: 30 sec max. (210 °C min.), IR35-00-3
Number of times: 3 max.
VPS
Package peak temperature: 215 °C, Time: 40 sec max. (200 °C min.), VP15-00-3
Number of times: 3 max.
Wave soldering
Solder bath temperature: 260 °C max., Time: 10 sec max.,
Number of times: 1, Preheating temperature: 120 °C max.,
(Package surface temperature)
Partial heating
Pin temperature: 300 °C max., Time: 3 sec max (per device side)
WS60-00-1
–
Caution Do not use two or more soldering methods in combination (except partial heating).
µPD178023GC-XXX-8BT: 80-pin plastic QFP (14 × 14 mm, 0.65-mm pitch)
µPD178024GC-XXX-8BT: 80-pin plastic QFP (14 × 14 mm, 0.65-mm pitch)
Soldering Method
Soldering Conditions
Recommended
Conditions Symbol
Infrared reflow
Package peak temperature: 235 °C, Time: 30 sec max. (210 °C min.), IR35-00-2
Number of times: 2 max.
VPS
Package peak temperature: 215 °C, Time: 40 sec max. (200 °C min.), VP15-00-2
Number of times: 2 max.
Wave soldering
Solder bath temperature: 260 °C max., Time: 10 sec max.,
Number of times: 1, Preheating temperature: 120 °C max.,
(Package surface temperature)
Partial heating
Pin temperature: 300 °C max., Time: 3 sec max (per device side)
WS60-00-1
–
Caution Do not use two or more soldering methods in combination (except partial heating).
46
Data Sheet U14126EJ1V0DS00
µPD178023, 178024
APPENDIX A. DEVELOPMENT TOOLS
The following development tools are available for development of systems using the µPD178023, 178024
subseries.
(1) Language processor software
RA78K0Notes 1, 2, 3
Assembler package common to 78K/0 series
CC78K0Notes 1, 2, 3
C compiler package common to 78K/0 series
DF178124Notes 1, 2, 3
Device file for µPD178024 subseries
CC78K0-LNotes 1, 2, 3
C compiler library source file common to 78K/0 series
(2) Flash memory writing tools
Fashpro III (Part number:
FL-PR3Note 4, PG-FL3)
Dedicated flash writer
FA-80GFNote 4
Flash memory writing adapter
FA-80GC-8BTNote 4
(3) Debugging tools
• When in-circuit emulator IE-78K0-NS is used
IE-78K0-NS
In-circuit emulator common to 78K/0 series
IE-70000-MC-PS-B
Power supply unit for IE-78K0-NS
IE-78K0-NS-PANote 5
Performance board for enhancing and expanding the IE-78K0-NS function
IE-70000-98-IF-C
Interface adapter necessary when a PC-9800 series (except notebook-type PC) is used as host
machine (C bus supported)
IE-70000-CD-IF-A
PC card and interface cable necessary when a notebook-type PC is used as host machine
(PCMCIA socket supported)
IE-70000-PC-IF-C
Interface adapter when a IBM PC/ATTM compatible machine is used (ISA bus supported)
IE-70000-PCI-IF
Interface adapter necessary when a PC with a PCI bus is used as host machine
IE-178134-NS-EM1Note 5
Emulation board for emulating the µPD178024 subseries
NP-80GFNote 4
Emulation probe for 80-pin plastic QFP (GF-3B9 type)
EV-9200G-80
Socket to be mounted on the board of the target system for 80-pin plastic QFP (GF-3B9 type)
NP-80GCNote 4
Emulation probe for 80-pin plastic QFP (GC-8BT type)
EV-9200GC-80
Socket to be mounted on the board of the target system for 80-pin plastic QFP (GC-8BT type)
SM78K0Notes 1, 2
System simulator common to 78K/0 series
ID78K0-NSNotes 1, 2
Integrated debugger common to 78K/0 series
DF178124Notes 1, 2, 3
Device file for µPD178024 subseries
Notes 1. PC-9800 series (MS-DOSTM + WindowsTM) based
2. IBM PC/AT compatible machine (Japanese/English Windows) based
3. HP9000 series 700TM (HP-UXTM) based, SPARCstationTM (SunOSTM, SolarisTM) based, NEWSTM
(NEW-OSTM) based
4. Products of Naito Densei Machida Mfg. Co., Ltd. (Tel: 044-822-3813). Consult NEC distributor when
purchasing these products.
5. Under development
Remark Use the RA78K0, CC78K0, and SM78K0 in combination with the DF178124.
Data Sheet U14126EJ1V0DS00
47
µPD178023, 178024
• When in-circuit emulator IE-78001-R-A is used
IE-78001-R-A
In-circuit emulator common to 78K/0 series
IE-70000-98-IF-C
Interface adapter necessary when a PC-9800 series (except notebook-type PC) is used as host
machine (C bus supported)
IE-70000-PC-IF-C
Interface adapter when a IBM PC/AT compatible machine is used (ISA bus supported)
IE-70000-PCI-IF
Interface adapter necessary when a PC with a PCI bus is used as host machine
IE-78000-R-SV3
Interface adapter and cable necessary when an EWS is used as host machine
IE-178134-NS-EM1Note4
Emulation board for emulating the µPD178024 subseries
IE-78K0-R-EX1
Emulation probe conversion board necessary when using IE-178134-NS-EM1 on IE-78001-R-A.
EP-78130GF-R
Emulation probe for 80-pin plastic QFP (GF-3B9 type)
EV-9200G-80
Socket to be mounted on the board of the target system for 80-pin plastic QFP (GF-3B9 type)
EP-78230GC-R
Emulation probe for 80-pin plastic QFP (GC-8BT type)
EV-9200GC-80
Socket to be mounted on the board of the target system for 80-pin plastic QFP (GC-8BT type)
SM78K0Notes 1, 2
System simulator common to 78K/0 series
ID78K0Notes 1, 2
Integrated debugger common to 78K/0 series
DF178124Notes 1, 2, 3
Device file for µPD178024 subseries
Real-time OS
RX78K0Notes 1, 2, 3
Real-time OS for 78K/0 series
MX78K0Notes 1, 2, 3
OS for 78K/0 series
Notes 1. PC-9800 series (MS-DOS + Windows) based
2. IBM PC/AT compatible machine (Japanese/English windows) based
3. HP9000 series 700 (HP-UX) based, SPARCstation (SunOS, Solaris) based, NEWS (NEW-OS) based
4. Under development
Remark Use SM78K0 in combination with the DF178124.
48
Data Sheet U14126EJ1V0DS00
µPD178023, 178024
APPENDIX B. RELATED DOCUMENTS
The related documents indicated in this publication may include preliminary versions. However, preliminary
versions are not marked as such.
Device Documents
Document No.
Title
Japanese
English
µPD178023, 178024 Data Sheet
U14126J
This document
µPD178024, 178124 Subseries User’s Manual
U13915J
U13915E
78K/0 Series User’s Manual—Instruction
U12326J
U12326E
78K/0 Series Instruction Set
U10904J
—
78K/0 Series Instruction Table
U10903J
—
U12704J
U12704E
78K/0 Series Application Note
Basics (I)
Development Tool Documents (User’s Manual)
Document No.
Title
Japanese
RA78K0 Assembler Package
English
Operation
U11802J
U11802E
Assembly Language
U11801J
U11801E
Structured Assembly
U11789J
U11789E
U12323J
EEU-1402
Operation
U11517J
U11517E
Language
U11518J
U11518E
IE-78001-R-A
To be prepared
To be prepared
IE-78K0-NS
U13731J
To be prepared
IE-178134-NS-EM1
To be prepared
To be prepared
EP-78230
EEU-985
EEU-1515
EP-78130
–
EEU-1470
Language
RA78K Series Structured Assembler Preprocessor
CC78K0 C Compiler
SM78K0 System Simulator Windows Based
Reference
U10181J
U10181E
SM78K Series System Simulator
External Parts User
Open Interface
Specifications
U10092J
U10092E
ID78K0 Integrated Debugger EWS Based
Reference
U11151J
–
ID78K0 Integrated Debugger PC Based
Reference
U11539J
U11539E
ID78K0 Integrated Debugger Windows Based
Guide
U11649J
U11649E
ID78K0-NS Integrated Debugger Windows Based
Reference
U12900J
U12900E
Caution The contents of the above documents are subject to change without notice. Please ensure that
the latest versions are used in design work, etc.
Data Sheet U14126EJ1V0DS00
49
µPD178023, 178024
Related Documents for Embedded Software (User’s Manual)
Document No.
Title
Japanese
78K/0 Series Real-time OS
78K/0 Series OS MX78K0
English
Fundamental
U11537J
U11537E
Installation
U11536J
U11536E
Fundamental
U12257J
U12257E
Other Documents
Document No.
Title
Japanese
English
SEMICONDUCTORS SELECTION GUIDE Products & Packages (CD-ROM)
X13769X
Semiconductor Device Mounting Technology Manual
C10535J
C10535E
Quality Guides on NEC Semiconductor Devices
C11531J
C11531E
NEC Semiconductor Device Reliability and Quality Control
C10983J
C10983E
Guide to Prevent Damage for Semiconductor Devices by Electrostatic Discharge (ESD)
C11892J
C11892E
Semiconductor Device Quality/Reliability Handbook
C12769J
—
Microcomputer Product Series Guide
U11416J
—
Caution The contents of the above documents are subject to change without notice. Ensure that the
latest versions are used in design work, etc.
50
Data Sheet U14126EJ1V0DS00
µPD178023, 178024
[MEMO]
Data Sheet U14126EJ1V0DS00
51
µPD178023, 178024
[MEMO]
52
Data Sheet U14126EJ1V0DS00
µPD178023, 178024
[MEMO]
Data Sheet U14126EJ1V0DS00
53
µPD178023, 178024
NOTES FOR CMOS DEVICES
1
PRECAUTION AGAINST ESD FOR SEMICONDUCTORS
Note:
Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and
ultimately degrade the device operation.
Steps must be taken to stop generation of static
electricity as much as possible, and quickly dissipate it once, when it has occurred. Environmental
control must be adequate. When it is dry, humidifier should be used. It is recommended to avoid
using insulators that easily build static electricity. Semiconductor devices must be stored and
transported in an anti-static container, static shielding bag or conductive material. All test and
measurement tools including work bench and floor should be grounded. The operator should be
grounded using wrist strap. Semiconductor devices must not be touched with bare hands. Similar
precautions need to be taken for PW boards with semiconductor devices on it.
2
HANDLING OF UNUSED INPUT PINS FOR CMOS
Note:
No connection for CMOS device inputs can be cause of malfunction. If no connection is provided
to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence
causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input
levels of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each
unused pin should be connected to V DD or GND with a resistor, if it is considered to have a
possibility of being an output pin. All handling related to the unused pins must be judged device
by device and related specifications governing the devices.
3
STATUS BEFORE INITIALIZATION OF MOS DEVICES
Note:
Power-on does not necessarily define initial status of MOS device. Production process of MOS
does not define the initial operation status of the device. Immediately after the power source is
turned ON, the devices with reset function have not yet been initialized. Hence, power-on does
not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until
the reset signal is received. Reset operation must be executed immediately after power-on for
devices having reset function.
Purchase of NEC I 2C components conveys a license under the Philips I 2C Patent Rights to use these components in an
I 2C system, provided that the system conforms to the I 2C Standard Specification as defined by Philips.
IEBus is a trademark of NEC Corporation.
MS-DOS and Windows are either registered trademarks or trademarks of Microsoft Corporation in
the United States and/or other countries.
PC/AT is a trademark of IBM Corporation.
HP9000 series 700 and HP-UX are trademarks of Hewlett-Packard Company.
SPARCstation is a trademark of SPARC International, Inc.
Solaris and SunOS are trademarks of Sun Microsystems, Inc.
NEWS and NEWS-OS are trademarks of Sony Corporation.
54
Data Sheet U14126EJ1V0DS00
µPD178023, 178024
Regional Information
Some information contained in this document may vary from country to country. Before using any NEC
product in your application, please contact the NEC office in your country to obtain a list of authorized
representatives and distributors. They will verify:
• Device availability
• Ordering information
• Product release schedule
• Availability of related technical literature
• Development environment specifications (for example, specifications for third-party tools and
components, host computers, power plugs, AC supply voltages, and so forth)
• Network requirements
In addition, trademarks, registered trademarks, export restrictions, and other legal issues may also vary
from country to country.
NEC Electronics Inc. (U.S.)
NEC Electronics (Germany) GmbH
NEC Electronics Hong Kong Ltd.
Santa Clara, California
Tel: 408-588-6000
800-366-9782
Fax: 408-588-6130
800-729-9288
Benelux Office
Eindhoven, The Netherlands
Tel: 040-2445845
Fax: 040-2444580
Hong Kong
Tel: 2886-9318
Fax: 2886-9022/9044
NEC Electronics Hong Kong Ltd.
Velizy-Villacoublay, France
Tel: 01-30-67 58 00
Fax: 01-30-67 58 99
Seoul Branch
Seoul, Korea
Tel: 02-528-0303
Fax: 02-528-4411
NEC Electronics (France) S.A.
NEC Electronics Singapore Pte. Ltd.
Milton Keynes, UK
Tel: 01908-691-133
Fax: 01908-670-290
Spain Office
Madrid, Spain
Tel: 91-504-2787
Fax: 91-504-2860
United Square, Singapore 1130
Tel: 65-253-8311
Fax: 65-250-3583
NEC Electronics Italiana s.r.l.
NEC Electronics (Germany) GmbH
Milano, Italy
Tel: 02-66 75 41
Fax: 02-66 75 42 99
Scandinavia Office
Taeby, Sweden
Tel: 08-63 80 820
Fax: 08-63 80 388
NEC Electronics (France) S.A.
NEC Electronics (Germany) GmbH
Duesseldorf, Germany
Tel: 0211-65 03 02
Fax: 0211-65 03 490
NEC Electronics (UK) Ltd.
NEC Electronics Taiwan Ltd.
Taipei, Taiwan
Tel: 02-2719-2377
Fax: 02-2719-5951
NEC do Brasil S.A.
Electron Devices Division
Rodovia Presidente Dutra, Km 214
07210-902-Guarulhos-SP Brasil
Tel: 55-11-6465-6810
Fax: 55-11-6465-6829
J99.1
Data Sheet U14126EJ1V0DS00
55
µPD178023, 178024
The export of this product from Japan is regulated by the Japanese government. To export this product may be prohibited
without governmental license, the need for which must be judged by the customer. The export or re-export of this product
from a country other than Japan may also be prohibited without a license from that country. Please call an NEC sales
representative.
• The information contained in this document is being issued in advance of the production cycle for the
device. The parameters for the device may change before final production or NEC Corporation, at its own
discretion, may withdraw the device prior to its production.
• No part of this document may be copied or reproduced in any form or by any means without the prior written
consent of NEC Corporation. NEC Corporation assumes no responsibility for any errors which may appear in
this document.
• NEC Corporation does not assume any liability for infringement of patents, copyrights or other intellectual property
rights of third parties by or arising from use of a device described herein or any other liability arising from use
of such device. No license, either express, implied or otherwise, is granted under any patents, copyrights or other
intellectual property rights of NEC Corporation or others.
• Descriptions of circuits, software, and other related information in this document are provided for illustrative
purposes in semiconductor product operation and application examples. The incorporation of these circuits,
software, and information in the design of the customer's equipment shall be done under the full responsibility
of the customer. NEC Corporation assumes no responsibility for any losses incurred by the customer or third
parties arising from the use of these circuits, software, and information.
• While NEC Corporation has been making continuous effort to enhance the reliability of its semiconductor devices,
the possibility of defects cannot be eliminated entirely. To minimize risks of damage or injury to persons or
property arising from a defect in an NEC semiconductor device, customers must incorporate sufficient safety
measures in its design, such as redundancy, fire-containment, and anti-failure features.
• NEC devices are classified into the following three quality grades:
"Standard", "Special", and "Specific". The Specific quality grade applies only to devices developed based on a
customer designated "quality assurance program" for a specific application. The recommended applications of
a device depend on its quality grade, as indicated below. Customers must check the quality grade of each device
before using it in a particular application.
Standard: Computers, office equipment, communications equipment, test and measurement equipment,
audio and visual equipment, home electronic appliances, machine tools, personal electronic
equipment and industrial robots
Special: Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster
systems, anti-crime systems, safety equipment and medical equipment (not specifically designed
for life support)
Specific: Aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life
support systems or medical equipment for life support, etc.
The quality grade of NEC devices is "Standard" unless otherwise specified in NEC's Data Sheets or Data Books.
If customers intend to use NEC devices for applications other than those specified for Standard quality grade,
they should contact an NEC sales representative in advance.
M5 98.8