DATA SHEET MOS INTEGRATED CIRCUIT µPD784031Y 16-/8-BIT SINGLE-CHIP MICROCONTROLLERS The µPD784031Y is based on the µPD784031 with an I2C bus control function appended, and is ideal for applications in audio-visual systems. The µPD784031Y is a ROM-less version of µPD784035Y and 784036Y. The functions are explained in detail in the following User’s Manual. Be sure to read this manual when designing your system. µPD784038, 784038Y Subseries User’s Manual - Hardware : U11316E 78K/IV Series User’s Manual - Instruction : U10905E FEATURES 78K/IV Series Timer/counter Pin-compatible with µPD78234 Subseries, 16-bit Timer/counter x 3 units µPD784026 Subseries, and µPD784038 16-bit Timer x 1 unit Subseries Standby function Minimum instruction execution time: 125 ns HALT/STOP/IDLE mode (@ 32-MHz operation) Clock division function I/O ports: 46 Watchdog timer: 1 channel Serial interface: 3 channels A/D converter: 8-bit resolution x 8 channels D/A converter: 8-bit resolution x 2 channels UART/IOE (3-wire serial I/O): 2 channels CSI (3-wire serial I/O, 2-wire serial I/O, I 2C bus): Supply voltage: VDD = 2.7 to 5.5 V 1 channel PWM output: 2 outputs APPLICATION FIELDS Cellular phones, cordless phones, audio-visual systems, etc. ORDERING INFORMATION Part Number Package Internal ROM (Bytes) Internal RAM (Bytes) µPD784031YGC-3B9 80-pin plastic QFP (14 x 14 mm, thickness 2.7 mm) None 2048 µPD784031YGC-8BT 80-pin plastic QFP (14 x 14 mm, thickness 1.4 mm) None 2048 µPD784031YGK-BE9 80-pin plastic TQFP (fine pitch) (12 x 12 mm) None 2048 The information in this document is subject to change without notice. Document No. U11504EJ1V0DS00 (1st edition) Date Published July 1997 N Printed in Japan The mark shows major revised points. © 1996 µPD784031Y 78K/IV SERIES PRODUCT DEVELOPMENT : Under mass production : Under development Standard models µPD784026 Enhanced A/D, 16-bit timer, and power management I2C bus supported Multimaster I2C bus supported µPD784038Y µPD784225Y µPD784038 Enhanced internal memory capacity, pin compatible with the µPD784026 Multimaster I2C bus supported Multimaster I2C bus supported µPD784216Y µPD784218Y µPD784216 100 pins, enhanced I/O and internal memory capacity µPD784054 µPD784046 ASSP models Equipped with 10-bit A/D µPD784908 Equipped with IEBusTM controller µPD78F4943 For CD-ROM, 56-Kbyte flash memory Multimaster I2C bus supported µPD784928Y µPD784928 µPD784915 Equipped with analog circuit for software servo control VCR, enhanced timer 2 µPD784225 80 pins, added ROM correction Enhanced function of the µPD784915 µPD784218 Enhanced internal memory capacity, added ROM correction µPD784031Y FUNCTIONS Item Function Number of basic instructions (mnemonics) 113 General-purpose register 8 bits x 16 registers x 8 banks, or 16 bits x 8 registers x 8 banks (memory mapping) Minimum instruction execution time 125 ns/250 ns/500 ns/1000 ns (at 32 MHz) Internal memory ROM None RAM 2048 bytes Memory space I/O port Pins with ancillary functionNote 1 Mbytes with program and data spaces combined Total 46 Input 8 I/O 34 Output 4 Pins with pullup resistor 32 LEDs direct drive output 8 Transistor direct drive 8 Real-time output port 4 bits x 2, or 8 bits x 1 Timer/counter Timer/counter 0: Timer register x 1 Capture register x 1 Compare register x 2 (16 bits) Pulse output • Toggle output • PWM/PPG output • One-shot pulse output Timer/counter 1: Timer register x 1 Capture register x 1 (8/16 bits) Capture/compare register x 1 Compare register x 1 Pulse output • Real-time output (4 bits x 2) Timer/counter 2: Timer register x 1 Capture register x 1 (8/16 bits) Capture/compare register x 1 Compare register x 1 Pulse output • Toggle output • PWM/PPG output Timer 3: (8/16 bits) Timer register x 1 Compare register x 1 PWM output 12-bit resolution x 2 channels Serial interface UART/IOE (3-wire serial I/O) : 2 channels (on-chip baud rate generator) CSI (3-wire serial I/O, 2-wire serial I/O, I2C bus) : 1 channel A/D converter 8-bit resolution x 8 channels D/A converter 8-bit resolution x 2 channels Watchdog timer 1 channel Standby HALT/STOP/IDLE mode Interrupt Hardware source 24 (internal: 17, external: 7 (variable sampling clock input: 1)) Software source BRK instruction, BRKCS instruction, operand error Non-maskable Internal: 1, external: 1 Maskable Internal: 16, external: 6 • 4 programmable priority levels • 3 processing styles: vectored interrupt/macro service/context switching Supply voltage VDD = 2.7 to 5.5 V Package 80-pin plastic QFP (14 x 14 mm, thickness 2.7 mm) 80-pin plastic QFP (14 x 14 mm, thickness 1.4 mm) 80-pin plastic TQFP (fine pitch) (12 x 12 mm) Note The pins with ancillary function are included in the I/O pins. 3 µPD784031Y CONTENTS 1. DIFFERENCES AMONG MODELS IN µPD784038Y SUBSERIES .................................................. 6 2. MAJOR DIFFERENCES FROM µPD784026 SUBSERIES AND µPD78234 SUBSERIES .............. 7 3. PIN CONFIGURATION (Top View) ................................................................................................... 8 4. BLOCK DIAGRAM ............................................................................................................................ 10 5. 6. PIN FUNCTION ............................................................................................................................... 11 5.1 Port Pins ................................................................................................................................................ 11 5.2 Non-port Pins ........................................................................................................................................ 12 5.3 Types of Pin I/O Circuits and Connections for Unused Pins ............................................................ 14 CPU ARCHITECTURE .................................................................................................................... 17 6.1 6.2 7. Memory Space ....................................................................................................................................... 17 CPU Registers ....................................................................................................................................... 19 6.2.1 General-purpose registers .......................................................................................................... 19 6.2.2 Control registers .......................................................................................................................... 20 6.2.3 Special function registers (SFRs) ............................................................................................... 21 PERIPHERAL HARDWARE FUNCTIONS ..................................................................................... 26 7.1 Ports ....................................................................................................................................................... 26 7.2 Clock Generation Circuit ...................................................................................................................... 27 7.3 Real-time Output Port ........................................................................................................................... 29 7.4 Timer/Counter ........................................................................................................................................ 30 7.5 PWM Output (PWM0, PWM1) ................................................................................................................ 32 7.6 A/D Converter ........................................................................................................................................ 33 7.7 D/A Converter ........................................................................................................................................ 34 7.8 Serial Interface ...................................................................................................................................... 35 7.9 7.8.1 Asynchronous serial interface/3-wire serial I/O (UART/IOE) ...................................................... 36 7.8.2 Clocked serial interface (CSI) ..................................................................................................... 38 Edge Detection Function ...................................................................................................................... 39 7.10 Watchdog Timer .................................................................................................................................... 40 8. 4 INTERRUPT FUNCTION ................................................................................................................. 41 8.1 Interrupt Sources .................................................................................................................................. 41 8.2 Vectored Interrupt ................................................................................................................................. 43 8.3 Context Switching ................................................................................................................................. 44 8.4 Macro Service ........................................................................................................................................ 44 8.5 Application Example of Macro Service ............................................................................................... 45 µPD784031Y 9. LOCAL BUS INTERFACE .............................................................................................................. 47 9.1 Memory Expansion ............................................................................................................................... 47 9.2 Memory Space ....................................................................................................................................... 48 9.3 Programmable Wait .............................................................................................................................. 49 9.4 Pseudo Static RAM Refresh Function ................................................................................................. 49 9.5 Bus Hold Function ................................................................................................................................ 49 10. STANDBY FUNCTION .................................................................................................................... 50 11. RESET FUNCTION ......................................................................................................................... 51 12. INSTRUCTION SET ........................................................................................................................ 52 13. ELECTRICAL SPECIFICATIONS ................................................................................................... 57 14. PACKAGE DRAWINGS .................................................................................................................. 77 15. RECOMMENDED SOLDERING CONDITIONS .............................................................................. 80 APPENDIX A. DEVELOPMENT TOOLS ............................................................................................... 82 APPENDIX B. RELATED DOCUMENTS ............................................................................................... 84 5 µPD784031Y 1. DIFFERENCES AMONG MODELS IN µPD784038Y SUBSERIES The only difference among the µPD784031Y, 784035Y, 784036Y, 784037Y, and 784038Y lies in the internal memory capacity. The µPD78P4038Y is provided with a 128-Kbyte one-time PROM or EPROM instead of the mask ROM of the µPD784035Y, 784036Y, 784037Y, and 784038Y. These differences are summarized in Table 1-1. Table 1-1. Differences among Models in µPD784038Y Subseries Part Number µPD784031Y µPD784035Y µPD784036Y µPD784037Y µPD784038Y µPD78P4038Y 48 Kbytes 64 Kbytes 96 Kbytes 128 Kbytes 128 Kbytes (mask ROM) (mask ROM) (mask ROM) (mask ROM) (one-time PROM Item Internal ROM None or EPROM) Internal RAM 2048 bytes Package 80-pin plastic QFP (14 x 14 mm, thickness 2.7 mm) 80-pin plastic QFP (14 x 14 mm, thickness 1.4 mm) 80-pin plastic TQFP (fine pitch) (12 x 12 mm) 6 3584 bytes 4352 bytes 80-pin ceramic WQFN (14 x 14 mm) µPD784031Y 2. MAJOR DIFFERENCES FROM µPD784026 SUBSERIES AND µPD78234 SUBSERIES Series Name µPD784038Y Subseries µPD784026 Subseries µPD78234 Subseries µPD784038 Subseries Item Number of basic instructions 113 65 (mnemonics) Minimum instruction execution time Memory space (program/data) Timer/counter 125 ns 160 ns 333 ns (@ 32-MHz operation) (@ 25-MHz operation) (@ 12-MHz operation) 1 Mbytes combined 64 Kbytes/1 Mbytes 16-bit timer/counter x 1 16-bit timer/counter x 1 8-/16-bit timer/counter x 2 8-bit timer/counter x 2 8-/16-bit timer x 1 8-bit timer x 1 Clock output function Provided None Watchdog timer Provided None Serial interface UART/IOE (3-wire serial UART/IOE (3-wire serial UART x 1 channel I/O) x 2 channels I/O) x 2 channels CSI (3-wire serial I/O, SBI) CSI (3-wire serial I/O, CSI (3-wire serial I/O, SBI) x 1 channel 2-wire serial I/O, I2C x 1 channel busNote) x 1 channel Interrupt Context Provided None 4 levels 2 levels Standby function HALT/STOP/IDLE mode HALT/STOP mode Operating clock Selectable from fXX/2, fXX/4, fXX/8, and fXX/16 Fixed to fXX/2 None Specifies ROM-less mode switching Priority Pin function MODE pin (always high level with µPD78233 and 78237) TEST pin Device test pin None Usually, low level Package 80-pin plastic QFP 80-pin plastic QFP 80-pin plastic QFP (14 x 14 mm, thickness 2.7 mm) (14 x 14 mm, thickness 2.7 mm) (14 x 14 mm, thickness 2.7 mm) 80-pin plastic QFP 80-pin plastic TQFP 94-pin plastic QFP (14 x 14 mm, thickness 1.4 mm) (fine pitch) (12 x 12 mm): (20 x 20 mm) 80-pin plastic TQFP µPD784021 only 84-pin plastic QFJ (fine pitch) (12 x 12 mm) 80-pin ceramic WQFN (1150 x 1150 mil) 80-pin ceramic WQFN (14 x 14 mm): 94-pin ceramic WQFN (14 x 14 mm): µPD78P4026 only (20 x 20 mm): µPD78P4038Y and µPD78P238 only 78P4038 only Note µPD784038Y Subseries only 7 µPD784031Y 3. PIN CONFIGURATION (Top View) • 80-pin plastic QFP (14 x 14 mm, thickness 2.7 mm) µPD784031YGC-3B9 • 80-pin plastic QFP (14 x 14 mm, thickness 1.4 mm) µPD784031YGC-8BT • 80-pin plastic TQFP (fine pitch) (12 x 12 mm) P31/TxD/SO1 P30/RxD/SI1 P27/SI0 P26/INTP5 P25/INTP4/ASCK/SCK1 P24/INTP3 P23/INTP2/CI P22/INTP1 P21/INTP0 P20/NMI AVREF3 AVREF2 ANO1 ANO0 AVSS AVREF1 AVDD P77/ANI7 P76/ANI6 P75/ANI5 µPD784031YGK-BE9 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 1 59 2 58 3 57 4 56 5 55 6 54 7 53 8 52 9 51 10 50 11 49 12 48 13 47 14 46 15 45 16 44 17 43 18 42 19 2021 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 4041 P66/WAIT/HLDRQ WR RD P63/A19 P62/A18 P61/A17 P60/A16 A15 A14 A13 A12 A11 A10 A9 A8 AD7 AD6 AD5 AD4 AD3 P32/SCK0/SCL P33/SO0/SDA P34/TO0 P35/TO1 P36/TO2 P37/TO3 RESET VDD1 X2 X1 VSS1 P00 P01 P02 P03 P04 P05 P06 P07 P67/REFRQ/HLDAK Note Directly connect the TEST pin to VSS0. 8 P74/ANI4 P73/ANI3 P72/ANI2 P71/ANI1 P70/ANI0 VDD0 P17 P16 P15 P14/TxD2/SO2 P13/TxD2/SI2 P12/ASCK2/SCK2 P11/PWM1 P10/PWM0 TESTNote VSS0 ASTB AD0 AD1 AD2 µPD784031Y : Address Bus P70 to P77 AD0 to AD7 : Address/Data Bus PWM0, PWM1 : Pulse Width Modulation Output ANI0 to ANI7 : Analog Input RD : Read Strobe ANO0, ANO1 : Analog Output REFRQ : Refresh Request ASCK, ASCK2 : Asynchronous Serial Clock RESET : Reset ASTB : Address Strobe RxD, RxD2 : Receive Data AVDD : Analog Power Supply SCK0 to SCK2 : Serial Clock A8 to A19 AVREF1 to AVREF3 : Reference Voltage : Port7 SCL : Serial Clock AVSS : Analog Ground SDA : Serial Data CI : Clock Input SI0 to SI2 : Serial Input HLDAK : Hold Acknowledge SO0 to SO2 : Serial Output HLDRQ : Hold Request TEST : Test INTP0 to INTP5 : Interrupt from Peripherals TO0 to TO3 : Timer Output NMI : Non-maskable Interrupt TxD, TxD2 : Transmit Data P00 to P07 : Port0 VDD0, VDD1 : Power Supply P10 to P17 : Port1 VSS0, VSS1 : Ground P20 to P27 : Port2 WAIT : Wait P30 to P37 : Port3 WR : Write Strobe X1, X2 : Crystal P60 to P63, P66, P67 : Port6 9 µPD784031Y 4. BLOCK DIAGRAM NMI INTP0 to INTP5 INTP3 TO0 TO1 TIMER/COUNTER0 (16 BITS) INTP0 TIMER/COUNTER1 (16 BITS) INTP1 INTP2/CI TO2 TO3 UART/IOE2 PROGRAMMABLE INTERRUPT CONTROLLER TIMER/COUNTER2 (16 BITS) BAUD-RATE GENERATOR UART/IOE1 BAUD-RATE GENERATOR CLOCKED SERIAL INTERFACE P00 to P03 P04 to P07 BUS I/F PWM0 REAL-TIME OUTPUT PORT PWM RAM PWM1 ANO0 ANO1 AVREF2 AVREF3 AVDD AVSS INTP5 10 RxD2/SI2 TxD2/SO2 ASCK2/SCK2 SCK0/SCL SO0/SDA SI0 A8 to A15 A16 to A19 RD WR WAIT/HLDRQ REFRQ/HLDAK PORT0 P00 to P07 PORT1 P10 to P17 PORT2 P20 to P27 PORT3 P30 to P37 D/A CONVERTER P60 to P63 PORT6 P66 to P67 ANI0 to ANI7 AVREF1 ASCK/SCK1 ASTB AD0 to AD7 78K/IV CPU CORE TIMER3 (16 BITS) RxD/SI1 TxD/SO1 A/D CONVERTER PORT7 WATCHDOG TIMER SYSTEM CONTROL P70 to P77 RESET TEST X1 X2 VDD0, VDD1 VSS0, VSS1 µPD784031Y 5. PIN FUNCTION 5.1 Port Pins Pin Name I/O Alternate Function P00 to P07 I/O – Function Port 0 (P0): • 8-bit I/O port • Can be used as real-time output port (4 bits x 2). • Can be set in input or output mode bitwise. • Pins set in input mode can be connected to internal pull-up resistors by software. • Can drive transistor. P10 I/O Port 1 (P1): PWM0 • 8-bit I/O port P11 PWM1 P12 ASCK2/SCK2 P13 RxD2/SI2 • Can be set in input or output mode bitwise. P14 P20 resistors by software. TxD2/SO2 P15 to P17 • Pins set in input mode can be connected to internal pull-up • Can drive LEDs. – Input NMI P21 INTP0 P22 INTP1 P23 INTP2/CI Port 2 (P2): • 8-bit input port • P20 cannot be used as general-purpose port pin (non-maskable P24 INTP3 P25 INTP4/ASCK/SCK1 P26 INTP5 P27 SI0 P30 I/O RxD/S1 P31 TxD/SO1 P32 SCK0/SCL P33 SO0/SDA P34 to P37 TO0 to TO3 interrupt). However, its input level can be checked by interrupt routine. • P22 through P27 can be connected to internal pull-up resistors by software in 6-bit units. • P25/INTP4/ASCK/SCK1 pin can operate as SCK1 output pin if so specified by CSIM1. Port 3 (P3): • 8-bit I/O port • Can be set in input or output mode bitwise. P60 to P63 I/O A16 to A19 P66 WAIT/HLDRQ P67 REFRQ/HLDAK • Pins set in input mode can be connected to internal pull-up resistors by software. Port 6 (P6): • P60 through P63 is dedicated ports for output. • P66 and P67 can be set in input or output mode bitwise. • Pins set in input mode can be connected to internal pull-up resistors by software. P70 to P77 I/O AN10 to AN17 Port 7 (P7): • 8-bit I/O port • Can be set in input or output mode bitwise. 11 µPD784031Y 5.2 Non-port Pins Pin Name TO0 to TO3 I/O Alternate Function Function Output P34 to P37 Timer output CI Input P23/INTP2 Count clock input to timer/counter 2 RxD Input P30/SI1 Serial data input (UART0) P13/SI2 Serial data input (UART2) P31/SO1 Serial data output (UART0) P14/SO2 Serial data output (UART2) P25/INTP4/SCK1 Baud rate clock input (UART0) P12/SCK2 Baud rate clock input (UART2) P33/SO0 Serial data input/output (2-wire serial I/O, I2C bus) P27 Serial data input (3-wire serial I/O0) RxD2 TxD Output TxD2 ASCK Input ASCK2 SDA I/O SI0 Input SI1 P30/RxD Serial data input (3-wire serial I/O1) SI2 P13/RxD2 Serial data input (3-wire serial I/O2) P33/SDA Serial data output (3-wire serial I/O0) P31/TxD Serial data output (3-wire serial I/O1) P14/TxD2 Serial data output (3-wire serial I/O2) P32/SCL Serial clock input/output (3-wire serial I/O0) SCK1 P25/INTP4/ASCK Serial clock input/output (3-wire serial I/O1) SCK2 P12/ASCK2 Serial clock input/output (3-wire serial I/O2) SCL P32/SCK0 Serial clock input/output (2-wire serial I/O, I2C bus) P20 External interrupt requests SO0 Output SO1 SO2 SCK0 NMI I/O Input – INTP0 P21 • Count clock input to timer/counter 1 • Capture trigger signal of CR11 or CR12 INTP1 P22 • Count clock input to timer/counter 2 • Capture trigger signal of CR22 INTP2 P23/CI • Count clock input to timer/counter 2 • Capture trigger signal of CR21 INTP3 P24 • Count clock input to timer/counter 0 • Capture trigger signal of CR02 INTP4 P25/ASCK/SCK1 INTP5 P26 AD0 to AD7 – Conversion start trigger input to A/D converter I/O – Time-division address/data bus (for external memory connection) A8 to A15 Output – Higher address bus (for external memory connection) A16 to A19 Output RD Output WR Output WAIT P60 to P63 Higher address when address is extended (for external memory connection) – Read strobe to external memory – Write strobe to external memory Input P66/HLDRQ Wait insertion REFRQ Output P67/HLDAK Refresh pulse output to external pseudo static memory HLDRQ Input P66/WAIT Bus hold request input HLDAK Output P67/REFRQ Bus hold acknowledge output ASTB Output – Latch timing output of time-division address (A0 through A7) (when accessing external memory) 12 µPD784031Y Pin Name I/O Alternate Function RESET Input – Chip reset X1 Input – Crystal connection for system clock oscillation X2 – (Clock can also be input to X1.) ANI0 to ANI7 Input P70 to P77 ANO0, ANO1 Output – – – AVREF1 Function Analog voltage input to A/D converter Analog voltage output from D/A converter Reference voltage to A/D converter AVREF2, AVREF3 Reference voltage to D/A converter AVDD A/D converter power supply AVSS A/D converter GND VDD0Note 1 Power supply of port VDD1Note 1 Power supply except for port VSS0Note 2 GND of port VSS1Note 2 GND except for port TEST Directly connect to VSS0 (IC test pin). Notes 1. Provide the same potential to VDD0 and VDD1. 2. Provide the same potential to VSS0 and VSS1. 13 µPD784031Y 5.3 Types of Pin I/O Circuits and Connections for Unused Pins Table 5-1 shows types of pin I/O circuits and the connections for unused pins. For the input/output circuit of each type, refer to Figure 5-1. Table 5-1. Types of Pin I/O Circuits and Connections for Unused Pins (1/2) Pin Name P00 to P07 I/O Circuit Type 5-H I/O I/O P10/PWM0 Recommended Connection for Unused Pins Input: Connect to VDD0. Output: Open P11/PWM1 P12/ASCK2/SCK2 8-C P13/RxD2/SI2 5-H P14/TxD2/SO2 P15 to P17 P20/NMI 2 Input Connect to VDD0 or VSS0. P21/INTP0 P22/INTP1 2-C Connect to VDD0. P23/INTP2/CI P24/INTP3 P25/INTP4/ASCK/SCK1 8-C I/O Input: Connect to VDD0. Output: Open P26/INTP5 2-C Input Connect to VDD0. 5-H I/O Input: Connect to VDD0. P27/SI0 P30/RxD/SI1 P31/TxD/SO1 P32/SCK0/SCL Output: Open 10-B P33/SO0/SDA P34/TO0 to P37/TO3 5-H AD0 to AD7 A8 to A15 OutputNote Open I/O Input: Connect to VDD0. P60/A16 to P63/A19 RD WR P66/WAIT/HLDRQ P67/REFRQ/HLDAK P70/ANI0 to P77/ANI7 Output: Open 20-A Input: Connect to VDD0 or VSS0. Output: Open ANO0, ANO1 12 ASTB 4-B Output Open Note I/O circuit type of these pins is 5-H. However these pins perform only as output by an internal circuit. 14 µPD784031Y Table 5-1. Types of Pin I/O Circuits and Connections for Unused Pins (2/2) Pin Name I/O Circuit Type RESET 2 TEST 1-A AVREF1 to AVREF3 I/O Recommended Connection for Unused Pins Input – Directly connect to VSS0. – Connect to VSS0. AVSS AVDD Caution Connect to VDD0. Connect an I/O pin whose input/output mode is unstable to VDD0 via a resistor of several 10 kΩ (especially if the voltage on the reset input pin rises higher than the low-level input level on power application or when the mode is switched between input and output by software). Remark Because the circuit type numbers shown in the above table are commonly used with all the models in the 78K Series, these numbers of some models are not serial (because some circuits are not provided to some models). 15 µPD784031Y Figure 5-1. Types of Pin I/O Circuits Type 1-A Type 2-C VDD0 P VDD0 N P IN pullup enable VSS0 Type 2 IN IN Schmitt trigger input with hysteresis characteristics Schmitt trigger input with hysteresis characteristics Type 4-B VDD0 pullup enable VDD0 data Type 5-H P P VDD0 data P OUT IN/OUT output disable N output disable VSS0 Push-pull output that can go into a high-impedance state (with both P-ch and N-ch off) N VSS0 input enable Type 12 Type 8-C VDD0 pullup enable P VDD0 data P Analog output voltage P IN/OUT output disable OUT N N VSS0 Type 10-B Type 20-A VDD0 VDD0 data pullup enable P P IN/OUT VDD0 data output disable P N VSS0 IN/OUT Comparator open drain output disable AVSS AVREF (threshold voltage) VSS0 input enable 16 + – N P N µPD784031Y 6. CPU ARCHITECTURE 6.1 Memory Space A memory space of 1 Mbytes can be accessed. Mapping of the internal data area (special function registers and internal RAM) can be specified the LOCATION instruction. The LOCATION instruction must be always executed after reset cancellation, and must not be used more than once. (1) When LOCATION 0 instruction is executed The internal data area is mapped in 0F700H to 0FFFFH. (2) When LOCATION 0FH instruction is executed The internal data area is mapped in FF700H to FFFFFH. 17 18 Figure 6-1. Memory Map of µPD784031Y On execution of LOCATION 0 instruction On execution of LOCATION 0FH instruction F F F F FH F FEF FH 0 FEF FH General-purpose registers (128 bytes) External memory (960 Kbytes) 0 FE3 1H Special function registers (SFR) 0 FE0 6H (256 bytes) Macro service control word area (44 bytes) Special function registers (SFR) (256 bytes) Internal RAM (2 Kbytes) FFE8 0H F FE 7 FH 0 FE8 0H 0 FE 7 FH 1 0 0 0 0H 0 F F F FH 0 F FDFH 0 F FD0H 0 FF 0 0H 0 FEF FH 0 FD0 0H 0 FCF FH F F F F FH F F FDFH F F FD0H FFF 0 0H F FEF FH FF 7 0 0H F F 6 F FH F F E 31 H FFE0 6H Data area (512 bytes) 0 FD0 0H 0 FCF FH Internal RAM (2 Kbytes) F FD0 0H F FCF FH External memory (1046272 bytes) Program/data area (1536 bytes) 0 F 7 0 0H 0 F 7 0 0H 0 F 6 F FH FF 7 0 0H Note External memory (63232 bytes) 0 1 0 0 0H 0 0 F F FH 0 0 F F FH CALLF entry area (2 Kbytes) 0 0 8 0 0H 0 0 7 F FH 0 0 8 0 0H 0 0 7 F FH 0 0 0 8 0H 0 0 0 7 FH 0 0 0 8 0H 0 0 0 7 FH 1 0 0 0 0H 0 F F F FH Note 0 0 0 4 0H 0 0 0 3 FH 0 0 0 0 0H Vector table area (64 bytes) 0 0 0 0 0H Note Base area and entry area for reset or interrupt. However, the internal RAM area is not used as a reset entry area. µPD784031Y 0 0 0 0 0H CALLT table area (64 bytes) µPD784031Y 6.2 CPU Registers 6.2.1 General-purpose registers Sixteen 8-bit general-purpose registers are available. Two 8-bit registers can be also used in pairs as a 16-bit register. Of the 16-bit registers, four can be used in combination with an 8-bit register for address expansion as 24-bit address specification registers. Eight banks of these registers are available which can be selected by using software or the context switching function. The general-purpose registers except V, U, T, and W registers for address expansion are mapped to the internal RAM. Figure 6-2. General-purpose Register Format A (R1) X (R0) AX (RP0) B (R3) C (R2) BC (RP1) R5 R4 RP2 R7 R6 RP3 V R9 VP (RP4) VVP (RG4) U R8 R11 R10 T UP (RP5) UUP (RG5) D (R13) E (R12) W DE (RP6) TDE (RG6) H (R15) L (R14) 8 banks WHL (RG7) Parentheses ( Caution HL (RP7) ) indicate an absolute name. Registers R4, R5, R6, R7, RP2, and RP3 can be used as X, A, C, B, AX, and BC registers, respectively, by setting the RSS bit of the PSW to 1. However, use this function only for recycling the program of the 78K/III Series. 19 µPD784031Y 6.2.2 Control registers (1) Program counter (PC) The program counter is a 20-bit register whose contents are automatically updated when the program is executed. Figure 6-3. Program Counter (PC) Format 19 0 PC (2) Program status word (PSW) This register holds the statuses of the CPU. Its contents are automatically updated when the program is executed. Figure 6-4. Program Status Word (PSW) Format PSWH 15 14 13 12 11 10 9 8 UF RBS2 RBS1 RBS0 – – – – 7 6 5 4 3 2 1 0 AC IE P/V 0 CY PSW PSWL S Z RSS Note Note This flag is provided to maintain compatibility with the 78K/III Series. Be sure to clear this flag to 0, except when the software for the 78K/III Series is used. (3) Stack pointer (SP) This is a 24-bit pointer that holds the first address of the stack. Be sure to write 0 to the higher 4 bits of this pointer. Figure 6-5. Stack Pointer (SP) Format 23 SP 20 0 20 0 0 0 0 µPD784031Y 6.2.3 Special function registers (SFRs) The special function registers, such as the mode registers and control registers of the internal peripheral hardware, are registers to which special functions are allocated. These registers are mapped to a 256-byte space of addresses 0FF00H through 0FFFFHNote. Note On execution of the LOCATION 0 instruction. FFF00H through FFFFFH on execution of the LOCATION 0FH instruction. Caution Do not access an address in this area to which no SFR is allocated. If such an address is accessed by mistake, the µPD784031Y may be in the deadlock status. This deadlock status can be cleared only by inputting the reset signal. Table 6-1 lists the special function registers (SFRs). The meanings of the symbols in this table are as follows: • Symbol ................................ Symbol indicating an SFR. This symbol is reserved for NEC’s assembler (RA78K4). It can be used as an sfr variable by the #pragma sfr command with the C compiler (CC78K4). • R/W ..................................... Indicates whether the SFR is read-only, write-only, or read/write. R/W : Read/write • Bit units for manipulation .... R : Read-only W : Write-only Bit units in which the value of the SFR can be manipulated. SFRs that can be manipulated in 16-bit units can be described as the operand sfrp of an instruction. To specify the address of this SFR, describe an even address. SFRs that can be manipulated in 1-bit units can be described as the operand of a bit manipulation instruction. • After reset ........................... Indicates the status of the register when the RESET signal has been input. 21 µPD784031Y Table 6-1. Special Function Registers (SFRs) (1/4) AddressNote Special Function Register (SFR) Name Symbol R/W 1 bit 8 bits 16 bits √ √ – √ √ – After Reset 0FF00H Port 0 P0 0FF01H Port 1 P1 0FF02H Port 2 P2 R √ √ – 0FF03H Port 3 P3 R/W √ √ – 0FF06H Port 6 P6 √ √ – 00H 0FF07H Port 7 P7 √ √ – Undefined P0L √ √ – 0FF0EH Port 0 buffer register L R/W Bit Units for Manipulation Undefined 0FF0FH Port 0 buffer register H P0H √ √ – 0FF10H Compare register (timer/counter 0) CR00 – – √ 0FF12H Capture/compare register (timer/counter 0) CR01 – – √ 0FF14H Compare register L (timer/counter 1) CR10 CR10W – √ √ 0FF15H Compare register H (timer/counter 1) – – 0FF16H Capture/compare register L (timer/counter 1) – √ 0FF17H Capture/compare register H (timer/counter 1) – – 0FF18H Compare register L (timer/counter 2) – √ 0FF19H Compare register H (timer/counter 2) – – 0FF1AH Capture/compare register L (timer/counter 2) – √ 0FF1BH Capture/compare register H (timer/counter 2) – – 0FF1CH Compare register L (timer 3) – √ 0FF1DH Compare register H (timer 3) – – – 0FF20H Port 0 mode register PM0 √ √ – 0FF21H Port 1 mode register PM1 √ √ – 0FF23H Port 3 mode register PM3 √ √ – 0FF26H Port 6 mode register PM6 √ √ – 0FF27H Port 7 mode register PM7 √ √ – 0FF2EH Real-time output port control register RTPC √ √ – 00H 0FF30H Capture/compare control register 0 CRC0 – √ – 10H 0FF31H Timer output control register TOC √ √ – 00H 0FF32H Capture/compare control register 1 CRC1 – √ – 0FF33H Capture/compare control register 2 CRC2 – √ – – CR11 CR11W – CR20 CR20W – CR21 CR21W – CR30 CR30W √ √ √ √ FFH 10H Note When the LOCATION 0 instruction is executed. When the LOCATION 0FH instruction is executed, “F0000H” is added to this value. 22 µPD784031Y Table 6-1. Special Function Registers (SFRs) (2/4) AddressNote 1 Special Function Register (SFR) Name Symbol R/W R Bit Units for Manipulation 1 bit 8 bits 16 bits – – √ – √ √ – – – √ – – √ √ – After Reset 0FF36H Capture register (timer/counter 0) CR02 0FF38H Capture register L (timer/counter 1) CR12 CR12W 0FF39H Capture register H (timer/counter 1) 0FF3AH Capture register L (timer/counter 2) 0FF3BH Capture register H (timer/counter 2) 0FF41H Port 1 mode control register PMC1 0FF43H Port 3 mode control register PMC3 √ √ – 0FF4EH Pull-up resistor option register PUO √ √ – 0FF50H Timer register 0 TM0 – – √ – – – √ – – – √ – – – √ – – – √ – 11H – CR22 CR22W – R/W R 0FF51H 0FF52H Timer register 1 0FF53H 0FF54H TM1W – Timer register 2 0FF55H 0FF56H TM1 TM2 TM2W – Timer register 3 0FF57H TM3 TM3W – √ 00H 0000H √ √ √ 0FF5CH Prescaler mode register 0 PRM0 0FF5DH Timer control register 0 TMC0 √ √ – 00H 0FF5EH Prescaler mode register 1 PRM1 – √ – 11H 0FF5FH Timer control register 1 TMC1 √ √ – 00H 0FF60H D/A conversion value setting register 0 DACS0 – √ – 0FF61H D/A conversion value setting register 1 DACS1 – √ – 0FF62H D/A converter mode register DAM √ √ – 03H 0FF68H A/D converter mode register ADM √ √ – 00H 0FF6AH A/D conversion result register ADCR R – √ – Undefined 0FF70H PWM control register PWMC R/W √ √ – 05H 0FF71H PWM prescaler register PWPR – √ – 00H 0FF72H PWM modulo register 0 PWM0 – – √ Undefined 0FF74H PWM modulo register 1 PWM1 – – √ 0FF7DH One-shot pulse output control register OSPC √ √ – 0FF80H I2C IICC √ √ – 0FF81H Prescaler mode register for serial clock SPRM – √ – 04H 0FF82H Clocked serial interface mode register CSIM √ √ – 00H √Note 3 √ – 01H 0FF83H bus control register Slave address register SVA R/W 0000H R/WNote 2 00H Notes 1. When the LOCATION 0 instruction is executed. When the LOCATION 0FH instruction is executed, “F0000H” is added to this value. 2. Bit 0 is read-only. 3. Only bit 0 can be manipulated in bit units. 23 µPD784031Y Table 6-1. Special Function Registers (SFRs) (3/4) AddressNote 1 Special Function Register (SFR) Name Symbol R/W 1 bit 8 bits 16 bits √ √ – After Reset 0FF84H Clocked serial interface mode register 1 CSIM1 0FF85H Clocked serial interface mode register 2 CSIM2 √ √ – 0FF86H Serial shift register SIO – √ – 0FF88H Asynchronous serial interface mode register ASIM √ √ – 0FF89H Asynchronous serial interface mode register 2 ASIM2 √ √ – 0FF8AH Asynchronous serial interface status register ASIS √ √ – 0FF8BH Asynchronous serial interface status register 2 ASIS2 √ √ – 0FF8CH Serial receive buffer: UART0 RXB – √ – Serial transmit shift register: UART0 TXS W – √ – Serial shift register: IOE1 SIO1 R/W – √ – Serial receive buffer: UART2 RXB2 R – √ – Serial transmit shift register: UART2 TXS2 W – √ – Serial shift register: IOE2 SIO2 R/W – √ – 0FF90H Baud rate generator control register BRGC – √ – 0FF91H Baud rate generator control register 2 BRGC2 – √ – 0FFA0H External interrupt mode register 0 INTM0 √ √ – 0FFA1H External interrupt mode register 1 INTM1 √ √ – 0FFA4H Sampling clock select register SCS0 – √ – 0FFA8H In-service priority register ISPR R √ √ – 0FFAAH Interrupt mode control register IMC R/W √ √ – 80H 0FFACH Interrupt mask register 0L MK0L MK0 √ √ √ FFFFH 0FFADH Interrupt mask register 0H MK0H √ √ 0FFAEH Interrupt mask register 1L MK1L √ √ – FFH 0FFC0H Standby control register STBC – √Note 2 – 30H 0FFC2H Watchdog timer mode register WDM – √Note 2 – 00H 0FFC4H Memory expansion mode register MM √ √ – 20H 0FFC5H Hold mode register HLDM √ √ – 00H 0FFC6H Clock output mode register CLOM √ √ – 0FFC7H Programmable wait control register 1 PWC1 – √ – AAH 0FFC8H Programmable wait control register 2 PWC2 – – √ AAAAH 0FF8DH R/W Bit Units for Manipulation R 00H Undefined 00H Notes 1. When the LOCATION 0 instruction is executed. When the LOCATION 0FH instruction is executed, “F0000H” is added to this value. 2. Data can be written by using only dedicated instructions such as MOV STBC, #byte and MOV WDM, #byte, and cannot be written with any other instructions. 24 µPD784031Y Table 6-1. Special Function Registers (SFRs) (4/4) AddressNote Special Function Register (SFR) Name Symbol R/W R/W Bit Units for Manipulation 1 bit 8 bits 16 bits √ √ – 0FFCCH Refresh mode register RFM 0FFCDH Refresh area specification register RFA √ √ – 0FFCFH Oscillation stabilization time specification OSTS – √ – – √ √ – After Reset 00H register 0FFD0H to External SFR area – 0FFDFH 0FFE0H Interrupt control register (INTP0) PIC0 √ √ – 0FFE1H Interrupt control register (INTP1) PIC1 √ √ – 0FFE2H Interrupt control register (INTP2) PIC2 √ √ – 0FFE3H Interrupt control register (INTP3) PIC3 √ √ – 0FFE4H Interrupt control register (INTC00) CIC00 √ √ – 0FFE5H Interrupt control register (INTC01) CIC01 √ √ – 0FFE6H Interrupt control register (INTC10) CIC10 √ √ – 0FFE7H Interrupt control register (INTC11) CIC11 √ √ – 0FFE8H Interrupt control register (INTC20) CIC20 √ √ – 0FFE9H Interrupt control register (INTC21) CIC21 √ √ – 0FFEAH Interrupt control register (INTC30) CIC30 √ √ – 0FFEBH Interrupt control register (INTP4) PIC4 √ √ – 0FFECH Interrupt control register (INTP5) PIC5 √ √ – 0FFEDH Interrupt control register (INTAD) ADIC √ √ – 0FFEEH Interrupt control register (INTSER) SERIC √ √ – 0FFEFH Interrupt control register (INTSR) SRIC √ √ – Interrupt control register (INTCSI1) CSIIC1 √ √ – 0FFF0H Interrupt control register (INTST) STIC √ √ – 0FFF1H Interrupt control register (INTCSI) CSIIC √ √ – 0FFF2H Interrupt control register (INTSER2) SERIC2 √ √ – 0FFF3H Interrupt control register (INTSR2) SRIC2 √ √ – Interrupt control register (INTCSI2) CSIIC2 √ √ – 0FFF4H Interrupt control register (INTST2) STIC2 √ √ – 0FFF5H Interrupt control register (INTSPC) SPCIC √ √ – 43H Note When the LOCATION 0 instruction is executed. When the LOCATION 0FH instruction is executed, “F0000H” is added to this value. 25 µPD784031Y 7. PERIPHERAL HARDWARE FUNCTIONS 7.1 Ports The ports shown in Figure 7-1 are provided to make various control operations possible. Table 7-1 shows the function of each port. Ports 0 through 6 can be connected to internal pull-up resistors by software when inputting. Figure 7-1. Port Configuration P00 Port 0 P07 P10 Port 1 P17 P20 to P27 8 Port 2 P30 Port 3 P37 P60 P63 P66 P67 P70 Port 6 Port 7 P77 26 µPD784031Y Table 7-1. Port Functions Port Name Pin Name Function Specification of Pull-up Resistor Connection by Software Port 0 P00 to P07 • Can be set in input or output mode in 1-bit units. All port pins in input mode • Can operate as 4-bit real-time output port (P00 through P03 and P04 through P07). • Can drive transistor. Port 1 P10 to P17 • Can be set in input or output mode in 1-bit units. All port pins in input mode • Can drive LEDs. Port 2 P20 to P27 • Input port In 6-bit units (P22 through P27) Port 3 P30 to P37 • Can be set in input or output mode in 1-bit units. All port pins in input mode Port 6 P60 to P63 • Output only All port pins in input mode P66, P67 • Can be set in input or output mode in 1-bit units. P70 to P77 • Can be set in input or output mode in 1-bit units. Port 7 – 7.2 Clock Generation Circuit An on-chip clock generation circuit necessary for operation is provided. This clock generation circuit has a divider circuit. If high-speed operation is not necessary, the internal operating frequency can be lowered by the divider circuit to reduce the current consumption. Figure 7-2. Block Diagram of Clock Generation Circuit X1 fXX 1/2 1/2 1/2 1/2 Selector Oscillation circuit X2 fCLK CPU Peripheral circuit fXX/2 UART/IOE INTP0 noise reduction circuit Oscillation stabilization timer Remark fXX : oscillation frequency or external clock input fCLK : internal operating frequency 27 µPD784031Y Figure 7-3. Example of Using Oscillation Circuit (1) Crystal/ceramic oscillation µ PD784031Y VSS1 X1 X2 (2) External clock • EXTC bit of OSTS = 1 µ PD74HC04, etc. Caution • EXTC bit of OSTS = 0 µ PD784031Y µ PD784031Y X1 X1 X2 Open X2 When using the clock oscillation circuit, wire the dotted portion in the above figure as follows to avoid adverse influences of wiring capacitance. • Keep the wiring length as short as possible. • Do not cross the wiring with other signal lines. • Do not route the wiring in the vicinity of lines through which a high alternating current flows. • Always keep the potential at the ground point of the capacitor in the oscillation circuit the same as VSS1. Do not ground to a ground pattern through which a high current flows. • Do not extract signals from the oscillation circuit. 28 µPD784031Y 7.3 Real-time Output Port The real-time output port outputs data stored in a buffer in synchronization with the coincidence interrupt generated by timer/counter 1 or with an external interrupt. As a result, pulses without jitter can be output. The real-time output port is therefore ideal for applications where arbitrary patterns must be output at specific intervals (such as open loop control of a stepping motor). The real-time output port mainly consists of port 0 and port 0 buffer registers (P0H and P0L) as shown in Figure 7-4. Figure 7-4. Block Diagram of Real-time Output Port Internal bus 8 4 Buffer register Real-time output port control register (RTPC) 8 INTP0 (from external source) INTC10 (from timer/counter 1) INTC11 (from timer/counter 1) 4 Output trigger control circuit P0H P0L 4 4 Output latch (P0) P07 P00 29 µPD784031Y 7.4 Timer/Counter Three units of timers/counters and one unit of timer are provided. Because a total of seven interrupt requests are supported, these timers/counters and timer can be used as seven units of timers/counters. Table 7-2. Operations of Timers/Counters Name Timer/Counter 0 Timer/Counter 1 Timer/Counter 2 Timer 3 8 bits – √ √ √ 16 bits √ √ √ √ 2ch 2ch 2ch 1ch Item Count width Operation Interval timer mode External event counter √ √ √ – One-shot timer – – √ – 2ch – 2ch – Toggle output √ – √ – PWM/PPG output √ – √ – One-shot pulse outputNote √ – – – – √ – – 1 input 1 input 2 inputs – 2 2 2 1 Function Timer output Real-time output Pulse width measurement Number of interrupt requests Note The one-shot pulse output function makes a pulse output level active by software and inactive by hardware (interrupt request signal). This function is different in nature from the one-shot timer function of timer/counter 2. 30 µPD784031Y Figure 7-5. Block Diagram of Timers/Counters Timer/counter 0 Timer register 0 (TM0) OVF Compare register (CR00) Match Compare register (CR01) Match Capture register (CR02) Edge detection INTP3 Software trigger TO0 Pulse output control Prescaler fXX/8 Selector Clear control TO1 INTC00 INTP3 INTC01 Timer/counter 1 Prescaler fXX/8 Selector Clear control Event input Timer register 1 (TM1/TM1W) OVF Compare register (CR10/CR10W) Match Capture/Compare register (CR11/CR11W) Match INTC10 To real-time output port Edge detection INTP0 INTC11 INTP0 Capture register (CR12/CR12W) Timer/counter 2 Edge detection INTP2/CI INTP2 INTP1 Timer register 2 (TM2/TM2W) OVF Compare register (CR20/CR20W) Match Capture/Compare register (CR21/CR21W) Match Pulse output control Prescaler fXX/8 Selector Clear control Capture register (CR22/CR22W) Edge detection TO2 TO3 INTC20 INTP1 INTC21 Timer 3 fXX/8 Prescaler Timer register 3 (TM3/TM3W) Clear Compare register (CR30/CR30W) Match CSI INTC30 Remark OVF: overflow flag 31 µPD784031Y 7.5 PWM Output (PWM0, PWM1) Two channels of PWM (pulse width modulation) output circuits with a resolution of 12 bits and a repeat frequency of 62.5 kHz (fCLK = 16 MHz) are provided. Both these PWM output channels can select a high or low level as the active level. These outputs are ideal for controlling the speed of a DC motor. Figure 7-6. Block Diagram of PWM Output Unit Internal bus 16 8 PWM modulo register PWMn 15 8 7 8 4 3 0 PWM control register (PWMC) 4 Reload control fCLK Prescaler 8-bit down counter Pulse control circuit 4-bit counter 1/256 Remark n = 0 or 1 32 Output control PWMn (output pin) µPD784031Y 7.6 A/D Converter An analog-to-digital (A/D) converter with eight multiplexed inputs (ANI0 through ANI7) is provided. This A/D converter is of successive approximation type. The result of conversion is retained by an 8-bit A/D conversion result register (ADCR). Therefore, high-speed, high-accuracy conversion can be performed (conversion time: approx. 7.5 µs at fCLK = 16 MHz). A/D conversion can be started in either of the following two modes: • Hardware start: Conversion is started by trigger input (INTP5). • Software start: Conversion is started by setting a bit of the A/D converter mode register (ADM). After started, the A/D converter operates in the following modes: • Scan mode: Two or more analog inputs are sequentially selected, and data to be converted are obtained from all the input pins. • Select mode: Only one analog input pin is used to continuously obtain converted values. These operation modes and whether starting or stopping the A/D converter are specified by the ADM. When the result of conversion is transferred to the ADCR, interrupt request INTAD is generated. By using this request and macro service, the converted values can be successively transferred to the memory. Figure 7-7. Block Diagram of A/D Converter Series resistor string Sample & hold circuit Input selector AVREF1 R/2 Voltage comparator R Successive approximation register (SAR) INTP5 Edge detection circuit Conversion trigger INTAD Control Circuit Tap selector ANI0 ANI1 ANI2 ANI3 ANI4 ANI5 ANI6 ANI7 R/2 AVSS Trigger enable 8 A/D converter mode register (ADM) A/D conversion result register (ADCR) 8 8 Internal bus 33 µPD784031Y 7.7 D/A Converter Two circuits of digital-to-analog (D/A) converters are provided. These D/A converters are of voltage output type and have a resolution of 8 bits. The conversion method is of R-2R resistor ladder type. By writing a value to be output to an 8-bit D/A conversion value setting register (DACSn: n = 0 or 1), an analog value is output to the ANOn (n = 0 or 1) pin. The output voltage range is determined by the voltage applied across the AVREF2 and AVREF3 pins. Because the output impedance is high, no current can be extracted from the output. If the impedance of the load is low, insert a buffer amplifier between the load and output pin. The ANOn pin goes into a high-impedance state while the RESET signal is low. After releasing reset, DACSn is cleared to 0. Figure 7-8. Block Diagram of D/A Converter ANOn 2R AVREF2 R 2R Selector R 2R AVREF3 R 2R DACSn DACEn Internal bus Remark n = 0 or 1 34 µPD784031Y 7.8 Serial Interface Three independent serial interface channels are provided. Asynchronous serial interface (UART)/3-wire serial I/O (IOE) x 2 Clocked serial interface (CSI) x 1 • 3-wire serial I/O (IOE) • 2-wire serial I/O (IOE) • I2C bus interface (I2C) Therefore, communication with an external system and local communication within the system can be simultaneously executed (refer to Figure 7-9). Figure 7-9. Example of Serial Interface (a) UART + I2C µ PD784031Y (master) µ PD4711A VDD µ PD6272 (EEPROMTM) [I2C] [UART] RS-232-C driver/receiver VDD RxD SDA SDA TxD SCL SCL Port µ PD78062Y (slave) µ PD4711A SDA [UART] RS-232-C driver/receiver LCD SCL RxD2 TxD2 Port (b) UART + 3-wire serial I/O + 2-wire serial I/O µ PD784031Y (master) µ PD4711A SO1 [UART] RxD RS-232-C driver/receiver TxD Port µ PD75108 (slave) [3-wire serial I/O] SI1 SO SCK1 INTPm SI SCK Note Port Port INT VDD VDD µ PD78014 (slave) SDA SB0 SCL INTPn SCK0 Note Port Port INT [2-wire serial I/O] Note Handshake line 35 µPD784031Y 7.8.1 Asynchronous serial interface/3-wire serial I/O (UART/IOE) Two channels of serial interfaces that can select an asynchronous serial interface mode and 3-wire serial I/O mode are provided. (1) Asynchronous serial interface mode In this mode, data of 1 byte following the start bit is transferred or received. Because an on-chip baud rate generator is provided, a wide range of baud rates can be set. Moreover, the clock input to the ASCK pin can be divided to define a baud rate. When the baud rate generator is used, a baud rate conforming to the MIDI standard (31.25 kbps) can be also obtained. Figure 7-10. Block Diagram in Asynchronous Serial Interface Mode Internal bus Receive buffer RXB, RXB2 Receive shift register RXD, RXD2 Transmit shift register TXS, TXS2 TXD, TXD2 Receive control parity check Baud rate generator ASCK, ASCK2 Selector 1/2m fXX/2 1/2n + 1 1/2m Remark fXX: oscillation frequency or external clock input n = 0 through 11 m = 16 through 30 36 INTSR, INTSR2 INTSER, INTSER2 Transmit control parity append INTST, INTST2 µPD784031Y (2) 3-wire serial I/O mode In this mode, the master device starts transfer by making the serial clock active and transfers 1-byte data in synchronization with this clock. This mode is used to communicate with a device having the conventional clocked serial interface. Basically, communication is established by using three lines: one serial clock (SCK) and two serial data (SI and SO) lines. Generally, to check the communication status, a handshake line is necessary. Figure 7-11. Block Diagram in 3-wire Serial I/O Mode Internal bus Direction control circuit SIO1, SIO2 SI1, SI2 Shift register Output latch SO1, SO2 Serial clock counter Serial clock control circuit Interrupt signal generation circuit Selector SCK1, SCK2 1/m INTCSI1, INTCSI2 1/2n + 1 fXX/2 Remark fXX: oscillation frequency or external clock input n = 0 through 11 m = 1 or 16 through 30 37 µPD784031Y 7.8.2 Clocked serial interface (CSI) In this mode, the master device starts transfer by making the serial clock active and communicates 1-byte data in synchronization with this clock. Figure 7-12. Block Diagram of Clocked Serial Interface Internal bus Direction control register Slave address register Match signal Set SI0 Selector Shift register Reset Output latch SO0/SDA N-ch open drain output (in 2-wire or I2C bus mode) Acknowledge detection control Start condition detection circuit Acknowledge detection circuit Wake-up control circuit Stop condition detection circuit Serial clock counter SCK0/SCL INTSPC Interrupt signal generation circuit Timer 3 output Serial clock control circuit Selector N-ch open drain output (in 2-wire or I2C bus mode) CLS0 CLS1 Remark fXX: oscillation frequency or external clock input 38 INTCSI fXX/16 Selector Prescaler fXX/2 µPD784031Y (1) 3-wire serial I/O mode This mode is to communicate with devices having the conventional clocked serial interface. Basically, communication is established in this mode with three lines: one serial clock (SCK0) and two serial data (SI0 and SO0) lines. Generally, a handshake line is necessary to check the communication status. (2) 2-wire serial I/O mode This mode is to transfer 8-bit data by using two lines: serial clock (SCL) and serial data bus (SDA). Generally, a handshake line is necessary to check the communication status. (3) I2C (Inter IC) bus mode This mode is to communicate with devices conforming to the I2C bus format. This mode is to transfer 8-bit data with two or more devices by using two lines: serial clock (SCL) and serial data bus (SDA). During transfer, a “start condition”, “data”, and “stop condition” can be output onto the serial data bus. During reception, these data can be automatically detected by hardware. 7.9 Edge Detection Function The interrupt input pins (NMI and INTP0 through INTP5) are used not only to input interrupt requests but also to input trigger signals to the internal hardware units. Because these pins operate at an edge of the input signal, they have a function to detect an edge. Moreover, a noise reduction circuit is also provided to prevent erroneous detection due to noise. Pin Name Detectable Edge Noise Reduction NMI Either of rising or falling edge By analog delay INTP0 to INTP3 Either or both of rising and falling edges By clock samplingNote INTP4, INTP5 Note By analog delay INTP0 can select a sampling clock. 39 µPD784031Y 7.10 Watchdog Timer A watchdog timer is provided to detect a hang up of the CPU. This watchdog timer generates a non-maskable interrupt unless it is cleared by software within a specified interval time. Once enabled to operate, the watchdog timer cannot be stopped by software. Whether the interrupt by the watchdog timer or the interrupt input from the NMI pin takes precedence can be specified. Figure 7-13. Block Diagram of Watchdog Timer Timer fCLK fCLK/220 fCLK/219 fCLK/217 Clear signal 40 Selector fCLK/221 INTWDT µPD784031Y 8. INTERRUPT FUNCTION As the servicing in response to an interrupt request, the three types shown in Table 8-1 can be selected by program. Table 8-1. Servicing of Interrupt Request Servicing Mode Vector interrupt Entity of Servicing Software Context switching Servicing Contents of PC and PSW Branches and executes servicing routine Saves to and restores (servicing is arbitrary). from stack. Automatically switches register bank, Saves to or restores from branches and executes servicing routine fixed area in register bank. (servicing is arbitrary). Macro service Firmware Executes data transfer between memory Retained and I/O (servicing is fixed). 8.1 Interrupt Sources Table 8-2 shows the interrupt sources available. As shown, interrupts are generated by 24 types of sources, execution of the BRK instruction or BRKCS instruction, or an operand error. The priority of interrupt servicing can be set to four levels, so that nesting can be controlled during interrupt servicing and that which of the two or more interrupts that simultaneously occur should be serviced first. When the macro service function is used, however, nesting always proceeds. The default priority is the priority (fixed) of the service that is performed if two or more interrupt requests, having the same request, simultaneously generate (refer to Table 8-2). 41 µPD784031Y Table 8-2. Interrupt Sources Type Default Source Priority Software – Name BRK instruction Internal/ Trigger Instruction execution Macro Service External – – – BRKCS instruction Non-maskable Maskable – Operand error If result of exclusive OR between byte of operand and byte is not FFH when MOV STBC, #byte, MOV WDM, #byte, or LOCATION instruction is executed NMI Detection of pin input edge External WDT Overflow of watchdog timer Internal 0 (highest) INTP0 Detection of pin input edge (TM1/TM1W capture trigger, TM1/TM1W event counter input) External √ 1 INTP1 Detection of pin input edge (TM2/TM2W capture trigger, TM2/TM2W event counter input) 2 INTP2 Detection of pin input edge (TM2/TM2W capture trigger, TM2/TM2W event counter input) 3 INTP3 Detection of pin input edge (TM0 capture trigger, TM0 event counter input) 4 INTC00 Generation of TM0-CR00 match signal Internal √ 5 INTC01 Generation of TM0-CR01 match signal 6 INTC10 Generation of TM1-CR10 match signal (in 8-bit operation mode) Generation of TM1W-CR10W match signal (in 16-bit operation mode) 7 INTC11 Generation of TM1-CR11 match signal (in 8-bit operation mode) Generation of TM1W-CR11W match signal (in 16-bit operation mode) 8 INTC20 Generation of TM2-CR20 match signal (in 8-bit operation mode) Generation of TM2W-CR20W match signal (in 16-bit operation mode) 9 INTC21 Generation of TM2-CR21 match signal (in 8-bit operation mode) Generation of TM2W-CR21W match signal (in 16-bit operation mode) 10 INTC30 Generation of TM3-CR30 match signal (in 8-bit operation mode) Generation of TM3W-CR30W match signal (in 16-bit operation mode) 11 INTP4 Detection of pin input edge External √ 12 INTP5 Detection of pin input edge 13 INTAD End of A/D conversion (transfer of ADCR) 14 INTSER Occurrence of ASI0 reception error – 15 INTSR End of ASI0 reception or CSI1 transfer √ Internal √ INTCSI1 16 INTST 17 INTCSI End of ASI0 transfer End of CSI1 transfer 18 INTSER2 Occurrence of ASI2 reception error – 19 INTSR2 End of ASI2 reception or CSI2 transfer √ INTCSI2 20 INTST2 End of ASI2 transfer 21 (lowest) INTSPC I2C bus stop condition interrupt Remark ASI: asynchronous serial interface CSI: clocked serial interface 42 µPD784031Y 8.2 Vectored Interrupt Execution branches to a servicing routing by using the memory contents of a vector table address corresponding to the interrupt source as the address of the branch destination. So that the CPU performs interrupt servicing, the following operations are performed: • On branching : Saves the status of the CPU (contents of PC and PSW) to stack • On returning : Restores the status of the CPU (contents of PC and PSW) from stack To return to the main routine from an interrupt service routine, the RETI instruction is used. The branch destination address is in a range of 0 to FFFFH. Table 8-3. Vector Table Address Interrupt Source Vector Table Address BRK instruction 003EH Operand error 003CH NMI 0002H WDT 0004H INTP0 0006H INTP1 0008H INTP2 000AH INTP3 000CH INTC00 000EH INTC01 0010H INTC10 0012H INTC11 0014H INTC20 0016H INTC21 0018H INTC30 001AH INTP4 001CH INTP5 001EH INTAD 0020H INTSER 0022H INTSR 0024H INTCSI1 INTST 0026H INTCSI 0028H INTSER2 002AH INTSR2 002CH INTCSI2 INTST2 002EH INTSPC 0030H 43 µPD784031Y 8.3 Context Switching When an interrupt request is generated or when the BRKCS instruction is executed, a predetermined register bank is selected by hardware. Context switching is a function that branches execution to a vector address stored in advance in the register bank, and to stack the current contents of the program counter (PC) and program status word (PSW) to the register bank. The branch address is in a range of 0 to FFFFH. Figure 8-1. Context Switching Operation when Interrupt Request is Generated Register bank n (0 to 7) 0000B <7> Transfer Register bank n (n = 0 to 7) PC19 to 16 PC15 to 0 <2> Save (bits 8 through 11 of temporary register) <6> Exchange <5> Save Temporary register <1> Save A X B C R5 R4 R7 R6 V VP U UP T D E W H L <3> Switching of register bank (RBS0 to RBS2 ← n) <4> RSS ← 0 IE ← 0 PSW 8.4 Macro Service This function is to transfer data between memory and a special function register (SFR) without intervention by the CPU. A macro service controller accesses the memory and SFR in the same transfer cycle and directly transfers data without loading it. Because this function does not save or restore the status of the CPU, or load data, data can be transferred at high speeds. Figure 8-2. Macro Service Read CPU Memory Write Internal bus 44 Write Macro service controller SFR Read µPD784031Y 8.5 Application Example of Macro Service (1) Transfer of serial interface Transfer data storage buffer (memory) Data n Data n – 1 Data 2 Data 1 Internal bus TxD Transfer shift register TXS (SFR) Transfer control INTST Each time macro service request INTST is generated, the next transfer data is transferred from memory to TXS. When data n (last byte) has been transferred to TXS (when the transfer data storage buffer has become empty), vectored interrupt request INTST is generated. (2) Reception of serial interface Receive data storage buffer (memory) Data n Data n – 1 Data 2 Data 1 Internal bus Receive buffer RxD RXB (SFR) Receive shift register Reception control INTSR Each time macro service request INTSR is generated, the receive data is transferred from RXB to memory. When data n (last byte) has been transferred to memory (when the receive data storage buffer has become full), vectored interrupt request INTSR is generated. 45 µPD784031Y (3) Real-time output port INTC10 and INTC11 serve as the output triggers of the real-time output port. The macro services for these can set the following output pattern and intervals simultaneously. Therefore, INTC10 and INTC11 can control two stepping motors independently of each other. They can also be used for PWM output or to control DC motors. Output pattern profile (memory) Output timing profile (memory) Pn Tn Pn – 1 Tn – 1 P2 T2 P1 T1 Internal bus Internal bus Match (SFR) P0L CR10 (SFR) INTC10 Output latch TM1 P00 to P03 Each time macro service request INTC10 is generated, the pattern and timing are transferred to the buffer register (P0L) and compare register (CR10), respectively. When the contents of the timer register 1 (TM1) coincide with those of CR10, INTC10 is generated again, and the contents of P0L are transferred to the output latch. When Tn (last byte) has transferred to CR10, vectored interrupt request INTC10 is generated. The same applies to INTC11. 46 µPD784031Y 9. LOCAL BUS INTERFACE The local bus interface can connect an external memory or I/O (memory mapped I/O) and support a memory space of 1 Mbytes (refer to Figure 9-1). Figure 9-1. Example of Local Bus Interface A16 to A19 Decoder µ PD784031Y RD Pseudo SRAM WR PROM µ PD27C1001A REFRQ Data bus AD0 to AD7 ASTB A8 to A15 Character generator µ PD24C1000 Latch Address bus Gate array I/O expansion Centronics I/F, etc. 9.1 Memory Expansion The memory capacity can be expanded in seven steps, from 256 bytes to 1 Mbytes, by connecting an external program memory and data memory. 47 µPD784031Y 9.2 Memory Space The 1-Mbyte memory space is divided into eight spaces of logical addresses. Each space can be controlled by using the programmable wait function and pseudo static RAM refresh function. Figure 9-2. Memory Space F F F F FH 512 Kbytes 8 0 0 0 0H 7 F F F FH 256 Kbytes 4 0 0 0 0H 3 F F F FH 128 Kbytes 2 0 0 0 0H 1 F F F FH 64 Kbytes 1 0 0 0 0H 0 F F F FH 16 Kbytes 0C0 0 0H 0 BF F FH 16 Kbytes 0 8 0 0 0H 0 7 F F FH 16 Kbytes 0 4 0 0 0H 0 3 F F FH 16 Kbytes 0 0 0 0 0H 48 µPD784031Y 9.3 Programmable Wait The memory space can be divided into eight spaces and wait states can be independently inserted in each of these spaces while the RD and WR signals are active. Even when a memory with a different access time is connected, therefore, the efficiency of the entire system does not drop. In addition, an address wait function that extends the active period of the ASTB signal is also provided so as to have a sufficient address decode time (this function can be set to the entire space). 9.4 Pseudo Static RAM Refresh Function The following refresh operations can be performed: • Pulse refresh : A bus cycle that outputs a refresh pulse to the REFRQ pin at a fixed cycle is inserted. The memory spaces is divided into eight spaces, and a refresh pulse can be output from the REFRQ pin while a specified memory space is accessed. Therefore, the normal memory access is not kept to wait by the refresh cycle. • Power-down self-refresh : The low level is output to the REFRQ pin in the standby mode to retain the contents of the pseudo static RAM. 9.5 Bus Hold Function A bus hold function is provided to facilitate connection of a DMA controller. When a bus hold request signal (HLDRQ) is received from an external bus master, the address bus, address/data bus, and ASTB, RD, and WR pins go into a highimpedance state when the current bus cycle has been completed. This makes the bus hold acknowledge (HLDAK) signal active, and releases the bus to the external bus master. Note that, while the bus hold function is used, the external wait function and pseudo static RAM refresh function cannot be used. 49 µPD784031Y 10. STANDBY FUNCTION This function is to reduce the power dissipation of the chip, and can be used in the following modes: • HALT mode : Stops supply of the operating clock to the CPU. This mode is used in combination with the normal operation mode for intermittent operation to reduce the average power dissipation. • IDLE mode : Stops the entire system with the oscillation circuit continuing operation. The power dissipation in this mode is close to that in the STOP mode. However, the time required to restore the normal program operation from this mode is almost the same as that from the HALT mode. • STOP mode : Stops the oscillator and thereby to stop all the internal operations of the chip. Consequently, the power dissipation is minimized with only leakage current flowing. These modes are programmable. The macro service can be started from the HALT mode. Figure 10-1. Transition of Standby Status 1 1 IN Se ts ID R L TP ESE E m o 4, T IN inp de TP u 5 t inp ut N o te te No ut inp 5 TP IN 4, TP I, I, NM NM IDLE (standby) Interrupt request of masked interrupt e2 ot IN tN es qu re put e pt in od ru T m E er Int RES ALT H ts STOP (standby) Se de mo ut ST inp s T t Se ESE R OP Macro service M a En cro s d of erv on ice e pr req oc u es est sin g Macro service request End of one processing End of macro service on bilizati on sta s Program ti la il c Os xpire operation Waits for time e oscillation stabilization HALT (standby) Notes 1. When INTP4 and INTP5 are not masked 2. Only interrupt requests that are not masked Remark Only the externally input NMI is valid. The watchdog timer cannot be used to release the standby mode (STOP/ IDLE mode). 50 µPD784031Y 11. RESET FUNCTION When the low level is input to the RESET pin, the internal hardware is initialized (reset status). When the RESET pin goes high, the following data are set to the program counter (PC). • Lower 8 bits of PC : contents of address 0000H • Middle 8 bits of PC : contents of address 0001H • Higher 4 bits of PC : 0 Program execution is started from a branch destination address which is the contents of the PC. Therefore, the system can be reset and started from any address. Set the contents of each register by program as necessary. The RESET input circuit has a noise reduction circuit to prevent malfunctioning due to noise. This noise reduction circuit is a sampling circuit by analog delay. Figure 11-1. Accepting Reset Signal Delay Delay Delay Initialize PC Executes instruction at reset start address RESET (input) Internal reset signal Reset starts Reset ends Assert the RESET signal active until the oscillation stabilization time (approx. 40 ms) elapses to execute a power-ON reset operation. Figure 11-2. Power-ON Reset Operation Oscillation stabilization time Delay Initialize PC Executes instruction at reset start address VDD RESET (input) Internal reset signal Reset ends 51 µPD784031Y 12. INSTRUCTION SET (1) 8-bit instructions (The instructions in parentheses are combinations realized by describing A as r) MOV, XCH, ADD, ADDC, SUB, SUBC, AND, OR, XOR, CMP, MULU, DIVUW, INC, DEC, ROR, ROL, RORC, ROLC, SHR, SHL, ROR4, DBNZ, PUSH, POP, MOVM, XCHM, CMPME, CMPMNE, CMPMNC, CMPMC, MOVBK, XCHBK, CMPBKE, CMPBKNE, CMPBKNC, CMPBKC, CHIKL, CHKLA Table 12-1. Instruction List by 8-bit Addressing Second Operand #byte A r saddr r' saddr' sfr !addr16 !!addr24 First Operand A r3 [WHL+] [WHL–] [saddrp] PSWL [%saddrg] PSWH MOV (MOV) (MOV) MOV (MOV)Note 6 MOV (MOV) MOV ADDNote 1 (XCH) XCH (XCH)Note 6 (XCH) (XCH) XCH (XCH) ADDNote 1 (ADD)Note 1 (ADD)Note 1 (ADD)Note 1 (ADD)Note 1,6 (ADD)Note 1 ADDNote 1 r mem MOV (MOV) MOV MOV MOV MOV ADDNote 1 (XCH) XCH XCH XCH XCH n NoneNote 2 (MOV) RORNote 3 MULU DIVUW (ADD)Note 1 ADDNote 1 ADDNote 1 ADDNote 1 INC DEC saddr MOV ADDNote 1 sfr MOV (MOV)Note 6 MOV (ADD)Note 1 ADDNote 1 MOV MOV INC XCH DEC ADDNote 1 DBNZ MOV PUSH ADDNote 1 (ADD)Note 1 ADDNote 1 POP CHKL CHKLA !addr16 MOV (MOV) MOV ADDNote 1 !!addr24 mem MOV ADDNote 1 [saddrp] [%saddrg] mem3 ROR4 ROL4 r3 MOV MOV PSWL PSWH B, C DBNZ STBC, WDM MOV [TDE+] (MOV) [TDE–] (ADD)Note 1 MOVBKNote 5 MOVMNote 4 Notes 1. The operands of ADDC, SUB, SUBC, AND, OR, XOR, and CMP are the same as that of ADD. 2. Either the second operand is not used, or the second operand is not an operand address. 3. The operands of ROL, RORC, ROLC, SHR, and SHL are the same as that of ROR. 4. The operands of XCHM, CMPME, CMPMNE, CMPMNC, and CMPMC are the same as that of MOVM. 5. The operands of XCHBK, CMPBKE, CMPBKNE, CMPBKNC, and CMPBKC are the same as that of MOVBK. 6. The code length of some instructions having saddr2 as saddr in this combination is short. 52 µPD784031Y (2) 16-bit instructions (The instructions in parentheses are combinations realized by describing AX as rp) MOVW, XCHW, ADDW, SUBW, CMPW, MULUW, MULW, DIVUX, INCW, DECW, SHRW, SHLW, PUSH, POP, ADDWG, SUBWG, PUSHU, POPU, MOVTBLW, MACW, MACSW, SACW Table 12-2. Instruction List by 16-bit Addressing Second Operand #word AX rp saddrp rp' saddrp' sfrp !addr16 !!addr24 First Operand AX rp mem [WHL+] n NoneNote 2 SHRW MULWNote 4 byte [saddrp] [%saddrg] (MOVW) (MOVW) (MOVW) (MOVW)Note 3 ADDWNote 1 (XCHW) (XCHW) (XCHW)Note 3 (XCHW) MOVW ADDWNote 1 MOVW (ADD)Note 1 (ADDW)Note 1 (ADDW)Note 1,3 (ADDW)Note 1 (MOVW) MOVW MOVW MOVW (XCHW) XCHW XCHW XCHW (MOVW) MOVW (MOVW) XCHW XCHW (XCHW) MOVW SHLW (ADDW)Note 1 ADDWNote 1 ADDWNote 1 ADDWNote 1 saddrp MOVW (MOVW)Note 3 MOVW ADDWNote 1 (ADDW)Note 1 ADDWNote 1 INCW DECW MOVW INCW XCHW DECW ADDWNote 1 sfrp !addr16 MOVW MOVW MOVW PUSH ADDWNote 1 (ADDW)Note 1 ADDWNote 1 POP MOVW (MOVW) MOVW MOVTBLW !!addr24 mem MOVW [saddrp] [%saddrg] PSW PUSH POP SP ADDWG SUBWG post PUSH POP PUSHU POPU [TDE+] (MOVW) SACW byte MACW MACSW Notes 1. The operands of SUBW and CMPW are the same as that of ADDW. 2. Either the second operand is not used, or the second operand is not an operand address. 3. The code length of some instructions having saddrp2 as saddrp in this combination is short. 4. The operands of MULUW and DIVUX are the same as that of MULW. 53 µPD784031Y (3) 24-bit instructions (The instructions in parentheses are combinations realized by describing WHL as rg) MOVG, ADDG, SUBG, INCG, DECG, PUSH, POP Table 12-3. Instruction List by 24-bit Addressing Second Operand #imm24 WHL rg saddrg !!addr24 mem1 [%saddrg] SP (MOVG) MOVG MOVG MOVG NoneNote rg' First Operand WHL rg (MOVG) (MOVG) (MOVG) (MOVG) (ADDG) (ADDG) (ADDG) ADDG (SUBG) (SUBG) (SUBG) SUBG MOVG (MOVG) MOVG MOVG ADDG (ADDG) ADDG DECG SUBG (SUBG) SUBG PUSH MOVG INCG POP saddrg (MOVG) MOVG !!addr24 (MOVG) MOVG mem1 MOVG [%saddrg] MOVG SP MOVG MOVG INCG DECG Note Either the second operand is not used, or the second operand is not an operand address. 54 µPD784031Y (4) Bit manipulation instructions MOV1, AND1, OR1, XOR1, SET1, CLR1, NOT1, BT, BF, BTCLR, BFSET Table 12-4. Bit Manipulation Instructions Second Operand CY saddr.bit sfr.bit /saddr.bit /sfr. bit A.bit X.bit /A.bit /X.bit PSWL.bit PSWH.bit /PSWL.bit /PSWH.bit mem2.bit /mem2.bit First Operand !addr16.bit !!addr24.bit /!addr16.bit /!!addr24.bit CY MOV1 AND1 AND1 OR1 OR1 NoneNote NOT1 SET1 CLR1 XOR1 saddr.bit MOV1 NOT1 sfr.bit SET1 A.bit CLR1 X.bit BF PSWL.bit BT PSWH.bit BTCLR mem2.bit BFSET !addr16.bit !!addr24.bit Note Either the second operand is not used, or the second operand is not an operand address. 55 µPD784031Y (5) Call and return/branch instructions CALL, CALLF, CALLT, BRK, RET, RETI, RETB, RETCS, RETCSB, BRKCS, BR, BNZ, BNE, BZ, BE, BNC, BNL, BC, BL, BNV, BPO, BV, BPE, BP, BN, BLT, BGE, BLE, BGT, BNH, BH, BF, BT, BTCLR, BFSET, DBNZ Table 12-5. Call and Return/Branch Instructions Operand of Instruction $addr20 $!addr20 !addr16 !!addr20 rp rg [rp] [rg] !addr11 [addr5] CALLF CALLF RBn None Address Basic instruction Compound instruction BCNote CALL BR BR CALL CALL CALL CALL CALL CALL BR BR BR BR BR BR BRKCS BRK RET RETCS RETI RETCSB RETB BF BT BTCLR BFSET DBNZ Note The operands of BNZ, BNE, BZ, BE, BNC, BNL, BL, BNV, BPO, BV, BPE, BP, BN, BLT, BGE, BLE, BGT, BNH, and BH are the same as BC. (6) Other instructions ADJBA, ADJBS, CVTBW, LOCATION, SEL, NOT, EI, DI, SWRS 56 µPD784031Y 13. ELECTRICAL SPECIFICATIONS Absolute Maximum Ratings (TA = 25°C) Parameter Ratings Unit VDD –0.5 to +7.0 V AVDD AVSS to VDD + 0.5 V AVSS –0.5 to +0.5 V Input voltage VI –0.5 to VDD + 0.5 V Output voltage VO –0.5 to VDD + 0.5 V Output current low-level IOL 1 pin 15 mA Total of output pins 100 mA 1 pin –10 mA Total of output pins –100 mA Supply voltage Output current high-level Symbol IOH Test Conditions Reference input voltage to A/D converter AVREF1 –0.5 to VDD + 0.3 V Reference input voltage AVREF2 –0.5 to VDD + 0.3 V to D/A converter AVREF3 –0.5 to VDD + 0.3 V TA –40 to +85 °C Tstg –65 to +150 °C Operating ambient temperature Storage temperature Caution The product quality may be damaged even if a value of only one of the above parameters exceeds the absolute maximum rating or any value exceeds the absolute maximum rating for an instant. That is, the absolute maximum rating is a rating value which may cause a product to be damaged physically. The absolute maximum rating values must therefore be observed in using the product. 57 µPD784031Y Operating Condition • Operating ambient temperature (TA) : –40 to +85°C • Rise, fall time (tr, tf) (unspecified pins) : 0 to 200 µs • Supply voltage and clock cycle time : refer to Figure 13-1 Figure 13-1. Supply Voltage and Clock Cycle Time 10000 Clock Cycle Time tCYK [ns] 4000 1000 Guaranteed Operation Range 125 100 62.5 10 0 1 2 3 4 5 Supply Voltage [V] 6 7 Capacitance (TA = 25°C, VDD = VSS = 0 V) Parameter Symbol Test Conditions MIN. TYP. MAX. Unit Input capacitance CI f = 1 MHz 10 pF Output capacitance CO Unmeasured pins returned to 10 pF 10 pF I/O capacitance 58 CIO 0 V. µPD784031Y Oscillator Characteristics (TA = –40 to +85°C, VDD = +4.5 to 5.5 V, VSS = 0 V) Resonator Recommended Circuit Ceramic resonator or crystal resonator VSS1 X1 C1 Caution MAX. Unit Oscillation frequency (fXX) 4 32 MHz X1 input frequency (fX) 4 32 MHz X1 input rise, fall time (tXR, tXF) 0 10 ns X1 input high-/low-level width (tWXH, tWXL) 10 125 ns C2 X2 HCMOS inverter MIN. X2 External clock X1 Parameter When using the clock oscillator, wiring in the area enclosed with the dotted line should be carried out as follows to avoid an adverse effect from wiring capacitance. • Wiring should be as short as possible. • Wiring should not cross other signal lines. • Wiring should not be placed close to a varying high current. • The potential of the oscillator capacitor ground should be the same as VSS1. Do not ground it to the ground pattern in which a high current flows. • Do not fetch a signal from the oscillator. 59 µPD784031Y Oscillator Characteristics (TA = –40 to +85°C, VDD = +2.7 to 5.5 V, VSS = 0 V) Resonator Recommended Circuit Ceramic resonator or crystal resonator VSS1 X1 C1 Caution MAX. Unit Oscillation frequency (fXX) 4 16 MHz X1 input frequency (fX) 4 16 MHz X1 input rise, fall time (tXR, tXF) 0 10 ns X1 input high-/low-level width (tWXH, tWXL) 10 125 ns C2 X2 HCMOS inverter MIN. X2 External clock X1 Parameter When using the clock oscillator, wiring in the area enclosed with the dotted line should be carried out as follows to avoid an adverse effect from wiring capacitance. • Wiring should be as short as possible. • Wiring should not cross other signal lines. • Wiring should not be placed close to a varying high current. • The potential of the oscillator capacitor ground should be the same as VSS1. Do not ground it to the ground pattern in which a high current flows. • Do not fetch a signal from the oscillator. 60 µPD784031Y DC Characteristics (TA = –40 to +85°C, VDD = AVDD = +2.7 to 5.5 V, VSS = AVSS = 0 V) (1/2) Parameter Input voltage low-level Input voltage high-level Output voltage low-level Symbol Test Conditions MIN. TYP. MAX. Unit VIL1 Except for pins shown in Notes 1, 2, 3, 4, 6 –0.3 0.3VDD V VIL2 Pins shown in Notes 1, 2, 3, 4, 6 –0.3 0.2VDD V VIL3 VDD = +5.0 V ± 10 % Pins shown in Notes 2, 3, 4 –0.3 +0.8 V VIH1 Except for pins shown in Notes 1, 6 0.7VDD VDD + 0.3 V VIH2 Pins shown in Notes 1, 6 0.8VDD VDD + 0.3 V VIH3 VDD = +5.0 V ± 10 % Pins shown in Notes 2, 3, 4 2.2 VDD + 0.3 V VOL1 IOL = 2 mA Except for pins shown in Note 6 0.4 V VOL2 IOL = 3 mA Pins shown in Note 6 0.4 V IOL = 6 mA 0.6 V 1.0 V Pins shown in Note 6 Output voltage high-level VOL3 VDD = +5.0 V ± 10 % IOL = 8 mA Pins shown in Notes 2, 5 VOH1 IOH = –2 mA VDD – 1.0 V VOH2 VDD = +5.0 V ± 10 % IOH = –5 mA Pins shown in Note 4 VDD – 1.4 V X1 input current low-level IIL EXTC = 0 0 V ≤ VI ≤ VIL2 –30 µA X1 input current high-level IIH EXTC = 0 VIH2 ≤ VI ≤ VDD +30 µA Notes 1. X1, X2, RESET, P12/ASCK2/SCK2, P20/NMI, P21/INTP0, P22/INTP1, P23/INTP2/CI, P24/INTP3, P25/INTP4/ASCK/SCK1, P26/INTP5, P27/SI0, TEST 2. AD0 to AD7, A8 to A15 3. P60/A16 to P63/A19, RD, WR, P66/WAIT/HLDRQ, P67/REFRQ/HLDAK 4. P00 to P07 5. P10 to P17 6. P32/SCK0/SCL, P33/SO0/SDA 61 µPD784031Y DC Characteristics (TA = –40 to +85°C, VDD = AVDD = +2.7 to 5.5 V, VSS = AVSS = 0 V) (2/2) Parameter Symbol Test Conditions MIN. TYP. MAX. Unit Input leakage current ILI 0 V ≤ VI ≤ VDD Except for X1 pin when EXTC = 0 ±10 µA Output leakage current ILO 0 V ≤ VO ≤ VDD ±10 µA VDD supply current IDD1 Operating mode IDD2 IDD3 Pull-up resistor 62 RL HALT mode IDLE mode (EXTC = 0) VI = 0 V fXX = 32 MHz VDD = +5.0 V ± 10 % 25 45 mA fXX = 16 MHz VDD = +2.7 to 3.3 V 12 25 mA fXX = 32 MHz VDD = +5.0 V ± 10 % 13 26 mA fXX = 16 MHz VDD = +2.7 to 3.3 V 8 12 mA fXX = 32 MHz VDD = +5.0 V ± 10 % 12 mA fXX = 16 MHz VDD = +2.7 to 3.3 V 8 mA 80 kΩ 15 µPD784031Y AC Characteristics (TA = –40 to +85°C, VDD = AVDD = +2.7 to 5.5 V, VSS = AVSS = 0 V) (1) Read/write operation (1/2) Parameter Address setup time ASTB high-level width Address hold time (from ASTB↓) Symbol tSAST tWSTH tHSTLA Address hold time (from RD↑) tHRA Address → RD↓ delay time tDAR Address float time (from RD↓) tFRA Address → data input time tDAID Test Conditions VDD = +5.0 V ± 10 % VDD = +5.0 V ± 10 % VDD = +5.0 V ± 10 % VDD = +5.0 V ± 10 % MIN. MAX. Unit (0.5 + a) T – 15 ns (0.5 + a) T – 31 ns (0.5 + a) T – 17 ns (0.5 + a) T – 40 ns 0.5T – 24 ns 0.5T – 34 ns 0.5T – 14 ns (1 + a) T – 9 ns (1 + a) T – 15 ns VDD = +5.0 V ± 10 % 0 ns (2.5 + a + n) T – 37 ns (2.5 + a + n) T – 52 ns ASTB↓ → data input time tDSTID VDD = +5.0 V ± 10 % (2 + n) T – 40 ns (2 + n) T – 60 ns RD↓ → data input time tDRID VDD = +5.0 V ± 10 % (1.5 + n) T – 50 ns (1.5 + n) T – 70 ns ASTB↓ → RD↓ delay time tDSTR 0.5T – 9 ns Data hold time (from RD↑) tHRID 0 ns RD↑ → address active time tDRA 0.5T – 8 ns 0.5T – 12 ns 1.5T – 8 ns 1.5T – 12 ns 0.5T – 17 ns (1.5 + n) T – 30 ns (1.5 + n) T – 40 ns 0.5T – 14 ns (1 + a) T – 5 ns (1 + a) T – 15 ns After program VDD = +5.0 V ± 10 % read After data VDD = +5.0 V ± 10 % read RD↑ → ASTB↑ delay time tDRST RD low-level width tWRL Address hold time (from WR↑) tHWA Address → WR↓ delay time tDAW ASTB↓ → data output delay time tDSTOD WR↓ → data output delay time tDWOD ASTB↓ → WR↓ output delay time tDSTW VDD = +5.0 V ± 10 % VDD = +5.0 V ± 10 % VDD = +5.0 V ± 10 % 0.5T – 9 0.5T + 19 ns 0.5T + 35 ns 0.5T – 11 ns ns Remark T : TCYK (system clock cycle time) a : 1 in address wait, 0 in the other conditions n : the number of wait (n ≥ 0) 63 µPD784031Y (1) Read/write operation (2/2) Parameter Data setup time (to WR↑) Data hold time (from WR↑)Note Symbol tSODW tHWOD WR↑ → ASTB↑ delay time tDWST WR low-level width tWWL Test Conditions VDD = +5.0 V ± 10 % VDD = +5.0 V ± 10 % VDD = +5.0 V ± 10 % MIN. MAX. Unit (1.5 + n) T – 30 ns (1.5 + n) T – 40 ns 0.5T – 5 ns 0.5T – 25 ns 0.5T – 12 ns (1.5 + n) T – 30 ns (1.5 + n) T – 40 ns Note The data hold time includes the time to hold VOH1 and VOL1 in the load condition of CL = 50 pF, RL = 4.7 kΩ. Remark T : TCYK (system clock cycle time) n : the number of wait (n ≥ 0) (2) Bus hold timing Parameter HLDRQ↑ → float delay time HLDRQ↑ → HLDAK↑ Symbol Test Conditions MIN. tFHQC tDHQHHAH VDD = +5.0 V ± 10 % delay time Float → HLDAK↑ delay time HLDRQ↓ → HLDAK↓ tDCFHA tDHQLHAL VDD = +5.0 V ± 10 % delay time HLDAK↓ → active delay time tDHAC VDD = +5.0 V ± 10 % Remark T : TCYK (system clock cycle time) a : 1 in address wait, 0 in the other conditions n : the number of wait (n ≥ 0) 64 MAX. Unit (6 + a + n) T + 50 ns (7 + a + n) T + 30 ns (7 + a + n) T + 40 ns 1T + 30 ns 2T + 40 ns 2T + 60 ns 1T – 20 ns 1T – 30 ns µPD784031Y (3) External wait timing Parameter Address → WAIT↓ input time ASTB↓ → WAIT↓ input time ASTB↓ → WAIT hold time ASTB↓ → WAIT↑ delay time RD↓ → WAIT↓ input time Symbol tDAWT tDSTWT tHSTWTH tDSTWTH tDRWTL Test Conditions MIN. VDD = +5.0 V ± 10 % VDD = +5.0 V ± 10 % VDD = +5.0 V ± 10 % VDD = +5.0 V ± 10 % RD↓ → WAIT↑ delay time tDRWTH VDD = +5.0 V ± 10 % (2 + a) T – 40 ns (2 + a) T – 60 ns 1.5T – 40 ns 1.5T – 60 ns ns (0.5 + n) T + 10 ns VDD = +5.0 V ± 10 % tHRWT Unit (0.5 + n) T + 5 VDD = +5.0 V ± 10 % RD↓ → WAIT↓ hold time MAX. (1.5 + n) T – 40 ns (1.5 + n) T – 60 ns T – 50 ns T – 70 ns nT + 5 ns nT + 10 WAIT↑ → data input time tDWTID VDD = +5.0 V ± 10 % ns (1 + n) T – 40 ns (1 + n) T – 60 ns 0.5T – 5 ns 0.5T – 10 ns WAIT↑ → WR↑ delay time tDWTW 0.5T ns WAIT↑ → RD↑ delay time tDWTR 0.5T ns WR↓ → WAIT↓ input time tDWWTL WR↓ → WAIT hold time WR↓ → WAIT↑ delay time tHWWT tDWWTH VDD = +5.0 V ± 10 % VDD = +5.0 V ± 10 % T – 50 ns T – 75 ns nT + 5 ns nT + 10 ns VDD = +5.0 V ± 10 % (1 + n) T – 40 ns (1 + n) T – 70 ns MAX. Unit Remark T : TCYK (system clock cycle time) a : 1 in address wait, 0 in the other conditions n : the number of wait (n ≥ 0) (4) Refresh timing Parameter Symbol Random read/write cycle time tRC REFRQ low-level pulse width tWRFQL Test Conditions VDD = +5.0 V ± 10 % MIN. 3T ns 1.5T – 25 ns 1.5T – 30 ns ASTB↓ → REFRQ delay time tDSTRFQ 0.5T – 9 ns RD↑ → REFRQ delay time tDRRFQ 1.5T – 9 ns WR↑ → REFRQ delay time tDWRFQ 1.5T – 9 ns REFRQ↑ → ASTB delay time tDRFQST 0.5T – 15 ns REFRQ high-level pulse width tWRFQH 1.5T – 25 ns 1.5T – 30 ns VDD = +5.0 V ± 10 % Remark T: TCYK (system clock cycle time) 65 µPD784031Y Serial Operation (TA = –40 to +85°C, VDD = +2.7 to 5.5 V, AVSS = VSS = 0 V) (1) CSI Parameter Serial clock cycle time (SCK0) Symbol tCYSK0 Test Conditions Input External clock when SCK0, SO0 are CMOS input/output MIN. tWSKL0 Input External clock when SCK0, SO0 are CMOS input/output Output Serial clock high-level width (SCK0) tWSKH0 Input External clock when SCK0, SO0 are CMOS input/output Output Unit 10/fXX + 380 ns T µs 5/fXX + 150 ns 0.5T – 40 µs 5/fXX + 150 ns 0.5T – 40 µs Output Serial clock low-level width (SCK0) MAX. SI0 setup time (to SCK0↑) tSSSK0 40 ns SI0 hold time (from SCK0↑) tHSSK0 5/fXX + 40 ns SO0 output delay time (from SCK0↓) tDSBSK1 CMOS push-pull output (3-wire serial I/O mode) 0 5/fXX + 150 ns tDSBSK2 Open drain output (2-wire serial I/O mode), RL = 1 kΩ 0 5/fXX + 400 ns Remarks 1. The values shown in the table above are those in the condition of CL = 100 pF. 2. T : serial clock cycle set by the software. The minimum value is 16/fXX. 3. fXX : oscillation frequency (2) I2C Parameter Symbol Standard Mode I2C Bus fXX = 4 to 32 MHz High-speed Mode I2C Bus fXX = 8 to 32 MHz MIN. MAX. MIN. MAX. 100 0 400 Unit SCL clock frequency fSCL 0 Low status hold time of SCL clock tLOW 4.7 1.3 µs High status hold time of SCL clock tHIGH 4.0 0.6 µs Data hold time tHD ; DAT 300 300 Data setup time tSU ; DAT 250 100 900 kHz ns ns SDA, SCL signal rise time tR 1000 20 + 0.1Cb 300 ns SDA, SCL signal fall time tF 300 20 + 0.1Cb 300 ns Cb 400 400 pF Load capacitance of each bus line 66 µPD784031Y (3) IOE1, IOE2 Parameter Serial clock cycle time Symbol tCYSK1 Input Test Conditions MIN. VDD = +5.0 V ± 10 % 250 ns 500 ns (SCK1, SCK2) Serial clock low-level width tWSKL1 tWSKH1 Unit Output Internal 16 frequency division T ns Input VDD = +5.0 V ± 10 % 85 ns 210 ns 0.5T – 40 ns 85 ns 210 ns 0.5T – 40 ns (SCK1, SCK2) Serial clock high-level width MAX. Output Internal 16 frequency division Input VDD = +5.0 V ± 10 % (SCK1, SCK2) Output Internal 16 frequency division SI1, SI2 setup time (to SCK1, SCK2↑) tSSSK1 40 ns SI1, SI2 hold time (from SCK1, SCK2↑) tHSSK1 40 ns SO1, SO2 output delay time tDSOSK 0 50 ns (from SCK1, SCK2↓) SO1, SO2 output hold time (from SCK1, SCK2↑) tHSOSK When transferring data 0.5tCYSK1 – 40 ns Remarks 1. The values shown in the table above are those in the condition of CL = 100 pF. 2. T: serial clock cycle set by the software. The minimum value is 16/fXX. (4) UART, UART2 Parameter ASCK clock input cycle time ASCK clock low-level width ASCK clock high-level width Symbol tCYASK tWASKL tWASKH Test Conditions VDD = +5.0 V ± 10 % VDD = +5.0 V ± 10 % VDD = +5.0 V ± 10 % MIN. MAX. Unit 125 ns 250 ns 52.5 ns 85 ns 52.5 ns 85 ns 67 µPD784031Y Other Operations Parameter Symbol Test Conditions MIN. MAX. Unit NMI low-level width tWNIL 10 µs NMI high-level width tWNIH 10 µs INTP0 low-level width tWIT0L 3tCYSMP + 10 ns INTP0 high-level width tWIT0H 3tCYSMP + 10 ns INTP1 to INTP3, CI low-level width tWIT1L 3tCYCPU + 10 ns INTP1 to INTP3, CI high-level width tWIT1H 3tCYCPU + 10 ns INTP4, INTP5 low-level width tWIT2L 10 µs INTP4, INTP5 high-level width tWIT2H 10 µs RESET low-level width tWRSL 10 µs RESET high-level width tWRSH 10 µs Remark tCYSMP : sampling clock set by the software tCYCPU : CPU operation clock set by the software A/D Converter Characteristics (TA = –40 to +85°C, VDD = AVDD = AVREF1 = +2.7 to 5.5 V, VSS = AVSS = 0 V) Parameter Symbol Test Conditions Resolution Total MIN. TYP. MAX. 8 Unit bit errorNote 1.0 % errorNote 0.8 % Quantization error ±1/2 LSB Linearity Conversion time Sampling time tCONV tSAMP FR = 1 120 tCYK FR = 0 180 tCYK FR = 1 24 tCYK FR = 0 36 tCYK Analog input voltage VIAN Analog input impedance RAN –0.3 1000 AVREF1 + 0.3 AVREF1 current AIREF1 0.5 1.5 mA AVDD supply current AIDD1 fXX = 32 MHz, CS = 1 2.0 5.0 mA AIDD2 STOP mode, CS = 0 1.0 20 µA Note Quantization error is not included. This is expressed in proportion to the full-scale value. Remark tCYK: system clock cycle time 68 V MΩ µPD784031Y D/A Converter Characteristics (TA = –40 to +85°C, VDD = AVDD = +2.7 to 5.5 V, VSS = AVSS = 0 V) Parameter Symbol Test Conditions Resolution Load condition 4 MΩ, 30 pF Load condition 2 MΩ, 30 pF Settling time Analog reference voltage TYP. MAX. 8 Total error Output resistance MIN. bit VDD = AVDD = AVREF2 = +2.7 to 5.5 V AVREF3 = 0 V 0.6 % VDD = AVDD = +2.7 to 5.5 V AVREF2 = 0.75VDD AVREF3 = 0.25VDD 0.8 % VDD = AVDD = AVREF2 = +2.7 to 5.5 V AVREF3 = 0 V 0.8 % VDD = AVDD = +2.7 to 5.5 V AVREF2 = 0.75VDD AVREF3 = 0.25VDD 1.0 % 10 µs Load condition 2 MΩ, 30 pF RO Unit DACS0, 1 = 55 H 10 kΩ AVREF2 0.75VDD VDD V AVREF3 0 0.25VDD V AVREF2, AVREF3 resistance value RAIREF DACS0, 1 = 55 H 4 8 kΩ Reference supply input current AIREF2 0 5 mA AIREF3 –5 0 mA 69 µPD784031Y Data Retention Characteristics (TA = –40 to +85°C) Parameter Symbol Test Conditions MIN. TYP. 2.5 MAX. Unit 5.5 V Data retention voltage VDDDR STOP mode Data retention current IDDDR VDDDR = +2.7 to 5.5 V 10 50 µA VDDDR = +2.5 V 2 10 µA VDD rise time tRVD 200 µs VDD fall time tFVD 200 µs VDD hold time (from setting STOP mode) tHVD 0 ms STOP release signal input time tDREL 0 ms Oscillation stabilization wait time tWAIT Crystal resonator 30 ms Ceramic resonator 5 ms pinsNote 0 0.1VDDDR V 0.9VDDDR VDDDR V Input voltage low-level VIL Input voltage high-level VIH Specified Note RESET, P20/NMI, P21/INTP0, P22/INTP1, P23/INTP2/CI, P24/INTP3, P25/INTP4/ASCK/SCK1, P26/INTP5, P27/SI0, P32/SCK0/SCL, and P33/SO0/SDA pins AC Timing Test Point VDD – 1 V 0.8VDD or 2.2 V 0.8VDD or 2.2 V Test Points 0.45 V 70 0.8 V 0.8 V µPD784031Y Timing Waveform (1) Read operation tWSTH ASTB tSAST tDRST tDSTID tHSTLA A8 to A19 tDAID tHRA AD0 to AD7 tDSTR tFRA tDAR tHRID tDRID tDRA RD tWRL (2) Write operation tWSTH ASTB tSAST tDWST tDSTOD tHSTLA A8 to A19 tHWA AD0 to AD7 tDSTW tDAW tHWOD tDWOD tSODW WR tWWL 71 µPD784031Y Hold Timing ADTB, A8 to A19, AD0 to AD7, RD, WR tFHQC tDCFHA tDHAC HLDRQ tDHQHHAH tDHQLHAL HLDAK External WAIT Signal Input Timing (1) Read operation ASTB tDSTWT tDSTWTH tHSTWTH A8 to A19 AD0 to AD7 tDAWT tDWTID RD tDWTR tDRWTL WAIT tHRWT tDRWTH (2) Write operation ASTB tDSTWT tDSTWTH tHSTWTH A8 to A19 AD0 to AD7 tDAWT WR tDWTW tDWWTL WAIT tHWWT tDWWTH 72 µPD784031Y Refresh Timing Waveform (1) Random read/write cycle tRC ASTB WR tRC tRC tRC tRC RD (2) When refresh memory access is simultaneous with read, write ASTB RD, WR tDSTRFQ tDRFQST tWRFQH REFRQ tWRFQL (3) Refresh after read ASTB tDRFQST RD tDRRFQ REFRQ tWRFQL (4) Refresh after write ASTB tDRFQST WR tDWRFQ REFRQ tWRFQL 73 µPD784031Y Serial Operation (1) CSI tWSKL0 tWSKH0 SCK tSSSK0 tHSSK0 tCYSK0 SI Input Data tDSBSK1 SO tHSBSK1 Output Data (2) I2C tR tF tHIGH tLOW SCL SDA tHD ; DAT tSU ; DAT (3) IOE1, IOE2 tWSKL1 tWSKH1 SCK tSSSK1 tCYSK1 SI Input Data tDSOSK SO tHSOSK Output Data (4) UART, UART2 tWASKH tWASKL ASCK, ASCK2 tCYASK 74 tHSSK1 µPD784031Y Interrupt Input Timing tWNIH tWNIL tWIT0H tWIT0L tWIT1H tWIT1L tWIT2H tWIT2L tWRSH tWRSL NMI INTP0 CI, INTP1 to INTP3 INTP4, INTP5 Reset Input Timing RESET 75 µPD784031Y External Clock Timing tWXH tWXL X1 tXR tXF tCYX Data Retention Characteristics STOP Mode Setting VDD VDDDR tHVD RESET NMI (release by falling edge) NMI (release by rising edge) 76 tFVD tRVD tDREL tWAIT µPD784031Y 14. PACKAGE DRAWINGS 80 PIN PLASTIC QFP (14×14) A B 41 40 60 61 detail of lead end C D S R Q 21 20 80 1 F J G H I M K P M N L NOTE Each lead centerline is located within 0.13 mm (0.005 inch) of its true position (T.P.) at maximum material condition. ITEM MILLIMETERS INCHES A 17.2±0.4 0.677±0.016 B 14.0±0.2 0.551 +0.009 –0.008 C 14.0±0.2 0.551 +0.009 –0.008 D 17.2±0.4 0.677±0.016 F 0.825 0.032 G 0.825 0.032 H 0.30±0.10 0.012 +0.004 –0.005 I 0.13 0.005 J 0.65 (T.P.) 0.026 (T.P.) K 1.6±0.2 L 0.8±0.2 0.063±0.008 0.031 +0.009 –0.008 M 0.15 +0.10 –0.05 0.006 +0.004 –0.003 N 0.10 0.004 P 2.7 0.106 Q 0.1±0.1 0.004±0.004 R 5°±5° 5°±5° S 3.0 MAX. 0.119 MAX. S80GC-65-3B9-4 Remark Dimensions and materials of ES products are the same as those of mass-produced products. 77 µPD784031Y 80 PIN PLASTIC QFP (14×14) A B 60 61 41 40 detail of lead end C S D R Q 80 1 21 20 F G H I M J P K M N NOTE Each lead centerline is located within 0.13 mm (0.005 inch) of its true position (T.P.) at maximum material condition. L ITEM MILLIMETERS INCHES A 17.20±0.20 0.677±0.008 B 14.00±0.20 0.551 +0.009 –0.008 C 14.00±0.20 0.551 +0.009 –0.008 D 17.20±0.20 0.677±0.008 F 0.825 0.032 G 0.825 0.032 H 0.32±0.06 0.013 +0.002 –0.003 I 0.13 0.005 J 0.65 (T.P.) 0.026 (T.P.) K 1.60±0.20 0.063±0.008 L 0.80±0.20 0.031 +0.009 –0.008 M 0.17 +0.03 –0.07 0.007 +0.001 –0.003 N 0.10 0.004 P 1.40±0.10 0.055±0.004 Q 0.125±0.075 0.005±0.003 R 3° +7° –3° 3° +7° –3° S 1.70 MAX. 0.067 MAX. P80GC-65-8BT Remark Dimensions and materials of ES products are the same as those of mass-produced products. 78 µPD784031Y 80-PIN PLASTIC TQFP (FINE PITCH) (12 × 12 mm) A B 60 41 61 40 21 F 80 1 20 H I M J K M P G R Q S D C detail of lead end N L NOTE Each lead centerline is located within 0.10 mm (0.004 inch) of its true position (T.P.) at maximum material condition. ITEM MILLIMETERS INCHES A 14.0±0.2 0.551 +0.009 –0.008 B 12.0±0.2 0.472 +0.009 –0.008 C 12.0±0.2 0.472 +0.009 –0.008 D 14.0±0.2 0.551 +0.009 –0.008 F 1.25 0.049 G 1.25 0.049 H 0.22 +0.05 –0.04 0.009±0.002 I 0.10 0.004 J 0.5 (T.P.) 0.020 (T.P.) K 1.0±0.2 0.039 +0.009 –0.008 L 0.5±0.2 0.020 +0.008 –0.009 M 0.145 +0.055 –0.045 0.006±0.002 N 0.10 0.004 P 1.05 0.041 Q 0.05±0.05 0.002±0.002 R 5°±5° 5°±5° S 1.27 MAX. 0.050 MAX. P80GK-50-BE9-4 Remark Dimensions and materials of ES products are the same as those of mass-produced products. 79 µPD784031Y 15. RECOMMENDED SOLDERING CONDITIONS This product should be soldered and mounted under the conditions recommended in the table below. For details of recommended soldering conditions, refer to the information document Semiconductor Device Mounting Technology Manual (C10535E). For soldering methods and conditions other than those recommended below, contact an NEC sales representative. Table 15-1. Surface Mounting Type Soldering Conditions (1/2) (1) µPD784031YGC-3B9: 80-pin plastic QFP (14 × 14 mm, thickness 2.7 mm) Soldering Method Infrared reflow Soldering Conditions Package peak temperature: 235°C, Duration: 30 sec. max. (at 210°C or above), Symbol IR35-00-3 Number of times: 3 times max. VPS Package peak temperature: 215°C, Duration: 40 sec. max. (at 200°C or above), Number of times: 3 times max. VP15-00-3 Wave soldering Solder bath temperature: 260°C max., Duration: 10 sec. max., Number of times: Once, Preliminary heat temperature: 120°C max. (Package surface temperature) WS60-00-1 Partial heating Pin temperature: 300°C max. Duration: 3 sec. max. (per device side) Caution — Use of more than one soldering method should be avoided (except in the case of partial heating). (2) µPD784031YGC-8BT: 80-pin plastic QFP (14 × 14 mm, thickness 1.4 mm) Soldering Method Soldering Conditions Symbol Infrared reflow Package peak temperature: 235°C, Duration: 30 sec. max. (at 210°C or above), Number of times: Twice max. IR35-00-2 VPS Package peak temperature: 215°C, Duration: 40 sec. max. (at 200°C or above), Number of times: Twice max. VP15-00-2 Wave soldering Solder bath temperature: 260°C max., Duration: 10 sec. max., Number of times: Once, Preliminary heat temperature: 120°C max. (Package surface temperature) WS60-00-1 Partial heating Pin temperature: 300°C max. Duration: 3 sec. max. (per device side) Caution 80 — Use of more than one soldering method should be avoided (except in the case of partial heating). µPD784031Y Table 15-1. Surface Mounting Type Soldering Conditions (2/2) (3) µPD784031YGK-BE9: 80-pin plastic TQFP (fine pitch) (12 × 12 mm) Soldering Method Soldering Conditions Symbol Infrared reflow Package peak temperature: 235°C, Duration: 30 sec. max. (at 210°C or above), Number of times: Twice max., Time limit: 7 daysNote (thereafter 10 hours prebaking required at 125°C) <precaution> Do not bake devices by packing them in non-heat resistant trays or packing materials such as magazine cases and tapes. Use heat-resistant trays. IR35-107-2 VPS Package peak temperature: 215°C, Duration: 40 sec. (at 200°C or above), Number of times: Twice max., Time limit: 7 daysNote (thereafter 10 hours prebaking VP15-107-2 required at 125°C) <precaution> Do not bake devices by packing them in non-heat resistant trays or packing materials such as magazine cases and tapes. Use heat-resistant trays. Partial heating Pin temperature: 300°C max. Duration: 3 sec. max. (per device side) — Note For the storage period after dry-pack decapsulation, storage conditions are max. 25°C, 65 % RH. Caution Use of more than one soldering method should be avoided (except in the case of partial heating). 81 µPD784031Y APPENDIX A. DEVELOPMENT TOOLS The following development tools are available for supporting development of a system using the µPD784031Y. Language Processor Software RA78K4Note 1 Assembler package common to 78K/IV Series CC78K4Note 1 C compiler package common to 78K/IV Series CC78K4-LNote 1 C compiler library source file common to 78K/IV Series PROM Writing Tool PG-1500 PROM programmer PA-78P4026GC Programmer adapter connected to PG-1500 PA-78P4038GK PA-78P4026KK PG-1500 controllerNote 2 PG-1500 control program Debugging Tool IE-784000-R In-circuit emulator common to 78K/IV Subseries IE-784000-R-BK Break board common to 78K/IV Series IE-784038-R-EM1 Emulation board for evaluation of µPD784038Y Subseries IE-784000-R-EM IE-70000-98-IF-B Interface adapter when PC-9800 Series (except notebook type) is used as host machine IE-70000-98N-IF Interface adapter and cable when notebook type PC-9800 Series is used as host machine IE-70000-PC-IF-B Interface adapter when IBM PC/ATTM is used as host machine IE-78000-R-SV3 Interface adapter and cable when EWS is used as host machine EP-78230GC-R Emulation probe for 80-pin plastic QFP (GC-3B9 and GC-8BT types) common to µPD784038Y Subseries EP-78054GK-R Emulation probe for 80-pin plastic TQFP (fine pitch) (GK-BE9 type) common to µPD784038Y Subseries EV-9200GC-80 Socket mounted on board of target system created for 80-pin plastic QFP (GC-3B9 and GC-8BT types) TGK-080SDW Adapter mounted on board of target system created for 80-pin plastic TQFP (fine pitch) (GK-BE9 type) EV-9900 Jig used to remove µPD78P4038YKK-T from EV-9200GC-80 SM78K4Note 3 System simulator common to 78K/IV Series ID78K4Note 3 Integrated debugger for IE-784000-R DF784038Note 4 Device file for µPD784038Y Subseries Real-time OS RX78K/IVNote 4 Real-time OS for 78K/IV Series MX78K4Note 2 OS for 78K/IV Series 82 µPD784031Y Notes 1. • PC-9800 Series (MS-DOSTM) based • IBM PC/AT and compatible machine (PC DOSTM, WindowsTM, MS-DOS, IBM DOSTM) based • HP9000 Series 700TM (HP-UXTM) based • SPARCstationTM (SunOSTM) based • NEWSTM (NEWS-OSTM) based 2. • PC-9800 Series (MS-DOS) based • IBM PC/AT and compatible machine (PC DOS, Windows, MS-DOS, IBM DOS) based 3. • PC-9800 Series (MS-DOS + Windows) based • IBM PC/AT and compatible machine (PC DOS, Windows, MS-DOS, IBM DOS) based • HP9000 Series 700 (HP-UX) based • SPARCstation (SunOS) based 4. • PC-9800 Series (MS-DOS) based • IBM PC/AT and compatible machine (PC DOS, Windows, MS-DOS, IBM DOS) based • HP9000 Series 700 (HP-UX) based • SPARCstation (SunOS) based Remarks 1. RA78K4, CC78K4, SM78K4, and ID78K4 are used in combination with DF784038. 2. TGK-080SDW is manufactured by TOKYO ELETECH Corporation. Consult your local NEC sales representative when purchasing it. 83 µPD784031Y APPENDIX B. RELATED DOCUMENTS Documents Related to Device Document Name Document No. English Japanese This manual U11504J µPD784035Y, 784036Y, 784037Y, 784038Y Data Sheet U10741E U10741J µPD78P4038Y Data Sheet U10742E U10742J µPD784038, 784038Y Subseries User’s Manual - Hardware U11316E U11316J – U11091J U10905E U10905J 78K/IV Series Instruction Table – U10594J 78K/IV Series Instruction Set – U10595J 78K/IV Series Application Note - Software Basics – U10095J µPD784031Y Data Sheet µPD784038Y Subseries Special Function Register Table 78K/IV Series User’s Manual - Instruction Documents Related to Development Tools (User’s Manuals) Document Name Document No. English Japanese Operation U11334E U11334J Language – U11162J EEU-1402 EEU-817 Operation – EEU-960 Language – EEU-961 – U12322J PG-1500 PROM Programmer EEU-1335 U11940J PG-1500 Controller - PC-9800 Series (MS-DOS) Based EEU-1291 EEU-704 PG-1500 Controller - IBM PC Series (PC DOS) Based U10540E EEU-5008 IE-784000-R EEU-1534 EEU-5004 IE-784038-R-EM1 U11383E U11383J EP-78230 EEU-1515 EEU-985 EP-78054GK-R EEU-1468 EEU-932 U10093E U10093J U10092E U10092J RA78K4 Assembler Package RA78K Series Structured Assembler Preprocessor CC78K4 Series CC78K Series Library Source File SM78K4 System Simulator - Windows Based Reference SM78K Series External Part User Open Interface Specifications ID78K4 Integrated Debugger - Windows Based Reference U10440E U10440J ID78K4 Integrated Debugger - HP9000 Series 700 (HP-UX) Based Reference To be released soon U11960J Caution The above related documents are subject to change without prior notice. Be sure to use the latest version when starting design. 84 µPD784031Y Documents Related to Embedded Software (User’s Manual) Document Name 78K/IV Series Real-time OS 78K/IV Series OS MX78K4 Document No. English Japanese Basics U10603E U10603J Installation U10604E U10604J Debugger – U10364J Basics – U11779J Other Documents Document Name Document No. English IC Package Manual Japanese C10943X Semiconductor Device Mounting Technology Manual C10535E C10535J Quality Grades on NEC Semiconductor Devices C11531E C11531J Reliability Quality Control on NEC Semiconductor Device C10983E C10983J – MEM-539 MEI-1202 C11893J – U11416J Electric Static Discharge (ESD) Test Semiconductor Devices Quality Assurance Guide Microcomputer Product Series Guide Caution The above related documents are subject to change without prior notice. Be sure to use the latest version when starting design. 85 µPD784031Y NOTES FOR CMOS DEVICES 1 PRECAUTION AGAINST ESD FOR SEMICONDUCTORS Note: Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. Environmental control must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using insulators that easily build static electricity. Semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. All test and measurement tools including work bench and floor should be grounded. The operator should be grounded using wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need to be taken for PW boards with semiconductor devices on it. 2 HANDLING OF UNUSED INPUT PINS FOR CMOS Note: No connection for CMOS device inputs can be cause of malfunction. If no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. CMOS device behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused pin should be connected to VDD or GND with a resistor, if it is considered to have a possibility of being an output pin. All handling related to the unused pins must be judged device by device and related specifications governing the devices. 3 STATUS BEFORE INITIALIZATION OF MOS DEVICES Note: Power-on does not necessarily define initial status of MOS device. Production process of MOS does not define the initial operation status of the device. Immediately after the power source is turned ON, the devices with reset function have not yet been initialized. Hence, power-on does not guarantee outpin levels, I/O settings or contents of registers. Device is not initialized until the reset signal is received. Reset operation must be executed immediately after power-on for devices having reset function. 86 µPD784031Y Regional Information Some information contained in this document may vary from country to country. Before using any NEC product in your application, please contact the NEC office in your country to obtain a list of authorized representatives and distributors. They will verify: • Device availability • Ordering information • Product release schedule • Availability of related technical literature • Development environment specifications (for example, specifications for third-party tools and components, host computers, power plugs, AC supply voltages, and so forth) • Network requirements In addition, trademarks, registered trademarks, export restrictions, and other legal issues may also vary from country to country. NEC Electronics Inc. (U.S.) NEC Electronics (Germany) GmbH NEC Electronics Hong Kong Ltd. Santa Clara, California Tel: 800-366-9782 Fax: 800-729-9288 Benelux Office Eindhoven, The Netherlands Tel: 040-2445845 Fax: 040-2444580 Hong Kong Tel: 2886-9318 Fax: 2886-9022/9044 NEC Electronics (Germany) GmbH Duesseldorf, Germany Tel: 0211-65 03 02 Fax: 0211-65 03 490 NEC Electronics Hong Kong Ltd. NEC Electronics (France) S.A. Velizy-Villacoublay, France Tel: 01-30-67 58 00 Fax: 01-30-67 58 99 Seoul Branch Seoul, Korea Tel: 02-528-0303 Fax: 02-528-4411 NEC Electronics (France) S.A. NEC Electronics Singapore Pte. Ltd. Spain Office Madrid, Spain Tel: 01-504-2787 Fax: 01-504-2860 United Square, Singapore 1130 Tel: 253-8311 Fax: 250-3583 NEC Electronics (UK) Ltd. Milton Keynes, UK Tel: 01908-691-133 Fax: 01908-670-290 NEC Electronics Italiana s.r.1. Milano, Italy Tel: 02-66 75 41 Fax: 02-66 75 42 99 NEC Electronics Taiwan Ltd. NEC Electronics (Germany) GmbH Scandinavia Office Taeby, Sweden Tel: 08-63 80 820 Fax: 08-63 80 388 Taipei, Taiwan Tel: 02-719-2377 Fax: 02-719-5951 NEC do Brasil S.A. Sao Paulo-SP, Brasil Tel: 011-889-1680 Fax: 011-889-1689 J96. 8 87 µPD784031Y Caution Purchase of NEC I2C components conveys a license under the Philips I2C Patent Rights to use these components in an I2C system, provided that the system conforms to the I2C Standard Specification as defined by Philips. EEPROM and IEBus are trademarks of NEC Corporation. MS-DOS and Windows are either registered trademarks or trademarks of Microsoft Corporation in the United States and/or other countries. IBM DOS, PC/AT, and PC DOS are trademarks of International Business Machines Corporation. HP9000 Series 700 and HP-UX are trademarks of Hewlett-Packard Company. SPARCstation is a trademark of SPARC International, Inc. SunOS is a trademark of Sun Microsystems, Inc. NEWS and NEWS-OS are trademarks of Sony Corporation. The related documents indicated in this publication may include preliminary versions. However, preliminary versions are not marked as such. No part of this document may be copied or reproduced in any form or by any means without the prior written consent of NEC Corporation. NEC Corporation assumes no responsibility for any errors which may appear in this document. NEC Corporation does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from use of a device described herein or any other liability arising from use of such device. No license, either express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of NEC Corporation or others. While NEC Corporation has been making continuous effort to enhance the reliability of its semiconductor devices, the possibility of defects cannot be eliminated entirely. To minimize risks of damage or injury to persons or property arising from a defect in an NEC semiconductor device, customers must incorporate sufficient safety measures in its design, such as redundancy, fire-containment, and anti-failure features. NEC devices are classified into the following three quality grades: “Standard”, “Special”, and “Specific”. The Specific quality grade applies only to devices developed based on a customer designated “quality assurance program” for a specific application. The recommended applications of a device depend on its quality grade, as indicated below. Customers must check the quality grade of each device before using it in a particular application. Standard: Computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots Special: Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support) Specific: Aircrafts, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems or medical equipment for life support, etc. The quality grade of NEC devices is “Standard” unless otherwise specified in NEC’s Data Sheets or Data Books. If customers intend to use NEC devices for applications other than those specified for Standard quality grade, they should contact an NEC sales representative in advance. Anti-radioactive design is not implemented in this product. M4 96.5