NEC UPD72107

DATA SHEET
MOS INTEGRATED CIRCUIT
µPD72107
LAP-B CONTROLLER
Link Access Procedure Balanced mode
The µPD72107 is an LSI that supports LAP-B protocol specified by the ITU-T recommended X.25 on a single
chip.
FEATURES
• Complied with ITU-T recommended X.25 (LAP-B84
• Memory-based interface
edition)
Memory-based command
HDLC frame control
Memory-based status
Memory-based transmit/receive data
Sequence control
• MAX.4 Mbps serial transfer rate
Flow control
• NRZ, NRZI coding
• ITU-T recommended X.75 supported
• TTC standard JT-T90 supported
• Optional functions
Option frame
Global address frame
Error check deletion frame
• Powerful test functions
Data loopback function
Loopback test link function
Frame trace function
• Abundant statistical information
• Detailed mode setting function
• Modem control function
• On-chip DMAC (Direct Memory Access Controller)
24-bit address
Byte/word transfer enabled (switch with external pin)
ORDERING INFORMATION
Part Number
Package
µPD72107CW
64-pin plastic shrink DIP (750 mils)
µPD72107GC-3B9
80-pin plastic QFP (14 x 14 mm)
µPD72107L
68-pin plastic QFJ (950 x 950 mils)
The information in this document is subject to change without notice.
Document No. S12962EJ5V0DS00 (5th edition)
Date Published October 1998 N CP(K)
Printed in Japan
©
1998
µPD72107
BLOCK DIAGRAM
D0-D7
A16D8
-A23D15
A0-A15
IORD
IOWR
MRD
MWR
UBE
CS
ASTB
AEN
READY
HLDRQ
HLDAK
CRQ
INT
CLRINT
B/W
PU
TxC
TxD
Internal controller
TxFIFO
RTS
CTS
Bus
interface
Internal bus
CD
Receiver
RxFIFO
DMAC
RxC
VCC
GND
RESET
CLK
RxD
Name
Function
Bus interface
An interface between the µPD72107 and external memory or external host processor
Internal controller
Manages LAP-B protocol including control of the DMAC block, transmitter block, and receiver block
DMAC
(Direct Memory
Access Controller)
Controls the transfer of data on the external memory to the internal controller or transmitter block,
and controls the writing of data in the internal controller or receiver block to the external memory
TxFIFO
A 16-byte buffer for when transmit data is sent from the DMAC to the transmitter block
RxFIFO
A 32-byte buffer for when receive data is sent from the receiver block to the DMAC
Transmitter
Converts the contents of TxFIFO into an HDLC frame and transmits it as serial data
Receiver
Receives HDLC frame and writes internal data to RxFIFO
Internal bus
An 8-bit address bus and 8-bit data bus that connect the internal controller, DMAC, FIFO, serial block,
and bus interface block
2
Transmitter
µPD72107
PIN CONFIGURATION (Top View)
64-pin plastic shrink DIP (750 mils)
µ PD72107CW
IC
1
64
RTS
RxC
2
63
CD
RxD
3
62
CRQ
TxC
4
61
AEN
TxD
5
60
ASTB
CTS
6
59
READY
IC
7
58
HLDAK
RESET
8
57
HLDRQ
NC
9
56
CLRINT
IC
10
55
INT
B/W
11
54
UBE
PU
12
53
MWR
CLK
13
52
MRD
GND
14
51
GND
A0
15
50
IOWR
A1
16
49
IORD
A2
17
48
CS
A3
18
47
VCC
A4
19
46
D7
A5
20
45
D6
A6
21
44
D5
A7
22
43
D4
A8
23
42
D3
A9
24
41
D2
A10
25
40
D1
A11
26
39
D0
A12
27
38
A23D15
A13
28
37
A22D14
A14
29
36
A21D13
A15
30
35
A20D12
A16D8
31
34
A19D11
A17D9
32
33
A18D10
3
µPD72107
80-pin plastic QFP (14 × 14 mm)
NC
D2
D5
D4
D3
VCC
NC
VCC
D7
D6
CS
GND
IOWR
IORD
UBE
MWR
MRD
INT
CLRINT
NC
µ PD72107GC-3B9
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61
NC
1
60
D1
HLDRQ
2
59
D0
HLDAK
3
58
A23D15
READY
ASTB
AEN
4
5
6
57
56
55
A22D14
A21D13
NC
NC
CRQ
CD
7
8
9
54
53
52
A20D12
A19D11
A18D10
RTS
10
51
NC
NC
IC
RxC
RxD
NC
11
12
13
14
15
50
49
48
47
46
NC
A17D9
A16D8
A15
A14
TxC
TxD
CTS
16
17
18
45
44
43
A13
A12
A11
IC
19
42
A10
NC
20
41
NC
A9
NC
A6
A7
A8
A1
A2
A3
A4
A5
A0
GND
GND
NC
B/W
PU
CLK
IC
NC
4
RESET
21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40
µPD72107
68-pin plastic QFJ (950 × 950 mils)
NC
2
1
HLDRQ
IC
3
HLDAK
RxC
4
READY
RxD
5
ASTB
NC
6
AEN
TxC
7
CRQ
TxD
8
CD
CTS
9
RTS
IC
µ PD72107L
RESET
10
68 67 66 65 64 63 62 61
60
CLRINT
IOWR
A0
17
53
IORD
A1
18
52
CS
A2
19
51
VCC
A3
20
50
VCC
A4
21
49
D7
A5
22
48
D6
A6
23
47
D5
A7
24
46
D4
A8
25
45
D3
A9
26
44
27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43
D2
D1
GND
54
D0
55
16
A23D15
15
GND
A22D14
GND
A21D13
MRD
A20D12
56
A19D11
14
A18D10
CLK
NC
MWR
A17D9
57
A16D8
13
A15
PU
A14
UBE
A13
INT
58
A12
59
12
A11
11
A10
IC
B/W
5
µPD72107
1. PINS
1.1 Pin Functions
SDIP
QFP
QFJ
Pin Name
VCC
GND
CLK
Active
I/O
Pin No.
Pin No.
Pin No.
47
68
50
70
51
14
27
15
51
28
16
74
55
13
26
14
Function
Level
–
–
+5 V power supply
–
–
Ground (0 V)
Note that there is more than one ground pin.
I
–
(Clock)
RESET
System clock input
Input clock of 1 MHz to 8.2 MHz.
8
22
10
I
L
(Reset)
Initializes the internal µ PD72107. Active width of
more than 7 CLK clock cycles is required (clock
input is required).
After reset, this pin becomes a bus slave.
PU
12
25
13
I
–
Pull up to high level when using in normal operation.
48
71
52
I
L
When bus master
(Pull Up)
CS
(Chip Select)
Set to disable.
When bus slave
Read/write operation from the host processor at low
level is enabled.
MRD
52
75
56
(Memory Read)
O
L
3-state
When bus master
Reads the data of the external memory at low level.
When bus slave
High impedance
MWR
53
76
57
(Memory Write)
O
L
3-state
When bus master
Writes the data to the external memory at low level.
When bus slave
High impedance
IORD
49
72
53
I
L
(I/O Read)
This pin is used when the external host processor
reads the contents of the internal registers of the
µ PD72107.
IOWR
50
73
54
I
L
(I/O Write)
This pin is used when the external host processor
writes the data to the internal registers of the
µ PD72107.
ASTB
(Address Strobe)
6
60
5
64
O
H
This pin is used to latch the address output from
the µ PD72107 externally.
µPD72107
SDIP
QFP
QFJ
Pin Name
NC
Active
I/O
Pin No.
Pin No.
Pin No.
9
1, 7,
1
11, 15,
5
20, 21,
35
(No Connection)
Function
Level
–
–
Use this pin open.
–
–
Do not connect anything to this pin.
I/O
L/H
29, 40,
41, 50,
51, 55,
61, 69,
80
IC
1
12
2
(Internally
7
19
9
10
23
11
54
77
58
Connected)
UBE
(Upper Byte
Enable)
3-state
When bus master (output)
The signal output from this pin changes according
to the input value of the B/W pin.
• Byte transfer mode (B/W = 0)
UBE is always high impedance.
• Word transfer mode (B/W = 1)
Indicates that valid data is either in pins D0 to D7
or pins A16D8 to A23D15 (or both).
UBE
A0
0
0
0
1
1
0
1
1
D0 to D7 A16D8 to A23D15
×
×
×
×
When bus slave (input)
UBE pin becomes input, and indicates that valid
data is either in pins D0 to D7 or pins A16D8 to
A23D15.
UBE
A0
D0 to D7 A16D8 to A23D15
0
0
0
1
1
0
×
1
1
×
×
×
7
µPD72107
Pin Name
B/W
SDIP
QFP
QFJ
Pin No.
Pin No.
Pin No.
11
24
12
I/O
Active
Function
Level
I
L/H
(Byte/Word)
Specifies the data bus that accesses the external
memory when bus master.
B/W = 0
Byte units (8 bits)
B/W = 1
Word units (16 bits)
After power-on, fix the status of the B/W pin.
In the case of word access, the lower data bus is the
contents data of even addresses.
READY
59
4
63
I
H
An input signal that is used to extend the MRD and
MWR signal widths output by the µPD72107 to
(Ready)
adapt to low-speed memory. When the READY
signal is low level, the MRD and MWR signals
maintain active low. Do not change the READY
signal at any time other than the specified setup/
hold time.
HLDRQ
57
2
61
O
H
A hold request signal to the external host processor.
When a DMA operation is performed in the µPD72107,
(Hold Request)
this signal is activated to switch from bus slave to
bus master.
HLDAK
58
3
62
I
H
A hold acknowledge signal from the external host
processor. When the µPD72107 detects that this
(Hold Acknowledge)
signal is active, the bus slave switches to bus
master, and a DMA operation is started.
AEN
61
6
65
O
H
(Address Enable)
When bus master, this signal enables the latched
higher addresses and outputs them to system address bus. This signal is also used for disabling
other system bus drivers.
A0, A1
15, 16
30, 31
17, 18
I/O
–
3-state
Bidirectional 3-state address lines.
When bus master (output)
Indicate the lower 2-bit addresses of memory access.
When bus slave (input)
Input addresses when the external host processor
I/O accesses the µPD72107.
A2 to A15
17 to 30
32 to 47
(except
40, 41)
19 to 32
O
3-state
–
When bus master
Output bit 2 to bit 15 of memory access addresses.
When bus slave
Become high impedance.
8
µPD72107
SDIP
Pin Name
A16D8 to A23D15
QFP
QFJ
Pin No.
Pin No.
Pin No.
31 to 38
48 to 58
33 to 41
Active
I/O
I/O
–
(except 50, (except 35) 3-state
39 to 46
59 to 67
Bidirectional 3-state address/data buses. Multiplex
pins of the higher 16 bits to 23 bits of addresses
51, 55)
D0 to D7
Function
Level
and the higher 8 bits to 15 bits of data.
42 to 49
(except 61)
I/O
–
3-state
Bidirectional 3-state data buses.
When bus master
When writing to external memory, these pins become
input if reading at output.
When bus slave
Usually, these pins become high impedance. When
the external host processor reads I/O of the µPD72107,
the internal register data is output.
CRQ
62
8
66
I
H
A signal requesting command execution to the
(Command
µPD72107 by the external host processor. The
Request)
µPD72107 starts fetching commands from on the
external memory at the rising edge of this signal.
INT
55
78
59
O
H
An interrupt signal from the µ PD72107 to the
56
79
60
I
H
A signal inactivating the INT signal being output by
(Interrupt)
CLRINT
external host processor.
the µPD72107. The µPD72107 generates the CLRINT
(Clear Interrupt)
signal in the LSI internal circuit at the rising edge of
this signal, and forcibly makes the INT output signal
low.
CTS
(Clear To Send)
6
18
8
I
–
A general-purpose input pin.
The µPD72107 reports the “CTS pin change detection
status” to the external host processor when the
input level of this pin is changed in the generalpurpose input/output pin support (setting RSSL to
1 by the “system initialization command”).
The
change of input level is recognized only when the
same level is sampled twice in succession after
sampling in 8-ms cycles and detecting the change.
Moreover, when the external host processor issues
a “general-purpose input/output pin read command”
to the µPD72107, the µPD72107 reports the pin
information of this pin to the external host processor
by a “general-purpose input/output pin read response
status”.
The change can be detected even in the clock input
stop status of TxC and RxC.
9
µPD72107
SDIP
Pin Name
RTS
QFP
QFJ
Pin No.
Pin No.
Pin No.
64
10
68
Active
I/O
O
Function
Level
–
(Request To Send)
A general-purpose output pin.
The output value of this pin can be changed by
issuing an “RTS pin write command” from the external
host processor to the µPD72107. Moreover, when
the external host processor issues a “general-purpose
input/output pin read command” to the µPD72107,
the µPD72107 reports the pin information of this pin
to the external host processor by a “general-purpose
input/output pin read response status”.
CD
63
9
67
I
–
A general-purpose input pin.
The µPD72107 reports the “CD pin change detection
(Carrier Detect)
status” to the external host processor when the
input level of this pin is changed in the generalpurpose input/output pin support (setting RSSL to
1 by the “system initialization command”).
The
change of input level is recognized only when the
same level is sampled twice in succession after
sampling in 8-ms cycles and detecting the change.
Moreover, when the external host processor issues
a “general-purpose input/output pin read command”
to the µPD72107, the µPD72107 reports the pin
information of this pin to the external host processor
by a “general-purpose input/output pin read response
status”.
The change can be detected even in the clock input
stop status of TxC and RxC.
TxD
5
17
7
O
–
A serial transmit data output pin.
4
16
6
I/O
–
When CLK is set to 01 or 10 by “operation mode
(Transmit Data)
TxC
(Transmit Clock)
3-state
setting LCW” (output)
Outputs a clock that divides by 16 the input signal
of the RxC pin or CLK pin made by the µPD72107.
Caution TxC becomes input because CLK = 00
is the default after reset. It becomes
output after setting CLK to 01 or 10 by
“operation mode setting LCW”.
When CLK is set to 00 by “operation mode setting
LCW” (input)
Inputs transmit clock externally.
Remark LCW: abbreviation for Link Command Word
10
µPD72107
SDIP
QFP
QFJ
Active
Pin Name
I/O
RxD
Function
Pin No.
Pin No.
Pin No.
Level
3
14
4
I
–
A serial receive data input pin.
2
13
3
I
–
When CLK is set to 01 or 10 by “operation mode
(Receive Data)
RxC
(Receive Clock)
setting LCW”
Sixteen times the clock input of the transmit/receive
clock for the on-chip DPLL of the µ PD72107
When CLK is set to 00 by “operation mode setting
LCW”
One time the clock input of the receive clock
Remark LCW: abbreviation for Link Command Word
1.2 Pin Status after Reset of µ PD72107
The status of the output pins and input/output pins after reset in the µ PD72107 is as shown in Table 1-1.
Table 1-1. Pin Status after Reset
Pin Number
I/O
During Reset
TxC
I/O Note
High impedance
TxD
O
H
I/O Note
High impedance
O Note
High impedance
A16D8 to A23D15
I/O Note
High impedance
D0 to D7
I/O Note
High impedance
MRD
O Note
High impedance
High impedance
Pin Name
64-pin SDIP
80-pin QFP
68-pin QFJ
4
16
6
5
17
7
15, 16
30, 31
17, 18
17 to 30
32 to 47
(except 40, 41)
19 to 32
31 to 38
48 to 58
(except 50, 51, 55)
33 to 41
(except 35)
39 to 46
59 to 67
(except 61)
42 to 49
52
75
56
A0, A1
A2 to A15
53
76
57
MWR
O Note
54
77
58
UBE
I/O Note
High impedance
55
78
59
INT
O
L
57
2
61
HLDRQ
O
L
60
5
64
ASTB
O
L
61
6
65
AEN
O
L
64
10
68
RTS
O
H
Note 3-state
Remarks 1. The status after reset is released is the same as the status during reset.
2. Input low level to the RESET pin for more than 7 clocks of the system clock.
11
µPD72107
2. ELECTRICAL SPECIFICATIONS
Absolute Maximum Ratings (TA = +25°C)
Parameter
Symbol
Conditions
Ratings
Unit
–0.5 to +7.0
V
Power supply voltage
VDD
Input voltage
VI
–0.5 to V DD + 0.3
V
Output voltage
VO
–0.5 to V DD + 0.3
V
Operating ambient temperature
TA
–40 to +85
°C
Storage temperature
Tstg
–40 to +125
°C
Caution Product quality may suffer if the absolute maximum rating is exceeded even momentarily for
any parameter. That is, the absolute maximum ratings are rated values at which the product
is on the verge of suffering physical damage, and therefore the product must be used under
conditions that ensure that the absolute maximum ratings are not exceeded.
DC Characteristics (TA = –40 to +85°C, VDD = 5 V ±10%)
Parameter
Input voltage, low
Symbol
Conditions
MIN.
TYP.
MAX.
Unit
VILC
CLK pin
–0.5
+0.8
V
VIL
Other pins
–0.5
+0.8
V
VIHC
CLK and PU pins
+3.3
VDD + 0.3
V
VIH
Other pins
+2.2
VDD + 0.3
V
Output voltage, low
VOL
I OL = 2.5 mA
0.4
V
Output voltage, high
VOH
I OH = –400 µA
Power supply current
I DD
At operation
Input leakage current
I LI
Output leakage current
I LO
Input voltage, high
0.7 × V DD
V
20
50
mA
0 V ≤ V IN ≤ V DD
±10
µA
0 V ≤ V OUT ≤ VDD
±10
µA
Capacitance (TA = +25°C, VDD = 0 V)
Parameter
Symbol
Conditions
MIN.
TYP.
MAX.
Unit
Input capacitance
CI
f C = 1 MHz
–
8
15
pF
Output capacitance
CO
Unmeasured pins returned to 0 V
–
8
15
pF
I/O capacitance
CIO
–
8
20
pF
12
µPD72107
AC Characteristics (TA = –40 to +85°C, VDD = 5 V ±10%)
When bus master (1)
Parameter
Symbol
Conditions
MIN.
MAX.
Unit
1000
ns
CLK cycle time
t CYK
121
CLK low-level time
t KKL
50
ns
CLK high-level time
t KKH
50
ns
CLK rise time
t KR
1.5 – 3.0 V
10
ns
CLK fall time
t KF
3.0 – 1.5 V
10
ns
Load condition
DUT
CL = 50 pF
CL includes jig capacitance.
Caution If the load capacitance exceeds 50 pF due to the configuration of the circuit, keep the load
capacitance of this device to within 50 pF by inserting a buffer or by some other means.
Remark DUT: device under test
AC test input/output waveform (except clock)
2.4 V
2.2 V
2.2 V
Test points
0.8 V
0.8 V
0.4 V
System clock
tKF
tKR
tKKL
3.0 V
CLK
1.5 V
tKKH
tCYK
13
µPD72107
When bus master (2)
Parameter
Symbol
Conditions
MIN.
MAX.
Unit
HLDRQ ↑ delay time (vs. CLK ↓)
t DHQH
100
ns
HLDRQ ↓ delay time (vs. CLK ↑)
t DHQL
100
ns
HLDAK setup time (vs. CLK ↑)
t SHA
35
ns
HLDAK hold time (vs. CLK ↑)
t HHA
20
ns
AEN ↑ delay time (vs. CLK ↓)
t DAEH
100
ns
AEN ↓ delay time (vs. CLK ↑)
t DAEL
100
ns
ASTB ↑ delay time (vs. CLK ↑)
t DSTH
70
ns
ASTB high-level width
t STSTH
ASTB ↓ delay time (vs. CLK ↓)
t DSTL
100
ns
ADR/UBE/MRD/MWR delay time
(vs. CLK ↑)
t DA
100
ns
ADR/UBE/MRD/MWR float time
(vs. CLK ↑)
t FA
70
ns
ADR setup time (vs. ASTB ↓)
t SAST
t KKH–35
ns
ADR hold time (vs. ASTB ↓)
t HSTA
t KKL –20
ns
MRD ↓ delay time (vs. ADR float)
t DAR
0
ns
MRD ↓ delay time (vs. CLK ↑)
t DRL
MRD low-level width
t RRL2
MRD ↑ delay time (vs. CLK ↑)
t DRH
Data setup time (vs. MRD ↑)
t SDR
100
ns
Data hold time (vs. MRD ↑)
t HRD
0
ns
MWR ↓ delay time (vs. CLK ↑)
t DWL
MWR low-level width
t WWL2
MWR ↑ delay time (vs. CLK ↑)
t DWH
READY setup time (vs. CLK ↑)
t SRY
35
ns
READY hold time (vs. CLK ↑)
t HRY
20
ns
14
t KKH–15
ns
70
2t CYK–50
ns
ns
70
70
2t CYK–50
ns
ns
ns
70
ns
When bus master
CLK
tDHQL
tDHQH
HLDRQ
tSHA
tHHA
tHHA
HLDAK
tDAEH
tDAEL
AEN
tDSTL
tDSTH
ASTB
tSTSTH
A16D8-A23D15
Hi-Z
Address
tSAST
A0, A1/A2-A15
UBE
tDA
Hi-Z
Output data
tHSTA
Hi-Z
Hi-Z
Address
tWWL2
MWR
Hi-Z
Hi-Z
tDWL
tHRY
tHRY
tDWH
READY
tFA
A16D8-A23D15
tSRY
Hi-Z
tSRY
Address
tDAR
tSDR
tHRD
tDRH
Hi-Z
MRD
15
tRRL2
tDRL
tFA
Hi-Z
µPD72107
tDA
Hi-Z
Input data
µPD72107
When bus slave (1)
Parameter
Symbol
Conditions
MIN.
MAX.
Unit
IOWR low-level width
tWWL
100
ns
CS low-level hold time
(vs. IOWR ↑)
t HWCS
0
ns
ADR/UBE/CS low-level setup time
(vs. IOWR ↓)
tSAW
0
ns
ADR/UBE hold time (vs. IOWR ↑)
t HWA
0
ns
Data setup time (vs. IOWR ↑)
t SDW
100
ns
Data hold time (vs. IOWR ↑)
t HWD
0
ns
IORD low-level width
t RRL
150
ns
ADR/CS low-level setup time
(vs. IORD ↓)
tSAR
35
ns
ADR/CS low-level hold time
(vs. IORD ↑)
t HRA
0
ns
Data delay time (vs. IORD ↓)
t DRD
Data float time (vs. IORD ↑)
t FRD
10
RESET low-level width
t RSTL
7tCYK
ns
VDD setup time (vs. RESET ↑)
t SVDD
1000
ns
RESET ↑ –1st • IOWR/IORD
tSYWR
2tCYK
ns
IOWR/IORD recovery time
t RVWR
200
ns
16
120
ns
100
ns
µPD72107
When bus slave
CS
tSAW
tWWL
tHWCS
IOWR
tHWA
A0-A23
UBE
tSDW
tHWD
D0-D15
CS
A0-A23
tSAR
tHRA
tRRL
IORD
tDRD
D0-D15
tFRD
Hi-Z
VDD
Hi-Z
tSVDD
tRSTL
RESET
tSYWR
IORD/IOWR
tRVWR
IORD
tRVWR
tRVWR
IOWR
tRVWR
17
µPD72107
When bus slave (2)
Parameter
Symbol
Conditions
MIN.
MAX.
Unit
IOWR/IORD high-level setup time
(vs. HLDAK ↑)
tSWR
–20
ns
IOWR/IORD high-level hold time
(vs. AEN ↓)
t HWR
100
ns
HLDAK
tSWR
IOWR/IORD
AEN
tHWR
IOWR/IORD
When bus slave (3)
Parameter
Symbol
Conditions
MIN.
MAX.
100
Unit
CLRINT high-level width
t CLCLH
INT ↑ delay time (vs. CLK ↑)
t DIH
100
ns
INT ↓ delay time (vs. CLRINT ↑)
t DIL
100
ns
CRQ high-level width
t CRCRH
100
CLK
CLRINT
tCLCLH
INT
tDIH
tDIL
CRQ
tCRCRH
18
ns
ns
µPD72107
Serial block (1)
Parameter
Symbol
Conditions
When on-chip DPLL is not used
MIN.
MAX.
Unit
250
DC
ns
TxC/RxC cycle time
t CYS
TxC/RxC low-level time
t SSL
110
ns
TxC/RxC high-level time
tSSH
110
ns
TxC/RxC rise time
t SR
20
ns
TxC/RxC fall time
t SF
12
ns
TxD delay time (vs. TxC ↓)
t DTXD
100
ns
RxD setup time (vs. RxC ↑)
t SRXD
50
ns
RxD hold time (vs. RxC ↑)
t HRXD
70
ns
Serial clock (when on-chip DPLL is not used)
tSF
tSR
tSSL
2.2 V
TxC/RxC
tSSH
0.8 V
tCYS
TxC (input)
tDTXD
tDTXD
TxD
RxC
tSRXD
tHRXD
RxD
19
µPD72107
Serial block (2)
Parameter
Symbol
RxC cycle time
Conditions
t CYR
MIN.
MAX.
When on-chip DPLL is used (source clock = RxC)
When on-chip DPLL is used (source clock = CLK)
30.3
125
1000
Unit
ns
RxC low-level time
t SSRL
When on-chip DPLL is used (source clock = RxC)
When on-chip DPLL is used (source clock = CLK)
10
50
ns
RxC high-level time
t SSRH
When on-chip DPLL is used (source clock = RxC)
When on-chip DPLL is used (source clock = CLK)
10
50
ns
RxC rise time
t SRR
When on-chip DPLL is used (source clock = RxC)
When on-chip DPLL is used (source clock = CLK)
5
10
ns
RxC fall time
t SRF
When on-chip DPLL is used (source clock = RxC)
When on-chip DPLL is used (source clock = CLK)
5
10
ns
Transmit/receive data cycle
t CYD
When on-chip DPLL is used (source clock = RxC)
When on-chip DPLL is used (source clock = CLK)
TxC low-level time
t TCTCL
TxC high-level time
t TCTCH
TxD delay time (vs. TxC ↓)
t DTCTD
TxD hold time (vs. TxC ↑)
t HTCTD
When on-chip DPLL is used
ns
16000
0.5tCYD–25
ns
0.5tCYD–25
ns
50
0.5tCYD–25
Serial clock (when on-chip DPLL is used)
tCYR
tSSRL
tSSRH
tSRF
tSRR
RxC
TxC
tTCTCL
tTCTCH
tDTCTD
tHTCTD
TxD
tCYD
20
500
2000
ns
ns
µPD72107
Serial block (3)
Parameter
Symbol
Conditions
MIN.
MAX.
Unit
RTS ↑ delay time (vs. CLK ↑)
t DRTH
100
ns
RTS ↓ delay time (vs. CLK ↑)
t DRTL
100
ns
CD setup time (vs. CLK ↑)
t SCD
35
ns
CD hold time (vs. CLK ↑)
t HCD
20
ns
CTS setup time (vs. CLK ↑)
t SCT
35
ns
CTS hold time (vs. CLK ↑)
t HCT
20
ns
CLK
RTS
tDRTL
tDRTH
tHCD
CD
tSCD
tHCT
CTS
tSCT
21
µPD72107
3. APPLICATION CIRCUIT EXAMPLE
(1) Connection with SIFC (µ PD98201)
µ PD72107
µPD98201
TxD
BINA
RxD
BOUT1
TxC
BCLK
LAP-B
SIFC
RxC
22
Local memory 64 Kbytes
RD
Host processor
MEMR
MEMW
IOR
IOW
WR
CS
UBE
A0-A15
D0-D15
µ PD72107
MRD
MWR
IORD
IOWR
CS
A
B
µ PD71086
OE
Decoder
AB0-AB7
AB8-AB15
A
B
µ PD71086
OE
A0-A15
A0-A15
4. SYSTEM CONFIGURATION EXAMPLES
µPD72107 System Configuration Example (Local Memory Type)
D0-D7
AB16-AB19
BHE
DB0-DB15
A
B
µ PD71086
OE
A
B
µ PD71086
OE
A16D8-A23D15
UBE
D0-D15
AEN
INT
Local
bus request
HLDRQ
HLDAK
23
µPD72107
WAIT
INT
Access
contention
resolution
circuit
24
µ PD72107 System Configuration Example (Main Memory Sharing Type)
µ PD72107
Host processor
µ PD70116
µ PD71059
INT
INTAK
INT
INTAK
INT
INTP
CS
A0
IORD
IOWR
CS
MRD
MWR
HLDRQ
HLDAK
AEN
ASTB
RD WR D0-D7
RD
WR
HLDRQ
HLDAK
ASTB
A16-A19
D0-D7
Decoder
STB OE
OE STB
µ PD71082
A16-A19
A16D8-A23D15
AD8-AD15
µ PD71082×3
A0-A15
A0-A15
AD0-AD7
UBE
UBE
BUF R/W
BUFEN
D8-D15
µ PD71086×2
T
OE
D0-D7
RD WR
CS UBE D0-D7 D8-D15
Memory
µPD72107
µPD72107
5. PACKAGE DRAWINGS
64 PIN PLASTIC SHRINK DIP (750 mil)
64
33
1
32
A
K
J
L
I
H
F
D
C
N
B
M
R
M
G
NOTES
1. Controlling dimension
millimeter.
2. Each lead centerline is located within 0.17 mm (0.007 inch) of
its true position (T.P.) at maximum material condition.
3. Item "K" to center of leads when formed parallel.
ITEM
MILLIMETERS
INCHES
A
58.0 +0.68
–0.20
2.283 +0.028
–0.008
B
1.78 MAX.
0.070 MAX.
C
1.778 (T.P.)
0.070 (T.P.)
D
0.50±0.10
0.020 +0.004
–0.005
F
0.9 MIN.
0.035 MIN.
G
3.2±0.3
0.126±0.012
H
0.51 MIN.
0.020 MIN.
I
4.05 +0.26
–0.20
0.159 +0.011
–0.008
J
5.08 MAX.
0.200 MAX.
K
19.05 (T.P.)
0.750 (T.P.)
L
17.0±0.2
0.669 +0.009
–0.008
M
0.25 +0.10
–0.05
0.010 +0.004
–0.003
N
0.17
0.007
R
0 to 15°
0 to 15°
P64C-70-750A,C-3
25
µPD72107
80 PIN PLASTIC QFP (14x14)
A
B
41
40
60
61
detail of lead end
C D
S
R
Q
21
20
80
1
F
J
G
I
H
M
K
P
M
N
L
NOTE
Each lead centerline is located within 0.13 mm (0.005 inch) of
its true position (T.P.) at maximum material condition.
ITEM
MILLIMETERS
INCHES
A
17.2±0.4
0.677±0.016
B
14.0±0.2
0.551 +0.009
–0.008
C
14.0±0.2
0.551 +0.009
–0.008
D
17.2±0.4
0.677±0.016
F
0.825
0.032
G
0.825
0.032
H
0.30±0.10
0.012 +0.004
–0.005
I
0.13
0.005
J
0.65 (T.P.)
0.026 (T.P.)
K
1.6±0.2
L
0.8±0.2
M
0.15 +0.10
–0.05
0.063±0.008
0.031 +0.009
–0.008
0.006 +0.004
–0.003
N
0.10
0.004
P
2.7±0.1
0.106 +0.005
–0.004
Q
0.1±0.1
0.004±0.004
R
5°±5°
5°±5°
S
3.0 MAX.
0.119 MAX.
S80GC-65-3B9-5
26
µPD72107
68 PIN PLASTIC QFJ (950 x 950 mil)
A
B
68
1
G
H
C D
J
E
F
S
U
K
Q
M
N
M
P
I
NOTES
1. Controlling dimension
S
T
ITEM
MILLIMETERS
25.2±0.2
0.992±0.008
B
24.20±0.1
0.953 +0.004
−0.005
C
24.20±0.1
0.953 +0.004
−0.005
D
25.2±0.2
0.992±0.008
E
1.94±0.15
0.076 +0.007
−0.006
F
0.6
0.024
G
4.4±0.2
0.173 +0.009
−0.008
H
2.8±0.2
0.110 +0.009
−0.008
I
0.9 MIN.
0.035 MIN.
J
3.4±0.1
0.134 +0.004
−0.005
K
1.27 (T.P.)
0.050 (T.P.)
M
0.42±0.08
0.017 +0.003
−0.004
N
0.12
0.005
P
23.12±0.2
0.910 +0.009
−0.008
Q
0.15
0.006
T
R 0.8
R 0.031
U
0.22 +0.08
−0.07
0.009 +0.003
−0.004
millimeter.
2. Each lead centerline is located within 0.12 mm of
its true position (T.P.) at maximum material condition.
INCHES
A
P68L-50A1-3
27
µPD72107
6. RECOMMENDED SOLDERING CONDITIONS
The µ PD72107 should be soldered and mounted under the following recommended conditions.
For the details of the recommended soldering conditions, refer to the document Semiconductor Device
Mounting Technology Manual (C10535E).
For soldering methods and conditions other than those recommended below, contact your NEC sales representative.
Surface mounting type
• µ PD72107GC-3B9: 80-pin plastic QFP (14 × 14 mm)
Soldering Method
Soldering Conditions
Recommended Condition Symbol
Infrared reflow
Package peak temperature: 235°C, Time: 30 sec. Max.
(at 210°C or higher), Count: three times or less
IR35-00-3
VPS
Package peak temperature: 215°C, Time: 40 sec. Max.
(at 200°C or higher), Count: three times or less
VP15-00-3
Wave soldering
Solder bath temperature: 260°C, Time: 10 sec. Max.,
Count: one time, Preheating temperature: 120°C Max.
(package surface temperature)
WS60-00-1
Partial heating
Pin temperature: 300°C Max., Duration: 3 sec. Max. (per pin row)
–
Caution Do not use different soldering methods together (except for partial heating).
• µ PD72107L: 68-pin plastic QFJ (950 × 950 mils)
Soldering Method
Soldering Conditions
Recommended Condition Symbol
VPS
Package peak temperature: 215°C, Time: 40 sec. Max.
(at 200°C or higher), Count: one time
Partial heating
Pin temperature: 300°C Max., Duration: 3 sec. Max. (per pin row)
VP15-00-1
–
Insertion type
• µ PD72107CW: 64-pin plastic shrink DIP (750 mils)
Soldering Method
Soldering Conditions
Wave soldering (pin only)
Solder bath temperature: 260°C Max., Time: 10 sec. Max.
Partial heating
Pin temperature: 300°C Max., Duration: 3 sec. Max. (per a pin)
Caution Wave soldering must be applied only to pins. Be sure to avoid jet soldering the package body.
28
µPD72107
[MEMO]
29
µPD72107
[MEMO]
30
µPD72107
NOTES FOR CMOS DEVICES
1 PRECAUTION AGAINST ESD FOR SEMICONDUCTORS
Note: Strong electric field, when exposed to a MOS device, can cause destruction
of the gate oxide and ultimately degrade the device operation. Steps must
be taken to stop generation of static electricity as much as possible, and
quickly dissipate it once, when it has occurred. Environmental control must
be adequate. When it is dry, humidifier should be used. It is recommended
to avoid using insulators that easily build static electricity. Semiconductor
devices must be stored and transported in an anti-static container, static
shielding bag or conductive material.
All test and measurement tools
including work bench and floor should be grounded. The operator should
be grounded using wrist strap. Semiconductor devices must not be touched
with bare hands. Similar precautions need to be taken for PW boards with
semiconductor devices on it.
2 HANDLING OF UNUSED INPUT PINS FOR CMOS
Note: No connection for CMOS device inputs can be cause of malfunction. If no
connection is provided to the input pins, it is possible that an internal input
level may be generated due to noise, etc., hence causing malfunction. CMOS
device behave differently than Bipolar or NMOS devices. Input levels of
CMOS devices must be fixed high or low by using a pull-up or pull-down
circuitry.
Each unused pin should be connected to V DD or GND with a
resistor, if it is considered to have a possibility of being an output pin. All
handling related to the unused pins must be judged device by device and
related specifications governing the devices.
3 STATUS BEFORE INITIALIZATION OF MOS DEVICES
Note: Power-on does not necessarily define initial status of MOS device. Production process of MOS does not define the initial operation status of the device.
Immediately after the power source is turned ON, the devices with reset
function have not yet been initialized. Hence, power-on does not guarantee
out-pin levels, I/O settings or contents of registers. Device is not initialized
until the reset signal is received. Reset operation must be executed immediately after power-on for devices having reset function.
31
µPD72107
The export of this product from Japan is prohibited without governmental license. To export or re-export this product from
a country other than Japan may also be prohibited without a license from that country. Please call an NEC sales
representative.
No part of this document may be copied or reproduced in any form or by any means without the prior written
consent of NEC Corporation. NEC Corporation assumes no responsibility for any errors which may appear in
this document.
NEC Corporation does not assume any liability for infringement of patents, copyrights or other intellectual property
rights of third parties by or arising from use of a device described herein or any other liability arising from use
of such device. No license, either express, implied or otherwise, is granted under any patents, copyrights or other
intellectual property rights of NEC Corporation or others.
While NEC Corporation has been making continuous effort to enhance the reliability of its semiconductor devices,
the possibility of defects cannot be eliminated entirely. To minimize risks of damage or injury to persons or
property arising from a defect in an NEC semiconductor device, customers must incorporate sufficient safety
measures in its design, such as redundancy, fire-containment, and anti-failure features.
NEC devices are classified into the following three quality grades:
"Standard", "Special", and "Specific". The Specific quality grade applies only to devices developed based on a
customer designated "quality assurance program" for a specific application. The recommended applications of
a device depend on its quality grade, as indicated below. Customers must check the quality grade of each device
before using it in a particular application.
Standard: Computers, office equipment, communications equipment, test and measurement equipment,
audio and visual equipment, home electronic appliances, machine tools, personal electronic
equipment and industrial robots
Special: Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster
systems, anti-crime systems, safety equipment and medical equipment (not specifically designed
for life support)
Specific: Aircrafts, aerospace equipment, submersible repeaters, nuclear reactor control systems, life
support systems or medical equipment for life support, etc.
The quality grade of NEC devices is "Standard" unless otherwise specified in NEC's Data Sheets or Data Books.
If customers intend to use NEC devices for applications other than those specified for Standard quality grade,
they should contact an NEC sales representative in advance.
Anti-radioactive design is not implemented in this product.
M4 96.5
2