[AKD4673-A] AKD4673-A Evaluation board Rev.0 for AK4673 GENERAL DESCRIPTION AKD4673 is an evaluation board for the AK4673, stereo CODEC with built-in MIC/HP amplifier and TSC. The AKD4673 can evaluate A/D converter and D/A converter of the CODEC separately in addition to loopback mode (A/D → D/A). The AKD4673 also has the digital audio interface and can achieve the interface with digital audio systems via opt-connector. Moreover, the AKD4673 can also evaluate A/D converter of the TSC with the control software. Ordering guide AKD4673 --- Evaluation board for AK4673 (Cable for connecting with printer port of IBM-AT, compatible PC and control software are packed with this. This control software does not support Windows NT.) FUNCTION • DIT/DIR with optical input/output • RCA connector for an external clock input • 10pin Header for serial control mode • Touch-Panel I/F DVDD TVDD AVDD HVDD GND Opt In Opt Out REG 3.3V REG LIN1/RIN1 LIN2/3/4 AK4114 RIN2/3/4 MIN Digital Audio I/F 10Pin Header AK4673 LOUT ROUT HP Jack Control I/F 10Pin Header HPL HPR Touch-Panel Figure 1. AKD4673 Block Diagram * Circuit diagram and PCB layout are attached at the end of this manual <KM086000> 2007/5 -1- [AKD4673-A] Operation sequence (1) Set up the power supply lines. (1-1) In case of using the regulator. JP State Set up the jumper pins. JP3 JP4 JP5 HVDD_SEL AVDD_SEL DVDD_SEL Short Short Short JP6 TVDD_SEL JP7 VCC_SEL JP106 TVDD2 JP107 TVDD1 JP109 TSVDD Short Short Short Short Short Set up the power supply lines. [REG] (red) = 5.0V [D3V] (orange) [AGND] (black) [DGND] (black) : for regulator (3.3V output : HVDD, AVDD, TVDD1, TVDD2, TSVDD, DVDD of AK4673) = 2.7 ∼ 3.6V : for AK4114 and logic (typ. 3.3V) = 0V : for analog ground = 0V : for logic ground (1-2) In case of using the power supply connectors. JP State Set up the jumper pins. JP3 JP4 JP5 HVDD_SEL AVDD_SEL DVDD_SEL Open Open Open Set up the power supply lines. [HVDD] (orange) = 1.6 ~ 3.6V [AVDD] (orange) = 1.6 ~ 3.6V [DVDD] (orange) = 1.6 ~ 3.6V [TVDD] (orange) = 1.6 ~ 3.6V [VCC] (orange) = 1.6 ∼ 3.6V [D3V] (orange) = 2.7 ∼ 3.6V [AGND] (black) = 0V [DGND] (black) = 0V JP6 TVDD_SEL JP7 VCC_SEL JP106 TVDD2 JP107 TVDD1 JP109 TSVDD Open Open Short Short Short : for HVDD of AK4673 (typ. 3.3V) : for AVDD and PVDD of AK4673 (typ. 3.3V) : for DVDD of AK4673 (typ. 3.3V) : for TVDD1, TVDD2, TSVDD of AK4673 (typ. 3.3V) : for logic (typ. 3.3V: = DVDD) : for AK4114 and logic (typ. 3.3V) : for analog ground : for logic ground * Each supply line should be distributed from the power supply unit. (2) Set up the evaluation mode, jumper pins and DIP switches. (See the followings.) (3) Power on. The AK4673 and AK4114 should be resets once bringing SW1 (PDN) and SW2 (DIR) “L” upon power-up. <KM086000> 2007/5 -2- [AKD4673-A] Evaluation mode In case of AK4673 evaluation using AK4114, it is necessary to correspond to audio interface format for AK4673 and AK4114. About AK4673’s audio interface format, refer to datasheet of AK4673. About AK4114’s audio interface format, refer to Table 2 in this manual. Evaluation of CODEC (1) External Slave Mode (1-1) Evaluation of A/D using DIT of AK4114 (1-2) Evaluation of D/A using DIR of AK4114 (1-3) Evaluation of Loop-back using AK4114 <default> (1-4) Evaluation of Loop-back that master clock is fed externally, BICK and LRCK are divided with a board (2) External Master Mode (2-1) Evaluation of A/D using DIT of AK4114 (2-2) Evaluation of D/A using DIR of AK4114 (2-3) Evaluation of Loop-back using AK4114 (2-4) Evaluation of Loop-back that master clock is fed externally (3) PLL Slave Mode (3-1) PLL Reference Clock : MCKI pin (3-1-1) Evaluation of A/D, D/A using PORT3 (DSP) (3-1-2) Evaluation of Loop-back that master clock is fed externally, BICK and LRCK are divided with a board (3-2) PLL Reference Clock : BICK or LRCK pin (3-2-1) Evaluation of A/D using DIT of AK4114 (3-2-2) Evaluation of D/A using DIR of AK4114 (3-2-3) Evaluation of Loop-back using AK4114 (4) PLL Master Mode (4-1) Evaluation of Loop-back using AK4114 (4-2) Evaluation of Loop-back that master clock is fed externally (4-3) Evaluation of Internal Loop-back using clock is fed externally Evaluation of TSC (1) Position, Pen Pressure <KM086000> 2007/5 -3- [AKD4673-A] Evaluation of CODEC JP104, JP102 should be set to short. JP103, JP105 should be set to open. (1) External Slave Mode When PMPLL bit is “0”, the AK4673 becomes EXT mode. Master clock is input from MCKI pin, the internal PLL circuit is not operated. This mode is compatible with I/F of the normal audio CODEC. The clocks required to operate are MCKI (256fs, 512fs or 1024fs), LRCK (fs) and BICK (≥32fs). The master clock (MCKI) should be synchronized with LRCK. The phase between these clocks does not matter. The input frequency of MCKI is selected by FS1-0 bits. JP23 (M/S) should be set to “Slave”. In addition, the register of AK4673 should be set to “EXT Slave Mode”. AK4673 DSP or μP MCKO 256fs, 512fs or 1024fs MCKI MCLK ≥ 32fs BICK 1fs LRCK BCLK LRCK SDTO SDTI SDTI SDTO Figure 2. EXT Slave Mode (1-1) Evaluation of A/D using DIT of AK4114 PORT2 (DIT) and X1 (X’tal) are used. Nothing should be connected to PORT1 (DIR) and PORT3 (DSP). The jumper pins should be set to the following. JP15 MCLK JP18 BICK_SEL JP21 LRCK_SEL JP19 PHASE JP22 4114_MCKI DIR EXT DIR 4040 DIR 4040 THR INV (1-2) Evaluation of D/A using DIR of AK4114 PORT1 (DIR) is used. Nothing should be connected to PORT2 (DIT) and PORT3 (DSP). The jumper pins should be set to the following. JP15 MCLK JP18 BICK_SEL JP21 LRCK_SEL JP24 SDTI_SEL JP19 PHASE DIR EXT DIR 4040 DIR 4040 DIR ADC THR INV When AK4114 is used, JP16 (MKFS) and JP17 (BCFS) are not used. Therefore, JP16 (MKFS) should be set to “256fs” and JP23 (BCFS) should be set to “64fs”. * The AK4114 operates at fs of 32kHz or more. If the fs is slower than 32kHz, this evaluation mode can’t be used. <KM086000> 2007/5 -4- [AKD4673-A] (1-3) Evaluation of Loop-back using AK4114 <Default> X1 (X’tal) is used. Nothing should be connected to PORT1 (DIR) and PORT3 (DSP). The jumper pins should be set to the following. JP15 MCLK JP18 BICK_SEL JP21 LRCK_SEL JP24 SDTI_SEL JP19 PHASE JP22 4114_MCKI DIR EXT DIR 4040 DIR 4040 DIR ADC THR INV When AK4114 is used, JP16 (MKFS) and JP17 (BCFS) are not used. Therefore, JP16 (MKFS) should be set to “256fs” and JP23 (BCFS) should be set to “64fs”. * The AK4114 operates at fs of 32kHz or more. If the fs is slower than 32kHz, this evaluation mode can’t be used. (1-4) Evaluation of Loop-back where master clock is fed externally, BICK and LRCK are generated by on-board divider. J11 (EXT) is used. MCKI is supplied from J11 (EXT). BICK and LRCK are generated by 74HC4040 on AKD4671-A. Nothing should be connected to PORT1 (DIR), PORT2 (DIT) and PORT3 (DSP). The jumper pins should be set as the following. JP14 EXT JP15 MCLK JP18 BICK_SEL JP21 LRCK_SEL JP24 SDTI_SEL JP19 PHASE DIR EXT DIR 4040 DIR 4040 DIR ADC THR INV When a termination (51Ω) is unnecessary, please set JP14 (EXT) open. JP16 (MKFS), JP17 (BCFS), and JP20 (LRCK) should be set according to the frequency of MCLK, BICK and LRCK. <KM086000> 2007/5 -5- [AKD4673-A] (2) External Master Mode The AK4673 becomes EXT Master Mode by setting PMPLL bit = “0” and M/S bit = “1”. Master clock can be input via MCKI pin, without using on-chip PLL circuit. The clock required to operate is MCKI (256fs, 512fs, or 1024 fs). The input frequency of MCKI is selected by FS1-0 bits. JP23 (M/S) should be set to “Master”. In addition, the register of AK4673 should be set to “EXT Master Mode”. AK4673 DSP or μP MCKO 256fs, 512fs or 1024fs MCKI MCLK 32fs or 64fs BICK 1fs LRCK BCLK LRCK SDTO SDTI SDTI SDTO Figure 3. EXT Master Mode (2-1) Evaluation of A/D using DIT of AK4114 X1 (X’tal) and PORT2 (DIT) are used. Nothing should be connected to PORT1 (DIR) and PORT3 (DSP). In Master Mode, BICK and LRCK of AK4671 should be input to AK4114. Please refer to Table 2 on page 13. BCKO bit = “1” (Register Address 04H) The jumper pins should be set as the following. JP15 MCLK JP18 BICK_SEL JP21 LRCK_SEL JP19 PHASE JP22 4114_MCKI DIR EXT DIR 4040 DIR 4040 THR INV * The AK4114 operates at fs of 32kHz or more. If the fs is slower than 32kHz, this evaluation mode can’t be used. (2-2) Evaluation of D/A using DIR of AK4114 PORT1 (DIR) is used. Nothing should be connected to PORT2 (DIT) and PORT3 (DSP). In Master Mode, BICK and LRCK of AK4671 should be input to AK4114. Please refer to Table 2 on page 13. BCKO bit = “1” (Register Address 04H). The jumper pins should be set as the following. JP15 MCLK JP18 BICK_SEL JP21 LRCK_SEL JP24 SDTI_SEL JP19 PHASE DIR EXT DIR 4040 DIR 4040 DIR ADC THR INV * The AK4114 operates at fs of 32kHz or more. If the fs is slower than 32kHz, this evaluation mode can’t be used. <KM086000> 2007/5 -6- [AKD4673-A] (2-3) Evaluation of Loop-back using AK4114 X1 (X’tal) is used. Nothing should be connected to PORT1 (DIR), PORT2 (DIT) and PORT3 (DSP). The jumper pins should be set as the following. JP15 MCLK JP18 BICK_SEL JP21 LRCK_SEL JP24 SDTI_SEL JP19 PHASE JP22 4114_MCKI DIR EXT DIR 4040 DIR 4040 DIR ADC THR INV JP16 (MKFS) should be set according to the frequency of MCLK. (2-4) Evaluation of Loop-back where master clock is fed externally J11 (EXT) is used. MCKI is supplied from J11 (EXT). BICK and LRCK are generated by 74HC4040 on AKD4671-A. Nothing should be connected to PORT1 (DIR), PORT2 (DIT) and PORT3 (DSP). The jumper pins should be set as the following. JP14 EXT JP15 MCLK JP18 BICK_SEL JP21 LRCK_SEL JP24 SDTI_SEL JP19 PHASE DIR EXT DIR 4040 DIR 4040 DIR ADC THR INV *When a termination (51Ω) is unnecessary, please set JP14 (EXT) open. JP16 (MKFS) should be set according to the frequency of MCLK. <KM086000> 2007/5 -7- [AKD4673-A] (3) PLL Slave Mode A reference clock of PLL is selected among the input clocks to MCKI, BICK or LRCK pin. The required clock to the AK4673 is generated by an internal PLL circuit. Input frequency is selected by PLL3-0 bits. BICK and LRCK inputs should be synchronized with MCKO output. The phase between MCKO and LRCK dose not matter. MCKO pin outputs the frequency selected by PS1-0 bits and the output is enabled by MCKO bit. Sampling frequency can be selected by FS3-0 bits. JP23 (M/S) should be set to “Slave”. In addition, the register of AK4673 should be set to “PLL Slave Mode”. (3-1) PLL Reference Clock : MCKI pin 11.2896MHz, 12MHz, 12.288MHz, 13MHz, 13.5MHz, 19.2MHz, 24MHz, 26MHz, 27MHz AK4673 DSP or μP MCKI 256fs/128fs/64fs/32fs MCKO ≥ 32fs BICK BCLK 1fs LRCK MCLK LRCK SDTO SDTI SDTI SDTO Figure 4. PLL Slave Mode 1 (PLL Reference Clock: MCKI pin) (3-1-1) Evaluation of A/D, D/A using PORT3 (DSP) PORT3 (DSP) is used. Nothing should be connected to PORT1 (DIR), PORT2 (DIT) and J11 (EXT). SDTI, SDTO, LRCK and BICK of PORT3 are respectively connected with SDTO, SDTI, LRCK and BICK of DSP. Connect the test pin (MCKO) to DSP when MCKO is supplied to DSP. The jumper pins should be set as the following. JP15 MCLK JP18 BICK_SEL JP21 LRCK_SEL JP24 SDTI_SEL JP19 PHASE DIR EXT DIR 4040 DIR 4040 DIR ADC THR INV (3-1-2) Evaluation of Loop-back that master clock is fed externally, BICK and LRCK are divided with a board J11 (EXT) is used. MCKI is supplied from J11 (EXT). BICK and LRCK are generated by 74HC4040 on AKD4671-A.Nothing should be connected to PORT1 (DIR), PORT2 (DIT) and PORT3 (DSP). The jumper pins should be set as the following. JP14 EXT JP15 MCLK JP18 BICK_SEL JP21 LRCK_SEL JP24 SDTI_SEL JP19 PHASE DIR EXT DIR 4040 DIR 4040 DIR ADC THR INV *When a termination (51Ω) is unnecessary, please set JP14 (EXT) open. JP16 (MKFS) should be set to MCKO; JP17 (BCFS), and JP20 (LRCK) should be set according to the frequency of BICK and LRCK. <KM086000> 2007/5 -8- [AKD4673-A] (3-2) PLL Reference Clock : BICK or LRCK pin AK4673 DSP or μP MCKO MCKI 32fs or 64fs BICK 1fs LRCK BCLK LRCK SDTO SDTI SDTI SDTO Figure 5. PLL Slave Mode 2 (PLL Reference Clock: BICK pin) AK4673 DSP or μP MCKO MCKI ≥ 32fs BICK BCLK 1fs LRCK LRCK SDTO SDTI SDTI SDTO Figure 6. PLL Slave Mode 2 (PLL Reference Clock: LRCK pin) (3-2-1) Evaluation of A/D using DIT of AK4114 X1 (X’tal) and PORT2 (DIT) are used. Nothing should be connected to PORT1 (DIR), PORT3 (DSP) and J11 (EXT). The jumper pins should be set as the following. JP15 MCLK JP14 EXT JP18 BICK_SEL JP21 JP22 LRCK_SEL 4114_MCKI JP19 PHASE DIR EXT DIR 4040 DIR 4040 THR INV * The AK4114 operates at fs of 32kHz or more. If the fs is slower than 32kHz, this evaluation mode can’t be used. <KM086000> 2007/5 -9- [AKD4673-A] (3-2-2) Evaluation of D/A using DIR of AK4114 PORT1 (DIR) is used. Nothing should be connected to PORT2 (DIT), PORT3 (DSP) and J11 (EXT). The jumper pins should be set as the following. JP18 BICK_SEL JP15 MCLK JP14 EXT JP21 LRCK_SEL JP24 SDTI_SEL JP19 PHASE DIR EXT DIR 4040 DIR 4040 THR INV DIR ADC * The AK4114 operates at fs of 32kHz or more. If the fs is slower than 32kHz, this evaluation mode can’t be used. (3-2-3) Evaluation of Loop-back using AK4114 X1 (X’tal) is used. Nothing should be connected to PORT1 (DIR), PORT2 (DIT), PORT3 (DSP) and J11 (EXT). The jumper pins should be set as the following. JP15 MCLK JP14 EXT JP18 BICK_SEL JP22 JP21 LRCK_SEL 4114_MCKI JP19 PHASE JP24 SDTI_SEL DIR EXT DIR 4040 DIR 4040 THR INV DIR ADC * The AK4114 operates at fs of 32kHz or more. If the fs is slower than 32kHz, this evaluation mode can’t be used. <KM086000> 2007/5 - 10 - [AKD4673-A] (4) PLL Master Mode When an external clock (11.2896MHz, 12MHz, 12.288MHz, 13MHz, 13.5MHz, 19.2MHz, 24MHz, 26MHz or 27MHz) is input to MCKI pin, the MCKO, BICK and LRCK clocks are generated by an internal PLL circuit. The MCKO output frequency is selected by PS1-0 bits and the output is enabled by MCKO bit. The BICK output frequency is selected between 32fs or 64fs, by BCKO bit. JP23 (M/S) should be set to “Master”. In addition, the register of AK4673 should be set to “PLL Master Mode”. 11.2896MHz, 12MHz, 12.288MHz, 13MHz, 13.5MHz, 19.2MHz, 24MHz, 26MHz, 27MHz DSP or μP AK4673 MCKI MCKO 256fs/128fs/64fs/32fs 32fs, 64fs BICK 1fs LRCK MCLK BCLK LRCK SDTO SDTI SDTI SDTO Figure 7. PLL Master Mode (4-1) Evaluation of Loop-back using AK4114 X1 (X’tal) is used. Nothing should be connected to PORT1 (DIR), PORT3 (DSP) and J11 (EXT). Using the AK4673’s internal PLL it is possible to evaluate various sampling frequencies. The jumper pins should be set to the following. JP15 MCLK JP18 BICK_SEL JP21 LRCK_SEL JP24 SDTI_SEL JP19 PHASE DIR EXT DIR 4040 DIR 4040 DIR ADC THR INV (4-2) Evaluation of Loop-back that master clock is fed externally J11 (EXT) is used. Nothing should be connected to PORT1 (DIR) and PORT3 (DSP). Exclude X’tal oscillator from X1. Using the AK4673’s internal PLL it is possible to evaluate various sampling frequencies. The jumper pins should be set to the following. JP14 EXT JP15 MCLK JP18 BICK_SEL JP21 LRCK_SEL JP24 SDTI_SEL JP19 PHASE DIR EXT DIR 4040 DIR <KM086000> 4040 DIR ADC THR INV 2007/5 - 11 - [AKD4673-A] (4-3) Evaluation of Internal Loop-back using clock is fed externally J11 (EXT) is used. Nothing should be connected to PORT1(DIR) and PORT3 (DSP). It can be evaluated at internal loop-back mode (LOOP bit = “1”). Using the AK4673’s internal PLL it is possible to evaluate various sampling frequencies. The jumper pins should be set to the following. JP14 EXT JP15 MCLK JP21 LRCK_SEL JP18 BICK_SEL JP24 SDTI_SEL JP19 PHASE DIR EXT DIR 4040 DIR 4040 DIR ADC THR INV Evaluation of TSC PORT4 (CTRL) should be directly connected to the parallel port. (Figure 9) JP103, JP105 should be set to short. JP102, JP104 should be set to open. (1) Position, Pen Pressure 4-wire touch-panel (X+, X-, Y+ and Y-) should be connected to J100 connector as the following figure. Touch Panel RED J100 AKM4673-A -57BGA Figure 8. Connect of Touch Panel <KM086000> 2007/5 - 12 - [AKD4673-A] DIP Switch set up [S1] : Mode Setting of AK4114 and AK4673 ON is “H”, OFF is “L”. No. 1 2 3 4 5 6 Name DIF2 DIF1 DIF0 OCKS1 CAD0 I2C ON (“H”) OFF (“L”) AK4114 Audio Format Setting See Table 2 AK4114 Master Clock Setting : See Table 3 AK4673Control Mode Setting : See Table 4 Default ON OFF OFF OFF OFF OFF Table 1. Mode Setting for AK4673 and AK4114 DIF2 DIF1 DIF0 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 AK4114DAUX 24bit, Left justified 24bit, Left justified 24bit, Left justified 24bit, Left justified 24bit, Left justified 24bit, I2S 24bit, Left justified 24bit, I2S AK4114SDTO 16bit, Right justified 18bit, Right justified 20bit, Right justified 24bit, Right justified 24bit, Left justified 24bit, I2S 24bit, Left justified 24bit, I2S LRCK I/O H/L O H/L O H/L O H/L O H/L O L/H O H/L I L/H I BICK 64fs 64fs 64fs 64fs 64fs 64fs 64-128fs 64-128fs I/O O O O O O O I I default Table 2. Setting for AK4114 Audio Interface Format OCKS1 0 1 MCKO1 256fs 512fs X’tal 256fs 512fs default Table 3. AK4114 Master Clock Setting <KM086000> 2007/5 - 13 - [AKD4673-A] Other jumper pins set up Main Board [JP1] (GND): Analog ground and Digital ground OPEN: Separated. SHORT: Common. (The connector “DGND” can be open.) <Default> [JP3] (HVDD_SEL): HVDD of the AK4673 OPEN: HVDD is supplied from “HVDD” jack. SHORT: Supplied from the regulator (“HVDD” jack should be open). <Default> [JP4] (AVDD_SEL): AVDD of the AK4673 OPEN: AVDD is supplied from “AVDD” jack. SHORT: Supplied from the regulator (“AVDD” jack should be open). <Default> [JP5] (DVDD_SEL): DVDD of the AK4673 OPEN: DVDD is supplied from “DVDD” jack. SHORT: DVDD is supplied from “AVDD” (“DVDD” jack should be open). <Default> [JP6] (TVDD_SEL): TVDD of the AK4673 OPEN: TVDD is supplied from “TVDD” jack. SHORT: TVDD is supplied from “DVDD” (“TVDD” jack should be open). <Default> [JP7] (VCC_SEL): VCC of the AK4673 OPEN: VCC is supplied from “VCC” jack. SHORT: VCC is supplied from “TVDD” (“VCC” jack should be open). <Default> [JP16] (MKFS): MCLK Frequency 256fs: 256fs. <Default> 512fs: 512fs. 1024fs: 1024fs. 384/768fs: 384fs MCKO: MCKO is used. [JP17] (BCFS): BICK Frequency 32fs: 32fs (When MCLK is 256fs or 512fs or 768fs or 1024fs.) 64fs: 64fs (When MCLK is 256fs or 512fs or 768fs or 1024fs.) <Default> 32fs-384: 32fs (When MCLK is 384fs.) 64fs-384: 64fs (When MCLK is 384fs.) [JP22] (4114_MCKI): AK4114 Clock Source OPEN: X’tal of AK4114 is used. <Default> SHORT: X’tal of AK4114 is not used. [JP25] (CTRL_SEL):Serial Control Interface (Must be set to I2C) 3-WIRE: Invalid I2C: I2C-bus Control Mode <Default> Sub Board [JP100] (I2CA_SEL): I2C (Must be set to H) H: Enable <Default> L: Unable <KM086000> 2007/5 - 14 - [AKD4673-A] The function of the toggle SW [SW1] (PDN): Power down of AK4673. Keep “H” during normal operation. [SW2] (DIR): Power down of AK4114. Keep “H” during normal operation. Keep “L” when AK4114 is not used. Indication for LED [LED1] (ERF): Monitor INT0 pin of the AK4114. LED turns on when some error has occurred to AK4114. Serial Control The AK4673 can be controlled via the printer port (parallel port) of IBM-AT compatible PC. Connect PORT4 (CTRL) with PC by 10 wire flat cable packed with the AKD4673.Table 3 shows switch and jumper settings for serial control. Connect PC 10 wire flat cable 10pin Connector CSN CCLK/SCI CDTI/SDA CDTO/ACK PENIRQN AKD4673 PORT4 Figure 9. Connect of 10 wire flat cable Mode I2C CAD0=0 CAD0=1 S1 I2C ON ON CAD0 OFF ON JP25 CTRL_SEL JP100 I2CA-SEL I2C H Table 4. Serial Control Setting <KM086000> 2007/5 - 15 - [AKD4673-A] Analog Input/Output Circuits (1) Input Circuits (1-1) LIN1/RIN1, LIN2/RIN2, LIN3/RIN3, LIN4/RIN4 Input Circuit J1 LIN1/RIN1 J2 LIN 1 R110 2.2k JP113 RIN1 R111 2.2k MPWR 6 LIN1 4 3 RIN1 C30 1u R10 (short) LIN2 JP8 LIN2 LIN3 LIN4 + 2 3 4 5 JP112 LIN1 LIN3 LIN_SEL LIN4 J3 RIN 1 R11 (short) RIN2 JP9 RIN2 RIN3 RIN4 + 2 3 4 5 C31 1u RIN3 RIN_SEL RIN4 Figure 10. LIN1/RIN1, LIN2/RIN2, LIN3/RIN3, LIN4/RIN4 Input Circuit LIN2/RIN2, LIN3/RIN3, LIN4/RIN4 shares J2/J3. JP8 (LIN_SEL) and JP9 (RIN_SEL) select each path. When microphone is connected to J1, JP112 and JP113 should be short. When LIN3/RIN3 paths of AK4673 are used, JP101 and JP108 should be set as below. AIN3bit =“1” (Register Address 21H) M IN VCOC R IN 3 LIN 3 JP 108 JP 101 <KM086000> 2007/5 - 16 - [AKD4673-A] When MIN (shared with LIN3) Input path of AK4673 is used, JP108 should be set as below. AIN3bit =“0” (Register Address 21H) MIN LIN3 JP108 <KM086000> 2007/5 - 17 - [AKD4673-A] (2) Output Circuits (2-1) HP Output Circuit 1 + RCA R17 (short) R18 16 JP12 HPL HPL C35 220u HP 6 + R19 (short) JP13 HPR C36 220u 2 3 4 5 J9 HP/LINE 4 3 HP HPR J7 HPL RCA 1 R20 16 J8 HPR 2 3 4 5 Figure 11. HP Output Circuit (2-1-1) In case that signal is output from J7 and J8. JP13 HPR JP12 HPL RCA HP RCA HP (2-1-2) In case that signal is output from J9. JP13 HPR JP12 HPL RCA HP RCA <KM086000> HP 2007/5 - 18 - [AKD4673-A] (2-2) LOUT/ROUT (LOP/LON) Output Circuit J9 HP/LINE 6 + 3.5ST 4 3 JP10 LOUT_SEL LOUT C33 1u R13 220 RCA 1 J5 LOUT 2 3 4 5 R14 10k + 3.5ST JP11 ROUT_SEL ROUT C34 1u R15 220 RCA 1 J6 ROUT R16 10k 2 3 4 5 Figure 12. LOUT/ROUT(LOP/LON) Output Circuit (2-1-1) In case that signal is output from J5 and J6. JP11 JP10 LOUT_SEL RCA ROUT_SEL RCA 3.5ST 3.5ST (2-1-1) In case that signal is output from J9. JP10 LOUT_SEL RCA 3.5ST JP11 ROUT_SEL RCA 3.5ST ∗ AKM assumes no responsibility for the trouble when using the above circuit examples. <KM086000> 2007/5 - 19 - [AKD4673-A] Control Software Manual For the Evaluation of CODEC Set-up of evaluation board and control software 1. Set up the AKD4673-A according to previous term. 2. Connect IBM-AT compatible PC with AKD4673-A by 10-line type flat cable (packed with AKD4673-A). Take care of the direction of 10pin header. (Please install the driver in the CD-ROM when this control software is used on Windows 2000/XP. Please refer “Installation Manual of Control Software Driver by AKM device control software”. In case of Windows95/98/ME, this installation is not needed. This control software does not operate on Windows NT.) 3. Insert the CD-ROM labeled “AK4673-A Evaluation Kit” into the CD-ROM drive. 4. Access the CD-ROM drive and double-click the icon of “AKD4673.exe” to set up the control program. 5. Then please evaluate according to the follows. Operation flow Keep the following flow. 1. Set up the control program according to explanation above. 2. Click “Port Reset” button. Explanation of each buttons [Port Reset] : [Write default] : [All Write] : [Function1] : [Function2] : [Function3] : [Function4] : [Function5]: [SAVE] : [OPEN] : [Write] : [Filter] : Set up the USB interface board (AKDUSBIF-A) . Initialize the register of AK4673. Write all registers that is currently displayed. Dialog to write data by keyboard operation. Dialog to write data by keyboard operation. The sequence of register setting can be set and executed. The sequence that is created on [Function3] can be assigned to buttons and executed. The register setting that is created by [SAVE] function on main window can be assigned to buttons and executed. Save the current register setting. Write the saved values to all register. Dialog to write data by mouse operation. Set Programmable Filter (FIL1, FIL3, EQ) of AK4673 easily. Indication of data Input data is indicated on the register map. Red letter indicates “H” or “1” and blue one indicates “L” or “0”. Blank is the part that is not defined in the datasheet. <KM086000> 2007/5 - 20 - [AKD4673-A] Explanation of each dialog 1. [Write Dialog]: Dialog to write data by mouse operation There are dialogs corresponding to each register. Click the [Write] button corresponding to each register to set up the dialog. If you check the check box, data becomes “H” or “1”. If not, “L” or “0”. If you want to write the input data to AK4673, click [OK] button. If not, click [Cancel] button. 2. [Function1 Dialog] : Dialog to write data by keyboard operation Address Box: Data Box: Input registers address in 2 figures of hexadecimal. Input registers data in 2 figures of hexadecimal. If you want to write the input data to AK4673, click [OK] button. If not, click [Cancel] button. 3. [Function2 Dialog] : Dialog to evaluate IVOL and DVOL Address Box: Input registers address in 2 figures of hexadecimal. Start Data Box: Input starts data in 2 figures of hexadecimal. End Data Box: Input end data in 2 figures of hexadecimal. Interval Box: Data is written to AK4673 by this interval. Step Box: Data changes by this step. Mode Select Box: If you check this check box, data reaches end data, and returns to start data. [Example] Start Data = 00, End Data = 09 Data flow: 00 01 02 03 04 05 06 07 08 09 09 08 07 06 05 04 03 02 01 00 If you do not check this check box, data reaches end data, but does not return to start data. [Example] Start Data = 00, End Data = 09 Data flow: 00 01 02 03 04 05 06 07 08 09 If you want to write the input data to AK4673, click [OK] button. If not, click [Cancel] button. <KM086000> 2007/5 - 21 - [AKD4673-A] 4. [Save] and [Open] 4-1. [Save] Save the current register setting data. The extension of file name is “akr”. (Operation flow) (1) Click [Save] Button. (2) Set the file name and push [Save] Button. The extension of file name is “akr”. 4-2. [Open] The register setting data saved by [Save] is written to AK4673. The file type is the same as [Save]. (Operation flow) (1) Click [Open] Button. (2) Select the file (*.akr) and Click [Open] Button. <KM086000> 2007/5 - 22 - [AKD4673-A] 5. [Function3 Dialog] The sequence of register setting can be set and executed. (1) Click [F3] Button. (2) Set the control sequence. Set the address, Data and Interval time. Set “-1” to the address of the step where the sequence should be paused. (3) Click [Start] button. Then this sequence is executed. The sequence is paused at the step of Interval="-1". Click [START] button, the sequence restarts from the paused step. This sequence can be saved and opened by [Save] and [Open] button on the Function3 window. The extension of file name is “aks”. Figure 13. Window of [F3] <KM086000> 2007/5 - 23 - [AKD4673-A] 6. [Function4 Dialog] The sequence that is created on [Function3] can be assigned to buttons and executed. When [F4] button is clicked, the window as shown in Figure 14 opens. Figure 14. [F4] window <KM086000> 2007/5 - 24 - [AKD4673-A] 6-1. [OPEN] buttons on left side and [START] buttons (1) Click [OPEN] button and select the sequence file (*.aks). The sequence file name is displayed as shown in Figure 15. Figure 15. [F4] window(2) (2) Click [START] button, then the sequence is executed. 3-2. [SAVE] and [OPEN] buttons on right side [SAVE] : The sequence file names can assign be saved. The file name is *.ak4. [OPEN] : The sequence file names assign that are saved in *.ak4 are loaded. 3-3. Note (1) This function doesn't support the pause function of sequence function. (2) All files need to be in same folder used by [SAVE] and [OPEN] function on right side. (3) When the sequence is changed in [Function3], the file should be loaded again in order to reflect the change. <KM086000> 2007/5 - 25 - [AKD4673-A] 7. [Function5 Dialog] The register setting that is created by [SAVE] function on main window can be assigned to buttons and executed. When [F5] button is clicked, the following window as shown in Figure 16 opens. Figure 16. [F5] window 7-1. [OPEN] buttons on left side and [WRITE] button (1) Click [OPEN] button and select the register setting file (*.akr). The register setting file name is displayed as shown in Figure 17. (2) Click [WRITE] button, then the register setting is executed. <KM086000> 2007/5 - 26 - [AKD4673-A] Figure 17. [F5] windows (2) 7-2. [SAVE] and [OPEN] buttons on right side [SAVE] : The register setting file names assign can be saved. The file name is *.ak5. [OPEN] : The register setting file names assign that are saved in *.ak5 are loaded. 7-3. Note (1) All files need to be in same folder used by [SAVE] and [OPEN] function on right side. (2) When the register setting is changed by [Save] Button in main window, the file should be loaded again in order to reflect the change. <KM086000> 2007/5 - 27 - [AKD4673-A] 8. [Filter Dialog] This dialog can easily set the AK4673’s programmable filter. Figure 18. [Filter] window 8-1. Value input columns on left side [Sampling Rate] [Cut Off Frequency of FIL1] [Cut Off Frequency of FIL3] [Pole Frequency of EQ] [Zero Frequency of EQ] [FIL3 GAIN] [EQ GAIN] Input value of sampling frequency [unit : Hz] <default : 44100> Input value of cut off frequency of FIL1 [unit : Hz] <default : 150> Input value of cut off frequency of FIL3 [unit : Hz] <default : 4000> Input value of pole frequency of EQ [unit : Hz] Input value of zero frequency of EQ [unit : Hz] Input value of gain of FIL3 (0~−10dB) [unit : dB] Input value of gain of EQ (+12~0dB) [unit : dB] 8-2. Check box on left side Check Box FIL1 FIL3 EQ LPF of FIL1 LPF of FIL3 Check FIL1 bit =“1” FIL3 bit =“1” EQ bit =“1” F1AS bit =“1”(LPF) F3AS bit =“1”(LPF) Check off FIL1 bit =“0” FIL3 bit =“0” EQ bit =“0” F1AS bit =“0”(HPF) F3AS bit =“0”(HPF) 8-2. [Register Setting] panel and [Register Setting] button on right side Click [Register setting] button, then filter coefficient set by 8-1 and 8-2 is written on [Register setting] panel. (It is also written to the actual control register of the AK4673.) <KM086000> 2007/5 - 28 - [AKD4673-A] Control Software Manual For the Evaluation of TSC Parallel Port Driver install Attached software is the application software, which checks the function of the AK4673. Windows(R) Win 98, Win 2K, and Win XP are supported. However, to make it operate on Win2K and XP, it is necessary to install driver in advance. Please follow a procedure with reference to DriverSetupe.pdf. Installation of a driver is unnecessary to use it by the Windows 98 system. Run the software (AK4673_TSC.exe) This software valuates the function of the AK4673 TSC block. First match Port Address of your PC environment. Measurements with pressed by pen or stylus on the touch panel are started when the start button is clicked after select Channel Selection, MODE, and Power Down 0. A result will be displayed on AD OUT Section. When carrying out position detection, the position where pen clicked on the touch panel is measured. Operation can set up two control commands. Continuous operation can be performed. Each data (mean, max, and min) is also displayed at the same time. PENIRQN can be seen by the break of a command. Figure 19. TSC control soft window <KM086000> 2007/5 - 29 - [AKD4673-A] Trouble Shooting 1. Application error is occurred and doesn’t start up If the operating system is Window2000/XP, Please install AKM port driver in advance of run the AK4673_TSC.exe. 2. MEAN value in AD OUT section does not change until click start button (cannot write control command to AK4673). Please set the port address correctly to your PC platform environment. 3. The mean, max, min value doesn't change wherever the pen is pressed down on the panel. There is a possibility of the trouble of the contact of the relay connector (plat 8pin-8-wire female dip converter) that connects the touch panel. Measure panel seat resistance (XP-XN, YP-YN), and check the resistance. Generally, the panel seat resistance is hundreds of Ω. There is a possibility that the touch panel is not correctly connected if the resistance is over thousands of kΩ. Please connect the connector and check the resistance value again. <KM086000> 2007/5 - 30 - [AKD4673-A] Revision History Date (YY/MM/DD) 07/05/30 Manual Revision KM086000 Board Revision 0 Reason Contents First edition IMPORTANT NOTICE These products and their specifications are subject to change without notice. When you consider any use or application of these products, please make inquiries the sales office of Asahi Kasei EMD Corporation (AKEMD) or authorized distributors as to current status of the products. AKEMD assumes no liability for infringement of any patent, intellectual property, or other rights in the application or use of any information contained herein. Any export of these products, or devices or systems containing them, may require an export license or other official approval under the law and regulations of the country of export pertaining to customs and tariffs, currency exchange, or strategic materials. AKEMD products are neither intended nor authorized for use as critical componentsNote1) in any safety, life support, or other hazard related device or systemNote2), and AKEMD assumes no responsibility for such use, except for the use approved with the express written consent by Representative Director of AKEMD. As used here: Note1) A critical component is one whose failure to function or perform may reasonably be expected to result, whether directly or indirectly, in the loss of the safety or effectiveness of the device or system containing it, and which must therefore meet very high standards of performance and reliability. Note2) A hazard related device or system is one designed or intended for life support or maintenance of safety or for applications in medicine, aerospace, nuclear energy, or other fields, in which its failure to function or perform may reasonably be expected to result in loss of life or in significant injury or damage to person or property. It is the responsibility of the buyer or distributor of AKEMD products, who distributes, disposes of, or otherwise places the product with a third party, to notify such third party in advance of the above content and conditions, and the buyer or distributor agrees to assume any and all responsibility and liability for and hold AKEMD harmless from any and all claims arising from the use of said product in the absence of such notification. <KM086000> 2007/5 - 31 - 端面 外 74HC14 E 1 2 3 4 5 6 7 8 9 10 12pin 11 CN2 YP XN XP TP130 TP131 VSS1 AVDD R109 51 TP137 PDN MPWR TP129 R106 2.2k JP110 RIN1 R107 2.2k JP111 LIN1 E 1 J100 1 SW1 PDN GND YN 1 C19 0.1u 8 7 6 5 4 3 2 1 H 12 A L 内 D TouchScreen D1 HSU119 1 Vcc R8 10k 2 7 8 9 10 11 12 13 1 C20 0.1u 4Y 4A 5Y 5A 6Y 6A 3 14 E 1A 1Y 2A 2Y 3A 3Y K U2 1 2 3 4 5 6 I2C VCC C AVDD B CSN/CAD0 A XP YP 1 C118 0.01u 13 JP103 JP104 14 JP105 SDAT 1 J2 D B1 C1 VSS1 AVDD C2 D1 I2CA A1 C116 0.1u XP D2 E1 YP E2 VCOC NC PDN XN F2 F1 G2 G1 YN H1 NC TP100 SDAA L I2CA-SEL C113 0.1u VCOM A2 RIN1/IN1+ B2 SDAA CN1 C114 2.2u TP101 SCLA 1 SDAA AVDD-IN C115 10u NC C119 0.01u MPWR JP102 CADA 1 CN4 J1 U1 JP100 H AVDD-IN 1 TP132 TP134 XP YP 1 1 RIN3 + 1 C121 0.01u R108 10k JP101 VCOC-SEL VCOC C120 0.01u TP135 VCOC/RIN3 1 YN 1 TP136 XN + TP138 YN TP139 CADA TP133 I2CA XN C117 4.7n TP128 VCOM 1 SCLA H2 SCLA RIN3 TP127 RIN1 48 D LIN3 SCLT 47 H3 SDTI LIN1/IN1- A3 RIN1 C112 1u 15 A4 + C110 10u TP125 TSVDD TP126 LIN1 JP109 LIN1 C111 1u 45 TP124 LIN2 TSVDD TP102 SDTI R101 J4 BICK TP103 51 SDTO R102 H5 NC J5 VSS3 LIN2 44 43 1 17 C109 0.1u 1 B3 TSVDD 1 NC LRCK + SDTO 51 1 J3 H4 16 CCLK/SCL 1 R100 + 46 CDTI/SDA LIN2/IN2- B4 RIN2 B5 NC A5 MIN/LIN3 B6 TP123 RIN2 RIN2 1 18 TP107 AK4673 1 VSS3 51 TP104 LRCK R103 1 19 4371_SDTO 20 TP105 51 BICK R104 TP122 LIN3/MIN 1 1 4371_LRCK C 22 51 1 TP106 DVDD TP108 1 TVDD2 23 24 PENIRQN-OUT C101 0.1u C102+ 10u C103 0.1u H6 JP106 TVDD2 DVDD TVDD C100+ 10u JP107 TVDD1 DVDD NC J7 TVDD1 H8 MCKO J9 NC TP109 LOUT/LOP A6 ROUT/LON A7 LIN4/IN4+ B7 NC B8 RIN4/IN4- A8 TVDD2 H7 20k 42 TP121 LOUT LOUT 41 TP120 ROUT ROUT 40 1 21 4371_BICK J6 R12 LIN3 JP108 MIN-SEL MIN 1 4371_SDTI C R105 open 39 LIN4 1 TVDD1 38 C104+ 10u C105 0.1u 37 TP119 1 LIN4 12pin C106 0.1u 1 1 A9 NC MUTET B9 HPL C9 C8 HPR HVDD D8 D9 VSS2 SCLT E9 E8 F9 SDAT CADT PENIRQN F8 G9 NC MCKI NC H9 J8 G8 NC 12pin 1 TP117 MUTET 1 + TP140 TP141 TP142 CADT SDAT SCLT + 10u C107 B C108 1u B 1 36 35 34 33 1 TP118 RIN4 1 32 31 1 30 29 28 27 TP111 MCKO 26 CN3 25 TP110 MCKI A 1TP113 TP112 HVDD TP114 TP115 VSS2 HPR HPL 1 1 1 TP116 PENIRQN A RIN4 HPL HPR HVDD SPP SPN 4371_MCKO 4371_MCKI 12pin Title Size AKD4673-A Document Number Rev A2 Date: A B C D 0 AK4673 Monday, December 11, 2006 E Sheet 1 of 5 A B C D E IN T45_RED AGND1 + OUT JP10 LOUT_SEL C22 + 0.1u C21 0.1u C33 1u 1 1 3.5ST LOUT 2 REG1 E GND T1 TA48033F C23 47u R13 220 RCA J5 LOUT 1 E 2 3 4 5 R14 10k 1 T45_BK 2 JP3 HVDD_SEL 1 HVDD J1 LIN1/RIN1 T45_OR 2 + 6 LIN1 4 3 RIN1 3.5ST + L1 (short) 1 1 HVDD1 JP11 ROUT_SEL ROUT C34 1u C24 47u R15 220 RCA J6 ROUT 1 2 3 4 5 R16 10k JP4 AVDD_SEL L2 1 1 T45_OR C25 47u AVDD 2 3 4 5 R9 10 1 T45_OR 2 + C26 47u C30 1u R10 (short) RCA DVDD HPL (short) R17 (short) 1 TVDD (short) 2 3 4 5 R11 (short) 1 C35 220u JP12 HPL HP RIN2 RIN3 RIN4 J9 HP/LINE 6 4 3 RIN3 RIN_SEL HP HPR JP7 VCC_SEL R19 (short) C36 220u JP13 HPR 1 1 1 2 + C28 47u 2 1 VCC 2 2 D3V J10 SPK/MOUT 6 SPP (short) R22 10k R21 (open) 1 + DGND1 C29 47u B C37 1u + 1 + 2 3 4 5 (short) L6 1 T45_OR 1 R20 16 B D3V1 J8 HPR RCA L5 T45_OR C RIN4 JP1 GND VCC1 2 3 4 5 R18 16 RIN2 JP9 + 2 C27 47u 2 C31 1u + + J7 HPL 1 2 1 T45_OR LIN3 LIN4 L4 1 D LIN_SEL J3 RIN TVDD1 LIN2 LIN3 LIN4 1 JP6 TVDD_SEL C LIN2 JP8 JP5 DVDD_SEL L3 1 1 DVDD1 J2 LIN (short) + 2 + 2 + AVDD1 1 D T45_BK 4 3 JP26 MOUT R23 (open) SPN C38 (short) A A Title Size A3 Date: A B C D AKD4673-A Document Number Rev Power Supply, I/O Monday, December 11, 2006 Sheet E 2 0 of 5 A B C D E E E D3V EXT_MCLK EXT_BICK 4114_BICK JP16 EXT 14 C39 0.1u JP14 EXT 7 C 10 7 2 9 1 CLK 11 RST MKFS 16 C42 0.1u Vcc 8 GND A B C D Q1 Q2 Q3 Q4 Q5 Q6 Q7 Q8 VD Q9 Q10 Q11 DGND Q12 64fs-384 32fs-384 64fs 32fs JP19 INV PHASE BCFS fs-384 fs 4040 4040 JP20 LRCK DIR JP21 LRCK_SEL 1 2 3 4 5 6 1A 1Y 2A 2Y 3A 3Y 14 Vcc 4Y 4A 5Y 5A 6Y 6A 8 9 10 11 12 13 C D2 HSU119 16 7 C40 0.1u C43 0.1u GND U7 74HC14 8 C44 0.1u 74AC163 L H SW2 DIR 8 9 10 11 12 13 2 U4 4114_INT0 4114_PDN R25 10k MCKO ENT ENP Vcc CLK LOAD CLR GND LED1 ERF R26 1k 4114_LRCK 14 13 12 11 15 QA QB QC QD Carry 9 7 6 5 3 2 4 13 12 14 15 1 U6 74HC4040 U3 74AC74 3 4 5 6 10 K R24 51 13 12 11 10 9 8 1CLR 2CLR 1D 2D 1CK 2CK 1PR 2PR 1Q 2Q 1Q 2Q D EXT_LRCK THR A DIR 1 1 2 3 4 5 6 JP18 BICK_SEL 1 2 3 4 5 JP15 MCLK DIR 3 J11 EXT JP17 256fs 512fs 1024fs 384/768fs MCKO A 4114_MCKO K D GND B 7 14 1 2 3 4 5 6 1A 1Y 2A 2Y 3A 3Y B Vcc 4Y 4A 5Y 5A 6Y 6A U5 74HCU04 C41 0.1u A A Title Size A3 Date: A B C D AKD4673-A Document Number Rev CLOCK Monday, December 11, 2006 Sheet E 0 3 of 5 A B C D E D3V E PORT1 E L7 (short) VCC 3 GND OUT 2 1 1 2 C45 0.1u TORX141 C46 0.1u R27 470 C54 10u + C55 0.1u 1 IPS0 2 38 37 INT1 R VCOM AVDD 40 41 AVSS 42 43 NC 44 45 46 47 NC RX0 ------OFF------ RX1 L S1 SW DIP-6 TEST1 1 2 3 4 5 6 RX2 H D INT0 36 NC OCKS0 35 3 DIF0 OCKS1 34 4 TEST2 CM1 33 5 DIF1 CM0 32 6 NC PDN 31 4114_INT0 DIF2 DIF1 DIF0 OCKS1 CAD0 I2C 1 2 3 4 5 6 D RX3 12 11 10 9 8 7 48 U8 R28 18k 39 C56 0.47u VCC CAD0 7 6 5 4 3 2 1 I2C AK4114 RP1 47k C 4114_PDN C53 5p MCKO JP22 4114_MCKI 7 DIF2 XTI 30 8 IPS1 XTO 29 9 P/SN DAUX 28 10 XTL0 MCKO2 27 11 XTL1 BICK 26 4114_BICK 12 VIN SDTO 25 4114_SDTO 1 C 2 X1 11.2896MHz C52 5p DAUX LRCK 24 MCKO1 23 C51 0.1u 22 DVSS DVDD 21 VOUT 20 UOUT 19 COUT 18 BOUT 17 TX1 16 15 DVSS 14 13 C49 0.1u TX0 B TVDD B C50 10u + + 4114_LRCK C48 10u 4114_MCKO PORT2 IN VCC 3 2 GND 1 C47 0.1u A A TOTX141 Title Size A3 Date: A B C D AKD4673-A Document Number Rev DIR/DIT Monday, December 11, 2006 Sheet E 0 4 of 5 A B C D E VCC D3V E U9 EXT_BICK 3 A1 B1 21 EXT_LRCK 4 A2 B2 20 5 A3 B3 19 6 A4 B4 18 7 A5 B5 17 8 A6 B6 16 R29 10k 7 6 5 4 3 2 1 PORT3 MCLK BICK LRCK SDTI VCC 2 GND 4 GND 6 8 10 SDTO 1 3 5 7 9 A7 B7 15 10 A8 B8 14 2 DIR OE 22 1 VCCA VCCB 24 VCCB 23 GND 13 7 6 5 4 3 2 1 RP3 47k C57 0.1u Slave D 11 GND 12 GND U10 C58 0.1u D A1 B1 21 4 A2 B2 20 5 A3 B3 19 6 A4 B4 18 7 A5 B5 17 MCKO 8 A6 B6 16 PENIRQN 9 A7 B7 15 DAUX 10 A8 B8 14 2 DIR 1 VCCA 11 GND 12 GND Master 3 C JP23 M/S 74AVC8T245 C59 0.1u JP24 ADC SDTI_SEL 4114_SDTO U11 DIR EXT_MCLK CAD0 I2C R30 10k PORT4 10 8 6 4 2 9 7 5 3 1 R31 10k CSN CCLK/SCI CDTI/SDA CDTO/SDA(ACK) PENIRQN R32 10k R33 R34 R35 E 4371_LRCK RP2 47k DSP B 9 4371_BICK JP25 CTRL_SEL 3-WIRE 470 470 470 OE 22 VCCB 24 VCCB 23 GND 13 4371_MCKO PENIRQN-OUT 4371_SDTO C C60 0.1u 3 A1 B1 21 4 A2 B2 20 5 A3 B3 19 6 A4 B4 18 4371_MCKI 7 A5 B5 17 4371_SDTI 8 A6 B6 16 CSN/CAD0 9 A7 B7 15 CCLK/SCL 10 A8 B8 14 CDTI/SDA 74AVC8T245 B 2 DIR 1 VCCA CTRL C61 0.1u PENIRQN 11 12 OE 22 VCCB 24 VCCB 23 GND 13 C62 0.1u GND GND 74AVC8T245 U12 A 1 3 5 9 11 13 1A 2A 3A 4A 5A 6A 14 Vcc C63 0.1u 7 1Y 2Y 3Y 4Y 5Y 6Y 2 4 6 8 10 12 R36 1k A Title Size A3 GND 74LVC07 A B Date: C D AKD4673-A Document Number Rev LOGIC Tuesday, October 17, 2006 Sheet E 0 5 of 5