NEC UPD77019GC-013-9EU

PRELIMINARY DATA SHEET
MOS INTEGRATED CIRCUIT
µPD77019-013
16 bits, Fixed-point Digital Signal Processor
The µPD77019-013 is a masked 16 bits fixed-point DSP (Digital Signal Processor) developed for digital signal
processing with its demand for high speed and precision.
The µPD77019-013 internal ROM area is masked already by the void code to use as RAM based DSP without mask
code ordering process. Also the µPD77019-013 can operate as simplified evaluate chip for as the µPD7701x family.
About mask ROM and mask option, there are following differences between the µPD77019-013 and µPD77019.
µ PD77019
µ PD77019-013
PLL clock multiple rate
Fixed to 4
Variable multiple rate (1, 2, 3, 4, 8) by mask
option
Crystal resonator
connection
Disable (PLL clock multiple rate is fixed to 4.)
Enable (PLL clock multiple rate is set to 1 by
mask option.)
Clock Input pin
External clock is connected to the X1 pin.
Leave the X2 pin open.
External clock is connected to the X1 pin.
Crystal is connected between the X1 pin and
X2 pin.
Clock output pin
Output internal system clock.
Low level fixed, or internal system clock
output is selectable by mask option.
Internal mask ROM
Not available (already masked by the void
code)
Coding user program or data when ordering
mask ROM.
Self boot
Enable to boot from external data area (Boot
information data is masked.) Refer to 2.6
Boot Function.
Enable to boot from internal data ROM or
external data area.
ORDERING INFORMATION
Part Number
Package
µ PD77019GC-013-9EU
100-pin plastic TQFP (FINE PITCH) (14 × 14 mm)
The µ PD7701x family consists of the µ PD77016, 77015, 77017, 77018, 77018A and µ PD77019.
The information in this document is subject to change without notice.
Document No. U13053EJ1V0DS00 (1st edition)
Date Published March 1998 N CP(K)
Printed in Japan
©
1998
µPD77019-013
FEATURES
• FUNCTIONS
• Instruction cycle: 16.6 ns (MIN.)
Operation clock: 60 MHz
External clock: 15 MHz
• Dual load/store
• Hardware loop function
• Conditional execution
• Executes product-sum operation in one instruction cycle
• PROGRAMMING
• 16 bits × 16 bits + 40 bits → 40 bits multiply accumulator
• 8 general registers (40 bits each)
• 8 ROM/RAM data pointer: each data memory area has 4 registers
• 10 source interrupts (external: 4, internal: 6)
• 3 operand instructions (example: R0 = R0 +R1L∗R2L)
• Nonpipeline on execution stage
• MEMORY AREAS
• Instruction memory area : 64K words × 32 bits
• Data memory areas : 64K words × 16 bits × 2 (X memory, Y memory)
• CLOCK GENERATOR
• On-chip PLL to provide higher operation clock (60 MHz max.) than the external clock. PLL clock multiple rate is
fixed to 4.
• ON-CHIP PERIPHERAL
• I/O port: 4 bits
• Serial I/O (16 bits): 2 channels
• Host I/O (8 bits): 1 channel
• CMOS
• +3 V single power supply
2
Preliminary Data Sheet
BLOCK DIAGRAM
X–Bus
External
Memory
Y–Bus
Serial
I/O #1
X Memory
Data
Pointers
X Memory
Y Memory
Data
Pointers
Y Memory
R0–R7
Preliminary Data Sheet
Serial
I/O #2
Main Bus
MPY
16×16+40 → 40
Ports
Interrupt
Control
Loop
Control
Stack
PC Stack
ALU (40)
Instruction
Memory
Host I/O
CPU Control
INT1 – INT4
IE I/O
WAIT RESET CLKOUT
X1
3
µPD77019-013
Wait
Controller
µPD77019-013
FUNCTIONAL PIN GROUPS
+3 V
SO1
SORQ1
Serial Interface #1
VDD
SOEN1
SCK1
INT2
INT3
SI1
SIEN1
INT4
SIAK1
X1
CLKOUT
SO2
SOEN2
SCK2
Serial Interface #2
TDO, TICE
TCK, TDI, TMS
SI2
SIEN2
Ports
(4)
RESET
INT1
Interrupts
(2)
Debugging
Interface
(3)
HOLDRQ
BSTB
HOLDAK
P0 - P3
Data Bus
Control
HCS
(2)
Host Interface
(8)
4
HA0, HA1
HRD
HRE
HWR
HWE
HD0 - HD7
GND
X/Y
DA0 - DA13
D0 - D15
WAIT
MRD
MWR
Preliminary Data Sheet
(14)
(16)
External
Data
Memory
Functional Differences among the µPD7701× Family
Item
µ PD77016
Internal instruction RAM
1.5K words
Internal instruction ROM
None
External instruction memory
µ PD77015
µ PD77017
µ PD77018
4K words
12K words
1K words each
2K words each
Data ROM (X/Y memory)
None
2K words each
4K words each
48K words each
Preliminary Data Sheet
Crystal
(at maximum operation speed)
–
Instruction
–
Power supply
Package
None
3K words each
12K words each
Channel 1 has the
same functions
as channel 2.
16.6 ns (60 MHz)
33/16.5/8.25/4.125 MHz
Variable multiple rate (1, 2, 4, 8 ) by mask option.
60/30/20/15/7.5 MHz
Variable multiple rate (1, 2, 3, 4, 8 ) by
mask option.
60 MHz
33 MHz
15 MHz
Multiple rate is
fixed to 4.
–
STOP instruction is added.
Channel 1 has the same functions as that of the µ PD77016.
Channel 2 has no SORQ2 or SIAK2 pin (Channel 2 is used for CODEC connection).
5V
160-pin plastic QFP
None
16K words each
30 ns (33 MHz)
66 MHz
Serial interface (2 Channels)
24K words
None
2K words each
External clock
(at maximum operation speed)
µ PD77019-013
4K words
48K words
Instruction cycle
(Maximum operation speed)
µ PD77019
256 words
Data RAM (X/Y memory)
External data memory
µ PD77018A
3V
100-pin plastic TQFP
100-pin plastic TQFP
116-pin plastic BGA
100-pin plastic TQFP
µPD77019-013
5
µPD77019-013
PIN CONFIGURATION (Top View)
µ PD77019GC-013-9EU
HCS
HD0
HD1
HRD
HWR
HA0
HA1
GND
X2
X1
TDO
CLKOUT
VDD
TICE
TCK
TDI
TMS
HOLDRQ
HOLDAK
MWR
GND
MRD
VDD
RESET
1
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76
75
HD2
INT4
2
74
HD3
INT3
3
73
HD4
INT2
4
72
HD5
INT1
5
71
HD6
I.C.
6
70
HD7
X/Y
7
69
VDD
DA13
8
68
GND
DA12
9
67
HWE
GND
10
66
HRE
VDD
11
65
P0
DA11
12
64
P1
DA10
13
63
P2
DA9
14
62
P3
DA8
15
61
SI2
DA7
16
60
SIEN2
DA6
17
59
SCK2
DA5
18
58
SO2
DA4
19
57
SOEN2
GND
20
56
VDD
VDD
21
55
GND
DA3
22
54
SOEN1
DA2
23
53
SORQ1
DA1
24
52
SO1
DA0
25
51
SIAK1
Preliminary Data Sheet
SCK1
SIEN1
SI1
D1
D0
D3
D2
GND
VDD
D4
D5
D6
D7
GND
VDD
D8
D9
D10
D11
VDD
GND
D12
D14
D13
26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
D15
6
BSTB
WAIT
100-pin plastic TQFP (FINE PITCH) (14 × 14 mm )
µPD77019-013
PIN IDENTIFICATION
BSTB:
Bus Strobe
CLKOUT:
Clock Output
D0-D15:
16 Bits Data Bus
DA0-DA13:
External Data Memory Address Bus
GND:
Ground
HA0,HA1:
Host Data Access
HCS:
Host Chip Select
HD0-HD7:
Host Data Bus
HOLDAK:
Hold Acknowledge
HOLDRQ:
Hold Request
HRD:
Host Read
HRE:
Host Read Enable
HWE:
Host Write Enable
HWR:
Host Write
I.C.:
Internally Connected
INT1-INT4:
Interrupt
MRD:
Memory Read Output
MWR:
Memory Write Output
P0-P3:
Port
RESET:
Reset
SCK1,SCK2:
Serial Clock Input
SI1,SI2:
Serial Data Input
SIAK1:
Serial Input Acknowledge
SIEN1,SIEN2:
Serial Input Enable
SO1,SO2:
Serial Data Output
SOEN1,SOEN2: Serial Output Enable
SORQ1:
Serial Output Request
TCK:
Test Clock Input
TDI:
Test Data Input
TDO:
Test Data Output
TICE:
Test In-Circuit Emulator
TMS:
Test Mode Select
V DD:
Power Supply
WAIT:
Wait Input
X1, X2:
Crystal connection
X/Y:
X/Y Memory Select
Preliminary Data Sheet
7
µPD77019-013
PIN NAME
Pin No.
Symbol
Pin No.
Symbol
Pin No.
Symbol
Symbol
1
RESET
26
D15
51
SIAK1
76
HD1
2
INT4
27
D14
52
SO1
77
HD0
3
INT3
28
D13
53
SORQ1
78
HCS
4
INT2
29
D12
54
SOEN1
79
HRD
5
INT1
30
GND
55
GND
80
HWR
6
I.C. Note 1
31
VDD
56
VDD
81
HA0
7
X/Y
32
D11
57
SOEN2
82
HA1
8
DA13
33
D10
58
SO2
83
GND
9
DA12
34
D9
59
SCK2
84
X2 Note 2
10
GND
35
D8
60
SIEN2
85
X1
11
VDD
36
GND
61
SI2
86
VDD
12
DA11
37
VDD
62
P3
87
CLKOUT
13
DA10
38
D7
63
P2
88
TDO
14
DA9
39
D6
64
P1
89
TICE
15
DA8
40
D5
65
P0
90
TCK
16
DA7
41
D4
66
HRE
91
TDI
17
DA6
42
GND
67
HWE
92
TMS
18
DA5
43
VDD
68
GND
93
HOLDRQ
19
DA4
44
D3
69
VDD
94
HOLDAK
20
GND
45
D2
70
HD7
95
MWR
21
VDD
46
D1
71
HD6
96
GND
22
DA3
47
D0
72
HD5
97
VDD
23
DA2
48
SI1
73
HD4
98
MRD
24
DA1
49
SIEN1
74
HD3
99
BSTB
25
DA0
50
SCK1
75
HD2
100
WAIT
Note 1. I.C. (Internally Connected): Leave this pin open.
2. Leave this pin open.
8
Pin No.
Preliminary Data Sheet
µPD77019-013
CONTENTS
1. PIN FUNCTIONS ............................................................................................................................... 10
1.1
Pin Functions ........................................................................................................................................... 10
1.2
Recommended Connection for Unused Pins ....................................................................................... 15
2. FUNCTIONS ...................................................................................................................................... 16
2.1
Pipeline Processing ................................................................................................................................ 16
2.1.1
Outline ........................................................................................................................................... 16
2.1.2
Instructions with Delay .................................................................................................................. 16
2.2
Program Control Unit .............................................................................................................................. 17
2.3
Operation Unit ......................................................................................................................................... 17
2.4
2.5
2.6
2.3.1
General register (R0 to R7) ........................................................................................................... 17
2.3.2
MAC: Multiply ACcumulator ......................................................................................................... 18
2.3.3
ALU: Arithmetic Logic Unit ........................................................................................................... 18
2.3.4
BSFT: Barrel ShiFTer ................................................................................................................... 18
2.3.5
SAC: Shifter And Count Circuit .................................................................................................... 18
2.3.6
CJC: Condition Judge Circuit ....................................................................................................... 19
Memory ..................................................................................................................................................... 19
2.4.1
Instruction RAM Outline ................................................................................................................ 20
2.4.2
Data Memory Outline .................................................................................................................... 21
2.4.3
Data Memory Addressing .............................................................................................................. 22
On-chip Peripheral Circuit ...................................................................................................................... 22
2.5.1
Serial Interface Outline .................................................................................................................. 22
2.5.2
Host Interface Outline ................................................................................................................... 22
2.5.3
General Input/output Ports Outline ................................................................................................ 22
2.5.4
Wait Cycle Register ....................................................................................................................... 22
Boot Function .......................................................................................................................................... 23
3. INSTRUCTIONS ................................................................................................................................ 24
3.1
Outline ...................................................................................................................................................... 24
3.2
Instruction Set and Operation ................................................................................................................ 25
4. ELECTRICAL SPECIFICATIONS ..................................................................................................... 33
5. PACKAGE DRAWING ...................................................................................................................... 53
6. RECOMMENDED SOLDERING CONDITIONS ................................................................................ 54
Preliminary Data Sheet
9
µPD77019-013
1. PIN FUNCTIONS
1.1 Pin Functions
• Power supply
Symbol
Pin No.
I/O
Function
VDD
11, 21, 31, 37, 43, 56, 69,
86, 97
–
+3V power supply
GND
10, 20, 30, 36, 42, 55, 68,
83, 96
–
Ground
• System control
Symbol
Pin No.
I/O
Function
X1
85
I
Clock input
X2
84
_
Leave this pin open
CLKOUT
87
O
Internal system clock output
RESET
1
I
Internal system reset signal input
• Interrupt
Symbol
INT4 - INT1
10
Pin No.
2-5
I/O
I
Function
Maskable external interrupt input
• Falling edge detection
Preliminary Data Sheet
µPD77019-013
• External data memory interface
Symbol
Pin No.
I/O
Function
X/Y
7
O
(3S)
Memory select signal output
• 0: X memory is used.
• 1: Y memory is used.
DA13 - DA0
8, 9, 12 -19, 22 - 25
O
(3S)
Address bus to external data memory
• External data memory is accessed.
• During the external memory is not accessed, these pins
keep the previous level.
These pins are set to low level; 0x0000, by reset.
They continue outputting low level until the first external
memory access.
D15 - D0
26 -29, 32 - 35, 38 - 41,
44 - 47
I/O
(3S)
16 bits data bus to external data memory
• External data memory is accessed.
MRD
98
O
(3S)
Read output
• Reads external memory
MWR
95
O
(3S)
Write output
• Writes external memory
WAIT
100
I
Wait signal input
• Wait cycle is input when external memory is read.
1: No wait
0: Wait
HOLDRQ
93
I
Hold request signal input
• Input low level when external data memory bus is
expected to use.
BSTB
99
O
Bus strobe signal output
• Outputs low level while the µPD77019-013 is occupying
external memory bus.
HOLDAK
94
O
Hold acknowledge signal output
• Outputs low level when the µPD77019-013 permits external
device to use external data memory bus.
Remark The state of the pins added 3S becomes high impedance when the external memory is not accessed
and when bus release signal (HOLDAK = 0) is output.
Preliminary Data Sheet
11
µPD77019-013
• Serial interface
Symbol
Pin No.
I/O
Function
SCK1
50
I
Clock input for serial 1
SORQ1
53
O
Serial output 1 request
SOEN1
54
I
Serial output 1 enable
SO1
52
O (3S)
Serial data output 1
SIEN1
49
I
Serial input 1 enable
SI1
48
I
Serial data input 1
SCK2
59
I
Clock input for serial 2
SOEN2
57
I
Serial output 2 enable
SO2
58
O (3S)
Serial data output 2
SIEN2
60
I
Serial input 2 enable
SI2
61
I
Serial data input 2
SIAK1
51
O
Serial input 1 acknowledge
Remark
12
The state of the pins added 3S becomes high impedance, when data output have been finished or RESET is input.
Preliminary Data Sheet
µPD77019-013
• Host interface
Symbol
Pin No.
I/O
Function
HA1
82
I
Specifies register which HD7 to HD0 access
1: Accesses HST: Host interface status register
when HA1 = 0
0: Accesses HDT(in): Host transmit data register when
HWR = 0
0: Accesses HDT(out): Host receive data register when
HRD = 0
HA0
81
I
Specifies bits of registers which HD7 to HD0 access
• 1: Accesses bits 15-8 of HST, HDT(in) or HDT(out)
• 0: Accesses bits 7-0 of HST, HDT(in) or HDT(out)
HCS
78
I
Chip select input
HRD
79
I
Host read input
HWR
80
I
Host write input
HRE
66
O
Host read enable output
HWE
67
O
Host write enable output
HD7 - HD0
70 - 77
Remark
I/O (3S)
8 bits host data bus
The state of the pins added 3S becomes high impedance when the host does not access host interface.
• I/O port
Symbol
P3 - P0
Pin No.
62 - 65
I/O
I/O
Function
I/O port
Preliminary Data Sheet
13
µPD77019-013
• Debugging interface
Symbol
Pin No.
I/O
Function
TDO
88
O
For debugging
TICE
89
O
For debugging
TCK
90
I
For debugging
TDI
91
I
For debugging
TMS
92
I
For debugging
• Other
Symbol
I.C.
Pin No.
6
I/O
_
Function
Internal connected pin. Leave this pin open.
Caution When any signal is applied to or read
out from this pin, normal operation of
the µ PD77019-013 is not assured.
14
Preliminary Data Sheet
µPD77019-013
1.2 Recommended Connection for Unused Pins
Pin
Recommended connection
I/O
INT1 - INT4
I
connect to V DD
X/Y
O
open
DA0 - DA13
O
D0 - D15 Note1
I/O
connect to V DD or GND, via a resistor
MRD, MWR
O
open
WAIT
I
connect to V DD
HOLDRQ
I
BSTB
O
HOLDAK
O
SCK1, SCK2
I
SI1, SI2
I
SOEN1, SOEN2
I
SIEN1, SIEN2
I
SORQ1
O
SO1, SO2
O
SIAK1
O
HA0, HA1
I
connect to V DD or GND
HCS
I
connect to V DD
HRD, HWR
I
HRE, HWE
O
HD0 - HD7 Note2
I/O
P0 - P3
I/O
open
connect to V DD or GND
connect to GND
open
open
connect to V DD or GND, via a resistor
TCK
I
connect to GND, via a resistor
TDO, TICE
O
open
TMS, TDI
I
open(pull-up internally)
CLKOUT
O
open
Notes 1. Can leave open, if no access to external data memory is
executed in the whole of program.
But in the HALT mode or STOP mode when the current
consumption is reduced, connect a pin as recommended
connection.
2. Can leave open, if HCS, HRD, HWR are fixed to high level.
But in the HALT mode or STOP mode when the current
consumption is reduced, connect a pin as recommended
connection.
Remark
I: Input pin, O: Output pin, I/O: Input/Output pin
Preliminary Data Sheet
15
µPD77019-013
2. FUNCTIONS
2.1 Pipeline Processing
This section describes the µ PD77019-013 pipeline processing.
2.1.1 Outline
The µ PD77019-013 basic operations are executed in following 3-stage pipeline.
(1) instruction fetch; if
(2) Instruction decoding; id
(3) execution; ex
When the µ PD77019-013 operates a result of a instruction just executed before, the data is input to ALU in
parallel with written back to general registers. Pipeline processing actualizes programming without delay time
to execute instructions and write back data. Three successive instructions and their processing timing are shown
below.
Pipeline Processing Timing
if1
id1
ex1
if2
id2
ex2
if3
id3
ex3
1 instruction cycle
2.1.2 Instructions with Delay
The following instructions have delay time in execution.
(1) Instructions to control interrupt
2 instruction cycles have been taken between instruction fetch and execution.
(2) Inter-register transfer instructions and immediate data set instructions
When data is set in data pointer, it needs 2 instruction cycles before the data is valid.
16
Preliminary Data Sheet
µPD77019-013
2.2 Program Control Unit
Program control unit controls not only count up of program counter in normal operation, but loop, repeat,
branch, halt and interrupt.
In addition to loop stack of loop 4 level and program stack of 15 level, software stack can be used for multiloop and multi-interrupt/subroutine call.
The µ PD77019-013 has external 4 interruptions and internal 6 interruptions from peripheral, and specifies
interrupt enable or disable independently.
The HALT and STOP instructions cause the µ PD77019-013 to place in low power standby mode.
When the HALT instruction is executed, power consumption decreases. HALT mode is released by interrupt
input or hardware reset input. It takes several system clock to recover.
When the STOP instruction is executed, power consumption decreases. STOP mode is released by hardware
reset input. It takes a few ms to recover.
2.3 Operation Unit
Operation unit consists of the following five parts.
– 40 bits general register × 8 for data load/store and input/output of operation data
– 16 bits × 16 bits + 40 bits → 40 bits multiply accumulator
– 40 bits Data ALU
– 40 bits barrel shifter
– SAC: shifter and count circuit.
Standard word length is 40 bits to make overflow check and adjustment easy, and to accumulate the result
of 16 bits × 16 bits multiplication correctly.
39
1 0
32 31
SSSSSSSS
Head room
0
Result of multiplication among two's complement data
2.3.1 General register (R0 to R7)
The µ PD77019-013 has eight 40 bits registers for operation input/output and load/store with memory. General
register consists of the following three parts.
– R0L to R7L (bit 15 to bit 0)
– R0H to R7H (bit 31 to bit 16)
– R0E to R7E (bit 39 to bit 32)
But each of RnL, RnH and RnE are treated as a register in the following conditions.
(1) General register used as 40 bits register
General registers are treated as 40 bits register, when they are used for the following aims.
(a) Operand for triminal operation (except for multiplier input)
(b) Operand for dyadic operation (except for multiplier and shift value)
(c) Operand for monadic operation (except for exponent instructions)
(d) Operand for operation
(e) Operand for conditional judge
(f)
Destination for load instruction (with sign extension and 0 clear)
Preliminary Data Sheet
17
µPD77019-013
(2) General register used as 32 bits register
Bit 31 to bit 0 of general register are treated as 32 bits register, when it is used for a operand of exponent
instruction.
(3) General register used as 24 bits register
Bit 39 to bit 16 of general register are treated as 24 bits register, when it is used for destination with extended
sign for a load/store instruction.
(4) General register used as 16 bits register
Bit 31 to bit 16 of general register are treated as 16 bits register, when it is used for the following aims.
(a) Signed operand for multiplier
(b) Source/destination for load/store instruction
Bit 15 to bit 0 of general register are treated as 16 bits register, when it is used for the following aims.
(c) Unsigned operand for multiplier
(d) Shift value for shift instruction
(e) Source/destination for load/store instruction
(f)
Source/destination for inter-register transfer instruction
(g) Destination for immediate data set instruction
(f)
Hardware loop times
(5) General register used as 8 bits register
Bit 39 to bit 32 of general register are treated as 8 bits register, when it is used for source/destination of load/
store instruction.
2.3.2 MAC: Multiply ACcumulator
MAC multiplies a pair of 16 bits data, and adds or subtract the result and 40 bits data. MAC outputs 40 bits
data.
MAC operates three types of multiplication: signed data × signed data, signed data × unsigned data and
unsigned data × unsigned data.
Result of multiplication and 40 bits data for addition can be added after 1 or 16 bits arithmetic shift right.
2.3.3 ALU: Arithmetic Logic Unit
ALU performs arithmetic operation and logic operation. Both input/output data are 40 bits.
2.3.4 BSFT: Barrel ShiFTer
BSFT performs shift right/left operation. Both input/output data are 40 bits. There are two types of shift right
operations; arithmetic shift right which sign is extended, and logic shift right which is input 0 in MSB first.
2.3.5 SAC: Shifter And Count Circuit
SAC calculates and outputs shift value for normalization. SAC is input 32 bits data and outputs the 40 bits
data. Then, bit 39 to bit 5 of output data is always 0.
18
Preliminary Data Sheet
µPD77019-013
2.3.6 CJC: Condition Judge Circuit
CJC judges whether condition is true or false with 40 bits input data. A conditional instruction is executed
when the result is true, and not executed when the result is false.
2.4 Memory
The µ PD77019-013 has one instruction memory area (64K words × 32 bits) and two data memory areas (64K
words × 16 bits each). It adopts Harvard-type architecture, with instruction memory area and data memory areas
separated.
The µ PD77019-013 has 2 sets of data addressing units, which are dedicated for addressing data memory
area. Each addressing unit consists of four data pointers, four index registers, a modulo register and addressing
ALU.
X memory area addresses are specified by DP0 to DP3, and Y memory area addresses are specified by DP4
to DP7. After memory access, DPn (with the same subscript), can be modified by DNn value. Modulo operation
is performed with DMX for DP0 to DP3, with DMY for DP4 to DP7.
Preliminary Data Sheet
19
µPD77019-013
2.4.1 Instruction RAM Outline
The µPD77019-013 has an instruction RAM (4K words × 32 bits).
A system vector area is assigned to 64 words of the instruction RAM. Internal instruction RAM is initialized
and rewritten by boot program.
Boot up ROM contains the program loading instruction code to internal instruction RAM.
µ PD77019-013
0 x FFFF
System (61 K words)
0x1200
0 x 1 1FF
Internal Instruction RAM
(4 K words)
0x0240
0 x 023F
0x0200
0 x 0 1FF
0x0100
0 x 0 0FF
0x0000
Caution
Vector (64 words)
System (256 words)
Bootup ROM (256 words)
When any data is accessed or stored to system address, normal operation of the device is
not assured.
20
Preliminary Data Sheet
µPD77019-013
2.4.2 Data Memory Outline
The µ PD77019-013 has two data memory areas (64K words × 16 bits each) in X and Y memory areas.
Every memory areas consists of 3K words × 16 bits data RAM. As the µ PD77019-013 has interface with the
external data memory, 16K words × 16 bits external data memory space can be added to X/Y memories.
Each data memory area includes on-chip peripheral area which consists of 64 words.
When the external data memory area is accessed, instruction cycle can be 2 or more by wait function.
µ PD77019-013
0 x FFFF
External Data Memory
(16 K words)
0 x C0 0 0
0 x BF F F
System (32 K words)
0x4005
0x4004
0x4000
0 x 3FFF
Boot (5 words)
System (1984 words)
0x3840
0 x 383F
0x3800
0 x 3 7FF
Peripheral (64 words)
System (11 K words)
0 x 0C0 0
0 x 0 BF F
Data RAM (3 K words)
0x0000
Caution
When any data is accessed or stored to system address, normal operation of the device is
not assured.
Preliminary Data Sheet
21
µPD77019-013
2.4.3 Data Memory Addressing
There are following two types of data memory addressing.
• Direct addressing
The address is specified in the instruction field.
• Indirect addressing
The address is specified by the data pointer (DP). DP can get a bit reverse before addressing. It can
update the DP value after accessing data memory.
2.5 On-chip Peripheral Circuit
The µ PD77019-013 includes serial interface, host interface, general input/output ports and wait cycle
registers. They are mapped in both X and Y memory areas, and are accessed as memory mapped I/O by the
µ PD77019-013 CPU.
2.5.1 Serial Interface Outline
The µ PD77019-013 has 2 channel serial interfaces. Serial I/O clock must be provided from external. Frame
length can be programmed independently to be 8 bits or 16 bits. MSB first or LSB first can also be selected.
Data is input/output by hand shaking for an external device, and by interrupts, polling or wait function in internal.
2.5.2 Host Interface Outline
The µ PD77019-013 has 8 bits parallel ports as host interface to input/output data to and from host CPU and
DMA controller. When an external device accesses host interface, HA0 and HA1 pins; which are host address
input pins; specifies bit 15 to bit 8 and bit 7 to bit 0. The µ PD77019-013 includes 3 registers consisting of 16
bits, which are dedicated for input data, output data and status. The µ PD77019-013 has three types of interface
method for internal and external data; interrupts, polling and wait function.
2.5.3 General Input/output Ports Outline
General input/output ports consist of 4 bits. User can set each port as input or output. The µ PD77019-013
includes two registers. One is 4 bits register for input/output data, and the other is 16 bits for control.
2.5.4 Wait Cycle Register
The wait cycle registers consist of 16 bits. It is used to set wait cycle number when external memory is
accessed. When external data memory area (0xC000 - 0xFFFF) is accessed, 0, 1, 3, or 7 wait cycle can be set.
When external data memory area is accessed, wait cycle can be also set by WAIT pin.
22
Preliminary Data Sheet
µPD77019-013
2.6 Boot Function
There are following cautions on using boot function of the µ PD77019-013.
The µ PD77019-013 has self-boot mode and host boot mode.
In host boot mode, the boot code is transferred from host side; external host CPU via host interface. The boot
function in host boot mode is same function as other µ PD7701x family products have.
In self-boot mode, the boot codes are transferred from external data memory or internal data ROM to
instruction RAM.
The µ PD77019-013 executes self-boot function transferred from external data memory only. Because internal
data ROM of the µ PD77019-013 is masked already and the boot codes cannot be transferred. Other µ PD7701x
family products store their boot information in 0x4000:Y-0x4004:Y. But the user cannot define these addresses,
because they are in the internal ROM of the µ PD77019-013.
Then in the µ PD77019-013, the following boot information is defined to Y data ROM for self-boot mode.
0x4000:Y
0
(Y memory boot/word boot)
0x4001:Y
0xC0C0
(DWTR value is set to 7 wait access mode)
0x4002:Y
0
(IWTR value is set to 0 wait access mode)
0x4003:Y
0xC000
(sta rt address of boot code stored)
0x4004:Y
0x1000
(4K words as program step)
To execute boot function in self-boot mode, connect external Y data area with more than the 8K words 16 bits
data width PROM (7 wait accessible) where the boot code should be stored.
Preliminary Data Sheet
23
µPD77019-013
3. INSTRUCTIONS
3.1 Outline
All µPD77019-013 instructions are one-word instructions, consisting of 32 bits. And they are executed in 16.6 ns
(min.) per instruction. There are following 9 instruction types.
(1) Trinomial instructions
: specify the Acc operation. 3 of general registers are specified optionally as the operation object.
(2) Dyadic operation instructions
: specify the Acc, ALU or shifter operation. 2 of general registers are specified optionally as the operation
object. Some instructions can specify a general register and immediate data.
(3) Monadic operation instructions
: specify operations by ALU. 1 general register is specified optionally as the operation object.
(4) Load/store instructions
: transfer 16 bits data from memory to general registers, from general registers to memory and between
general registers.
(5) Inter-register transfer instructions
: transfer data between general register and other registers.
(6) Immediate data set instructions
: set immediate data at general registers or each registers of address operation unit.
(7) Branch instructions
: specify the direction of the program flow.
(8) Hardware loop instructions
: specify times of instruction repeating.
(9) Control Instructions
: specify the control program.
24
Preliminary Data Sheet
µPD77019-013
3.2 Instruction Set and Operation
An operation is written according to the rules for expressing. An expression of instructions having two or more
descriptions can have only one selected.
(a) Expressions and selectable registers
Expression and selectable registers are shown as follows.
Expression
Selectable registers
ro, ro', ro"
R0 - R7
rl, rl'
R0L - R7L
rh, rh'
R0H - R7H
re
R0E - R7E
reh
R0EH - R7EH
dp
DP0 - DP7
dn
DN0 - DN7
dm
DMX, DMY
dpx
DP0 - DP3
dpy
DP4 - DP7
dpx_mod
DPn, DPn++, DPn– –, DPn##, DPn%%, !DPn## (n = 0 - 3)
dpy_mod
DPn, DPn++, DPn– –, DPn##, DPn%%, !DPn## (n = 4 - 7)
dp_imm
DPn##imm (n = 0 - 7)
∗×××
content of memory address ×××
Example
When the content of DP0 register is 1000, ∗DP0 shows the content of memory
address 1000.
Preliminary Data Sheet
25
µPD77019-013
(b) Modifying data pointers
Data pointers are modified after memory access. The results are valid immediately after instruction execution.
It is impossible to modify without memory access.
Description
Operation
DPn
No operation: DPn value does not change.
DPn++
DPn ← DPn+1
DPn– –
DPn ← DPn–1
DPn ← DPn + DNn: Adds DN0-DN7 corresponding to DP0-DP7
DPn##
Example DP0 ← DP0 + DN0
DPn%%
!DPn##
(n = 0 - 3)
DPn = ((DPL + DNn )mod (DMX + 1)) + DPH
(n = 4 - 7)
DPn = ((DPL + DNn )mod (DMY + 1)) + DPH
Access memory after DPn value is bit-reversed
After memory access, DPn ← DPn + DNn
DPn ← DPn + imm
DPn##imm
(c) Concurrent processing instructions
shows concurrent processing instruction.
Instruction names are shown in abbreviation.
TRI
: Trinomial
DYAD
: Dyadic
MONAD : Monadic
TRANS
: Inter-register transfer
IMM
: Immediate data set
BR
: Branch
LOOP
: Hardware loop
CTR
: Control
(d) State of Overflow flag (OV)
The following marks show the µPD77019-013 overflow flag state.
↔
: Not affected
: 1 is set when the result of operation is overflow.
Caution
If overflow does not occur after operation, OV is not reset, and keeps the state before
operation.
26
Preliminary Data Sheet
µPD77019-013 INSTRUCTION SET
Concurrent Writing Processing
Name
Operation
TRI.
DYAD. MONAD.
Load/
store
TRANS.
IMM.
Flag
BR. LOOP.
CTL. OV
ro = ro + rh∗rh'
ro ← ro+rh∗rh'
↔
Multiply sub
ro = ro–rh∗rh'
ro ← ro–rh∗rh'
↔
Sign unsign
Multiply add
ro = ro + rh∗rl
(rl should be a plus
integral number.)
ro ← ro+rh∗rl
Unsign unsign
Multiply add
ro=ro+rl∗rl'
(rl and rl' should be a plus
integral number.)
ro ← ro+rl∗rl'
1 bit shift Multiply add
ro=(ro>>1)+rh∗rh'
16 bits shift Multiply add
ro = (ro>>16)+rh∗rh'
ro ← ro +rh∗rh'
2
ro
ro ← 16 +rh∗rh'
2
Multiply
ro=rh∗rh'
ro ← rh∗rh'
Add
ro"=ro+ro'
ro" ← ro+ro'
Immediate add
ro'=ro+imm
ro' ← ro+imm (imm≠1)
↔ ↔
Sub
ro"=ro–ro'
ro" ← ro–ro'
↔
Immediate sub
ro'=ro–imm
ro' ← ro–imm (imm≠1)
↔
Arithmetic right shift
ro'=ro SRA rl
ro' ← ro >> rl
Immediate arithmetic
right shift
ro'=ro SRA imm
ro' ← ro >> imm
Logic right shift
ro'=ro SRL rl
ro' ← ro >> rl
Immediate Logic right shift
ro'=ro SRL imm
ro' ← ro >> imm
Logic left shift
ro'=ro SLL rl
ro' ← ro << rl
Immediate logic left shift
ro'=ro SLL imm
ro' ← ro << imm
↔
Multiply add
Trinomial
↔
↔
Preliminary Data Sheet
Dyadic
Mnemonic
µPD77019-013
27
28
Concurrent Writing Processing
Name
Mnemonic
Operation
And
ro" = ro & ro'
ro" ← ro & ro'
Immediate and
ro' = ro & imm
ro' ← ro & imm
Or
ro" = ro | ro'
ro" ← ro | ro'
Immediate or
ro' = ro | imm
ro' ← ro | imm
Exclusive or
ro" = ro ^ ro'
ro" ← ro ^ ro'
Immediate exclusive or
ro = ro ^ imm
ro ← ro ^ imm
Less than
ro" = LT(ro, ro')
if(ro<ro')
{ro" ← 0x0000000001}
else {ro" ← 0x0000000000}
Clear
CLR(ro)
ro ← 0x0000000000
Increment
ro' = ro + 1
ro' ← ro + 1
Decrement
ro' = ro – 1
ro' ← ro – 1
Absolute
ro' = ABS (ro)
if (ro<0)
{ro' ← –ro}
else {ro' ← ro}
One's complement
ro' = ~ro
ro' ← ~ro
Two's complement
ro' = –ro
ro' ← –ro
Clip
ro' = CLIP (ro)
if (ro>0x007FFFFFFF)
{ro' ← 0x007FFFFFFF]
else if, (ro<0xFF80000000)
{ro' ← 0xFF80000000}
else {ro' ← ro}
Round
ro' = ROUND (ro)
if (ro>0x007FFF0000)
{ro' ← 0x007FFF0000}
else if, (ro>0xFF80000000)
{ro' ← 0xFF80000000}
else {ro' ←
(ro + 0x8000) & 0xFFFFFF0000}
Exponent
ro' = EXP (ro)
ro' ← log2
Substitution
ro' = ro
ro' ← ro
TRI.
DYAD. MONAD.
Load/
store
TRANS.
IMM.
Flag
BR. LOOP.
CTL. OV
Dyadic
↔ ↔
↔
↔
Preliminary Data Sheet
Monadic
µPD77019-013
↔
1
)
ro
↔
(
Concurrent Writing Processing
Name
Operation
ro'+ = ro
ro' ← ro'+ro
Degression
ro'– = ro
ro' ← ro'–ro
Division
ro'/ = ro
if (sign(ro')==sign(ro))
{ro' ← (ro'–ro)<<1}
else
{ro' ← (ro'+ro)<<1}
if (sign(ro')==0
{ro' ← ro'+1}
Parallel load/store
Note 1, Note 2
ro=∗dpx_mod ro'=∗dpy_mod
ro ← ∗dpx, ro' ← ∗dpy
ro=∗dpx_mod ∗dpy_mod=rh
ro ← ∗dpx, ∗dpy ← rh
∗dpx_mod=rh ro=∗dpy_mod
∗dpx ← rh, ro ← ∗dpy
∗dpx_mod=rh ∗dpy_mod=rh'
∗dpx ← rh, ∗dpy ← rh'
dest=∗dpx_mod dest'=∗dpy_mod
dest ← ∗dpx, dest' ← ∗dpy
dest=∗dpx_mod ∗dpy_mod=source
dest ← ∗dpx, ∗dpy ← source
∗dpx_mod=source dest=∗dpy_mod
∗dpx ← source, dest ← ∗dpy
∗dpx_mod=source ∗dpy_mod=source'
∗dpx ← source, ∗dpy ← source'
DYAD. MONAD.
Load/
store
TRANS.
IMM.
BR. LOOP.
CTL. OV
↔
Preliminary Data Sheet
Cumulation
TRI.
Flag
↔ ↔
Monadic
Mnemonic
Load/store
Section load/store
Note 1, Note 2, Note 3
Notes 1.
One or both of a mnemonic pair can be written.
2.
After execution of load/store, data is modified by mod.
3.
One of following mnemonic should be selected: dest, dest' = {ro, reh, re, rh, rl}, source, source' = {re, rh, rl}.
µPD77019-013
29
30
Concurrent Writing Processing
Name
Direct addressing
load/store
Note 1
Mnemonic
Operation
dest = ∗addr
dest ← ∗addr
∗addr = source
∗addr ← source
dest = ∗dp_imm
dest ← ∗dp
∗dp_imm = source
∗dp ← source
dest = rl
dest ← rl
rl = source
rl ← source
rl = imm
(provided imm = 0-0xFFFF)
rl ← imm
dp = imm
(provided imm = 0-0xFFFF)
dp ← imm
dn = imm
(provided imm = 0-0xFFFF)
dn ← imm
dm = imm
(provided imm = 1-0xFFFF)
dm ← imm
TRI.
DYAD. MONAD.
Load/
store
TRANS.
IMM.
Flag
BR. LOOP.
CTL. OV
Load/store
Immediate index
load/store
Note 2
Inter-register
transfer
Inter-register transfer
Note 3
Immediate data set
Preliminary Data Sheet
Immediate
data set
Notes 1.
One of following mnemonic should be selected: dest = {ro, reh, re, rh, rl}, source = {re, rh, rl}, add =
2.
One of following mnemonic should be selected: dest = {ro, reh, re, rh, rl}, source = {re, rh, rl}.
3.
Any register except general registers should be selected as dest or source.
0: X-0xFFFF:X memory
0: Y-0xFFFF:Y memory
.
µPD77019-013
Concurrent Writing Processing
Name
Branch
Mnemonic
Operation
Preliminary Data Sheet
Jump
JMP imm
PC ← imm
Inter-register indirect jump
JMP dp
PC ← dp
Subroutine call
CALL imm
SP ← SP + 1
STK ← PC + 1
PC ← imm
Inter-register indirect
subroutine call
CALL dp
SP ← SP + 1
STK ← PC + 1
PC ← dp
Return
RET
PC ← STK
SP ← SP – 1
Return from interrupt
RETI
PC ← STK
STK ← SP – 1 Restore the
interrupt enable flag
Repeat
REP count
start
repeat
end
Loop
Hardware
loop
LOOP count
(Mnemonics more than two lines)
start
repeat
end
DYAD. MONAD.
Load/
store
TRANS.
IMM.
BR. LOOP.
CTL. OV
RC ← count
RF ← 0
PC ← PC
RC ← RC – 1
PC ← PC + 1
RF ← 1
RC ← count
RF ← 0
PC ← PC
RC ← RC – 1
PC ← PC + 1
RF ← 1
31
Loop pop
LPOP
LC ← LSR3
LE ← LSR2
LS ← LSR1
LSP ← LSP–1
No operation
NOP
PC ← PC + 1
Halt
HALT
CPU stop
Stop
STOP
CPU, PLL, OSC Stop
If
IF (ro cond)
Conditional judge
Forget interrupt
FINT
Forget interrupt requests
Note1
Note2
µPD77019-013
Control
TRI.
Flag
µPD77019-013
Notes 1.
The HALT instruction causes all function except for clock and PLL to halt. The system is placed in much
less power consumption mode.
The contents of internal registers and memories are maintained.
HALT is released by interrupt input. It takes several system clock to recover.
2.
The STOP instruction causes all function including clock and PLL to stop. The system is placed in a
minimum-power consumption mode.
The contents of internal registers and memories are not maintained.
After the STOP instruction is executed, pin status is maintained.
STOP is released by hardware reset. It takes a few ms to recover.
32
Preliminary Data Sheet
µPD77019-013
4. ELECTRICAL SPECIFICATIONS
Absolute Maximum Ratings (TA = +25 ˚C)
Parameters
Symbol
Conditions
Ratings
Unit
–0.5 to +4.6
V
–0.5 to +4.1
V I < V DD +0.5 V
V
Power supply voltage
V DD
Input voltage
VI
Output voltage
VO
–0.5 to +4.6
V
Storage temperature
T stg
–65 to +150
˚C
Operating ambient temperature
TA
–40 to +85
˚C
Caution
2.7 V ≤ V DD ≤ 3.6 V
Exposure to Absolute Maximum Ratings for extended periods may affect device reliability;
exceeding the ratings could cause permanent damage. The parameters apply independently.
The device should be operated within the limits specified under DC and AC Characteristics.
Recommended Operating Conditions
Parameters
Operating voltage
Symbol
V DD
Input voltage
Conditions
MIN.
TYP.
MAX.
Unit
t cC ≥ 20.0 ns
2.7
3.0
3.6
V
t cC ≥ 16.6 ns
3.0
3.3
3.6
V
V DD
V
MAX.
Unit
VI
0
Capacitance (TA = +25 ˚C, VDD = 0 V)
Parameters
Symbol
Input capacitance
CI
Output capacitance
CO
Input/output capacitance
C IO
Conditions
f = 1 MHz
Unmeasured pins returned to
0 V.
Preliminary Data Sheet
MIN.
TYP.
10
pF
10
pF
10
pF
33
µPD77019-013
DC Characteristics (TA = –40 to +85 ˚C, VDD = 2.7 to 3.6 V)
Parameters
Symbol
Conditions
MIN.
TYP.
MAX.
Unit
High level input voltage
VIH
Except for X1
0.7VDD
VDD
V
High level X1 input voltage
VIHC
X1 input
0.8VDD
VDD
V
Low level input voltage
VIL
0
0.2VDD
V
High level output voltage
VOH
IOH = –2.0 mA
0.7VDD
V
IOH = –100 µA
0.8VDD
V
Low level output voltage
VOL
IOL = 2.0 mA
High level input leak current
ILIH
Low level input leak current
Pull-up pin current
Power supply current
0.2VDD
V
Except for TDI, TMS, VI = VDD
10
µA
ILIL
Except for TDI, TMS, VI = 0 V
–10
µA
IPI
TDI, TMS, 0 V ≤ VI ≤ VDD
–250
µA
IDD
Active mode, tcC = 25 ns,
VIH = VDD, VIL = 0 V, no load
TBD
IDDH
HALT mode, tcC = 200 ns,
VIH = VDD, VIL = 0 V, no load
IDDS
STOP mode, TA = +60°C, VIH = VDD, VIL = 0 V,
150
Note 1
mA
15Note 2
mA
100
µA
no load
Notes 1. The MAX. value is measured when a special program that MAX. switching required is executed, and VDD
= 3.6 V condition.
You can convert by each operation frequency f[MHz] on by each power supply VDD[V].
Max. current value (TA = +25°C) = (1.40 × VDD – 1.74) × f + 18 [mA]
2. This value is measured when VDD = 3.6 V condition.
You can convert by each operation frequency f[MHz] on by each power supply VDD[V].
HALT current value (TA = +25°C) = (0.17 × VDD – 0.38) × f + 5.9 [mA]
AC Timing Test Points
0.8VDD
0.5VDD
0.2VDD
Test points
0.8VDD
0.5VDD
0.2VDD
Input (except for X1)
0.7VDD
0.45VDD
0.2VDD
Test points
0.7VDD
0.45VDD
0.2VDD
Output
0.7VDD
0.45VDD
0.2VDD
Test points
0.7VDD
0.45VDD
0.2VDD
X1
34
Preliminary Data Sheet
µPD77019-013
AC Characteristics (T A = –40 to +85 ˚C, V DD = 2.7 to 3.6 V)
Clock
Required Timing Condition (V DD = 2.7 V to 3.6 V)
Parameters
Symbol
Conditions
PLL multiple rate: 4 (fixed)
MIN.
TYP.
MAX.
Unit
80
160
ns
CLKIN cycle time
t cCX
CLKIN high level width
t wCXH
8
t cCX – 8
– 2t rfCXNote
ns
CLKIN low level width
t wCXL
8
t cCX – 8
– 2t rfCXNote
ns
CLKIN rise/fall time
t rfCX
15
ns
MAX.
Unit
66.6
160
ns
Note 0.5t cCX – t rfCX ≥ 8 (MIN.)
Required Timing Condition (V DD = 3.0 V to 3.6 V)
Parameters
Symbol
Conditions
PLL multiple rate: 4 (fixed)
MIN.
TYP.
CLKIN cycle time
t cCX
CLKIN high level width
t wCXH
6.5
t cCX – 6.5
– 2t rfCXNote
ns
CLKIN low level width
t wCXL
6.5
t cCX – 6.5
– 2t rfCXNote
ns
CLKIN rise/fall time
t rfCX
15
ns
MAX.
Unit
Note 0.5t cCX – t rfCX ≥ 6.5 (MIN.)
Switching Characteristics
Parameters
Internal clock cycle time
Symbol
tcC
CLKOUT cycle time
tcCO
CLKOUT level width
twCO
CLKOUT rise/fall time
trfCO
Conditions
MIN.
TYP.
Active mode
tcCX/NNote
ns
HALT mode
8tcCX/NNote
ns
tcC
ns
0.5tcCO – 5
ns
5
ns
Note N: PLL multiple rate (N = 4)
Preliminary Data Sheet
35
µPD77019-013
Reset, Interrupt
Required Timing Condition
Parameters
RESET low level width
RESET recovery time
Symbol
t W(RL)
Conditions
MIN.
MAX.
Unit
External clock is input,
at power on or STOP mode
µs
Active mode or HALT mode
4t cC Note 2
ns
4t cC
ns
ns
ns
t rec(R)
INT1-INT4 low level width
t W(INTL)
3t cC Note 2
INT1-INT4 recovery time
t rec(INT)
3t cC
Notes 1.
TYP.
100 Note 1
The t w(RL) indicates a time between oscillator starts to provide clock and PLL becomes stable. The
t w(RL) depends on the rating of oscillator. At power on, the t w(RL) is measured after the point that power
supply voltage reaches to 2.7V.
2.
36
Note that, during HALT mode, t cC is extended to 8 times as long as that of Active mode.
Preliminary Data Sheet
µPD77019-013
Clock Input/Output Timing
tcCX
twCXH
trfCX
trfCX
trfCO
trfCO
twCXL
X1
tcC
Internal clock
tcCO
twCO
twCO
CLKOUT
Reset Timing
tw(RL)
trec(R)
RESET
Interrupt Timing
trec(INT)
tw(INTL)
INT1 - INT4
Preliminary Data Sheet
37
µPD77019-013
External Data Memory Access
Required Timing Condition
Parameters
Symbol
Conditions
MIN.
TYP.
MAX.
Unit
Read data setup time
t suDDRD
15
ns
Read data hold time
t hDDRD
0
ns
WAIT setup time
t suWA
12
ns
WAIT hold time
t hWA
0
ns
Switching Characteristics
Parameters
Symbol
Address output delay time
t dDA
Address output hold time
t hDA
MRD output delay time
t dDR
MRD hold time
t hDR
Write data output valid time
t vDDWD
Write data output hold time
t hDDWD
MWR output delay time
Conditions
MIN.
TYP.
MAX.
Unit
8
ns
0
ns
8
0
ns
ns
16
ns
0
ns
tdDW
0.25t cC – 5
ns
MWR setup time
t suDW
0
ns
MWR low level width
t wDWL
0.5t cC – 3
+ t cDW Note
ns
MWR high level width
t wDWH
0.5t cC – 5
ns
Note t cDW : Data wait cycle
External Data Memory Access Timing (Read)
CLKOUT
tdDA
thDA
DA0 DA13,
X/Y
tsuDDRD
thDDRD
D0 - D15
thDR
tdDR
MRD
tsuWA
thWA
tsuWA
WAIT
38
Preliminary Data Sheet
thWA
External Data Memory Access Timing (Write)
CLKOUT
tdDA
thDA
tvDDWD
tvDDWD
DA0 - DA13,
X/Y
Preliminary Data Sheet
D0 - D15
Hi-Z
thDDWD
Hi-Z
tdDW
tsuDW
twDWL
twDWH
MWR
tsuWA
tsuWA
thWA
39
µPD77019-013
WAIT
thWA
µPD77019-013
Bus Arbitration
Required Timing Condition
Parameters
Symbol
Conditions
MIN.
TYP.
MAX.
Unit
HOLDRQ setup time
t suHRQ
12
ns
HOLDRQ hold time
t hHRQ
0
ns
Switching Characteristics
Parameters
Symbol
Conditions
MIN.
TYP.
MAX.
BSTB hold time
t hBS
BSTB output delay time
t dBS
12
ns
HOLDAK output delay time
t dHAK
12
ns
Data hold time when bus arbitration
t h(BS-D)
30
ns
Data valid time after bus arbitration
t v(BS-D)
15
ns
40
Preliminary Data Sheet
0
Unit
ns
Bus Arbitration Timing (Bus idle)
CLKOUT
(Bus busy)
Bus idle
thBS
Bus release
Bus idle
(Bus busy)
tdBS
Preliminary Data Sheet
BSTB
thHRQ
tsuHRQ
tsuHRQ
thHRQ
HOLDRQ
tdHAK
tdHAK
HOLDAK
th(BS-D)
X/Y, DA0 - DA13,
MRD, MWR
tv(BS-D)
Hi-Z
µPD77019-013
41
42
Bus Arbitration Timing (Bus busy)
CLKOUT
(Bus busy)
Bus busy
Bus idle
Preliminary Data Sheet
thBS
Bus release
Bus idle
(Bus busy)
tdBS
BSTB
tsuHRQ
tsuHRQ
thHRQ
thHRQ
HOLDRQ
tdHAK
tdHAK
HOLDAK
th(BS-D)
X/Y, DA0 - DA13,
tv(BS-D)
Hi-Z
MRD, MWR
µPD77019-013
µPD77019-013
Serial Interface
Required Timing Condition
Parameters
Symbol
Conditions
MIN.
TYP.
MAX.
Unit
SCK input cycle time
t cSC
2t cC
ns
SCK input high/low level width
t wSC
25
ns
SCK input rise/fall time
t rfSC
SOEN recovery time
t recSOE
20
ns
SOEN hold time
t hSOE
0
ns
SIEN recovery time
t recSIE
20
ns
SIEN hold time
t hSIE
0
ns
SI setup time
t suSI
20
ns
SI hold time
t hSI
0
ns
20
ns
Switching Characteristics
Parameters
Symbol
SORQ output delay time
t dSOR
SORQ hold time
t hSOR
SO valid time
t vSO
SO hold time
t hSO
SIAK output delay time
t dSIA
SIAK hold time
t hSIA
Conditions
MIN.
TYP.
MAX.
Unit
30
ns
0
ns
30
0
ns
ns
30
0
ns
ns
Notes for Serial Clock
Serial clock inputs SCK1 and SCK2 are sensitive to any kind of interfering signals (noise on power supply,
induced voltage, etc.). Spurious signals can cause malfunction of the device. Special care for the serial clock
design should be taken. Careful grounding, decoupling and short wiring of SCK1 and SCK2 are recommended.
Intersection of SCK1 and SCK2 with other serial interface lines or close wiring to lines carrying high frequency
signals or large changing currents should be avoided.
It considers for the serial clock to make a waveform stable especially about the rising and falling.
Example 1. good example
Straight rising form and falling
form
Example 2. no good example
It doesn’t bound. It doesn’t make
noise one above another.
Preliminary Data Sheet
Example 3. no good example
It doesn’t make a stair stepping.
43
44
Serial Output Timing 1
tcSC
twSC
trfSC
trfSC
twSC
SCK1,
SCK2
tdSOR
thSOR
SORQ1
trecSOE
trecSOE
Preliminary Data Sheet
thSOE
thSOE
SOEN1,
SOEN2
tvSO
SO1,
SO2
Hi-Z
thSO
tvSO
1st
Last
Hi-Z
µPD77019-013
Serial Output Timing 2 (Continual output)
tcSC
twSC
trfSC
trfSC
twSC
SCK1,
SCK2
thSOR
tdSOR
SORQ1
trecSOE
Preliminary Data Sheet
thSOE
SOEN1,
SOEN2
tvSO
SO1,
SO2
Last
thSO
1st
Last
Hi-Z
µPD77019-013
45
46
Serial Input Timing 1
tcSC
twSC
trfSC
trfSC
twSC
SCK1,
SCK2
tdSIA
thSIA
SIAK1
Preliminary Data Sheet
trecSIE
trecSIE
SIEN1,
SIEN2
thSIE
thSIE
tsuSI
SI1,
SI2
thSI
1st
2nd
3rd
µPD77019-013
Serial Input Timing 2 (Continual input)
tcSC
twSC
trfSC
trfSC
twSC
SCK1,
SCK2
tdSIA
thSIA
SIAK1
Preliminary Data Sheet
trecSIE
thSIE
SIEN1,
SIEN2
tsuSI
SI1,
SI2
Last–1
Last
thSI
1st
2nd
3rd
µPD77019-013
47
µPD77019-013
Host Interface
Required Timing Condition
Parameters
Symbol
Conditions
MIN.
TYP.
MAX.
Unit
HRD delay time
t dHR
0
ns
HRD width
t wHR
2t cC
ns
HCS, HA0, HA1 read hold time
t hHCAR
0
ns
HCS, HA0, HA1 write hold time
t hHCAW
0
ns
HRD, HWR recovery time
t recHS
2t cC
ns
HWR delay time
tdHW
0
ns
HWR width
t wHW
2t cC
ns
HWR hold time
t hHDW
0
ns
HWR setup time
t suHDW
20
ns
Switching Characteristics
Parameters
Symbol
Conditions
MIN.
TYP.
MAX.
Unit
HRE, HWE output delay time
t dHE
30
ns
HRE, HWE hold time
t hHE
30
ns
HRD valid time
t vHDR
30
ns
HRD hold time
t hHDR
48
Preliminary Data Sheet
0
ns
Host Interface Timing (Read)
CLKOUT
HCS, HA0, HA1
thHCAR
Preliminary Data Sheet
tdHR
twHR
trecHS
HRD
thHDR
tvHDR
Hi-Z
HD0 - HD7
tdHE
Hi-Z
thHE
HRE
µPD77019-013
49
50
Host Interface Timing (Write)
CLKOUT
HCS, HA0, HA1
thHCAW
Preliminary Data Sheet
tdHW
twHW
trecHS
HWR
thHDW
tsuHDW
HD0 - HD7
tdHE
thHE
HWE
µPD77019-013
µPD77019-013
General Input/Output Ports
Required Timing Condition
Parameters
Symbol
Conditions
MIN.
TYP.
MAX.
Unit
Port input setup time
t suPI
20
ns
Port input hold time
t hPI
10
ns
Switching Characteristics
Parameters
Port output delay time
Symbol
Conditions
MIN.
0
t dPO
TYP.
MAX.
Unit
30
ns
General Input/Output Ports Timing
CLKOUT
tdPO
P0 - P3
(Output)
tsuPI
thPI
P0 - P3
(Input)
Preliminary Data Sheet
51
µPD77019-013
Debugging Interface (JTAG)
Required Timing Condition
Parameters
Symbol
Conditions
MIN.
TYP.
MAX.
Unit
TCK cycle time
t cTCK
4t cC
ns
TCK high/low level width
t wTCK
50
ns
TCK rise/fall time
t rfTCK
TMS, TDI setup time
t suDI
10
ns
TMS, TDI hold time
t hDI
0
ns
Input pin setup time
t suJIN
10
ns
Input pin hold time
t hJIN
0
ns
20
ns
Switching Characteristics
Parameters
Symbol
Conditions
MIN.
TYP.
MAX.
Unit
TDO output delay time
t dDO
30
ns
Output pin output delay time
t dJOUT
30
ns
Debugging Interface Timing
tcTCK
twTCK
trfTCK
twTCK
trfTCK
TCK
tsuDI
TMS,
TDI
thDI
Valid
Valid
tdDO
TDO
tsuJIN
Capture
state
thJIN
Valid
tdJOUT
Update
state
Remark For the details of JTAG, refer to “IEEE1149.1.”
52
Preliminary Data Sheet
Valid
µPD77019-013
5. PACKAGE DRAWING
100 PIN PLASTIC TQFP (FINE PITCH) (
14)
A
B
75
76
51
50
F
100
1
G
R
Q
S
D
C
detail of lead end
26
25
H
I
M
J
M
P
K
N
L
NOTE
Each lead centerline is located within 0.10 mm (0.004 inch) of
its true position (T.P.) at maximum material condition.
ITEM
A
MILLIMETERS
16.0±0.2
INCHES
0.630±0.008
B
14.0±0.2
0.551 +0.009
–0.008
C
14.0±0.2
0.551 +0.009
–0.008
D
16.0±0.2
0.630±0.008
F
G
1.0
1.0
0.039
0.039
H
0.22 +0.05
–0.04
0.009±0.002
I
0.10
0.004
J
0.5 (T.P.)
0.020 (T.P.)
K
1.0±0.2
0.039 +0.009
–0.008
L
0.5±0.2
0.020 +0.008
–0.009
M
0.145 +0.055
–0.045
0.006±0.002
N
0.10
0.004
P
1.0±0.1
0.039 +0.005
–0.004
Q
0.1±0.05
0.004±0.002
R
3° +7°
–3°
3° +7°
–3°
S
1.27 MAX.
0.050 MAX.
S100GC-50-9EU-1
Preliminary Data Sheet
53
µPD77019-013
6. RECOMMENDED SOLDERING CONDITIONS
When soldering this product, it is highly recommended to observe the conditions as shown below. If other
soldering processes are used, or if the soldering is performed under different conditions, please make sure to
consult with our sales offices.
For more details, refer to our document “SEMICONDUCTOR DEVICE MOUNTING TECHNOLOGY MANUAL”
(C10535E).
Surface Mount Device
µ PD77019GC-013-9EU: 100-pin plastic TQFP (FINE PITCH) (14 × 14mm)
Process
Infrared ray reflow
Conditions
Peak temperature: 235 ˚C or below (Package surface temperature),
Symbol
IR35-103-2
Reflow time: 30 seconds or less (at 210 ˚C or higher),
Maximum number of reflow processes : 2 times,
Exposure limit Note : 3 days (10 hours pre-baking is required at 125 ˚C
afterwards).
Vapor Phase Soldering
Peak temperature: 215 ˚C or below (Package surface temperature),
VP15-103-2
Reflow time: 40 seconds or less (at 200 ˚C or higher),
Maximum number of reflow processes : 2 times,
Exposure limit Note : 3 days (10 hours pre-baking is required at 125 °C
afterwards).
Partial heating method
Pin temperature : 300 ˚C or below,
Heat time : 3 seconds or less (Per each side of the device)
Note
Maximum allowable time from taking the soldering package out of dry pack to soldering.
Storage conditions: 25 °C and relative humidity of 65 % or less.
Caution
Apply only one kind of soldering condition to a device, except for “partial heating method”,
or the device will be damaged by heat stress.
54
Preliminary Data Sheet
µPD77019-013
NOTES FOR CMOS DEVICES
1 PRECAUTION AGAINST ESD FOR SEMICONDUCTORS
Note: Strong electric field, when exposed to a MOS device, can cause destruction
of the gate oxide and ultimately degrade the device operation. Steps must
be taken to stop generation of static electricity as much as possible, and
quickly dissipate it once, when it has occurred. Environmental control must
be adequate. When it is dry, humidifier should be used. It is recommended
to avoid using insulators that easily build static electricity. Semiconductor
devices must be stored and transported in an anti-static container, static
shielding bag or conductive material.
All test and measurement tools
including work bench and floor should be grounded. The operator should
be grounded using wrist strap. Semiconductor devices must not be touched
with bare hands. Similar precautions need to be taken for PW boards with
semiconductor devices on it.
2 HANDLING OF UNUSED INPUT PINS FOR CMOS
Note: No connection for CMOS device inputs can be cause of malfunction. If no
connection is provided to the input pins, it is possible that an internal input
level may be generated due to noise, etc., hence causing malfunction. CMOS
devices behave differently than Bipolar or NMOS devices. Input levels of
CMOS devices must be fixed high or low by using a pull-up or pull-down
circuitry.
Each unused pin should be connected to VDD or GND with a
resistor, if it is considered to have a possibility of being an output pin. All
handling related to the unused pins must be judged device by device and
related specifications governing the devices.
3 STATUS BEFORE INITIALIZATION OF MOS DEVICES
Note: Power-on does not necessarily define initial status of MOS device. Production
process of MOS does not define the initial operation status of the device.
Immediately after the power source is turned ON, the devices with reset
function have not yet been initialized. Hence, power-on does not guarantee
out-pin levels, I/O settings or contents of registers. Device is not initialized
until the reset signal is received. Reset operation must be executed immediately after power-on for devices having reset function.
Preliminary Data Sheet
55
µPD77019-013
[MEMO]
No part of this document may be copied or reproduced in any form or by any means without the prior written
consent of NEC Corporation. NEC Corporation assumes no responsibility for any errors which may appear in
this document.
NEC Corporation does not assume any liability for infringement of patents, copyrights or other intellectual property
rights of third parties by or arising from use of a device described herein or any other liability arising from use
of such device. No license, either express, implied or otherwise, is granted under any patents, copyrights or other
intellectual property rights of NEC Corporation or others.
While NEC Corporation has been making continuous effort to enhance the reliability of its semiconductor devices,
the possibility of defects cannot be eliminated entirely. To minimize risks of damage or injury to persons or
property arising from a defect in an NEC semiconductor device, customers must incorporate sufficient safety
measures in its design, such as redundancy, fire-containment, and anti-failure features.
NEC devices are classified into the following three quality grades:
"Standard", "Special", and "Specific". The Specific quality grade applies only to devices developed based on a
customer designated "quality assurance program" for a specific application. The recommended applications of
a device depend on its quality grade, as indicated below. Customers must check the quality grade of each device
before using it in a particular application.
Standard: Computers, office equipment, communications equipment, test and measurement equipment,
audio and visual equipment, home electronic appliances, machine tools, personal electronic
equipment and industrial robots
Special: Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster
systems, anti-crime systems, safety equipment and medical equipment (not specifically designed
for life support)
Specific: Aircrafts, aerospace equipment, submersible repeaters, nuclear reactor control systems, life
support systems or medical equipment for life support, etc.
The quality grade of NEC devices is "Standard" unless otherwise specified in NEC's Data Sheets or Data Books.
If customers intend to use NEC devices for applications other than those specified for Standard quality grade,
they should contact an NEC sales representative in advance.
Anti-radioactive design is not implemented in this product.
M4 96.5