ETC UPD780053GK-XXX-9EU

DATA SHEET
MOS INTEGRATED CIRCUIT
µPD780053,780054,780055,780056,780058
780053Y, 780054Y,780055Y,780056Y
8-BIT SINGLE-CHIP MICROCONTROLLERS
DESCRIPTION
The µPD780053, 780054, 780055, 780056, and 780058 (hereafter, referred to as µPD78005x) are products of the
µPD780058 Subseries in the 78K/0 Series. The µPD780053Y , 780054Y, 780055Y, and 780056Y (hereafter referred
to as µPD78005xY) are products of the µPD780058Y Subseries in the 78K/0 Series.
These microcontrollers show a reduction in the EMI (Electro Magnetic Interference) noise generated internally
compared to the conventional type, the µPD78054 Subseries. Also they have provided is an 8-bit resolution A/D
converter, 8-bit resolution D/A converter, timers, serial interfaces, real-time output ports, interrupt functions, and
various other peripheral hardware.
The µPD780058Y Subseries is based on the µPD780058 Subseries but with the addition of an I2C bus interface
function supporting multi-master.
Flash memory versions, the µPD78F0058 and 78F0058Y and various development tools are also available.
Detailed function descriptions are provided in the following user’s manuals. Be sure to read them before
designing.
µPD780058, 780058Y Subseries User’s Manual: U12013E
78K/0 Series User’s Manual - Instruction:
U12326E
FEATURES
• Internal high-capacity ROM & RAM
Item
Program Memory
Part Number
•
•
•
•
•
•
•
•
(ROM)
µPD780053, 780053Y
24 KB
µPD780054, 780054Y
32 KB
µPD780055, 780055Y
40 KB
µPD780056, 780056Y
48 KB
µPD780058
60 KB
Data Memory
Internal High-Speed RAM
Internal Buffer RAM
1,024 bytes
32 bytes
Internal Expansion RAM
None
1,024 bytes
External memory expansion space: 64 KB
Minimum instruction execution time can be changed from high-speed (0.4 µs) to ultra-low-speed (122 µs)
I/O ports: 68 (N-ch open-drain: 4)
8-bit resolution A/D converter: 8 channels (VDD = 1.8 to 5.5 VNote)
8-bit resolution D/A converter: 2 channels (VDD = 1.8 to 5.5 VNote)
Serial interface:
3 channels
Timer:
5 channels
Supply voltage:
VDD = 1.8 to 5.5 V
Note The operation voltage of the A/D converter and D/A converter of the µPD780058 is VDD = 2.7 to 5.5 V.
The information in this document is subject to change without notice. Before using this document, please
confirm that this is the latest version.
Not all devices/types available in every country. Please check with local NEC representative for
availability and additional information.
Document No. U12182EJ3V0DS00 (3rd edition)
Date Published March 2001 N CP(K)
Printed in Japan
The mark
shows major revised points.
©
1997, 2001
µPD780053, 780054, 780055, 780056, 780058, 780053Y, 780054Y, 780055Y, 780056Y
APPLICATIONS
Car audio systems, cellular phones, pagers, printers, AV equipment, cameras, PPCs, vending machines, etc.
ORDERING INFORMATION
Part Number
µPD780053GC-×××-8BT
80-pin plastic QFP (14 × 14)
µPD780053GK-×××-9EU
80-pin plastic TQFP (fine pitch) (12 × 12)
µPD780054GC-×××-8BT
80-pin plastic QFP (14 × 14)
µPD780054GK-×××-9EU
80-pin plastic TQFP (fine pitch) (12 × 12)
µPD780055GC-×××-8BT
80-pin plastic QFP (14 × 14)
µPD780055GK-×××-9EU
80-pin plastic TQFP (fine pitch) (12 × 12)
µPD780056GC-×××-8BT
80-pin plastic QFP (14 × 14)
µPD780056GK-×××-9EU
80-pin plastic TQFP (fine pitch) (12 × 12)
µPD780058GC-×××-8BT
80-pin plastic QFP (14 × 14)
µPD780058GK-×××-9EU
80-pin plastic TQFP (fine pitch) (12 × 12)
µPD780053YGC-×××-8BT
80-pin plastic QFP (14 × 14)
µPD780053YGK-×××-9EU
80-pin plastic TQFP (fine pitch) (12 × 12)
µPD780054YGC-×××-8BT
80-pin plastic QFP (14 × 14)
µPD780054YGK-×××-9EU
80-pin plastic TQFP (fine pitch) (12 × 12)
µPD780055YGC-×××-8BT
80-pin plastic QFP (14 × 14)
µPD780055YGK-×××-9EU
80-pin plastic TQFP (fine pitch) (12 × 12)
µPD780056YGC-×××-8BT
80-pin plastic QFP (14 × 14)
µPD780056YGK-×××-9EU
80-pin plastic TQFP (fine pitch) (12 × 12)
Remark
2
Package
××× indicates ROM code suffix.
Data Sheet U12182EJ3V0DS
µPD780053, 780054, 780055, 780056, 780058, 780053Y, 780054Y, 780055Y, 780056Y
78K/0 SERIES LINEUP
The products in the 78K/0 Series are listed below. The names enclosed in boxes are subseries name.
Products in mass production
Products under development
Y subseries products are compatible with I2C bus.
Control
100-pin
100-pin
100-pin
µ PD78075B
µ PD78078
µ PD78070A
100-pin
80-pin
80-pin
µ PD780058
µ PD78058F
80-pin
µPD78054
µPD780065
64-pin
µ PD780078
64-pin
64-pin
64-pin
µ PD780034A
µ PD780024A
µPD78014H
64-pin
µPD78018F
µ PD78083
80-pin
42/44-pin
EMI-noise reduced version of the µPD78078
µPD78078Y
µ PD78054 with timer and enhanced external interface
µ PD78070AY
ROMless version of the µ PD78078
µ PD78078Y with enhanced serial I/O and limited function
µ PD780018AY
µ PD780058Y
µ PD78058FY
µ PD78054 with enhanced serial I/O
EMI-noise reduced version of the µ PD78054
µ PD78018F with UART and D/A converter, and enhanced I/O
µ PD780024A with expanded RAM
µ PD780034A with timer and enhanced serial I/O
µ PD780078Y
µ PD780034AY µ PD780024A with enhanced A/D converter
µ PD780024AY µ PD78018F with enhanced serial I/O
EMI-noise reduced version of the µ PD78018F
µ PD78054Y
µ PD78018FY
Basic subseries for control
On-chip UART, capable of operating at low voltage (1.8 V)
Inverter control
64-pin
µPD780988
On-chip inverter control circuit and UART. EMI-noise reduced.
VFD drive
78K/0
Series
100-pin
µ PD780208
µ PD78044F with enhanced I/O and VFD C/D. Display output total: 53
80-pin
µ PD780232
µPD78044H
For panel control. On-chip VFD C/D. Display output total: 53
80-pin
80-pin
µPD78044F
Basic subseries for driving VFD. Display output total: 34
µ PD78044F with N-ch open-drain I/O. Display output total: 34
LCD drive
120-pin
µ PD780338
120-pin
µ PD780328
µPD780318
µ PD780308
µPD78064B
µPD78064
120-pin
100-pin
100-pin
100-pin
µ PD780308 with enhanced display function and timer. Segment signal output: 40 pins max.
µ PD780308 with enhanced display function and timer. Segment signal output: 32 pins max.
µ PD780308 with enhanced display function and timer. Segment signal output: 24 pins max.
µPD780308Y
µ PD78064 with enhanced SIO, and expanded ROM and RAM
EMI-noise reduced version of the µ PD78064
µ PD78064Y
Basic subseries for driving LCDs, on-chip UART
Bus interface supported
100-pin
80-pin
µ PD780948
µ PD78098B
On-chip DCAN controller
µ PD78054 with IEBusTM controller. EMI-noise reduced
80-pin
µ PD780701Y
On-chip DCAN/IEBus controller
80-pin
µ PD780833Y
On-chip controller compliant with J1850 (CLASS2)
Meter control
100-pin
µPD780958
For industrial meter control
80-pin
µPD780852
µPD780824
On-chip automobile meter controller/driver
For automobile meter driver. On-chip DCAN controller
80-pin
Remark
VFD (Vacuum Fluorescent Display) is referred to as "FIPTM (Fluorescent Indicator Panel) in some
documents, but the functions of the two are the same.
Data Sheet U12182EJ3V0DS
3
µPD780053, 780054, 780055, 780056, 780058, 780053Y, 780054Y, 780055Y, 780056Y
The major functional differences among the subseries are listed below.
• Non-Y subseries
Function
Subseries Name
Control
ROM
Capacity
Timer
8-Bit 16-Bit Watch WDT A/D
µPD78075B 32 K to 40 K 4 ch
µPD78078
µPD78070A
8-Bit 10-Bit 8-Bit
1 ch
1 ch
1 ch
8 ch
A/D
–
Serial Interface
I/O
VDD External
MIN.
Value Expansion
88
1.8 V
61
2.7 V
D/A
2 ch 3 ch (UART: 1 ch)
48 K to 60 K
–
µPD780058 24 K to 60 K 2 ch
3 ch (time-division UART: 1ch)
68
1.8 V
µPD78058F 48 K to 60 K
3 ch (UART: 1ch)
69
2.7 V
µPD78054
√
16 K to 60 K
2.0 V
µPD780065 40 K to 48 K
–
µPD780078 48 K to 60 K
2 ch
µPD780034A 8 K to 32 K
1 ch
–
µPD780024A
8 ch
8 ch
4 ch (UART: 1 ch)
60
2.7 V
3 ch (UART: 2ch)
52
1.8 V
3 ch (UART: 1ch)
51
2 ch
53
1 ch (UART: 1ch)
33
–
µPD78014H
µPD78018F 8 K to 60 K
µPD78083
Inverter
8 K to 16 K
–
µPD780988 16 K to 60 K 3 ch Note
–
–
–
1 ch
–
8 ch
–
3 ch (UART: 2ch)
47
4.0 V
√
1 ch
8 ch
–
–
2 ch
74
2.7 V
–
40
4.5 V
68
2.7 V
54
1.8 V
control
VFD
drive
µPD780208 32 K to 60 K 2 ch
1 ch
1 ch
µPD780232 16 K to 24 K 3 ch
–
–
4 ch
µPD78044H 32 K to 48 K 2 ch
1 ch
1 ch
8 ch
1 ch
µPD78044F 16 K to 40 K
LCD
drive
2 ch
µPD780338 48 K to 60 K 3 ch
2 ch
1 ch
1 ch
–
10 ch 1 ch 2 ch (UART: 1ch)
µPD780328
62
µPD780318
70
µPD780308
2 ch
1 ch
8 ch
–
–
µPD78064B 32 K
µPD78064
3 ch (time-division UART: 1ch)
–
57
2.0 V
79
4.0 V
√
69
2.7 V
–
2 ch (UART: 1ch)
16 K to 32 K
Bus
µPD780948 60 K
2 ch
interface
supported µPD78098B 40 K to 60 K
1 ch
Meter
control
µPD780958 48 K to 60 K 4 ch
2 ch
–
1 ch
–
–
–
2 ch (UART: 1ch)
69
2.2 V
–
Dash
board
control
µPD780852 32 K to 40 K 3 ch
1 ch
1 ch
1 ch
5 ch
–
–
3 ch (UART: 1ch)
56
4.0 V
–
2 ch (UART: 1ch)
59
2 ch
1 ch
1 ch
8 ch
–
–
2 ch
µPD780824 32 K to 60 K
Note 16-bit timer: 2 channels
10-bit timer: 1 channel
4
3 ch (UART: 1ch)
Data Sheet U12182EJ3V0DS
µPD780053, 780054, 780055, 780056, 780058, 780053Y, 780054Y, 780055Y, 780056Y
The major functional differences among the subseries are listed below.
• Y subseries
Function
Subseries Name
Control
ROM
Timer
Capacity
8-Bit 16-Bit Watch WDT
µPD78078Y 48 K to 60 K 4 ch
µPD78070AY
1 ch
D/A
VDD External
MIN.
Value Expansion
2 ch 3 ch (UART: 1 ch, I2C: 1 ch) 88
1.8 V
61
2.7 V
8-Bit 10-Bit 8-Bit
1 ch
1 ch
A/D
A/D
8 ch
–
Serial Interface
–
µPD780018AY 48 K to 60 K
–
µPD780058Y 24 K to 60 K 2 ch
2
3 ch (I C: 1ch)
I/O
88
2
2 ch 3 ch (time-division UART: 1 ch,I C: 1 ch) 68
µPD78058FY 48 K to 60 K
2
3 ch (UART: 1 ch, I C: 1 ch)
69
µPD78054Y 16 K to 60 K
2 ch
µPD780034AY 8 K to 32 K
–
8 ch
–
1 ch
2
4 ch (UART: 2 ch, I C: 1 ch)
8 ch
1 ch
1.8 V
–
2 ch (I2C:1 ch)
µPD780308Y 48 K to 60 K 2 ch
52
3 ch (UART: 1 ch, I C: 1 ch) 51
µPD78018FY 8 K to 60 K
1 ch
1 ch
8 ch
–
–
µPD78064Y 16 K to 32 K
Remark
2.7 V
2
µPD780024AY
Bus
µPD780701Y 60 K
interface
supported µPD780833Y
1.8 V
2.0 V
µPD780078Y 48 K to 60 K
LCD
drive
√
53
2.0 V
–
67
3.5 V
–
65
4.5 V
2
3 ch (time-division UART: 1 ch,I C: 1 ch) 57
2 ch (UART: 1 ch, I2C: 1 ch)
3 ch
2 ch
1 ch
1 ch 16 ch
–
–
4 ch (UART: 1 ch, I2C: 1 ch)
Functions other than the serial interface are common to both the Y and non-Y subseries.
Data Sheet U12182EJ3V0DS
5
µPD780053, 780054, 780055, 780056, 780058, 780053Y, 780054Y, 780055Y, 780056Y
OVERVIEW OF FUNCTIONS
µPD780053
µPD780054
µPD780055
µPD780056
µPD780053Y
µPD780054Y
µPD780055Y
µPD780056Y
Product Name
Item
Internal
memory
ROM
24 KB
High-speed RAM
1,024 bytes
Buffer RAM
32 bytes
Expanded RAM
None
32 KB
40 KB
48 KB
60 KB
1,024 bytes
Memory space
64 KB
General-purpose registers
8 bits × 32 registers (8 bits × 8 registers × 4 banks)
Minimum instruction execution
time
When main system
clock is selected
When subsystem
clock is selected
On-chip minimum instruction execution time variable function
Instruction set
•
•
•
•
I/O ports
Total:
• CMOS input :
• CMOS I/O :
• N-ch open-drain I/O:
A/D converter
• 8-bit resolution × 8 channels
Operating voltage range
µPD780058
0.4 µs/0.8 µs/1.6 µs/3.2 µs/6.4 µs/12.8 µs (@5.0 MHz operation)
122 µs (@32.768 kHz operation)
16-bit operation
Multiply/divide (8 bits × 8 bits, 16 bits ÷ 8 bits)
Bit manipulation (set, reset, test, Boolean operation)
BCD adjust, etc.
68
2
62
4
VDD = 1.8 to 5.5 V
D/A converter
• 8-bit resolution × 2 channels
Operating voltage range
Serial interface
VDD = 1.8 to 5.5 V
VDD = 2.7 to 5.5
VDD = 2.7 to 5.5
Note 1 2
Note 2
/I C bus
mode selectable: 1 channel
• 3-wire serial I/O/2-wire serial I/O/SBI
• 3-wire serial I/O mode (automatic data transmit/receive function for up to 32 bytes
provided on-chip): 1 channel
• 3-wire serial I/O/UART mode (time division transfer function provided on-chip)
selectable: 1 channel
Timers
•
•
•
•
Timer outputs
3 (14-bit PWM output × 1)
Clock output
19.5 kHz, 39.1 kHz, 78.1 kHz, 156 kHz, 313 kHz, 625 kHz, 1.25 MHz, 2.5 MHz, 5.0 MHz
(@5.0 MHz operation with main system clock)
32.768 kHz (@32.768 kHz operation with subsystem clock)
Buzzer output
Vectored
interrupt
sources
16-bit timer/event counter:
8-bit timer/event counter:
Watch timer:
Watchdog timer:
1
2
1
1
channel
channels
channel
channel
1.2 kHz, 2.4 kHz, 4.9 kHz, 9.8 kHz (@5.0 MHz operation with main system clock)
Maskable
Internal: 13, External: 6
Non-maskable
Internal: 1
Software
1
Test inputs
Internal: 1, external: 1
Supply voltage
VDD = 1.8 to 5.5 V
Operating ambient temperature
TA = –40 to +85°C
Package
• 80-pin plastic QFP (14 × 14)
• 80-pin plastic TQFP (fine pitch) (12 × 12)
Notes 1. µPD78005x only
2. µPD78005xY only
6
Data Sheet U12182EJ3V0DS
µPD780053, 780054, 780055, 780056, 780058, 780053Y, 780054Y, 780055Y, 780056Y
CONTENTS
1.
PIN CONFIGURATION (TOP VIEW)...........................................................................................
8
2.
BLOCK DIAGRAM ......................................................................................................................... 10
3.
PIN FUNCTIONS ............................................................................................................................ 11
3.1
Port Pins .................................................................................................................................................. 11
3.2
Non-Port Pins ......................................................................................................................................... 13
3.3
Pin I/O Circuits and Recommended Connection of Unused Pins .................................................. 15
4.
MEMORY SPACE ........................................................................................................................... 19
5.
PERIPHERAL HARDWARE FUNCTION FEATURES ............................................................... 20
5.1
6.
Ports ......................................................................................................................................................... 20
5.2
Clock Generator ..................................................................................................................................... 21
5.3
Timer/Event Counter .............................................................................................................................. 21
5.4
Clock Output Controller ........................................................................................................................ 24
5.5
Buzzer Output Controller ...................................................................................................................... 24
5.6
A/D Converter ......................................................................................................................................... 25
5.7
D/A Converter ......................................................................................................................................... 26
5.8
Serial Interfaces ..................................................................................................................................... 27
5.9
Real-Time Output Ports ......................................................................................................................... 29
INTERRUPT AND TEST FUNCTIONS ....................................................................................... 30
6.1
Interrupt Functions ................................................................................................................................ 30
6.2
Test Functions ........................................................................................................................................ 34
7.
EXTERNAL DEVICE EXPANSION FUNCTION ......................................................................... 35
8.
STANDBY FUNCTION ................................................................................................................... 35
9.
RESET FUNCTION......................................................................................................................... 35
10. MASK OPTION ................................................................................................................................ 36
11. INSTRUCTION SET ....................................................................................................................... 37
12. ELECTRICAL SPECIFICATIONS .................................................................................................. 39
13. CHARACTERISTICS CURVES (REFERENCE VALUES) ......................................................... 69
14. PACKAGE DRAWINGS ................................................................................................................. 71
15. RECOMMENDED SOLDERING CONDITIONS ........................................................................... 73
APPENDIX A. DEVELOPMENT TOOLS .......................................................................................... 75
APPENDIX B. RELATED DOCUMENTS .......................................................................................... 78
Data Sheet U12182EJ3V0DS
7
µPD780053, 780054, 780055, 780056, 780058, 780053Y, 780054Y, 780055Y, 780056Y
1. PIN CONFIGURATION (TOP VIEW)
• 80-pin plastic QFP (14 × 14)
µPD780053GC-×××-8BT, 780054GC-×××-8BT, 780055GC-×××-8BT, 780056GC-×××-8BT, 780058GC-×××-8BT,
780053YGC-×××-8BT, 780054YGC-×××-8BT, 780055YGC-×××-8BT, 780056YGC-×××-8BT
• 80-pin plastic TQFP (fine pitch) (12 × 12)
µPD780053GK-×××-9EU, 780054GK-×××-9EU, 780055GK-×××-9EU, 780056GK-×××-9EU,
P00/INTP0/TI00
P01/INTP1/TI01
P02/INTP2
P03/INTP3
P04/INTP4
P05/INTP5
VSS0
VDD1
X2
X1
IC
XT2
XT1/P07
VDD0
AV REF0
P10/ANI0
P11/ANI1
P12/ANI2
P13/ANI3
P14/ANI4
780058GK-×××-9EU, 780053YGK-×××-9EU, 780054YGK-×××-9EU, 780055YGK-×××-9EU, 780056YGK-×××-9EU
7
54
P122/RTP2
P70/SI2/RxD0
8
53
P121/RTP1
P71/SO2/TxD0
9
52
P120/RTP0
P72/SCK2/ASCK
10
51
P37
P20/SI1
11
50
P36/BUZ
P21/SO1
12
49
P35/PCL
P22/SCK1
13
48
P34/TI2
P23/STB/TxD1
14
47
P33/TI1
P24/BUSY/RxD1
15
46
P32/TO2
P25/SI0/SB0 [/SDA 0]
16
45
P31/TO1
P26/SO0/SB1 [/SDA 1]
17
44
P30/TO0
P27/SCK0 [/SCL]
18
43
P67/ASTB
P40/AD0
19
42
P66/WAIT
P41/AD1
20
41
21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40
Cautions 1.
2.
RESET
P65/WR
P64/RD
P63
P123/RTP3
AV REF1
P62
55
P61
6
P60
P124/RTP4
P131/ANO1
P57/A15
56
P56/A14
5
VSS1
P125/RTP5
P130/ANO0
P55/A13
57
P54/A12
4
P53/A11
P126/RTP6
AV SS
P52/A10
58
P51/A9
3
P50/A8
P127/RTP7
P17/ANI7
P47/AD7
59
P46/AD6
2
P45/AD5
P16/ANI6
P44/AD4
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61
60
P43/AD3
1
P42/AD2
P15/ANI5
Connect the IC (Internally Connected) pin directly to VSS0 or VSS1.
Connect the AVSS pin to VSS0.
Remarks 1. [ ]: µPD78005xY only
2. When the microcontroller is used in applications where the noise generated inside the microcontroller
needs to be reduced, the implementation of noise reduction measures, such as supplying voltage
to VDD0 and VDD1 individually and connecting VSS0 and VSS1 to different ground lines, is recommended.
8
Data Sheet U12182EJ3V0DS
µPD780053, 780054, 780055, 780056, 780058, 780053Y, 780054Y, 780055Y, 780056Y
PIN IDENTIFICATION
A8 to A15:
Address bus
P130, P131:
Port 13
AD0 to AD7:
Address/data bus
PCL:
Programmable clock
ANI0 to ANI7:
Analog input
RD:
Read strobe
ANO0, ANO1:
Analog output
RESET:
Reset
ASCK:
Asynchronous serial clock
RTP0 to RTP7:
Real-time output port
ASTB:
Address strobe
RxD0, RxD1:
Receive data
AVREF0, AVREF1:
Analog reference voltage
SB0, SB1:
Serial bus
AVSS:
Analog ground
SCK0 to SCK2:
Serial clock
BUSY:
Busy
SCL:
Serial clock
BUZ:
Buzzer clock
SDA0, SDA1:
Serial data
IC:
Internally connected
SI0 to SI2:
Serial input
INTP0 to INTP5:
Interrupt from peripherals
SO0 to SO2:
Serial output
P00 to P05, P07:
Port 0
STB:
Strobe
P10 to P17:
Port 1
TI00, TI01:
Timer input
P20 to P27:
Port 2
TI1, TI2:
Timer input
P30 to P37:
Port 3
TO0 to TO2:
Timer output
P40 to P47:
Port 4
TxD0, TxD1:
Transmit data
P50 to P57:
Port 5
VDD0, VDD1:
Power supply
P60 to P67:
Port 6
VSS0, VSS1:
Ground
P70 to P72:
Port 7
WAIT:
Wait
P120 to P127:
Port 12
WR:
Write strobe
X1, X2:
Crystal (main system clock)
XT1, XT2:
Crystal (subsystem clock)
Data Sheet U12182EJ3V0DS
9
µPD780053, 780054, 780055, 780056, 780058, 780053Y, 780054Y, 780055Y, 780056Y
2. BLOCK DIAGRAM
TO0/P30
TI00/INTP0/P00
TI01/INTP1/P01
16-bit timer/
event counter
TO1/P31
TI1/P33
8-bit timer/
event counter 1
TO2/P32
TI2/P34
8-bit timer/
event counter 2
Port 0
P00
P01 to P05
P07
Port 1
P10 to P17
Port 2
P20 to P27
Port 3
P30 to P37
Port 4
P40 to P47
Port 5
P50 to P57
Port 6
P60 to P67
Port 7
P70 to P72
Port 12
P120 to P127
Port 13
P130, P131
Watchdog timer
Watch timer
SI0/SB0[/SDA0]/P25
SO0/SB1[/SDA1]/P26
SCK0[/SCL]/P27
Serial
interface 0
78K/0
CPU core
SI1/P20
SO1/P21
SCK1/P22
STB/TxD1/P23
BUSY/RxD1/P24
Serial
interface 1
BUSY/RxD1/P24
STB/TxD1/P23
SI2/RxD0/P70
SO2/TxD0/P71
SCK2/ASCK/P72
Serial
interface 2
ROM
RAM
ANI0/P10 to
ANI7/P17
AV SS
AVREF0
ANO0/P130,
ANO1/P131
AV SS
Real-time
output port
A/D converter
D/A converter
External access
AD0/P40 to
AD7/P47
A8/P50 to
A15/P57
RD/P64
WR/P65
WAIT/P66
ASTB/P67
System control
RESET
X1
X2
XT1/P07
XT2
AV REF1
INTP0/P00 to
INTP5/P05
Interrupt
control
BUZ/P36
Buzzer output
PCL/P35
Clock output
control
VDD0,
VDD1
VSS0,
VSS1
IC
Remarks 1. The internal ROM and RAM capacity varies depending on the product.
2. [ ]: µPD78005xY only
10
Data Sheet U12182EJ3V0DS
RTP0/P120 to
RTP7/P127
µPD780053, 780054, 780055, 780056, 780058, 780053Y, 780054Y, 780055Y, 780056Y
3. PIN FUNCTIONS
3.1 Port Pins (1/2)
Pin Name
Function
I/O
P00
Input
P01
I/O
Port 0
7-bit I/O port
P02
After
Reset
Alternate
Function
Input only
Input
INTP0/TI00
Input/output can be specified in 1-bit units.
When used as an input port, an on-chip pull-up
resistor can be specified by software.
Input
INTP1/TI01
INTP2
P03
INTP3
P04
INTP4
P05
INTP5
P07Note 1
Input
Input only
Input
XT1
P10 to P17
I/O
Port 1
8-bit I/O port.
Input/output can be specified in 1-bit units.
When used as an input port, an on-chip pull-up resistor can be
specified by softwareNote 2.
Input
ANI0 to ANI7
P20
I/O
Port 2
8-bit I/O port.
Input/output can be specified in 1-bit units.
When used as an input port, an on-chip pull-up resistor can be
specified by software.
Input
SI1
P21
P22
P23
SO1
SCK1
STB/TxD1
P24
BUSY/RxD1
P25
SI0/SB0[/SDA0]
P26
SO0/SB1[/SDA1]
P27
SCK0 [/SCL]
I/O
P30
P31
P32
P33
Port 3
8-bit I/O port.
Input/output can be specified in 1-bit units.
When used as an input port, an on-chip pull-up resistor can be specified
by software.
Input
TO0
TO1
TO2
TI1
P34
TI2
P35
PCL
P36
BUZ
P37
–
P40 to P47
I/O
Port 4
8-bit I/O port.
Input/output can be specified in 8-bit units.
When used as an input port, an on-chip pull-up resistor can be
specified by software. The test input flag (KRIF) is set to 1 by falling
edge detection.
Input
AD0 to AD7
Notes 1. When using the P07/XT1 pins as an input port, set bit 6 (FRC) of the processor clock control register
(PCC) to 1. Do not use the on-chip feedback resistor of the subsystem clock oscillator.
2. When using the P10/ANI0 to P17/ANI7 pins as the A/D converter analog input pins, set port 1 to the
input mode. At this time, on-chip pull-up resistors are automatically disconnected.
Remark
[ ] µPD78005xY only
Data Sheet U12182EJ3V0DS
11
µPD780053, 780054, 780055, 780056, 780058, 780053Y, 780054Y, 780055Y, 780056Y
3.1 Port Pins (2/2)
Pin Name
I/O
Function
After
Reset
P50 to P57
I/O
Port 5
8-bit I/O port.
LEDs can be driven directly.
Input/output can be specified in 1-bit units.
When used as an input port, an on-chip pull-up resistor can be specified by
software.
Input
P60
I/O
Port 6
8-bit I/O port. Input/output can be specified in
1-bit units.
N-ch open-drain input/
output port. An on-chip pullup resistor can be specified
by the mask option. LEDs
can be driven directly.
Input
P61
P62
P63
P64
When used as an input
port, an on-chip pull-up
resistor can be specified by
software.
P65
P66
A8 to A15
–
RD
WR
WAIT
P67
P70
Alternate
Function
ASTB
I/O
P71
P72
Port 7
3-bit I/O port.
Input/output can be specified in 1-bit units.
When used as an input port, an on-chip pull-up resistor can be specified by
software.
Input
SI2/RxD0
SO2/TxD0
SCK2/ASCK
P120 to P127
I/O
Port 12
8-bit I/O port.
Input/output can be specified in 1-bit units.
When used as an input port, on-chip pull-up resistor can be specified by
software.
Input
RTP0 to RTP7
P130, P131
I/O
Port 13
2-bit I/O port.
Input/output can be specified in 1-bit units.
When used as an input port, an on-chip pull-up resistor can be specified by
software.
Input
ANO0, ANO1
12
Data Sheet U12182EJ3V0DS
µPD780053, 780054, 780055, 780056, 780058, 780053Y, 780054Y, 780055Y, 780056Y
3.2 Non-Port Pins (1/2)
Pin Name
INTP0
I/O
Input
INTP1
Function
External interrupt request input for which the valid edge (rising edge,
falling edge, or both rising edge and falling edges) can be specified.
After
Reset
Input
Alternate
Function
P00/TI00
P01/TI01
INTP2
P02
INTP3
P03
INTP4
P04
INTP5
SI0
P05
Input
Serial interface serial data input
Input
SI1
P20
SI2
SO0
P70/RxD
Output
Input
Serial interface serial data output
SO1
P71/TxD
I/O
Serial interface serial data input/output
Input
SB1
P25/SI0 [/SDA0]
P26/SO0 [/SDA1]
µPD78005xY only
SDA0
P25/SI0/SB0
SDA1
SCK0
P26/SB1 [/SDA1]
P21
SO2
SB0
P25/SB0 [/SDA0]
P26/SO0/SB1
I/O
Serial interface serial clock input/output
Input
P27 [/SCL]
SCK1
P22
SCK2
P72/ASCK
µPD78005xY only
SCL
STB
BUSY
RxD0
Output
P27/SCK0
Serial interface automatic transmit/receive strobe output
Input
P23/TxD1
Input
Serial interface automatic transmit/receive busy input
Input
P24/RxD1
Input
Asynchronous serial interface serial data input
Input
P70/SI2
Output
Asynchronous serial interface serial data output
Input
Input
Asynchronous serial interface serial clock input
Input
P72/SCK2
Input
External count clock input to the 16-bit timer (TM0)
Input
P00/INTP0
RxD1
TxD0
P24/BUSY
TxD1
ASCK
TI00
P71/SO2
P23/STB
TI01
Capture trigger signal input to the capture register (CR00)
P01/INTP1
TI1
External count clock input to the 8-bit timer (TM1)
P33
TI2
External count clock input to the 8-bit timer (TM2)
TO0
16-bit timer (TM0) output (also used for 14-bit PWM output)
Output
TO1
TO2
P34
Input
P30
8-bit timer (TM1) output
P31
8-bit timer (TM2) output
P32
PCL
Output
Clock output (for trimming of main system clock and subsystem clock)
Input
P35
BUZ
Output
Buzzer output
Input
P36
RTP0 to RTP7
Output
Real-time output port from which data is output in synchronization with a trigger
Input
P120 to P127
Lower address/data bus for expanding memory externally
Input
P40 to P47
AD0 to AD7
Remark [
I/O
]: µPD78005xY only
Data Sheet U12182EJ3V0DS
13
µPD780053, 780054, 780055, 780056, 780058, 780053Y, 780054Y, 780055Y, 780056Y
3.2 Non-Port Pins (2/2)
Pin Name
Function
I/O
After
Reset
Alternate
Function
A8 to A15
Output
Higher address bus for expanding memory externally
Input
P50 to P57
RD
Output
Strobe signal output for reading from external memory
Input
P64
Strobe signal output for writing to external memory
WR
WAIT
Input
ASTB
Output
ANI0 to ANI7
Input
ANO0, ANO1
Output
P65
Wait insertion at external memory access
Input
P66
Strobe output that externally latches address information output to ports 4
and 5 to access external memory.
Input
P67
A/D converter analog input
Input
P10 to P17
D/A converter analog output
Input
P130, P131
AVREF0
Input
A/D converter reference voltage input (also used for analog power supply)
–
–
AVREF1
Input
D/A converter reference voltage input
–
–
A/D converter and D/A converter ground potential
Use at the same potential as VSS0.
–
–
AVSS
–
RESET
Input
System reset input
–
–
X1
Input
Connecting crystal resonator for main system clock oscillation
–
–
X2
–
–
–
XT1
Input
XT2
–
VDD0
–
VSS0
Connecting crystal resonator for subsystem clock oscillation
Input
P07
–
–
Port block positive power supply
–
–
–
Port block ground potential
–
–
VDD1
–
Positive power supply (except for port and analog blocks)
–
–
VSS1
–
Ground potential (except for port and analog blocks)
–
–
IC
–
Internally connected. Connect directly to VSS0 or VSS1.
–
–
14
Data Sheet U12182EJ3V0DS
µPD780053, 780054, 780055, 780056, 780058, 780053Y, 780054Y, 780055Y, 780056Y
3.3 Pin I/O Circuits and Recommended Connection of Unused Pins
The I/O circuit type of each pin and recommended connection of unused pins are shown in Table 3-1.
For the I/O circuit configuration of each type, see Figure 3-1.
Table 3-1. Pin I/O Circuit Type (1/2)
Pin Name
I/O Circuit
Type
I/O
P00/INTP0/TI00
2
Input
P01/INTP1/TI01
8-C
I/O
16
Input
P10/ANI0 to P17/ANI7
11-D
I/O
P20/SI1
8-C
P21/SO1
5-H
P22/SCK1
8-C
P23/STB/TxD1
5-H
P24/BUSY/RxD1
8-C
P25/SI0/SB0 [/SDA0]
10-B
P02/INTP2
Recommended Connection
Connect to VSS0.
Input: Independently connect to VSS0 via a resistor.
Output:Leave open.
P03/INTP3
P04/INTP4
P05/INTP5
P07/XT1
Connect to VDD0.
Input: Independently connect to VDD0 or VSS0 via a resistor.
Output: Leave open.
P26/SO0/SB1 [/SDA1]
P27/SCK0 [/SCL]
P30/TO0
5-H
P31/TO1
P32/TO2
P33/TI1
8-C
P34/TI2
P35/PCL
5-H
P36/BUZ
P37
P40/AD0 to P47/AD7
5-N
Input: Independently connect to VDD0 via a resistor.
Output: Leave open.
P50/A8 to P57/A15
5-H
Input: Independently connect to VDD0 or VSS0 via a resistor.
Output: Leave open.
P60 to P63
13-J
Input: Independently connect to VDD0 via a resistor.
Output: Leave open.
P64/RD
5-H
Input: Independently connect to VDD0 or VSS0 via a resistor.
Outpu: Leave open.
P65/WR
P66/WAIT
P67/ASTB
Remark
[
]: µPD78005xY only.
Data Sheet U12182EJ3V0DS
15
µPD780053, 780054, 780055, 780056, 780058, 780053Y, 780054Y, 780055Y, 780056Y
Table 3-1. Pin I/O Circuit Type (2/2)
Pin Name
I/O Circuit Type
P70/SI2/RxD0
8-C
P71/SO2/TxD0
5-H
P72/SCK2/ASCK
8-C
P120/RTP0 to
5-H
Recommended Connection
I/O
I/O
Input: Independently connect to VDD0 or VSS0 via a resistor.
Output: Leave open.
P127/RTP7
P130/ANO0,
Input: Independently connect to VSS0 via a resistor.
Output: Leave open.
12-C
P131/ANO1
RESET
2
Input
XT2
16
–
AVREF0
–
–
Leave open.
Connect to VSS0.
AVREF1
Connect to VDD0.
AVSS
Connect to VSS0.
IC
Directly connect to VSS0 or VSS1.
16
Data Sheet U12182EJ3V0DS
µPD780053, 780054, 780055, 780056, 780058, 780053Y, 780054Y, 780055Y, 780056Y
Figure 3-1. Pin I/O Circuits (1/2)
Type 2
Type 8-C
VDD0
Pull-up
enable
P-ch
IN
VDD0
Data
P-ch
IN/OUT
Schmitt-triggered input with hysteresis characteristics
VDD0
Type 5-H
Pull-up
enable
Output
disable
N-ch
VSS0
VDD0
Type 10-B
Pull-up
enable
P-ch
P-ch
VDD0
Data
VDD0
Data
P-ch
P-ch
IN/OUT
Output
disable
IN/OUT
Open drain
Output disable
N-ch
VSS0
N-ch
VSS0
Input
enable
Type 5-N
Pull-up
enable
Pull-up
enable
P-ch
P-ch
IN/OUT
P-ch
IN/OUT
Output
disable
P-ch
VDD0
Data
VDD0
Data
VDD0
Type 11-D
VDD0
N-ch
Output
disable
Comparator
VSS0
N-ch
P-ch
+
−
VSS0
N-ch
VSS0
VREF (threshold voltage)
Input
enable
Data Sheet U12182EJ3V0DS
17
µPD780053, 780054, 780055, 780056, 780058, 780053Y, 780054Y, 780055Y, 780056Y
Figure 3-1. Pin Input/Output Circuits (2/2)
VDD0
Type 12-C
Pull-up
enable
Type 16
Feed back
P-ch
cut-off
VDD0
Data
P-ch
P-ch
IN/OUT
Output
disable
Input
enable
N-ch
VSS0
P-ch
XT1
Analog output
voltage
N-ch
VSS0
Type 13-J
VDD0
Mask
option
IN/OUT
Data
Output disable
N-ch
VSS0
VDD0
RD
P-ch
Middle-voltage input buffer
18
Data Sheet U12182EJ3V0DS
XT2
µPD780053, 780054, 780055, 780056, 780058, 780053Y, 780054Y, 780055Y, 780056Y
4. MEMORY SPACE
Figure 4-1 shows the memory map of the µPD78005x and 78005xY.
Figure 4-1. Memory Map
FFFFH
Special function registers
(SFRs) 256 × 8 bits
FF00H
FEFFH
FEE0H
FEDFH
FA7FH
General-purpose
registers
32 × 8 bits
Reserved
F800H
F7FFH
Internal expanded RAM
1,024 × 8 bits
Internal high-speed
RAM
FB00H
FAFFH
ReservedNote 2
F000H
Reserved
Data memory
space
FAE0H
FADFH
FAC0H
FABFH
Note 1
F400H
F3FFH
nnnnH
Internal buffer RAM
32 × 8 bits
Program area
1000H
0FFFH
Reserved
CALLF entry area
FA80H
FA7FH
0800H
07FFH
Program area
External memory
0080H
007FH
Program memory
space
nnnnH + 1
nnnnH
CALLT table area
0040H
003FH
Internal ROMNote 3
Vector table area
0000H
0000H
Notes 1. µPD780058 only
2. If external device expansion functions are to be employed for the µPD780058, set the size of the internal
ROM to 56 KB or less using internal the memory size switching register (IMS).
3. The internal ROM capacity depends on the product (see the table below).
Part Number
Last Address of Internal
ROM nnnnH
µPD780053, 780053Y
5FFFH
µPD780054, 780054Y
7FFFH
µPD780055, 780055Y
9FFFH
µPD780056, 780056Y
BFFFH
µPD780058
EFFFH
Data Sheet U12182EJ3V0DS
19
µPD780053, 780054, 780055, 780056, 780058, 780053Y, 780054Y, 780055Y, 780056Y
5. PERIPHERAL HARDWARE FUNCTION FEATURES
5.1 Ports
The following three types of I/O ports are available.
• CMOS input (P00, P07):
2
• CMOS I/O (P01 to P05, port 1 to port 5, P64 to P67, port 7, port 12, port 13):
62
• N-ch open-drain I/O (P60 to P63):
4
Total:
68
Table 5-1. Port Functions
Port Name
Port 0
Pin Name
Function
P00, P07
Input only
P01 to P05
I/O port. Input/output can be specified in 1-bit units.
When used as an input port, an on-chip pull-up resistor can be specified by software.
Port 1
P10 to P17
I/O port. Input/output can be specified in 1-bit units.
When used as an input port, an on-chip pull-up resistor can be specified by software.
Port 2
P20 to P27
I/O port. Input/output can be specified in 1-bit units.
When used as an input port, an on-chip pull-up resistor can be specified by software.
Port 3
P30 to P37
I/O port. Input/output can be specified in 1-bit units.
When used as an input port, an on-chip pull-up resistor can be specified by software.
Port 4
P40 to P47
I/O port. Input/output can be specified in 8-bit units.
When used as an input port, an on-chip pull-up resistor can be specified by software.
The test flag (KRIF) is set to 1 by falling edge detection.
Port 5
P50 to P57
I/O port. Input/output can be specified in 1-bit units.
When used as an input port, an on-chip pull-up resistor can be specified by software.
LEDs can be driven directly.
Port 6
P60 to P63
N-ch open-drain I/O port. Input/output can be specified in 1-bit units.
On-chip pull-up resistor can be used by mask option.
LEDs can be driven directly.
P64 to P67
I/O port. Input/output can be specified in 1-bit units.
When used as an input port, an on-chip pull-up resistor can be specified by software.
Port 7
P70 to P72
I/O port. Input/output can be specified in 1-bit units.
When used as an input port, an on-chip pull-up resistor can be specified by software.
Port 12
P120 to P127
I/O port. Input/output can be specified in 1-bit units.
When used as an input port, an on-chip pull-up resistor can be specified by software.
Port 13
P130, P131
I/O port. Input/output can be specified in 1-bit units.
When used as an input port, an on-chip pull-up resistor can be specified by software.
20
Data Sheet U12182EJ3V0DS
µPD780053, 780054, 780055, 780056, 780058, 780053Y, 780054Y, 780055Y, 780056Y
5.2 Clock Generator
Two types of generators, a main system clock generator and a subsystem clock generator, are available.
The minimum instruction execution time can be changed.
• 0.4 µs/0.8 µs/1.6 µs/3.2 µs/6.4 µs/12.8 µs (@5.0 MHz operation with main system clock)
• 122 µs (@32.768 kHz operation with subsystem clock)
Figure 5-1. Clock Generator Block Diagram
XT1/P07
XT2
Subsystem
clock
oscillator
fXT
Watch timer, clock
output function
Prescaler
1
X1
X2
Main system fX
clock
oscillator
Selector
Scaler
2
Clock to peripheral
hardware
Prescaler
fXX
fXX fXX fXX
2 22 23
fXX fXT
24 2
fX
2
STOP
Selector
Standby
controller
Wait
controller
CPU clock
(fCPU)
To INTP0
sampling clock
5.3 Timer/Event Counter
Five timer/event counter channels are incorporated.
• 16-bit timer/event counter: 1 channel
• 8-bit timer/event counter: 2 channels
• Watch timer:
1 channel
• Watchdog timer:
1 channel
Table 5-2. Operations of Timer/Event Counter
Operation
mode
Function
16-Bit Timer/
Event Counter
8-Bit Timer/
Event Counter
Watch Timer
Watchdog Timer
Interval timer
1 channel
2 channels
1 channel
1 channel
External event counter
1 channel
2 channels
–
–
Timer output
1 output
2 outputs
–
–
PWM output
1 output
–
–
–
Pulse width measurement
1 input
–
–
–
Square wave output
1 output
2 outputs
–
–
One-shot pulse output
1 output
–
–
–
2
2
2
1
Interrupt request
Data Sheet U12182EJ3V0DS
21
µPD780053, 780054, 780055, 780056, 780058, 780053Y, 780054Y, 780055Y, 780056Y
Figure 5-2. Block Diagram of 16-Bit Timer/Event Counter
Internal bus
INTP1
TI01/P01/INTP1
16-bit capture/
compare register
(CR00)
Selector
INTTM00
PWM pulse
output
controller
Match
Watch timer
output
Output controller
TO0/P30
2fXX
fXX
16-bit timer counter
(TM0)
Selector
fXX/2
fXX/2 2
TI00/P00/INTP0
Clear
Edge
detector
Selector
Match
INTTM01
INTP0
16-bit capture/
compare register
(CR01)
Internal bus
Figure 5-3. Block Diagram of 8-Bit Timer/Event Counter
Internal bus
INTTM1
8-bit compare
register (CR10)
8-bit compare
register (CR20)
Selector
Match
Match
Output
controller
INTTM2
fXX/2 to fXX/2 9
fX/211
Selector
8-bit timer
counter 1 (TM1)
Selector
TI1/P33
Clear
8-bit timer
counter 2 (TM2)
Clear
fXX/2 to fXX/2 9
fX/211
TO2/P32
Selector
Selector
TI2/P34
Output
controller
Internal bus
22
Data Sheet U12182EJ3V0DS
TO1/P31
µPD780053, 780054, 780055, 780056, 780058, 780053Y, 780054Y, 780055Y, 780056Y
Figure 5-4. Block Diagram of Watch Timer
fW
2 14
Selector
fXX/2 7
Selector
fW
5-bit counter
Selector
Prescaler
fXT
INTWT
fW
2 13
fW
24
fW
25
fW
26
fW
27
fW
28
fW
29
INTTM3
Selector
To 16-bit timer/
event counter
Figure 5-5. Block Diagram of Watchdog Timer
fXX
Prescaler
23
fXX
24
fXX
25
fXX
26
fXX
27
fXX
28
fXX
29
fXX
2 11
INTWDT
maskable
interrupt request
Selector
8-bit counter
Controller
RESET
INTWDT
non-maskable
interrupt request
Data Sheet U12182EJ3V0DS
23
µPD780053, 780054, 780055, 780056, 780058, 780053Y, 780054Y, 780055Y, 780056Y
5.4 Clock Output Controller
Clocks with the following frequencies can be output as the clock output.
• 19.5 kHz/39.1 kHz/78.1 kHz/156 kHz/313 kHz/625 kHz/1.25 MHz/2.5 MHz/5.0 MHz (@5.0 MHz operation with
main system clock)
• 32.768 kHz (@32.768 kHz operation with subsystem clock)
Figure 5-6. Block Diagram of Clock Output Controller
fXX
fXX/2
fXX/2 2
fXX/2 3
Synchronization
circuit
Selector
fXX /2 4
Output controller
fXX /2 5
fXX /2 6
fXX /2 7
fXT
5.5 Buzzer Output Controller
Clocks with the following frequencies can be output as the buzzer output.
• 1.2 kHz/2.4 kHz/4.9 kHz/9.8 kHz (@5.0 MHz operation with main system clock)
Figure 5-7. Block Diagram of Buzzer Output Controller
f XX /2 9
f XX /2 10
Selector
Output controller
f XX /2 11
24
Data Sheet U12182EJ3V0DS
BUZ/P36
PCL/P35
µPD780053, 780054, 780055, 780056, 780058, 780053Y, 780054Y, 780055Y, 780056Y
5.6 A/D Converter
An A/D converter consists of eight 8-bit resolution channels is incorporated.
The following two types of the A/D conversion operation startup methods are available.
• Hardware start
• Software start
Figure 5-8. Block Diagram of A/D Converter
Series resistor string
Sample & hold circuit
ANI0/P10
ANI1/P11
AVREF0
(funcitons alternately
as analog power supply)
Voltage comparator
ANI2/P12
Tap
selector
ANI3/P13
ANI4/P14
Selector
AVSS
ANI5/P15
ANI6/P16
Succesive approxmation
register (SAR)
ANI7/P17
INTP3/P03
Edge
detector
AVSS
INTAD
Controller
INTP3
A/D conversion
result register (ADCR)
Internal bus
Data Sheet U12182EJ3V0DS
25
µPD780053, 780054, 780055, 780056, 780058, 780053Y, 780054Y, 780055Y, 780056Y
5.7 D/A Converter
A D/A converter consisting of two 8-bit resolution channels is incorporated.
The conversion method is the R-2R resistor ladder method.
Figure 5-9. D/A Converter Block Diagram
AVREF1
ANOn
Selector
DACSn
write
AVSS
INTTMx
D/A conversion value set register n
(DACSn)
DAMm
D/A converter
mode register
Internal bus
n = 0, 1
m = 4, 5
x = 1, 2
26
Data Sheet U12182EJ3V0DS
µPD780053, 780054, 780055, 780056, 780058, 780053Y, 780054Y, 780055Y, 780056Y
5.8 Serial Interfaces
Three clocked serial interface channels are incorporated.
• Serial interface channel 0
• Serial interface channel 1
• Serial interface channel 2
Table 5-3. Types and Functions of Serial Interface
Serial Interface Channel 0
Function
µPD78005x
Serial Interface Channel 1
√ (MSB/LSB first switching
possible)
3-wire serial I/O mode
3-wire serial I/O mode with
automatic transmit/receive
function
SBI (serial bus interface) mode
2
I C bus mode
√ (MSB/LSB first switching
possible)
√ (MSB first)
–
–
√ (MSB first)
Asynchronous serial interface
(UART) mode (on-chip time
division transfer function)
√ (MSB/LSB first switching
possible)
√ (MSB/LSB first switching
possible)
–
√ (MSB first)
2-wire serial I/O mode
Serial Interface Channel 2
µPD78005xY
–
–
–
–
–
–
–
–
√ (On-chip dedicated baud
rate generator)
–
Figure 5-10. Block Diagram of Serial Interface Channel 0 (1/2)
(a) µPD78005x
Internal bus
SI0/SB0/P25
Selector
Serial I/O shift
register 0 (SIO0)
Output
latch
SO0/SB1/P26
Selector
SCK0/P27
Busy/acknowledge
output circuit
Bus release/command/
acknowledge detector
Serial clock counter
Interrupt
request
signal
generator
INTCSI0
fXX/2 to fXX/28
Serial clock
controller
Data Sheet U12182EJ3V0DS
Selector
TO2
27
µPD780053, 780054, 780055, 780056, 780058, 780053Y, 780054Y, 780055Y, 780056Y
Figure 5-10. Block Diagram of Serial Interface Channel 0 (2/2)
(b) µPD78005xY
Internal bus
SI0/SB0/SDA0/P25
Selector
Serial I/O shift
register 0 (SIO0)
Output
latch
SO0/SB1/SDA1/P26
Selector
Start condition/stop
condition/acknowledge
detector
Serial clock counter
SCK0/SCL/P27
Acknowledge
output circuit
Interrupt
request
signal
generator
INTCSI0
fXX/2 to fXX8/2
Serial clock
controller
Selector
TO2
Figure 5-11. Block Diagram of Serial Interface Channel 1
Internal bus
Automatic data transmit/
receive address pointer
(ADTP)
Buffer RAM
Automatic data
transmit/receive
interval specification
register (ADTI)
Match
SI1/P20
Serial I/O shift register 1 (SIO1)
SO1/P21
5-bit counter
STB/TxD1/P23
Handshake
controller
BUSY/RxD1/P24
SCK1/P22
Serial clock counter
Interrupt request
signal generator
INTCSI1
8
fXX/2 to fXX/2
Serial clock controller
28
Data Sheet U12182EJ3V0DS
Selector
TO2
µPD780053, 780054, 780055, 780056, 780058, 780053Y, 780054Y, 780055Y, 780056Y
Figure 5-12. Block Diagram of Serial Interface Channel 2
RxD1/BUSY/P24
TxD0/SO2/P71
TxD1/STB/P23
Direction controller
Direction controller
Transmit shift register
(TXS/SIO2)
Selector
RxD0/SI2/P70
Receive buffer register
(RXB/SIO2)
Receive shift register
(RXS)
Transmit controller
Selector
Internal bus
Receive controller
INTST
INTSER
INTSR/INTCSI2
SCK output
controller
ASCK/SCK2/P72
Baud rate
generator
fXX to fXX/210
5.9 Real-Time Output Ports
Data set previously in the real-time output buffer register is transferred to the output latch by hardware concurrently
with timer interrupt request and external interrupt request generation in order to output off-chip. This is the real-time
output function. Pins used to output off-chip are called real-time output ports.
By using a real-time output port, a signal with no jitter can be output. This is most applicable to control of stepper
motors, etc.
Figure 5-13. Block Diagram of Real-Time Output Port
Internal bus
INTP2
INTTM1
INTTM2
Output trigger
controller
Real-time output
buffer register
higher 4 bits
(RTBH)
Real-time output
buffer register
lower 4 bits
(RTBL)
Real-time output port mode
register (RTPM)
Output latch
P127
P120
Data Sheet U12182EJ3V0DS
29
µPD780053, 780054, 780055, 780056, 780058, 780053Y, 780054Y, 780055Y, 780056Y
6. INTERRUPT AND TEST FUNCTIONS
6.1 Interrupt Functions
The interrupt function includes, three different kinds of interrupts from 21 sources, as shown below.
• Non-maskable: 1
• Maskable:
19
• Software:
1
Table 6-1. Interrupt Source List (1/2)
Interrupt Type
Note 1
Default
Priority
Interrupt Source
Name
Internal/
Externa
Vector Table
Address
Basic
Configuration
TypeNote 2
0004H
(A)
Trigger
Non-maskable
–
INTWDT
Watchdog timer overflow
(with watchdog timer mode 1 selected)
Maskable
0
INTWDT
Watchdog timer overflow
(with interval timer mode selected)
1
INTP0
Pin input edge detection
Internal
(B)
External
0006H
(C)
(D)
2
INTP1
0008H
3
INTP2
000AH
4
INTP3
000CH
5
INTP4
000EH
6
INTP5
0010H
7
INTCSI0
End of serial interface channel 0
transfer
8
INTCSI1
End of serial interface channel 1
transfer
0016H
9
INTSER
Occurrence of serial interface channel
0018H
Internal
0014H
(B)
2 UART reception error
10
11
INTSR
End of serial interface channel 2
UART reception
INTCSI2
End of serial interface channel 2
3-wire transfer
INTST
End of serial interface channel 2
UART transmission
001AH
001CH
Notes 1. Default priority is the priority order when several maskable interrupt requests are generated simultaneously.
0 is the highest order and 17 is the lowest.
2. Basic configuration types (A) to (E) correspond to (A) to (E) in Figure 6-1.
Remark There are two types of interrupt source for the watchdog timer: Non-maskable interrupts and maskable
interrupts (internal). Only one of these interrupts can be selected.
30
Data Sheet U12182EJ3V0DS
µPD780053, 780054, 780055, 780056, 780058, 780053Y, 780054Y, 780055Y, 780056Y
Table 6-1. Interrupt Source List (2/2)
Note 1
Interrupt
Type
Default
Priority
Maskable
Software
Interrupt Source
Name
Internal/
Externa
Vector Table
Address
Basic
Configuration
TypeNote 2
Internal
001EH
(B)
Trigger
12
INTTM3
Reference time interval signal from watch
timer
13
INTTM00
Generation of match signal of 16-bit
timer counter and capture/compare
register (CR00)
0020H
14
INTTM01
Generation of match signal of 16-bit
timer counter and capture/compare
register (CR01)
0022H
15
INTTM1
Generation of match signal of 8-bit
timer/event counter 1
0024H
16
INTTM2
Generation of match signal of 8-bit timer/
event counter 2
0026H
17
INTAD
End of conversion by A/D converter
0028H
BRK
Execution of BRK instruction
–
–
003EH
(E)
Notes 1. Default priority is the priority order when several maskable interrupt requests are generated simultaneously.
0 is the highest order and 17 is the lowest.
2. Basic configuration types (A) to (E) correspond to (A) to (E) in Figure 6-1.
Data Sheet U12182EJ3V0DS
31
µPD780053, 780054, 780055, 780056, 780058, 780053Y, 780054Y, 780055Y, 780056Y
Figure 6-1. Basic Configuration of Interrupt Function (1/2)
(A) Internal non-maskable interrupt
Internal bus
Interrupt
request
Vector table
address
generator
Priority controller
Standby release
signal
(B) Internal maskable interrupt
Internal bus
MK
Interrupt
request
PR
IE
ISP
Vector table
address
generator
Priority
controller
IF
Standby release
signal
(C) External maskable interrupt (INTP0)
Internal bus
Interrupt
request
Sampling clock
select register
(SCS)
External interrupt
mode register
(INTM0)
Sampling
clock
Edge
detector
MK
IF
IE
PR
Priority
controller
ISP
Vector table
address
generator
Standby release
signal
32
Data Sheet U12182EJ3V0DS
µPD780053, 780054, 780055, 780056, 780058, 780053Y, 780054Y, 780055Y, 780056Y
Figure 6-1. Basic Configuration of Interrupt Function (2/2)
(D) External maskable interrupt (except INTP0)
Internal bus
External interrupt
mode register
(INTM0)
Interrupt
request
MK
IE
ISP
Priority
controller
IF
Edge detector
PR
Vector table
address
generator
Standby release
signal
(E) Software interrupt
Internal bus
Priority
controller
Interrupt
request
IF:
Interrupt request flag
IE:
Interrupt enable flag
Vector table
address
generator
ISP: In-service priority flag
MK: Interrupt mask flag
PR: Priority specification flag
Data Sheet U12182EJ3V0DS
33
µPD780053, 780054, 780055, 780056, 780058, 780053Y, 780054Y, 780055Y, 780056Y
6.2 Test Functions
The test function includes the two test input sources shown in Table 6-2 below.
Table 6-2. Test Input Source List
Test Input Source
Internal/External
Trigger
Name
INTWT
Watch timer overflow
Internal
INTPT4
Port 4 falling edge detection
External
Figure 6-2. Basic Configuration of Test Function
Internal bus
MK
Test input
flag
IF:
Standby release
signal
IF
Test input flag
MK: Test mask flag
34
Data Sheet U12182EJ3V0DS
µPD780053, 780054, 780055, 780056, 780058, 780053Y, 780054Y, 780055Y, 780056Y
7. EXTERNAL DEVICE EXPANSION FUNCTION
The external device expansion function connects external devices to areas other than the internal ROM, RAM, and
SFR areas.
Ports 4 to 6 are used for external device connection.
8. STANDBY FUNCTION
The following two standby functions are available for further reduction of system current consumption.
• HALT mode:
In this mode, the CPU operating clock is stopped.
The average current consumption can be reduced by intermittent operation by combining this
mode with the normal operation mode.
• STOP mode: In this mode oscillation of the main system clock is stopped. All the operations performed on
the main system clock are suspended, and only the subsystem clock is used, resulting in
extremely small power consumption.
Figure 8-1. Standby Function
CSS = 1
Main system
clock operation
Interrupt
request
CSS = 0
HALT
instruction
STOP
instruction
Interrupt
request
Subsystem clock
operationNote
Interrupt
request
HALT mode
(Clock supply to CPU is
stopped, oscillation
continues)
STOP mode
(Main system clock
oscillation stopped)
HALT
instruction
HALT modeNote
(Clock supply to CPU is
stopped, oscillation
continues)
Note The current consumption can be reduced by stopping the main system clock.
When the CPU is operating on the subsystem clock, set the MCC (bit 7 of the processor clock control register
(PCC)) to stop the main system clock. The STOP instruction cannot be used.
Caution
When the main system clock is stopped and the system is operating on the subsystem clock,
wait until the oscillation stabilization time has been secured by the program before switching
back to the main system clock.
Remark CSS: Bit 4 of the processor clock control register (PCC).
9. RESET FUNCTION
The following two reset methods are available.
• External reset by RESET signal input
• Internal reset by watchdog timer program loop time detection
Data Sheet U12182EJ3V0DS
35
µPD780053, 780054, 780055, 780056, 780058, 780053Y, 780054Y, 780055Y, 780056Y
10. MASK OPTION
The µPD78005x and 78005xY have the following mask options.
• Pull-up resistor
An on-chip pull-up resistor for P60 to P63 (I/O port) can be specified in 1-bit units.
<1> Specifies on-chip pull-up resistor.
<2> Does not specify on-chip pull-up resistor.
36
Data Sheet U12182EJ3V0DS
µPD780053, 780054, 780055, 780056, 780058, 780053Y, 780054Y, 780055Y, 780056Y
11. INSTRUCTION SET
(1) 8-bit instructions
MOV, XCH, ADD ADDC, SUB, SUBC, AND, OR, XOR, CMP, MULU, DIVUW, INC, DEC, ROR, ROL, RORC,
ROLC, ROR4, ROL4, PUSH, POP, DBNZ
Second
Operand
#byte
A
rNote
sfr
saddr
!addr16
PSW
[DE]
[HL]
r
$addr16
1
None
[HL + B]
First
Operand
A
[HL + Byte]
[HL + C]
ADD
MOV
MOV
MOV
MOV
ADDC
XCH
XCH
XCH
XCH
SUB
ADD
ADD
SUBC
ADDC
AND
MOV
MOV
MOV
MOV
ROR
XCH
XCH
XCH
ROL
ADD
ADD
ADD
RORC
ADDC
ADDC
ADDC
ADDC
ROLC
SUB
SUB
SUB
SUB
SUB
SUBC
OR
SUBC
SUBC
SUBC
SUBC
XOR
AND
AND
AND
AND
AND
CMP
OR
OR
OR
OR
OR
MOV
XOR
XOR
XOR
XOR
XOR
CMP
CMP
CMP
CMP
CMP
MOV
ADD
INC
DEC
ADDC
SUB
SUBC
AND
OR
XOR
CMP
DBNZ
B, C
sfr
MOV
MOV
saddr
MOV
MOV
DBNZ
ADD
INC
DEC
ADDC
SUB
SUBC
AND
OR
XOR
CMP
!addr16
PSW
MOV
MOV
MOV
PUSH
POP
[DE]
[HL]
MOV
ROR4
ROL4
[HL + Byte]
[HL + B]
[HL + C]
MOV
X
MULU
C
DIVUW
Note Except r = A
Data Sheet U12182EJ3V0DS
37
µPD780053, 780054, 780055, 780056, 780058, 780053Y, 780054Y, 780055Y, 780056Y
(2) 16-bit instructions
MOV, XCHW, ADDW, SUBW, CMPW, PUSH, POP, INCW, DECW
Second Operand
First Operand
#word
AX
rpNote
MOVW
XCHW
AX
ADDW
SUBW
CMPW
rp
MOVW
MOVWNote
sfrp
MOVW
MOVW
saddrp
MOVW
!addr16
SP
MOVW
MOVW
MOVW
MOVW
sfrp
MOVW
saddrp
!addr16
MOVW
MOVW
SP
None
MOVW
INCW
DECW
PUSH
POP
Note Only when rp = BC, DE, or HL
(3) Bit manipulation instructions
MOV1, AND1, OR1, XOR1, SET1, CLR1, NOT1, BT, BF, BTCLR
Second Operand
First Operand
A.bit
sfr.bit
saddr.bit
PSW.bit
[HL].bit
CY
$addr16
None
A.bit
MOV1
BT
BF
BTCLR
SET1
CLR1
sfr.bit
MOV1
BT
BF
BTCLR
SET1
CLR1
saddr.bit
MOV1
BT
BF
BTCLR
SET1
CLR1
PSW.bit
MOV1
BT
BF
BTCLR
SET1
CLR1
[HL].bit
MOV1
BT
BF
BTCLR
SET1
CLR1
MOV1
AND1
OR1
XOR1
CY
MOV1
AND1
OR1
XOR1
MOV1
AND1
OR1
XOR1
MOV1
AND1
OR1
XOR1
MOV1
AND1
OR1
XOR1
(4) Call instruction/branch instructions
CALL, CALLF, CALLT, BR, BC, BNC, BZ, BNZ, BT, BF, BTCLR, DBNZ
AX
Second Operand
First Operand
Basic instruction
BR
Compound
instruction
!addr16
CALL
BR
!addr11
CALLF
[addr5]
CALLT
$addr16
BR, BC, BNC
BZ, BNZ
BT, BF
BTCLR
DBNZ
(5) Other instructions
ADJBA, ADJBS, BRK, RET, RETI, RETB, SEL, NOP, EI, DI, HALT, STOP
38
Data Sheet U12182EJ3V0DS
SET1
CLR1
NOT1
µPD780053, 780054, 780055, 780056, 780058, 780053Y, 780054Y, 780055Y, 780056Y
12. ELECTRICAL SPECIFICATIONS
Absolute Maximum Ratings (TA = 25°C)
Parameter
Supply voltage
Input voltage
Symbol
Conditions
Ratings
Unit
VDD
–0.3 to +6.5
V
AVREF0
–0.3 to VDD + 0.3
V
AVREF1
–0.3 to VDD + 0.3
V
AVSS
–0.3 to +0.3
V
–0.3 to VDD + 0.3
V
–0.3 to +16
V
–0.3 to VDD + 0.3
V
AVSS – 0.3 to AVREF0 + 0.3
V
VI1
P00 to P05, P07, P10 to P17, P20 to P27, P30 to P37,
P40 to P47, P50 to P57, P64 to P67, P70 to P72,
P120 to P127, P130, P131, X1, X2, XT2, RESET
VI2
P60 to P63
N-ch open drain
Output voltage
VO
Analog input voltage
V AN
P10 to P17
Output
current, high
IOH
Per pin
–10
mA
Total for P01 to P05, P30 to P37, P56, P57, P60 to P67,
–15
mA
–15
mA
Peak value
30
mA
rms value
15
mA
Peak value
100
mA
rms value
70
mA
Peak value
100
mA
rms value
70
mA
Total for P10 to P17, P20 to P27,
P40 to P47, P70 to P72, P130, P131
Peak value
50
mA
rms value
20
mA
Total for P01 to P05, P30 to P37,
P64 to P67, P120 to P127
Peak value
50
mA
rms value
20
mA
TA
–40 to +85
°C
Tstg
–65 to +150
°C
Analog input pin
P120 to P127
Total for P10 to P17, P20 to P27, P40 to P47,
P50 to P55, P70 to P72, P130, P131
IOLNote
Output
current, low
Per pin
Total for P50 to P55
Total for P56, P57, P60 to P63
Operating ambient
temperature
Storage
temperature
Note
The rms value should be calculated as follows: [rms value] = [Peak value] × √Duty
Caution
Product quality may suffer if the absolute maximum rating is exceeded even momentarily for any
parameter. That is, the absolute maximum ratings are rated values at which the product is on the
verge of suffering physical damage, and therefore the product must be used under conditions that
ensure that the absolute maximum ratings are not exceeded.
Data Sheet U12182EJ3V0DS
39
µPD780053, 780054, 780055, 780056, 780058, 780053Y, 780054Y, 780055Y, 780056Y
Main System Clock Oscillator Characteristics (TA = –40 to +85°C, VDD = 1.8 to 5.5 V)
Resonator
Ceramic
resonator
Recommended Circuit
X2
C2
Crystal
resonator
X2
C2
External
clock
X1 IC
C1
X1 IC
C1
X2
µ PD74HCU04
X1
Parameter
Conditions
Oscillation
frequency (fX)Note 1
VDD = Oscillation
voltage range
Oscillation
stabilization timeNote 2
After VDD reaches
oscillation voltage range
MIN.
TYP.
1.0
1.0
Oscillation
frequency (fX)Note 1
Oscillation
stabilization timeNote 2
MIN.
VDD = 4.5 to 5.5 V
MAX.
Unit
5.0
MHz
4
ms
5.0
MHz
10
ms
30
X1 input
frequency (fX)Note 1
1.0
5.0
MHz
X1 input
high-/low-level width
(tXH , tXL)
85
500
ns
Notes 1. Indicates only oscillator characteristics. Refer to AC Characteristics for instruction execution time.
2. Time required to stabilize oscillation after reset or STOP mode release.
Cautions 1. When using the main system clock oscillator, wire as follows in the area enclosed by the broken
lines in the above figures to avoid an adverse effect from wiring capacitance.
• Keep the wiring length as short as possible.
• Do not cross the wiring with the other signal lines.
• Do not route the wiring near a signal line through which a high fluctuating current flows.
• Always make the ground point of the oscillator capacitor the same potential as VSS1.
• Do not ground the capacitor to a ground pattern through which a high current flows.
• Do not fetch signals from the oscillator.
2. When the main system clock is stopped and the system is operating on the subsystem clock,
wait until the oscillation stabilization time has been secured by the program before switching
back to the main system clock.
Remark For the resonator selection and oscillator constant, customers are requested to either evaluate the
oscillation themselves or apply to the resonator manufacturer for evaluation.
40
Data Sheet U12182EJ3V0DS
µPD780053, 780054, 780055, 780056, 780058, 780053Y, 780054Y, 780055Y, 780056Y
Subsystem Clock Oscillator Characteristics (TA = –40 to +85°C, VDD = 1.8 to 5.5 V)
Resonator
Recommended Circuit
Crystal
resonator
IC XT2
XT1
R2
C4
External
clock
Parameter
Conditions
Oscillation
frequency (fXT)Note 1
Oscillation
stabilization timeNote 2
C3
XT1
XT2
µ PD74HCU04
MIN.
TYP.
MAX.
Unit
32
32.768
35
kHz
1.2
2
s
VDD = 4.5 to 5.5 V
10
XT1 input
frequency (fXT)Note 1
32
100
kHz
XT1 input
high-/low-level width
(tXTH , tXTL)
5
15
µs
Notes 1. Indicates only oscillator characteristics. Refer to AC Characteristics for instruction execution time.
2. Time required to stabilize oscillation after VDD reaches oscillation voltage MIN.
Cautions 1. When using the subsystem clock oscillator, wire as follows in the area enclosed by the broken
lines in the above figures to avoid an adverse effect from wiring capacitance.
• Keep the wiring length as short as possible.
• Do not cross the wiring with the other signal lines.
• Do not route the wiring near a signal line through which a high fluctuating current flows.
• Always make the ground point of the oscillator capacitor the same potential as VSS1.
• Do not ground the capacitor to a ground pattern through which a high current flows.
• Do not fetch signals from the oscillator.
2. The subsystem clock oscillator is designed as a low-amplitude circuit for reducing current
consumption, and is more prone to malfunction due to noise than the main system clock
oscillator. Particular care is therefore required with the wiring method when the subsystem
clock is used.
Remark For the resonator selection and oscillator constant, customers are requested to either evaluate the
oscillation themselves or apply to the resonator manufacturer for evaluation.
Capacitance (TA = 25°C, VDD = VSS = 0 V)
Parameter
Symbol
Conditions
MIN.
TYP.
MAX.
Unit
Input
capacitance
CIN
f = 1 MHz
Unmeasured pins returned to 0 V.
15
pF
I/O
capacitance
CIO
f = 1 MHz
Unmeasured pins returned
to 0 V.
P01 to P05, P10 to P17,
P20 to P27, P30 to P37,
P40 to P47, P50 to P57,
P64 to P67, P70 to P72,
P120 to P127, P130, P131
15
pF
P60 to P63
20
pF
Remark
Unless specified otherwise, the characteristics of alternate-function pins are the same as those of port pins.
Data Sheet U12182EJ3V0DS
41
µPD780053, 780054, 780055, 780056, 780058, 780053Y, 780054Y, 780055Y, 780056Y
DC Characteristics (TA = –40 to +85°C, VDD = 1.8 to 5.5 V)
Parameter
Input voltage,
Symbol
VIH1
high
VIH2
VIH3
Conditions
MIN.
MAX.
Unit
0.7VDD
VDD
V
0.8VDD
VDD
V
P00 to P05, P20, P22, P24 to P27, VDD = 2.7 to 5.5 V
0.8VDD
VDD
V
P33, P34, P70, P72, RESET
0.85VDD
VDD
V
0.7VDD
15
V
0.8VDD
15
V
VDD – 0.5
VDD
V
VDD – 0.2
VDD
V
0.8VDD
VDD
V
2.7 V ≤ VDD < 4.5 V
0.9VDD
VDD
V
Note
0.9VDD
VDD
V
P10 to P17, P21, P23, P30 to P32, VDD = 2.7 to 5.5 V
0
0.3VDD
V
P35 to P37, P40 to P47,
P50 to P57, P64 to P67, P71,
P120 to P127, P130, P131
0
0.2VDD
V
P00 to P05, P20, P22, P24 to P27, VDD = 2.7 to 5.5 V
0
0.2VDD
V
P10 to P17, P21, P23, P30 to P32, VDD = 2.7 to 5.5 V
P35 to P37, P40 to P47,
P50 to P57, P64 to P67, P71,
P120 to P127, P130, P131
P60 to P63
VDD = 2.7 to 5.5 V
(N-ch open drain)
VIH4
VIH5
Input voltage,
low
VIL1
VIL2
X1, X2
VDD = 2.7 to 5.5 V
4.5 V ≤ VDD ≤ 5.5 V
XT1/P07, XT2
P33, P34, P70, P72, RESET
VIL3
VIL4
VIL5
Output voltage,
VOH
Output voltage,
low
Remark
42
X1, X2
0
0.15VDD
V
4.5 V ≤ VDD ≤ 5.5 V
0
0.3VDD
V
2.7 V ≤ VDD < 4.5 V
0
0.2VDD
V
0
0.1VDD
V
0
0.4
V
0
0.2
V
0
0.2VDD
V
VDD = 2.7 to 5.5 V
4.5 V ≤ VDD ≤ 5.5 V
XT1/P07, XT2
2.7 V ≤ VDD < 4.5 V
0
0.1VDD
V
Note
0
0.1VDD
V
VDD = 4.5 to 5.5 V, IOH = –1 mA
VDD – 1.0
IOH = –100 µA
high
Note
P60 to P63
VOL1
TYP.
V
VDD – 0.5
P50 to P57, P60 to P63
VDD = 4.5 to 5.5 V,
IOL = 15 mA
P01 to P05, P10 to P17, P20 to
P27, P30 to P37, P40 to P47,
P64 to P67, P70 to P72, P120 to
P127, P130, P131
VDD = 4.5 to 5.5 V,
IOL = 1.6 mA
VOL2
SB0, SB1, SCK0
VDD = 4.5 to 5.5 V,
open drain,
pulled-up (R = 1 kΩ)
VOL3
IOL = 400 µA
V
0.4
2.0
V
0.4
V
0.2VDD
V
0.5
V
When P07/XT1 pin is used as P07, the inverse phase of P07 should be input to XT2 pin using an inverter.
Unless specified otherwise, the characteristics of alternate-function pins are the same as those of port pins.
Data Sheet U12182EJ3V0DS
µPD780053, 780054, 780055, 780056, 780058, 780053Y, 780054Y, 780055Y, 780056Y
DC Characteristics (TA = –40 to +85°C, VDD = 1.8 to 5.5 V)
Parameter
Input leakage
current, high
Symbol
ILIH1
Conditions
VIN = VDD
ILIH2
Input leakage
current, low
MAX.
Unit
P00 to P05, P10 to P17, P20 to P27,
P30 to P37, P40 to P47, P50 to P57,
P60 to P67, P70 to P72, P120 to
P127, P130, P131, RESET
MIN.
TYP.
3
µA
X1, X2, XT1/P07, XT2
20
µA
ILIH3
VIN = 15 V
P60 to P63
80
µA
ILIL1
VIN = 0 V
P00 to P05, P10 to P17, P20 to P27,
P30 to P37, P40 to P47, P50 to P57,
P64 to P67, P70 to P72,
P120 to P127, P130, P131, RESET
–3
µA
X1, X2, XT1/P07, XT2
–20
µA
–3 Note
µA
ILIL2
ILIL3
P60 to P63
Output leakage
current, high
ILOH
VOUT = VDD
3
µA
Output leakage
ILOL
VOUT = 0 V
–3
µA
R1
VIN = 0 V, P60 to P63
20
40
120
kΩ
R2
VIN = 0 V, P01 to P05, P10 to P17, P20 to P27,
P30 to P37, P40 to P47, P50 to P57, P64 to P67,
P70 to P72, P120 to P127, P130, P131
15
30
90
kΩ
current, low
Mask option pull-up
resistor
Software pull-up
resistor
Note
When pull-up resistors are not connected to P60 to P63 (specified by the mask option), a low-level input
leakage current of –200 µA (MAX.) flows only for 1.5 clocks (without wait) after a read instruction has been
executed to port 6 (P6) or port mode register 6 (PM6). At times other than this 1.5-clock interval, a –3 µA
(MAX.) current flows.
Remark
Unless specified otherwise, the characteristics of alternate-function pins are the same as those of port pins.
Data Sheet U12182EJ3V0DS
43
µPD780053, 780054, 780055, 780056, 780058, 780053Y, 780054Y, 780055Y, 780056Y
DC Characteristics (TA = –40 to +85°C, VDD = 1.8 to 5.5 V)
Parameter
Power supply
current Note 5
Symbol
IDD1
IDD2
Conditions
5.0 MHz crystal oscillation
operating mode
(fXX = 2.5 MHz)Note 3
TYP.
MAX.
±10%Note 1
MIN.
3.5
7.7
mA
VDD = 3.0 V ±10%Note 2
0.92
2.2
mA
VDD = 2.0 V ±10%Note 2
0.47
1.2
mA
6.1
12.3
mA
1.6
3.5
mA
5.5
mA
2.4
mA
2.1
mA
0.92
mA
1.1
mA
0.46
mA
7.5
mA
2.9
mA
3.3
mA
0.48
1.2
mA
46
92
µA
VDD = 5.0 V
5.0 MHz crystal oscillation
operating mode
(fXX = 5.0 MHz)Note 4
VDD = 5.0 V
±10%Note 1
VDD = 3.0 V
±10%Note 2
5.0 MHz crystal oscillation
HALT mode
(fXX = 2.5 MHz)Note 3
VDD = 5.0 V ±10%
Peripheral functions
operating
Peripheral functions
not operating
0.97
Unit
VDD = 3.0 V ±10%
Peripheral functions
operating
Peripheral functions
not operating
0.38
VDD = 2.0 V ±10%
Peripheral functions
operating
Peripheral functions
not operating
5.0 MHz crystal oscillation
HALT mode
(fXX = 5.0 MHz)Note 4
0.19
VDD = 5.0 V ±10%
Peripheral functions
operating
Peripheral functions
not operating
1.2
VDD = 3.0 V ±10%
Peripheral functions
operating
Peripheral functions
not operating
IDD3
IDD4
IDD5
IDD6
44
32.768 kHz crystal oscillation
operating modeNote 6
32.768 kHz crystal oscillation
HALT modeNote 6
XT1 = VDD
STOP mode
When feedback resistor is used
XT1 = VDD
STOP mode
When feedback resistor is not
used
VDD = 5.0 V ±10%
VDD = 3.0 V ±10%
25
50
µA
VDD = 2.0 V ±10%
12.5
25
µA
VDD = 5.0 V ±10%
22.5
50
µA
VDD = 3.0 V ±10%
3.2
13.2
µA
VDD = 2.0 V ±10%
1.5
11.5
µA
VDD = 5.0 V ±10%
1.0
30
µA
VDD = 3.0 V ±10%
0.5
10
µA
VDD = 2.0 V ±10%
0.3
10
µA
VDD = 5.0 V ±10%
0.1
30
µA
VDD = 3.0 V ±10%
0.05
10
µA
VDD = 2.0 V ±10%
0.05
10
µA
Data Sheet U12182EJ3V0DS
µPD780053, 780054, 780055, 780056, 780058, 780053Y, 780054Y, 780055Y, 780056Y
Notes 1. High-speed mode operation (when the processor clock control register (PCC) is set to 00H).
2. Low-speed mode operation (when the PCC is set to 04H).
3. Operation with main system clock fXX = fX/2 (when the oscillation mode select register (OSMS) is set to 00H)
4. Operation with main system clock fXX = fX (when OSMS is set to 01H)
5. Refer to the current flowing to the VDD0 and VDD1 pins. The current flowing to the A/D converter, D/A
converter, and on-chip pull-up resistor is not included.
6. When the main system clock operation is stopped.
AC Characteristics
(1) Basic operation (TA = –40 to +85°C, VDD = 1.8 to 5.5 V)
Parameter
Symbol
Cycle time
(Minimum
instruction
execution time)
TCY
Conditions
Operating with main system
MIN.
VDD = 2.7 to 5.5 V
clock (fXX = 2.5 MHz)Note 1
Operating with main system
clock (fXX = 5.0
MHz)Note 2
3.5 V ≤ VDD ≤ 5.5 V
2.7 V ≤ VDD ≤ 3.5 V
TI00 input high-/
low-level width
tTIH00
3.5 V ≤ VDD ≤ 5.5 V
tTIL00
2.7 V ≤ VDD < 3.5 V
TI01 input high-/
tTIH01
low-level width
tTIL01
TI1, TI2 input
fTI1
MAX.
Unit
0.8
64
µs
2.0
64
µs
0.4
32
µs
32
µs
125
µs
0.8
40Note 3
Operating on subsystem clock
VDD = 2.7 to 5.5 V
tTIH1
2/fsam +
µs
2/fsam +
0.2Note 4
µs
2/fsam +
0.5Note 4
µs
10
µs
20
µs
VDD = 4.5 to 5.5 V
high-/low-level
tTIL1
VDD = 4.5 to 5.5 V
122
0.1Note 4
frequency
TI1, TI2 input
TYP.
0
4
MHz
0
275
kHz
100
ns
1.8
µs
width
Interrupt request
input high-/
tINTH
INTP0
tINTL
3.5 V ≤ VDD ≤ 5.5 V 2/fsam + 0.1Note 4
µs
2.7 V ≤ VDD < 3.5 V 2/fsam +
0.2Note 4
µs
2/fsam +
0.5Note 4
µs
low-level width
INTP1 to INTP5, P40 to P47
RESET lowlevel width
tRSL
VDD = 2.7 to 5.5 V
VDD = 2.7 to 5.5 V
10
µs
20
µs
10
µs
20
µs
Notes 1. Operation with main system clock fXX = fX/2 (when the oscillation mode select register (OSMS) is set to 00H)
2. Operation with main system clock fXX = fX (when OSMS is set to 01H)
3. Value when external clock is used. When a crystal resonator is used, it is 114 µs (MIN.)
4. Selection of fsam = fXX/2N, fXX/32, fXX/64, and fXX/128 is possible with bits 0 and 1 (SCS0, SCS1) of the sampling
clock selection register (SCS) (when N= 0 to 4).
Data Sheet U12182EJ3V0DS
45
µPD780053, 780054, 780055, 780056, 780058, 780053Y, 780054Y, 780055Y, 780056Y
TCY vs. VDD (@fXX = fX main system clock operation)
60
60
10
10
Operation guaranteed
range
Cycle time TCY [µs]
Cycle time TCY [µs]
TCY vs. VDD (@fXX = fX/2 main system clock operation)
2.0
1.0
0.5
0.4
2.0
1.0
0.5
0.4
0
0
1
2
3
4
5
6
1
Supply voltage VDD [V]
46
Operation
guaranteed
range
2
3
4
5
Supply voltage VDD [V]
Data Sheet U12182EJ3V0DS
6
µPD780053, 780054, 780055, 780056, 780058, 780053Y, 780054Y, 780055Y, 780056Y
(2) Read/write operation
(a) When MCS = 1, PCC2 to PCC0 = 000B (TA = –40 to +85°C, VDD = 3.5 to 5.5 V)
Parameter
Symbol
Conditions
MIN.
MAX.
Unit
ASTB high-level width
tASTH
0.85tCY – 50
ns
Address setup time
tADS
0.85tCY – 50
ns
Address hold time
tADH
50
ns
Time from address to data input
tADD1
(2.85 + 2n) tCY – 80
ns
tADD2
(4 + 2n) tCY – 100
ns
tRDD1
(2 + 2n) tCY – 100
ns
tRDD2
(2.85 + 2n) tCY – 100
ns
Time from RD↓ to data input
Read data hold time
tRDH
0
ns
RD low-level width
tRDL1
(2 + 2n) tCY – 60
ns
tRDL2
(2.85 + 2n) tCY – 60
ns
Time from RD↓ to WAIT↓ input
Time from WR↓ to WAIT↓ input
tRDWT1
0.85tCY – 50
ns
tRDWT2
2tCY – 60
ns
tWRWT
2tCY – 60
ns
(2 + 2n) tCY
ns
WAIT low-level width
tWTL
(1.15 + 2n) tCY
Write data setup time
tWDS
(2.85 + 2n) tCY – 100
ns
Write data hold time
tWDH
20
ns
WR low-level width
tWRL
(2.85 + 2n) tCY – 60
ns
Delay time from ASTB↓ to RD↓
tASTRD
25
ns
Delay time from ASTB↓ to WR↓
tASTWR
0.85tCY + 20
ns
Delay time from RD↑ to ASTB↑
at external fetch
tRDAST
0.85tCY – 10
1.15tCY + 20
ns
Time from RD↑ to address hold
tRDADH
0.85tCY – 50
1.15tCY + 50
ns
Time from RD↑ to write data output
tRDWD
40
Time from WR↓ to write data output
tWRWD
0
50
ns
Time from WR↑ to address hold
tWRADH
0.85tCY
1.15tCY + 40
ns
Delay time from WAIT↑ to RD↑
tWTRD
1.15tCY + 40
3.15tCY + 40
ns
Delay time from WAIT↑ to WR↑
tWTWR
1.15tCY + 30
3.15tCY + 30
ns
at external fetch
Remarks
1.
MCS: Bit 0 of the oscillation mode selection register (OSMS)
2.
3.
PCC2 to PCC0: Bits 2 to 0 of the processor clock control register (PCC)
tCY = TCY/4
4.
n indicates the number of waits.
Data Sheet U12182EJ3V0DS
ns
47
µPD780053, 780054, 780055, 780056, 780058, 780053Y, 780054Y, 780055Y, 780056Y
(b) When MCS = 0 or PCC2 to PCC0 ≠ 000B (TA = –40 to +85°C, VDD = 2.7 to 5.5 V)
Parameter
Symbol
Conditions
MIN.
MAX.
Unit
ASTB high-level width
tASTH
tCY – 80
ns
Address setup time
tADS
tCY – 80
ns
Address hold time
tADH
0.4tCY – 10
Time from address to data input
tADD1
(3 + 2n) tCY – 160
ns
tADD2
(4 + 2n) tCY – 200
ns
tRDD1
(1.4 + 2n) tCY – 70
ns
tRDD2
(2.4 + 2n) tCY – 70
ns
Time from RD↓ to data input
Read data hold time
RD low-level width
Time from RD↓ to WAIT↓ input
Time from WR↓ to WAIT↓ input
ns
tRDH
0
ns
tRDL1
(1.4 + 2n) tCY – 20
ns
tRDL2
(2.4 + 2n) tCY – 20
ns
tRDWT1
tCY – 100
ns
tRDWT2
2tCY – 100
ns
2tCY – 100
ns
(2 + 2n) tCY
ns
tWRWT
WAIT low-level width
tWTL
(1 + 2n) tCY
Write data setup time
tWDS
(2.4 + 2n) tCY – 60
Write data hold time
tWDH
20
ns
WR low-level width
tWRL
(2.4 + 2n) tCY – 20
ns
Delay time from ASTB↓ to RD↓
tASTRD
0.4tCY – 30
ns
Delay time from ASTB↓ to WR↓
tASTWR
1.4tCY – 30
ns
Delay time from RD↑ to
ASTB↑ at external fetch
tRDAST
tCY – 10
tCY + 20
ns
Time from RD↑ to address
hold at external fetch
tRDADH
tCY – 50
tCY + 50
ns
Time from RD↑ to write data
output
tRDWD
0.4tCY – 20
Time from WR↓ to write data
output
tWRWD
0
60
ns
Time from WR↑ to address hold
tWRADH
tCY
tCY + 60
ns
Delay time from WAIT↑ to RD↑
tWTRD
0.6tCY + 180
2.6tCY + 180
ns
Delay time from WAIT↑ to WR↑
tWTWR
0.6tCY + 120
2.6tCY + 120
ns
Remarks
48
1.
MCS: Bit 0 of the oscillation mode selection register (OSMS)
2.
3.
PCC2 to PCC0: Bits 2 to 0 of the processor clock control register (PCC)
tCY = TCY/4
4.
n indicates the number of waits.
Data Sheet U12182EJ3V0DS
ns
ns
µPD780053, 780054, 780055, 780056, 780058, 780053Y, 780054Y, 780055Y, 780056Y
(c) When MCS = 0 or PCC2 to PCC0 ≠ 000B (TA = –40 to +85°C, VDD = 1.8 to 2.7 V)
Parameter
Symbol
Conditions
MIN.
MAX.
Unit
ASTB high-level width
tASTH
tCY – 150
ns
Address setup time
tADS
tCY – 150
ns
Address hold time
tADH
0.37tCY – 40
Time from address to data input
tADD1
(3 + 2n) tCY – 320
ns
tADD2
(4 + 2n) tCY – 300
ns
tRDD1
(1.37 + 2n) tCY – 120
ns
tRDD2
(2.37 + 2n) tCY – 120
ns
Time from RD↓ to data input
ns
Read data hold time
tRDH
0
ns
RD low-level width
tRDL1
(1.37 + 2n) tCY – 20
ns
tRDL2
(2.37 + 2n) tCY – 20
Time from RD↓ to WAIT↓ input
Time from WR↓ to WAIT↓ input
ns
tRDWT1
tCY – 200
ns
tRDWT2
2tCY – 200
ns
2tCY – 200
ns
(2 + 2n) tCY
ns
tWRWT
WAIT low-level width
tWTL
(1 + 2n) tCY
Write data setup time
tWDS
(2.37 + 2n) tCY – 100
ns
Write data hold time
tWDH
20
ns
WR low-level width
tWRL
(2.37 + 2n) tCY – 20
ns
Delay time from ASTB↓ to RD↓
tASTRD
0.37tCY – 50
ns
Delay time from ASTB↓ to WR↓
tASTWR
1.37tCY – 50
ns
Delay time from RD↑ to ASTB at
external fetch
tRDAST
tCY – 10
tCY + 20
ns
Time from RD↑ to address hold
tRDADH
tCY – 50
tCY + 50
ns
Time from RD↑ to write data output
tRDWD
0.37tCY – 40
Time from WR↓ to write data output
tWRWD
0
Time from WR↑ to address hold
tWRADH
tCY
tCY + 120
ns
Delay time from WAIT↑ to RD↑
tWTRD
0.63tCY + 350
2.63tCY + 350
ns
Delay time from WAIT↑ to WR↑
tWTWR
0.63tCY + 240
2.63tCY + 240
ns
at external fetch
Remarks
1.
2.
MCS: Bit 0 of the oscillation mode selection register (OSMS)
PCC2 to PCC0: Bits 2 to 0 of the processor clock control register (PCC)
3.
4.
tCY = TCY/4
n indicates the number of waits.
Data Sheet U12182EJ3V0DS
ns
120
ns
49
µPD780053, 780054, 780055, 780056, 780058, 780053Y, 780054Y, 780055Y, 780056Y
(3) Serial interface (TA = –40 to +85°C, VDD = 1.8 to 5.5 V)
(a) Serial interface channel 0
(i) 3-wire serial I/O mode (SCK0... Internal clock output)
Parameter
SCK0 cycle time
SCK0 high-/low-level
Symbol
tKCY1
tKH1, tKL1
Conditions
tSIK1
SI0 hold time
(from SCK0↑)
tKSI1
Delay time from SCK0↓
to SO0 output
tKSO1
TYP.
MAX.
Unit
4.5 V ≤ VDD ≤ 5.5 V
800
ns
2.7 V ≤ VDD < 4.5 V
1,600
ns
2.0 V ≤ VDD < 2.7 V
3,200
ns
4,800
ns
VDD = 4.5 to 5.5 V
tKCY1/2 – 50
ns
tKCY1/2 – 100
ns
4.5 V ≤ VDD ≤ 5.5 V
100
ns
2.7 V ≤ VDD < 4.5 V
150
ns
2.0 V ≤ VDD < 2.7 V
300
ns
400
ns
400
ns
width
SI0 setup time
(to SCK0↑)
MIN.
C = 100 pFNote
300
ns
MAX.
Unit
Note C is the load capacitance of the SCK0 and SO0 output lines.
(ii) 3-wire serial I/O mode (SCK0... External clock input)
Parameter
SCK0 cycle time
SCK0 high-/low-level
Symbol
tKCY2
tKH2, tKL2
width
SI0 setup time
(to SCK0↑)
tSIK2
SI0 hold time
(from SCK0↑)
tKSI2
Delay time from SCK0↓
tKSO2
Conditions
tR2, tF2
TYP.
4.5 V ≤ VDD ≤ 5.5 V
800
ns
2.7 V ≤ VDD < 4.5 V
1,600
ns
2.0 V ≤ VDD < 2.7 V
3,200
ns
4,800
ns
4.5 V ≤ VDD ≤ 5.5 V
400
ns
2.7 V ≤ VDD < 4.5 V
800
ns
2.0 V ≤ VDD < 2.7 V
1,600
ns
2,400
ns
100
ns
150
ns
400
ns
2.0 V ≤ VDD ≤ 5.5 V
C = 100 pFNote
VDD = 2.0 to 5.5V
to SO0 output
SCK0 rise/fall time
MIN.
When using external device
300
ns
500
ns
160
ns
1,000
ns
expansion function
When not using external device
expansion function
Note C is the load capacitance of the SO0 output line.
50
Data Sheet U12182EJ3V0DS
µPD780053, 780054, 780055, 780056, 780058, 780053Y, 780054Y, 780055Y, 780056Y
(iii) 2-wire serial I/O mode (SCK0... Internal clock output)
Parameter
SCK0 cycle time
Symbol
tKCY3
Conditions
R = 1 kΩ,
C = 100
SCK0 high-level width
SCK0 low-level width
SB0, SB1 setup time
pFNote
tKL3
(to SCK0↑)
SB0, SB1 hold time
(from SCK0↑)
tKSI3
Delay time from SCK0↓
tKSO3
MAX.
Unit
1,600
ns
2.0 V ≤ VDD ≤ 2.7 V
3,200
ns
4,800
ns
tKCY3/2 – 160
ns
tKCY3/2 – 190
ns
tKCY3/2 – 50
ns
tKCY3/2 – 100
ns
4.5 V ≤ VDD ≤ 5.5 V
300
ns
2.7 V ≤ VDD < 4.5 V
350
ns
2.0 V ≤ VDD < 2.7 V
400
ns
500
ns
600
ns
VDD = 4.5 to 5.5 V
tSIK3
TYP.
2.7 V ≤ VDD ≤ 5.5 V
VDD = 2.7 to 5.5 V
tKH3
MIN.
ns
0
300
ns
to SB0, SB1 output
Note
R and C are the load resistance and load capacitance of the SCK0, SB0, and SB1 output lines.
(iv) 2-wire serial I/O mode (SCK0... Internal clock input)
Parameter
SCK0 cycle time
SCK0 high-level width
SCK0 low-level width
SB0, SB1 setup time
Symbol
tKCY4
tKH4
tKL4
tSIK4
Conditions
MIN.
tKSI4
Delay time from SCK0↓
to SB0, SB1 output
tKSO4
SCK0 rise/fall time
Unit
1,600
ns
2.0 V ≤ VDD < 2.7 V
3,200
ns
4,800
ns
2.7 V ≤ VDD ≤ 5.5 V
650
ns
2.0 V ≤ VDD < 2.7 V
1,300
ns
2,100
ns
2.7 V ≤ VDD ≤ 5.5 V
800
ns
2.0 V ≤ VDD < 2.7 V
1,600
ns
2,400
ns
100
ns
150
ns
tKCY4/2
ns
VDD = 2.0 to 5.5 V
R = 1 kΩ,
C = 100
tR4, tF4
MAX.
2.7 V ≤ VDD ≤ 5.5 V
(to SCK0↑)
SB0, SB1 hold time
(from SCK0↑)
TYP.
pFNote
4.5 V ≤ VDD ≤ 5.5 V
0
300
ns
2.0 V ≤ VDD < 4.5 V
0
500
ns
0
800
ns
160
ns
1,000
ns
When using external device
expansion function
When not using external device
expansion function
Note
R and C are the load resistance and load capacitance of the SB0 and SB1 output lines.
Data Sheet U12182EJ3V0DS
51
µPD780053, 780054, 780055, 780056, 780058, 780053Y, 780054Y, 780055Y, 780056Y
(v) SBI mode (SCK0... Internal clock output) (µPD78005x only)
Parameter
SCK0 cycle time
Symbol
tKCY5
Conditions
MIN.
TYP.
MAX.
Unit
4.5 V ≤ VDD ≤ 5.5 V
800
ns
2.0 V ≤ VDD < 4.5 V
3,200
ns
4,800
ns
4.5 V ≤ VDD ≤ 5.5 V
SCK0 high-/low-level
width
tKH5, tKL5
SB0, SB1 setup time
(to SCK0↑)
tSIK5
SB0, SB1 hold time
(from SCK0↑)
tKSI5
Delay time from SCK0↓
to SB0, SB1 output
tKSO5
SB0, SB1↓ from SCK0↑
tKSB
tKCY5
ns
SCK0↓ from SB0, SB1↓
tSBK
tKCY5
ns
SB0, SB1 high-level width
tSBH
tKCY5
ns
SB0, SB1 low-level width
tSBL
tKCY5
ns
Note
tKCY5/2 – 50
ns
tKCY5/2 – 150
ns
4.5 V ≤ VDD ≤ 5.5 V
100
ns
2.0 V ≤ VDD < 4.5 V
300
ns
R = 1 kΩ,
C = 100
VDD = 4.5 to 5.5 V
pFNote
400
ns
tKCY5/2
ns
0
250
ns
0
1,000
ns
R and C are the load resistance and load capacitance of the SCK0, SB0, and SB1 output lines.
(vi) SBI mode (SCK0... External clock input) (µPD78005x only)
Parameter
SCK0 cycle time
SCK0 high-/low-level
width
SB0, SB1 setup time
(to SCK0↑)
Symbol
tKCY6
tKH6, tKL6
tSIK6
Conditions
MIN.
TYP.
MAX.
Unit
4.5 V ≤ VDD ≤ 5.5 V
800
ns
2.0 V ≤ VDD < 4.5 V
3,200
ns
4,800
ns
4.5 V ≤ VDD ≤ 5.5 V
400
ns
2.0 V ≤ VDD < 4.5 V
1,600
ns
2,400
ns
4.5 V ≤ VDD ≤ 5.5 V
100
ns
2.0 V ≤ VDD < 4.5 V
300
ns
400
ns
tKCY6/2
ns
SB0, SB1 hold time
(from SCK0↑)
tKSI6
Delay time from SCK0↓
to SB0, SB1 output
tKSO6
SB0, SB1↓ from SCK0↑
tKSB
tKCY6
ns
SCK0↓ from SB0, SB1↓
tSBK
tKCY6
ns
SB0, SB1 high-level width
tSBH
tKCY6
ns
SB0, SB1 low-level width
tSBL
tKCY6
ns
SCK0 rise/fall time
tR6, tF6
R = 1 kΩ,
C = 100 pFNote
VDD = 4.5 to 5.5 V
0
300
ns
0
1,000
ns
When using external device
expansion function
When not using external device
expansion function
Note
52
R and C are the load resistance and load capacitance of the SB0 and SB1 output lines.
Data Sheet U12182EJ3V0DS
160
ns
1,000
ns
µPD780053, 780054, 780055, 780056, 780058, 780053Y, 780054Y, 780055Y, 780056Y
(vii) I2C bus mode (SCL ... Internal clock output) (µPD7800xY only)
Parameter
SCL cycle time
Symbol
tKCY7
Conditions
R = 1 KΩ,
C = 100
SCL high-level width
SCL low-level width
pFNote
tKH7
SDA0, SDA1 setup time
(to SCL↑)
tSIK7
SDA0, SDA1 hold time
(from SCL↓)
tKSI7
Delay time from SCL↓
tKSO7
SDA0, SDA1↓ from SCL↑ or
SDA0, SDA1↑ from SCL↓
tKSB
SCL↓ from SDA0, SDA1↓
tSBK
Unit
µs
2.0 V ≤ VDD < 2.7 V
20
µs
30
µs
tKCY7 – 160
ns
tKCY7 – 190
ns
tKCY7 – 50
ns
tKCY7 – 100
ns
2.7 V ≤ VDD ≤ 5.5 V
200
ns
2.0 V ≤ VDD < 2.7 V
300
ns
400
ns
0
ns
4.5 V ≤ VDD ≤ 5.5 V
0
300
ns
2.0 V ≤ VDD < 4.5 V
0
500
ns
0
600
ns
VDD = 2.0 to 5.5 V
SDA0, SDA1 high-level width tSBH
Note
MAX.
10
VDD = 4.5 to 5.5 V
to SDA0, SDA1 output
TYP.
2.7 V ≤ VDD ≤ 5.5 V
VDD = 2.7 to 5.5 V
tKL7
MIN.
200
ns
400
ns
500
ns
500
ns
R and C are the load resistance and load capacitance of the SCL, SDA0, and SDA1 output lines.
(viii) I2C bus mode (SCL ... External clock input) (µPD78005xY only)
Parameter
SCL cycle time
SCL high-/low-level width
Symbol
Conditions
tKCY8
tKH8
VDD = 2.0 to 5.5 V
tKL8
SDA0, SDA1 setup time
(to SCL↑)
tSIK8
SDA0, SDA1 hold time
(from SCL↓)
tKSI8
Delay time from SCL↓
to SDA0, SDA1 output
tKSO8
SDA0, SDA1↓ from SCL↑ or
SDA0, SDA1↑ from SCL↑
tKSB
SCL↓ from SDA0, SDA1↓
SDA0, SDA1 high-level width
SCL rise/fall time
Note
VDD = 2.0 to 5.5 V
R = 1 kΩ,
C = 100
tSBK
tSBH
pFNote
MIN.
TYP.
MAX.
Unit
1,000
ns
400
ns
600
ns
200
ns
300
ns
0
ns
4.5 V ≤ VDD ≤ 5.5 V
0
300
ns
2.0 V ≤ VDD < 4.5 V
0
500
ns
0
600
ns
VDD = 2.0 to 5.5 V
VDD = 2.0 to 5.5 V
tR8
When using external device expansion
function
tF8
When not using external device
expansion function
200
ns
400
ns
500
ns
500
ns
800
ns
160
ns
1
µs
R and C are the load resistance and load capacitance of the SDA0 and SDA1 output lines.
Data Sheet U12182EJ3V0DS
53
µPD780053, 780054, 780055, 780056, 780058, 780053Y, 780054Y, 780055Y, 780056Y
(b) Serial interface channel 1
(i) 3-wire serial I/O mode (SCK1...Internal clock output)
Parameter
SCK1 cycle time
SCK1 high/low-level width
SI1 setup time (to SCK1↑)
SI1 hold time (from SCK1↑)
Delay time from SCK1↓ to SO1
output
Symbol
tKCY9
tKH9, tKL9
tSIK9
Conditions
TYP.
MAX.
Unit
4.5 V ≤ VDD ≤ 5.5 V
800
ns
2.7 V ≤ VDD < 4.5 V
1,600
ns
2.0 V ≤ VDD < 2.7 V
3,200
ns
4,800
ns
tKCY9/2 – 50
ns
tKCY9/2 – 100
ns
4.5 V ≤ VDD ≤ 5.5 V
100
ns
2.7 V ≤ VDD < 4.5 V
150
ns
2.0 V ≤ VDD < 2.7 V
300
ns
400
ns
400
ns
VDD = 4.5 to 5.5 V
tKSI9
tKSO9
MIN.
C = 100
pFNote
300
ns
MAX.
Unit
Note C is the load capacitance of the SCK1 and SO1 output lines.
(ii) 3-wire serial I/O mode (SCK1...External clock input)
Parameter
SCK1 cycle time
SCK1 high/low-level width
Symbol
tKCY10
tSIK10
SI1 hold time (from SCK1↑)
tKIS10
SCK1 rise/fall time
tKSO10
tR10, tF10
TYP.
ns
2.7 V ≤ VDD < 4.5 V
1,600
ns
2.0 V ≤ VDD < 2.7 V
3,200
ns
4,800
ns
400
ns
2.7 V ≤ VDD < 4.5 V
800
ns
2.0 V ≤ VDD < 2.7 V
1,600
ns
2,400
ns
100
ns
150
ns
400
ns
VDD = 2.0 to 5.5 V
C = 100
pFNote
VDD = 2.0 to 5.5 V
When using external device
expansion function
When not using external device
expansion function
Note C is the load capacitance of the SO1 output line.
54
MIN.
800
tKH10,tKL10 4.5 V ≤ VDD ≤ 5.5 V
SI1 setup time (to SCK1↑)
Delay time from SCK1↓ to SO1
output
Conditions
4.5 V ≤ VDD ≤ 5.5 V
Data Sheet U12182EJ3V0DS
300
ns
500
ns
160
ns
1,000
ns
µPD780053, 780054, 780055, 780056, 780058, 780053Y, 780054Y, 780055Y, 780056Y
(iii) 3-wire serial I/O mode with automatic transmit/receive function (SCK1...Internal clock output)
Parameter
SCK1 cycle time
SCK1 high-/low-level width
SI1 setup time (to SCK1↑)
Symbol
tKCY11
tSIK11
SI1 hold time (from SCK1↑)
tKSI11
tKSO11
STB↑ from SCK1↑
tSBD
Strobe signal high-level width
tSBW
MIN.
TYP.
MAX.
Unit
800
ns
2.7 V ≤ VDD < 4.5 V
1,600
ns
2.0 V ≤ VDD < 2.7 V
3,200
ns
tKH11,tKL11 VDD = 4.5 to 5.5 V
Delay time from SCK1↓ to SO1
output
Busy signal setup time
Conditions
4.5 V ≤ VDD ≤ 5.5 V
4,800
ns
tKCY11/2 – 50
ns
tKCY11/2 – 100
ns
4.5 V ≤ VDD ≤ 5.5 V
100
ns
2.7 V ≤ VDD < 4.5 V
150
ns
2.0 V ≤ VDD < 2.7 V
300
ns
400
ns
400
C = 100 pFNote
ns
300
ns
tKCY11/2 – 100
tKCY11/2 + 100
ns
2.7 V ≤ VDD < 5.5 V
tKCY11 – 30
tKCY11 + 30
ns
2.0 V < VDD < 2.7 V
tKCY11 – 60
tKCY11 + 60
ns
tKCY11 – 90
tKCY11 + 90
ns
tBYS
100
ns
(to busy signal detection timing)
Busy signal hold time
tBYH
(from busy signal detection timing)
4.5 V ≤ VDD ≤ 5.5 V
100
ns
2.7 V ≤ VDD < 4.5 V
150
ns
2.0 V ≤ VDD < 2.7 V
200
ns
300
SCK1↓ from busy inactive
tSPS
ns
2tKCY11
ns
Note C is the load capacitance of the SCK1 and SO1 output lines.
Data Sheet U12182EJ3V0DS
55
µPD780053, 780054, 780055, 780056, 780058, 780053Y, 780054Y, 780055Y, 780056Y
(iv) 3-wire serial I/O mode with automatic transmit/receive function (SCK1...External clock input)
Parameter
SCK1 cycle time
SCK1 high-/low-level width
SI1 setup time (to SCK1↑)
SI1 hold time (from SCK1↑)
Delay time from SCK1↓ to SO1
Symbol
tKCY12
tKH12,
tKL12
tSIK12
Conditions
tR12, tF12
Unit
ns
2.7 V ≤ VDD < 4.5 V
1,600
ns
2.0 V ≤ VDD < 2.7 V
3,200
ns
4,800
ns
4.5 V ≤ VDD ≤ 5.5 V
400
ns
2.7 V ≤ VDD < 4.5 V
800
ns
2.0 V ≤ VDD < 2.7 V
1,600
ns
2,400
ns
100
ns
150
ns
400
ns
VDD = 2.0 to 5.5 V
C = 100
pFNote
VDD = 2.0 to 5.5 V
When using external device
expansion function
When not using external device
expansion function
Note C is the load capacitance of the SO1 output line.
56
MAX.
800
output
SCK1 rise/fall time
TYP.
4.5 V ≤ VDD ≤ 5.5 V
tKSI12
tKSO12
MIN.
Data Sheet U12182EJ3V0DS
300
ns
500
ns
160
ns
1,000
ns
µPD780053, 780054, 780055, 780056, 780058, 780053Y, 780054Y, 780055Y, 780056Y
(c) Serial interface channel 2
(i) 3-wire serial I/O mode (SCK2...Internal clock output)
Parameter
SCK2 cycle time
Symbol
tKCY13
Conditions
MIN.
TYP.
MAX.
Unit
4.5 V ≤ VDD ≤ 5.5 V
800
ns
2.7 V ≤ VDD < 4.5 V
1,600
ns
2.0 V ≤ VDD < 2.7 V
3,200
ns
4,800
ns
tKCY13/2 – 50
ns
tKCY13/2 – 100
ns
SCK2 high-/low-level width
tKH13,
tKL13
VDD = 4.5 to 5.5 V
SI2 setup time (to SCK2↑)
tSIK13
4.5 V ≤ VDD ≤ 5.5 V
100
ns
2.7 V ≤ VDD < 4.5 V
150
ns
2.0 V ≤ VDD < 2.7 V
300
ns
400
ns
400
ns
SI2 hold time (from SCK2↑)
tKSI13
Delay time from SCK2↓ to SO2
output
tKSO13
C = 100 pFNote
300
ns
MAX.
Unit
Note C is the load capacitance of the SO2 output line.
(ii) 3-wire serial I/O mode (SCK2...External clock input)
Parameter
SCK2 cycle time
SCK2 high-/low-level width
SI2 setup time (to SCK2↑)
SI2 hold time (from SCK2↑)
Delay time from SCK2↓ to SO2
output
SCK2 rise/fall time
Symbol
tKCY14
tKH14,
tKL14
tSIK14
Conditions
TYP.
4.5 V ≤ VDD ≤ 5.5 V
800
ns
2.7 V ≤ VDD < 4.5 V
1,600
ns
2.0 V ≤ VDD < 2.7 V
3,200
ns
4,800
ns
400
ns
4.5 V ≤ VDD ≤ 5.5 V
2.7 V ≤ VDD < 4.5 V
800
ns
2.0 V ≤ VDD < 2.7 V
1,600
ns
2,400
ns
100
ns
150
ns
400
ns
VDD = 2.0 to 5.5 V
tKSI14
tKSO14
MIN.
C = 100
pFNote
VDD = 2.0 to 5.5 V
300
ns
500
ns
tR14,
Other than below
160
ns
tF14
VDD = 4.5 to 5.5 V
1
µs
When not using external device
expansion function
Note C is the load capacitance of the SO2 output line.
Data Sheet U12182EJ3V0DS
57
µPD780053, 780054, 780055, 780056, 780058, 780053Y, 780054Y, 780055Y, 780056Y
(iii) UART mode (Dedicated baud rate generator output)
Parameter
Symbol
Transfer rate
Conditions
MIN.
TYP.
MAX.
Unit
4.5 V ≤ VDD ≤ 5.5 V
78,125
bps
2.7 V ≤ VDD < 4.5 V
39,063
bps
2.0 V ≤ VDD < 2.7 V
19,531
bps
9,766
bps
MAX.
Unit
(iv) UART mode (External clock input)
Parameter
ASCK cycle time
ASCK high-/low-level width
Symbol
tKCY15
MIN.
TYP.
4.5 V ≤ VDD ≤ 5.5 V
800
ns
2.7 V ≤ VDD < 4.5 V
1,600
ns
2.0 V ≤ VDD < 2.7 V
3,200
ns
4,800
ns
tKH15,
4.5 V ≤ VDD ≤ 5.5 V
400
ns
tKL15
2.7 V ≤ VDD < 4.5 V
800
ns
2.0 V ≤ VDD < 2.7 V
1,600
ns
2,400
ns
4.5 V ≤ VDD ≤ 5.5 V
39,063
bps
2.7 V ≤ VDD < 4.5 V
19,531
bps
2.0 V ≤ VDD < 2.7 V
9,766
bps
6,510
bps
tR15,
VDD = 4.5 to 5.5 V,
1,000
ns
tF15
when not using external device
160
ns
Transfer rate
ASCK rise/fall time
Conditions
expansion function.
58
Data Sheet U12182EJ3V0DS
µPD780053, 780054, 780055, 780056, 780058, 780053Y, 780054Y, 780055Y, 780056Y
AC Timing Measurement Points (Excluding X1, XT1 Inputs)
0.8VDD
0.2VDD
0.8VDD
0.2VDD
Point of
measurement
Clock Timing
1/fX
tXL
tXH
VIH4 (MIN.)
VIL4 (MAX.)
X1 input
1/fXT
tXTL
tXTH
VIH5 (MIN.)
VIL5 (MAX.)
XT1 input
TI Timing
tTIL00, tTIL01
tTIH00, tTIH01
TI00, TI01
1/fTI1
tTIL1
tTIH1
TI1, TI2
Data Sheet U12182EJ3V0DS
59
µPD780053, 780054, 780055, 780056, 780058, 780053Y, 780054Y, 780055Y, 780056Y
Read/Write Operation
External fetch (no wait):
A8 to A15
Higher 8-bit address
tADD1
Lower
8-bit
address
AD0 to AD7
Hi-Z
Operation
code
tRDADH
tRDD1
tADS
tASTH
tADH
tRDAST
ASTB
RD
tRDL1
tASTRD
tRDH
External fetch (wait insertion):
A8 to A15
Higher 8-bit address
tADD1
Lower
8-bit
address
AD0 to AD7
Hi-Z
Operation
code
tRDADH
tRDD1
tADS
tASTH
tADH
tRDAST
ASTB
RD
tASTRD
tRDL1
tRDH
WAIT
tRDWT1
60
tWTL
Data Sheet U12182EJ3V0DS
tWTRD
µPD780053, 780054, 780055, 780056, 780058, 780053Y, 780054Y, 780055Y, 780056Y
External data access (no wait):
A8 to A15
Higher 8-bit address
tADD2
Lower
8-bit
address
AD0 to AD7
Hi-Z
Read data
Hi-Z
Hi-Z
Write data
tRDD2
tADS
tADH
tRDH
tASTH
ASTB
RD
tASTRD
tRDWD
tRDL2
tWDH
tWDS
tWRADH
tWRWD
WR
tASTWR
tWRL
External data access (wait insertion):
A8 to A15
Higher 8-bit address
tADD2
Lower
8-bit
address
AD0 to AD7
Hi-Z
Read data
Hi-Z
Hi-Z
Write data
tRDD2
tADS
tADH
tRDH
tASTH
ASTB
tASTRD
RD
tRDWD
tRDL2
tWDH
tWDS
tWDWR
WR
tASTWR
tWRL
tWRADH
WAIT
tRDWT2
tWTRD
tWTL
Data Sheet U12182EJ3V0DS
tWRWT
tWTL
tWTWR
61
µPD780053, 780054, 780055, 780056, 780058, 780053Y, 780054Y, 780055Y, 780056Y
Serial Transfer Timing
3-wire serial I/O mode:
tKCYm
tKLm
tKHm
tFn
tRn
SCK0 to SCK2
tSIKm
SI0 to SI2
tKSIm
Input data
tKSOm
SO0 to SO2
Output data
m = 1, 2, 9, 10, 13, 14
n = 2, 10, 14
2-wire serial I/O mode:
tKCY3, 4
tKL3, 4
tKH3, 4
tF4
tR4
SCK0
tSIK3, 4
tKSI3, 4
tKSO3, 4
SB0, SB1
62
Data Sheet U12182EJ3V0DS
µPD780053, 780054, 780055, 780056, 780058, 780053Y, 780054Y, 780055Y, 780056Y
SBI mode (bus release signal transfer):
tKCY5, 6
tKL5, 6
tKH5, 6
tF6
tR6
SCK0
tKSB
tSBL
tSBK
tSBH
tSIK5, 6
tKSI5, 6
SB0, SB1
tKSO5, 6
SBI mode (command signal transfer):
tKCY5,6
tKL5, 6
tR6
tKH5, 6
tF6
SCK0
tSIK5, 6
tSBK
tKSB
tKSI5, 6
SB0, SB1
tKSO5, 6
I2C bus mode:
tF8
tR8
tKCYm
SCL
tKLm
tKSIm
tSIKm
tKHm
tKSOm
tKSB
tKSB
tSBK
SDA0,
SDA1
tSBH
tSIKm
m = 7, 8
Data Sheet U12182EJ3V0DS
63
µPD780053, 780054, 780055, 780056, 780058, 780053Y, 780054Y, 780055Y, 780056Y
3-wire serial I/O mode with automatic transmit/receive function:
SO1
D2
SI1
D2
D1
D1
D0
D7
D0
D7
tKSI11, 12
tKH11, 12
tF12
tSIK11, 12
tKSO11, 12
SCK1
tR12
tKL11, 12
tSBD
tSBW
tKCY11, 12
STB
3-wire serial I/O mode with automatic transmit/receive function (busy processing):
SCK1
7
8
9Note
10Note
tBYS
10 + nNote
tBYH
1
tSPS
BUSY
(Active high)
Note
The signal is not actually driven low here; it is shown as such to indicate the timing.
UART mode (external clock input):
t KCY15
t KL15
t KH15
tR15
ASCK
64
Data Sheet U12182EJ3V0DS
tF15
µPD780053, 780054, 780055, 780056, 780058, 780053Y, 780054Y, 780055Y, 780056Y
A/D Converter Characteristics (Except µPD780058) (TA = –40 to +85°C, VDD = 1.8 to 5.5 V, AVSS = VSS = 0 V)
Parameter
Symbol
Conditions
Resolution
Overall errorNote 1
Conversion time
Analog input voltage
Reference voltage
AVREF0 current
MIN.
TYP.
8
8
MAX.
Unit
8
bit
1.8 V ≤ AVREF0 < 2.7 V
+1.4
%FSR
2.7 V ≤ AVREF0 < 5.5 V
+0.6
%FSR
TCONV1
1.8 V ≤ AVREF0 < 2.7 V
40
100
µs
TCONV2
2.7 V ≤ AVREF0 < 5.5 V
16
100
µs
AVSS
AVREF0
V
1.8
VDD
V
500
1,500
µA
0
3
µA
VIAN
AVREF0
IREF0
When A/D converter is
operatingNote 2
When A/D converter is not operatingNote 3
Notes 1. Excludes quantization error (±1/2 LSB). This value is indicated as a ratio to the full-scale value (%FSR).
2. The current flowing to the AVREF0 pin when bit 7 (CS) of the A/D converter mode register (ADM) is 1.
3. The current flowing to the AVREF0 pin when bit 7 (CS) of the A/D converter mode register (ADM) is 0.
A/D Converter Characteristics (µPD780058) (TA = –40 to +85°C, VDD = 2.7 to 5.5 V, AVSS = VSS = 0 V)
Parameter
Symbol
Conditions
Resolution
Overall
MIN.
TYP.
MAX.
Unit
8
8
8
bit
+0.6
%FSR
errorNote 1
Conversion time
Analog input voltage
Reference voltage
AVREF0 current
TCONV
16
100
µs
VIAN
AVSS
AVREF0
V
AVREF0
2.7
VDD
V
500
1,500
µA
0
3
µA
IREF0
When A/D converter is
operatingNote 2
When A/D converter is not
operatingNote 3
Notes 1. Excludes quantization error (±1/2 LSB). This value is indicated as a ratio to the full-scale value (%FSR).
2. The current flowing to the AVREF0 pin when bit 7 (CS) of the A/D converter mode register (ADM) is 1.
3. The current flowing to the AVREF0 pin when bit 7 (CS) of the A/D converter mode register (ADM) is 0.
Caution The operating voltage range of the A/D converter and D/A converter of the µPD780058 is VDD = 2.7 to
5.5 V.
Data Sheet U12182EJ3V0DS
65
µPD780053, 780054, 780055, 780056, 780058, 780053Y, 780054Y, 780055Y, 780056Y
D/A Converter Characteristics (Except µPD780058) (TA = –40 to +85°C, VDD = 1.8 to 5.5 V, AVSS = VSS = 0 V)
Parameter
Symbol
Conditions
MIN.
TYP.
MAX.
Unit
8
bit
R = 2 MΩNote 1
1.2
%
MΩNote 1
0.8
%
Resolution
Overall error
R=4
R = 10
MΩNote 1
C = 30 pFNote 1 AVREF1 = 1.8 to 2.7 V
Settling time
Output resistance
Analog reference voltage
AVREF1 current
RO
Note 2
Resistance between AVREF1 and AVSS RAIREF1
%
10
µs
15
µs
8
AVREF1
IREF1
0.6
kΩ
1.8
Note 2
DACS0, DACS1 =
55HNote 2
4
VDD
V
2.5
mA
8
kΩ
Notes 1. R and C are the D/A converter output pin load resistance and load capacitance, respectively.
2. Value for one D/A converter channel
Remark DACS0 and DACS1: D/A conversion value setting registers 0, 1
D/A Converter Characteristics (µPD780058) (TA = –40 to +85°C, VDD = 2.7 to 5.5 V, AVSS = VSS = 0 V)
Parameter
Symbol
Conditions
MIN.
TYP.
MAX.
Unit
8
bit
R=2
MΩNote 1
1.2
%
R=4
MΩNote 1
0.8
%
0.6
%
15
µs
Resolution
Overall error
R = 10 MΩNote 1
Settling time
Output resistance
Analog reference voltage
AVREF1 current
C = 30 pF
RO
Note 1
Note 2
AVREF1
IREF1
Resistance between AVREF1 and AVSS RAIREF1
8
2.7
kΩ
VDD
V
2.5
mA
Note 2
DACS0, DACS1 = 55HNote 2
4
8
kΩ
Notes 1. R and C are the D/A converter output pin load resistance and load capacitance, respectively.
2. Value for one D/A converter channel
Remark DACS0 and DACS1: D/A conversion value setting registers 0, 1
Caution The operating voltage range of the A/D converter and D/A converter of the µPD780058 is VDD = 2.7 to
5.5 V.
66
Data Sheet U12182EJ3V0DS
µPD780053, 780054, 780055, 780056, 780058, 780053Y, 780054Y, 780055Y, 780056Y
Data Memory STOP Mode Low Supply Voltage Data Retention Characteristics (TA = –40 to +85°C)
Parameter
Symbol
Data retention supply
voltage
VDDDR
Data retention supply
current
IDDDR
Release signal set time
tSREL
Oscillation stabilization
tWAIT
wait time
Conditions
MIN.
TYP.
1.8
VDDDR = 1.8 V
Subsystem clock stop and feed-back resistor
disconnected
0.1
MAX.
Unit
5.5
V
10
µA
µs
0
17
Release by RESET
2 /fX
ms
Release by interrupt request
Note
ms
Selection of 212/fXX and 214/fXX to 217/fXX is possible with bits 0 to 2 (OSTS0 to OSTS2) of the oscillation stabilization
time selection register (OSTS).
Note
Remark
fXX: Main system clock frequency (fX or fX/2)
fX: Main system clock oscillation frequency
Data Retention Timing (STOP Mode Release by RESET)
Internal reset operation
HALT mode
Operating mode
STOP mode
Data retension mode
VDD
VDDDR
tSREL
STOP instruction execution
RESET
tWAIT
Data Retention Timing (Standby Release Signal: STOP Mode Release by Interrupt Request Signal)
HALT mode
Operating mode
STOP mode
Data retention mode
VDD
VDDDR
tSREL
STOP instruction execution
Standby release signal
(Interrupt request)
tWAIT
Data Sheet U12182EJ3V0DS
67
µPD780053, 780054, 780055, 780056, 780058, 780053Y, 780054Y, 780055Y, 780056Y
Interrupt Request Input Timing
tINTL
tINTH
INTP0 to INTP5
RESET Input Timing
tRSL
RESET
68
Data Sheet U12182EJ3V0DS
µPD780053, 780054, 780055, 780056, 780058, 780053Y, 780054Y, 780055Y, 780056Y
13. CHARACTERISTICS CURVES (REFERENCE VALUES)
VDD vs IDD (fX = 5.0 MHz, fXX = 2.5 MHz)
(TA = 25°C)
10
PCC = 00H
PCC = 01H
PCC = 02H
PCC = 03H
PCC = 04H
PCC = 30H
HALT (X1 oscillating, XT1 oscillating)
Supply current IDD [mA]
1
0.1
PCC = B0H
HALT (X1 stopped, XT1 oscillating)
0.01
0.001
0
2
3
4
5
6
7
Supply voltage VDD [V]
Data Sheet U12182EJ3V0DS
69
µPD780053, 780054, 780055, 780056, 780058, 780053Y, 780054Y, 780055Y, 780056Y
VDD vs IDD (fX = fXX = 5.0 MHz)
10
PCC = 00H
PCC = 01H
PCC = 02H
PCC = 03H
PCC = 04H
PCC = 30H
HALT (X1 oscillating,
XT1 oscillating)
Supply current IDD [mA]
1
Approximately the same curve
0.1
PCC = B0H
HALT (X1 stopped, XT1 oscillating)
0.01
0.001
0
2
3
4
5
Supply voltage VDD [V]
70
Data Sheet U12182EJ3V0DS
6
7
µPD780053, 780054, 780055, 780056, 780058, 780053Y, 780054Y, 780055Y, 780056Y
14.
PACKAGE DRAWINGS
80-PIN PLASTIC QFP (14x14)
A
B
60
61
41
40
detail of lead end
S
C
D
R
Q
80
1
21
20
F
J
G
I
H
M
P
K
S
N
S
L
M
NOTE
Each lead centerline is located within 0.13 mm of
its true position (T.P.) at maximum material condition.
ITEM
MILLIMETERS
A
17.20±0.20
B
14.00±0.20
C
14.00±0.20
D
17.20±0.20
F
0.825
G
0.825
H
I
0.32±0.06
0.13
J
0.65 (T.P.)
K
1.60±0.20
L
0.80±0.20
M
0.17 +0.03
−0.07
N
P
0.10
1.40±0.10
Q
0.125±0.075
R
3° +7°
−3°
S
1.70 MAX.
P80GC-65-8BT-1
Data Sheet U12182EJ3V0DS
71
µPD780053, 780054, 780055, 780056, 780058, 780053Y, 780054Y, 780055Y, 780056Y
80-PIN PLASTIC TQFP (FINE PITCH) (12x12)
A
B
60
41
61
40
detail of lead end
S
C
D
Q
80
R
21
1
20
F
G
J
I
H
M
K
P
S
N
S
L
M
NOTE
ITEM
Each lead centerline is located within 0.10 mm of
its true position (T.P.) at maximum material condition.
MILLIMETERS
A
14.0±0.2
B
12.0±0.2
C
12.0±0.2
D
14.0±0.2
F
1.25
G
1.25
H
I
0.22±0.05
0.10
J
0.5 (T.P.)
K
1.0±0.2
L
0.5±0.2
M
0.145±0.05
N
P
0.10
1.0±0.05
Q
0.1±0.05
R
3° +7°
−3°
S
1.2 MAX.
S80GK-50-9EU-1
72
Data Sheet U12182EJ3V0DS
µPD780053, 780054, 780055, 780056, 780058, 780053Y, 780054Y, 780055Y, 780056Y
15.
RECOMMENDED SOLDERING CONDITIONS
The µ PD78005x and 78005xY should be soldered and mounted under the following recommended conditions.
For details of the recommended soldering conditions, refer to the document Semiconductor Device
Mounting Technology Manual (C10535E).
For soldering methods and conditions other than those recommended below, contact an NEC sales
representative.
Table 15-1. Surface Mounting Type Soldering Conditions (1/2)
µ PD780053GC-×××-8BT: 80-pin plastic QFP (14 × 14)
µ PD780054GC-×××-8BT: 80-pin plastic QFP (14 × 14)
µ PD780055GC-×××-8BT: 80-pin plastic QFP (14 × 14)
µ PD780056GC-×××-8BT: 80-pin plastic QFP (14 × 14)
µ PD780058GC-×××-8BT: 80-pin plastic QFP (14 × 14)
µ PD780053YGC-×××-8BT: 80-pin plastic QFP (14 × 14)
µ PD780054YGC-×××-8BT: 80-pin plastic QFP (14 × 14)
µ PD780055YGC-×××-8BT: 80-pin plastic QFP (14 × 14)
µ PD780056YGC-×××-8BT: 80-pin plastic QFP (14 × 14)
Soldering
Soldering Conditions
Recommended
Method
Condition Symbol
Infrared reflow
Package peak temperature: 235°C, Time: 30 seconds max.
IR35-00-2
(at 210°C or higher), Count: Twice or less
VPS
Package peak temperature: 215°C, Time: 40 seconds max.
VP15-00-2
(at 200°C or higher), Count: Twice or less
Wave soldering
Soldering bath temperature: 260°C or less, Time: 10 seconds max.,
WS60-00-1
Count: Once, Preheating temperature: 120°C max. (package surface temperature)
Partial heating
Caution
Pin temperature: 300°C or less, Time: 3 seconds max. (per pin row)
–
Do not use different soldering methods together (except for partial heating).
Data Sheet U12182EJ3V0DS
73
µPD780053, 780054, 780055, 780056, 780058, 780053Y, 780054Y, 780055Y, 780056Y
Table 15-1. Surface Mounting Type Soldering Conditions (2/2)
µ PD780053GK-×××-9EU: 80-pin plastic TQFP (12 × 12)
µ PD780054GK-×××-9EU: 80-pin plastic TQFP (12 × 12)
µ PD780055GK-×××-9EU: 80-pin plastic TQFP (12 × 12)
µ PD780056GK-×××-9EU: 80-pin plastic TQFP (12 × 12)
µ PD780058GK-×××-9EU: 80-pin plastic TQFP (12 × 12)
µ PD780053YGK-×××-9EU: 80-pin plastic TQFP (12 × 12)
µ PD780054YGK-×××-9EU: 80-pin plastic TQFP (12 × 12)
µ PD780055YGK-×××-9EU: 80-pin plastic TQFP (12 × 12)
µ PD780056YGK-×××-9EU: 80-pin plastic TQFP (12 × 12)
Soldering
Soldering Conditions
Method
Recommended
Condition Symbol
Infrared reflow
Package peak temperature: 235°C, Time: 30 seconds max. (at 210°C or higher),
IR35-107-2
Count: Twice or less, Exposure limit: 7 daysNote (after that, prebake at 125°C for 10 hours)
VPS
Package peak temperature: 215°C, Time: 40 seconds max. (at 200°C or higher),
VP15-107-2
Count: Twice or less, Exposure limit: 7 daysNote (after that, prebake at 125°C for 10 hours)
Wave soldering
Partial heating
–
Pin temperature: 300°C or less, Time: 3 seconds max. (per pin row)
–
–
Note After opening the dry pack, store it below 25°C and 65% RH for the allowable storage period.
Caution
74
Do not use different soldering methods together (except for partial heating).
Data Sheet U12182EJ3V0DS
µPD780053, 780054, 780055, 780056, 780058, 780053Y, 780054Y, 780055Y, 780056Y
APPENDIX A.
DEVELOPMENT TOOLS
The following development tools are available for system development using the µ PD780058 and 780058Y
Subseries. Also, refer to (5) Cautions on using development tools.
(1) Language processing software
RA78K0
Assembler package common to the 78K/0 Series
CC78K0
C compiler package common to the 78K/0 Series
DF780058
Device file for the µ PD780058, 780058Y Subseries
CC78K0-L
C compiler library source file common to the 78K/0 Series
(2) Flash memory writing tools
Flashpro III (Part number:
FL-PR3, PG-FL3)
Dedicated flash programmer for microcontrollers incorporating flash memory
FA-80GC-8BT
FA-80GK-9EU
Adapter for flash memory writing
(3) Debugging tools
• When using the IE-78K0-NS in-circuit emulator
IE-78K0-NS
In-circuit emulator common to the 78K/0 Series
IE-70000-MC-PS-B
Power supply unit for IE-78K0-NS
IE-78K0-NS-PA
Performance board to enhance and expand the functions of the IE-78K0-NS
IE-70000-98-IF-C
Interface adapter used when a PC-9800 series PC (except notebook types) is used as
the host machine (C bus supported)
IE-70000-CD-IF-A
PC card and interface cable used when a PC-9800 series notebook-types PC is used as
the host machine (PCMCIA socket supported)
IE-70000-PC-IF-C
Adapter necessary when an IBM PC/AT TM or compatible is used as the host machine
(ISA bus supported)
IE-70000-PCI-IF-A
Interface adapter necessary when using a PC with PCI bus as the host machine
IE-780308-NS-EM1
Emulation board common to the µ PD780308 Subseries
NP-80GC
Emulation probe for 80-pin plastic QFP (GC-8BT type)
NP-80GK
Emulation probe for 80-pin plastic TQFP (GK-9EU type)
TGK-080SDW
Conversion adapter to connect the NP-80GK and a target system board 80-pin plastic
TQFP (GK-9EU type) can be mounted
EV-9200GC-80
Socket to be mounted on a target system board made for 80-pin plastic QFP (GC-8BT
type)
ID78K0-NS
Integrated debugger for IE-78K0-NS
SM78K0
System simulator common to the 78K/0 Series
DF780058
Device file for the µ PD780058, 780058Y Subseries
Data Sheet U12182EJ3V0DS
75
µPD780053, 780054, 780055, 780056, 780058, 780053Y, 780054Y, 780055Y, 780056Y
• When using the IE-78001-R-A in-circuit emulator
IE-78001-R-A
In-circuit emulator common to the 78K/0 Series
IE-70000-98-IF-C
Adapter used when PC-9800 series PC (except notebook type) is used as host machine
(C bus supported)
IE-70000-PC-IF-C
Interface adapter when using IBM PC/AT or compatible as host machine (ISA bus
supported)
IE-78000-R-SV3
Interface adapter and cable used when EWS is used as the host machine
IE-780308-NS-EM1
IE-780308-R-EM
Emulation board common to the µ PD780308 Subseries
IE-78K0-R-EX1
Emulation probe conversion board necessary when using the IE-780308-NS-EM1 on the
IE-78001-R-A
EP-78230GC-R
Emulation probe for 80-pin plastic QFP (GC-8BT type)
EP-78054GK-R
Emulation probe for 80-pin plastic TQFP (GK-9EU type)
TGK-080SDW
Conversion adapter to connect the EP-78054GK-R and a target system on which an 80pin plastic TQFP (GK-9EU type) can be mounted
EV-9200GC-80
Socket to be mounted on a target system board made for 80-pin plastic QFP (GC-8BT
type)
ID78K0
Integrated debugger for IE-78001-R-A
SM78K0
78K/0 Series common system simulator
DF780058
Device file for the µ PD780058, 780058Y Subseries
(4) Real-time OS
RX78K0
Real-time OS for the 78K/0 Series
MX78K0
OS for the 78K/0 Series
76
Data Sheet U12182EJ3V0DS
µPD780053, 780054, 780055, 780056, 780058, 780053Y, 780054Y, 780055Y, 780056Y
(5) Cautions on using development tools
• The ID78K0-NS, ID78K0, and SM78K0 are used in combination with the DF780058.
• The CC78K0 and RX78K0 are used in combination with the RA78K0 and DF780058.
• The FL-PR3, FA-80GC-8BT, FA80GK-9EU, NP-80GC, and NP-80GK are products of Naito Densei Machida
Mfg. Co., Ltd. (TEL: +81-44-822-3813).
• TGK-080SDW is a product made by TOKYO ELETECH CORPORATION.
For further information, contact Daimaru Kogyo, Ltd.
Tokyo Electronics Department (TEL: +81-3-3820-7112)
Osaka Electronics Department (TEL: +81-6-6-244-6672)
• For third-party development tools, see the Single-Chip Microcontroller Development Tool Selection Guide
(U11069E).
• The host machine and OS suitable for each software are as follows:
Host Machine [OS]
PC
EWS
Windows TM]
Software
PC-9800 series [Japanese
IBM PC/AT compatibles
[Japanese/English Windows]
HP9000 series 700 TM [HP-UX TM ]
SPARCstation TM [SunOS TM]
NEWS TM (RISC) [NEWS-OS TM ]
RA78K0
√ Note
√
CC78K0
√ Note
√
ID78K0-NS
√
–
ID78K0
√
√
SM78K0
√
–
RX78K0
√ Note
√
MX78K0
√ Note
√
Note DOS-based software
Data Sheet U12182EJ3V0DS
77
µPD780053, 780054, 780055, 780056, 780058, 780053Y, 780054Y, 780055Y, 780056Y
APPENDIX B.
RELATED DOCUMENTS
The related documents indicated in this publication may include preliminary versions. However, preliminary versions
are not marked as such.
Documents Related to Devices
Document Name
Document No.
µPD780058, 780058Y Subseries User’s Manual
U12013E
µPD780053, 780054, 780055, 780056, 780058, 780053Y, 780054Y, 780055Y,
This document
780056Y Data Sheet
µPD78F0058, 78F0058Y Data Sheet
U12092E
78K/0 Series User’s Manual Instruction
U12326E
Documents Related to Development Tools (User’s Manuals)
Document Name
RA78K0 Assembler Package
CC78K0 C Compiler
Document No.
Operation
U11802E
Assembly Language
U11801E
Structured Assembly
Language
U11789E
Operation
U11517E
Language
IE-78K0-NS
U11518E
U13731E
IE-78001-R-A
To be prepared
IE-780308-NS-EM1
U13304E
IE-780308-R-EM
U11362E
EP-78230
EEU-1515
EP-78054GK-R
–
SM78K0S, SM78K0 System Simulator Ver.2.10 or Later
Operation
U14611E
SM78K Series System Simulator Ver.2.10 or Later
External Part User Open
Interface Specifications
U15006E
ID78K0-NS Integrated Debugger Ver.2.00 or Later
Operation
U14379E
Windows Based
Windows Based
ID78K0 Integrated Debugger Windows Based
Caution
Reference
U11539E
Guide
U11649E
The related documents listed above are subject to change without notice. Be sure to use the latest
version of each document for designing.
78
Data Sheet U12182EJ3V0DS
µPD780053, 780054, 780055, 780056, 780058, 780053Y, 780054Y, 780055Y, 780056Y
Documents Related to Embedded Software (User’s Manuals)
Document Name
78K/0 Series Real-Time OS
78K/0 Series OS MX78K0
Document No.
Fundamentals
U11537E
Installation
U11536E
Fundamental
U12257E
Other Related Documents
Document Name
Document No.
SEMICONDUCTOR SELECTION GUIDE Products & Packages (CD-ROM)
X13769X
Semiconductor Device Mounting Technology Manual
C10535E
Quality Grades on NEC Semiconductor Devices
C11531E
NEC Semiconductor Device Reliability/Quality Control System
C10983E
Guide to Prevent Damage for Semiconductor Devices by Electrostatic Discharge (ESD)
C11892E
Caution
The related documents listed above are subject to change without notice. Be sure to use the latest
version of each document for designing.
Data Sheet U12182EJ3V0DS
79
µPD780053, 780054, 780055, 780056, 780058, 780053Y, 780054Y, 780055Y, 780056Y
NOTES FOR CMOS DEVICES
1
PRECAUTION AGAINST ESD FOR SEMICONDUCTORS
Note:
Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and
ultimately degrade the device operation. Steps must be taken to stop generation of static electricity
as much as possible, and quickly dissipate it once, when it has occurred. Environmental control
must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using
insulators that easily build static electricity. Semiconductor devices must be stored and transported
in an anti-static container, static shielding bag or conductive material. All test and measurement
tools including work bench and floor should be grounded. The operator should be grounded using
wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need
to be taken for PW boards with semiconductor devices on it.
2
HANDLING OF UNUSED INPUT PINS FOR CMOS
Note:
No connection for CMOS device inputs can be cause of malfunction. If no connection is provided
to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence
causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels
of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused
pin should be connected to V DD or GND with a resistor, if it is considered to have a possibility of
being an output pin. All handling related to the unused pins must be judged device by device and
related specifications governing the devices.
3
STATUS BEFORE INITIALIZATION OF MOS DEVICES
Note:
Power-on does not necessarily define initial status of MOS device. Production process of MOS
does not define the initial operation status of the device. Immediately after the power source is
turned ON, the devices with reset function have not yet been initialized. Hence, power-on does
not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the
reset signal is received. Reset operation must be executed immediately after power-on for devices
having reset function.
Purchase of NEC I2C components conveys a license under the Philips I2C Patent Rights to use these
components in an I 2C system, provided thst the system conforms to the I 2C Standard Specification as
defined by Philips.
FIP and IEbus are trademarks of NEC Corporation.
Windows is either a registered trademark or trademark of Microsoft Corporation in the United States and/or
other countries.
PC/AT is a trademark of IBM Corporation.
HP9000 series 700 and HP-UX are trademarks of Hewlett-Packard Company.
SPARCstation is a trademark of SPARC International, Inc.
Solaris and SunOS are trademarks of Sun Microsystems, Inc.
NEWS and NEWS-OS are trademarks of Sony Corporation.
80
Data Sheet U12182EJ3V0DS
µPD780053, 780054, 780055, 780056, 780058, 780053Y, 780054Y, 780055Y, 780056Y
Regional Information
Some information contained in this document may vary from country to country. Before using any NEC
product in your application, pIease contact the NEC office in your country to obtain a list of authorized
representatives and distributors. They will verify:
•
Device availability
•
Ordering information
•
Product release schedule
•
Availability of related technical literature
•
Development environment specifications (for example, specifications for third-party tools and
components, host computers, power plugs, AC supply voltages, and so forth)
•
Network requirements
In addition, trademarks, registered trademarks, export restrictions, and other legal issues may also vary
from country to country.
NEC Electronics Inc. (U.S.)
NEC Electronics (Germany) GmbH
NEC Electronics Hong Kong Ltd.
Santa Clara, California
Tel: 408-588-6000
800-366-9782
Fax: 408-588-6130
800-729-9288
Benelux Office
Eindhoven, The Netherlands
Tel: 040-2445845
Fax: 040-2444580
Hong Kong
Tel: 2886-9318
Fax: 2886-9022/9044
NEC Electronics (France) S.A.
Velizy-Villacoublay, France
Tel: 01-3067-5800
Fax: 01-3067-5899
Seoul Branch
Seoul, Korea
Tel: 02-528-0303
Fax: 02-528-4411
NEC Electronics (France) S.A.
NEC Electronics Singapore Pte. Ltd.
Milton Keynes, UK
Tel: 01908-691-133
Fax: 01908-670-290
Madrid Office
Madrid, Spain
Tel: 091-504-2787
Fax: 091-504-2860
Novena Square, Singapore
Tel: 253-8311
Fax: 250-3583
NEC Electronics Italiana s.r.l.
NEC Electronics (Germany) GmbH
Milano, Italy
Tel: 02-66 75 41
Fax: 02-66 75 42 99
Scandinavia Office
Taeby, Sweden
Tel: 08-63 80 820
Fax: 08-63 80 388
NEC Electronics (Germany) GmbH
Duesseldorf, Germany
Tel: 0211-65 03 02
Fax: 0211-65 03 490
NEC Electronics (UK) Ltd.
NEC Electronics Hong Kong Ltd.
NEC Electronics Taiwan Ltd.
Taipei, Taiwan
Tel: 02-2719-2377
Fax: 02-2719-5951
NEC do Brasil S.A.
Electron Devices Division
Guarulhos-SP, Brasil
Tel: 11-6462-6810
Fax: 11-6462-6829
J01.2
Data Sheet U12182EJ3V0DS
81
µPD780053, 780054, 780055, 780056, 780058, 780053Y, 780054Y, 780055Y, 780056Y
The export of this product from Japan is regulated by the Japanese government. To export this product may be prohibited
without governmental license, the need for which must be judged by the customer. The export or re-export of this product
from a country other than Japan may also be prohibited without a license from that country. Please call an NEC sales
representative.
• The information in this document is current as of November, 2000. The information is subject to
change without notice. For actual design-in, refer to the latest publications of NEC's data sheets or
data books, etc., for the most up-to-date specifications of NEC semiconductor products. Not all
products and/or types are available in every country. Please check with an NEC sales representative
for availability and additional information.
• No part of this document may be copied or reproduced in any form or by any means without prior
written consent of NEC. NEC assumes no responsibility for any errors that may appear in this document.
• NEC does not assume any liability for infringement of patents, copyrights or other intellectual property rights of
third parties by or arising from the use of NEC semiconductor products listed in this document or any other
liability arising from the use of such products. No license, express, implied or otherwise, is granted under any
patents, copyrights or other intellectual property rights of NEC or others.
• Descriptions of circuits, software and other related information in this document are provided for illustrative
purposes in semiconductor product operation and application examples. The incorporation of these
circuits, software and information in the design of customer's equipment shall be done under the full
responsibility of customer. NEC assumes no responsibility for any losses incurred by customers or third
parties arising from the use of these circuits, software and information.
• While NEC endeavours to enhance the quality, reliability and safety of NEC semiconductor products, customers
agree and acknowledge that the possibility of defects thereof cannot be eliminated entirely. To minimize
risks of damage to property or injury (including death) to persons arising from defects in NEC
semiconductor products, customers must incorporate sufficient safety measures in their design, such as
redundancy, fire-containment, and anti-failure features.
• NEC semiconductor products are classified into the following three quality grades:
"Standard", "Special" and "Specific". The "Specific" quality grade applies only to semiconductor products
developed based on a customer-designated "quality assurance program" for a specific application. The
recommended applications of a semiconductor product depend on its quality grade, as indicated below.
Customers must check the quality grade of each semiconductor product before using it in a particular
application.
"Standard": Computers, office equipment, communications equipment, test and measurement equipment, audio
and visual equipment, home electronic appliances, machine tools, personal electronic equipment
and industrial robots
"Special": Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster
systems, anti-crime systems, safety equipment and medical equipment (not specifically designed
for life support)
"Specific": Aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life
support systems and medical equipment for life support, etc.
The quality grade of NEC semiconductor products is "Standard" unless otherwise expressly specified in NEC's
data sheets or data books, etc. If customers wish to use NEC semiconductor products in applications not
intended by NEC, they must contact an NEC sales representative in advance to determine NEC's willingness
to support a given application.
(Note)
(1) "NEC" as used in this statement means NEC Corporation and also includes its majority-owned subsidiaries.
(2) "NEC semiconductor products" means any semiconductor product developed or manufactured by or for
NEC (as defined above).
M8E 00. 4