DATA SHEET MOS INTEGRATED CIRCUIT µPD789304, 789306, 789314, 789316 8-BIT SINGLE-CHIP MICROCONTROLLER The µPD789304, 789306, 789314, and 789316 belong to the µPD789306, 789316 Subseries (for LCD drivers) in the 78K/0S Series. Flash memory versions (µPD78F9306, 78F9316) that can be operated using the same power supply voltage as mask ROM versions are available, along with various development tools. Detailed function descriptions are provided in the following user’s manuals. Be sure to read them before designing. µPD789306, 789316 Subseries User’s Manual: U14800E 78K/0S Series User’s Manual Instructions: U11047E FEATURES • ROM and RAM capacities Item Program Memory (ROM) Part Number • Data Memory Internal High-Speed RAM µPD789304, 789314 8 KB µPD789306, 789316 16 KB 512 bytes LCD Display RAM 24 bytes Main system clock Ceramic/crystal oscillation: µPD789304, 789306 RC oscillation: • I/O ports: 23 • Serial interface: 2 channels µPD789314, 789316 Switchable between 3-wire serial I/O mode and UART mode: 1 channel 3-wire serial I/O mode: • 1 channel LCD controller/driver Segment signals: 24, common signals: 4 • Timer: 5 channels • Power supply voltage: VDD = 1.8 to 5.5 V APPLICATIONS Remote control devices, healthcare equipment, etc. The information in this document is subject to change without notice. Before using this document, please confirm that this is the latest version. Not all devices/types available in every country. Please check with local NEC representative for availability and additional information. Document No. U14384EJ1V0DS00 (1st edition) Date Published March 2001 N CP(K) Printed in Japan The mark shows major revised points. © 1999 1999 1996, µPD789304, 789306, 789314, 789316 ORDERING INFORMATION Part Number Package µPD789304GC-×××-AB8 64-pin plastic QFP (14 × 14) µPD789304GK-×××-9ET 64-pin plastic TQFP (12 × 12) µPD789306GC-×××-AB8 64-pin plastic QFP (14 × 14) µPD789306GK-×××-9ET 64-pin plastic TQFP (12 × 12) µPD789314GC-×××-AB8 64-pin plastic QFP (14 × 14) µPD789314GK-×××-9ET 64-pin plastic TQFP (12 × 12) µPD789316GC-×××-AB8 64-pin plastic QFP (14 × 14) µPD789316GK-×××-9ET 64-pin plastic TQFP (12 × 12) Remark 2 ××× indicates ROM code suffix. Data Sheet U14384EJ1V0DS µPD789304, 789306, 789314, 789316 78K/0S SERIES LINEUP The products in the 78K/0S Series are listed below. The names enclosed in boxes are subseries names. Products in mass production Products under development Y subseries products support SMB. Small-scale package, general-purpose applications 44-pin 42-/44-pin 30-pin 28-pin µ PD789074 with added subsystem clock µ PD789014 with enhanced timer and increased ROM, RAM capacity µ PD789026 with enhanced timer µ PD789046 µ PD789026 µPD789074 µ PD789014 On-chip UART and capable of low voltage (1.8 V) operation Small-scale package, general-purpose applications and A/D converter 44-pin 44-pin 30-pin 30-pin 30-pin 30-pin 30-pin 30-pin µ PD789177 µ PD789167 µ PD789156 µ PD789146 µ PD789134A µ PD789124A µ PD789114A µ PD789104A µ PD789177Y µ PD789167Y µ PD789167 with enhanced A/D converter µ PD789104A with enhanced timer µ PD789146 with enhanced A/D converter µ PD789104A with added EEPROMTM µ PD789124A with enhanced A/D converter RC oscillation version of the µ PD789104A µ PD789104A with enhanced A/D converter µ PD789026 with added A/D converter and multiplier Inverter control 44-pin µ PD789842 On-chip inverter controller and UART VFD drive 78K/0S Series 52-pin µ PD789871 Total display outputs: 25 LCD drive 80-pin 80-pin 80-pin 64-pin 64-pin 64-pin 64-pin 64-pin 64-pin µ PD789488 µ PD789417A µ PD789407A µ PD789456 µ PD789446 µ PD789436 µ PD789426 µ PD789316 µ PD789306 A/D converter and on-chip voltage booster type LCD (28 × 4) µ PD789407A with enhanced A/D converter A/D converter and resistance division type LCD (28 × 4) µ PD789446 with enhanced A/D converter A/D converter and on-chip voltage booster type LCD (15 × 4) µPD789426 with enhanced A/D A/D converter and on-chip voltage booster type LCD (5 × 4) RC oscillation version of the µPD789306 On-chip voltage booster type LCD (24 × 4) Dot LCD drive 144-pin 88-pin µ PD789835 µ PD789830 Segment/common outputs: 96 Segments: 40, commons: 16 ASSP 80-pin 52-pin µ PD789477 µ PD789467 52-pin µ PD789327 µ PD789803 µPD789800 µ PD789840 µ PD789861 µ PD789860 64-pin 44-pin 44-pin 20-pin 20-pin µ PD789488 with added remote control receiver and resistance division type LCD For remote controller, with A/D converter and on-chip voltage booster type LCD For remote controller, with SIO and resistance division type LCD For PC keyboard, on-chip USB HUB function For PC keyboard, on-chip USB function For keypad, on-chip POC RC oscillation version of the µPD789860 For keyless entry, on-chip POC and key return circuit Data Sheet U14384EJ1V0DS 3 µPD789304, 789306, 789314, 789316 The major functional differences among the subseries are listed below. Function VDD ROM Capacity 8-Bit 16-Bit Watch WDT 8-Bit 10-Bit A/D A/D Serial Interface Subseries Name Small-scale package, generalpurpose applications µPD789046 16 K µPD789026 4 K to 16 K µPD789074 2 K to 8 K µPD789014 2 K to 4 K 2 ch − Smallscale package, generalpurpose applications and A/D converter µPD789177 16 K to 24 K 3 ch 1 ch 1 ch 1 ch 1 ch 1 ch − − − 1 ch (UART: 1 ch) I/O MIN. Value Remarks 34 1.8 V − 24 22 − − 8 ch 8 ch − − 4 ch 4 ch − − 4 ch 4 ch − RC-oscillation version µPD789114A − 4 ch − µPD789104A 4 ch − 1 ch µPD789167 µPD789156 8 K to 16 K − 1 ch µPD789146 µPD789134A 2 K to 8 K µPD789124A 1 ch (UART: 1 ch) 31 20 On-chip EEPROM Inverter control µPD789842 8 K to 16 K 3 ch Note 1 ch 1 ch 8 ch − 1 ch (UART: 1 ch) 30 4.0 V − VFD drive µPD789871 4 K to 8 K 3 ch – 1 ch 1 ch – – 1 ch 33 2.7 V – LCD drive µPD789488 32 K 3 ch 1 ch 1 ch 1 ch − 8 ch 2 ch (UART: 1 ch) 45 1.8 V − µPD789417A 12 K to 24 K 7 ch 1 ch (UART: 1 ch) 43 µPD789407A 7 ch − – 6 ch 6 ch – µPD789436 – 6 ch µPD789426 6 ch – µPD789456 µPD789446 µPD789316 12 K to 16 K 2 ch 8 K to 16 K – 30 40 2 ch (UART: 1 ch) 23 µPD789306 Dot LCD drive ASSP – µPD789835 24 K to 60 K 6 ch – µPD789830 24 K 1 ch 1 ch µPD789477 24 K 3 ch 1 ch µPD789467 4 K to 24 K 2 ch – 1 ch 1 ch 3 ch 1 ch 1 ch 8 ch 8 K to 16 K µPD789800 8K µPD789840 − 4 ch 4K − µPD789860 28 1.8 V − 30 2.7 V – 2 ch (UART: 1 ch) – 45 1.8 V On-chip LCD 18 1 ch 21 2 ch (USB: 1 ch) 41 3.6 V 1 ch 29 2.8 V – − 31 4.0 V 14 1.8 V RC-oscillation version, on-chip EEPROM On-chip EEPROM Note 10-bit timer: 1 channel 4 1 ch (UART: 1 ch) 1 ch – µPD789803 – – µPD789327 µPD789861 RC-oscillation version Data Sheet U14384EJ1V0DS µPD789304, 789306, 789314, 789316 OVERVIEW OF FUNCTIONS µPD789304 Item Internal memory ROM 8 KB High-speed RAM 512 bytes LCD display RAM 24 bytes µPD789306 16 KB Main system clock (oscillation frequency) Ceramic/crystal oscillation (1.0 to 5.0 MHz) Subsystem clock (oscillation frequency) Crystal oscillation (32.768 kHz) Minimum instruction execution time 0.4 µs/1.6 µs (@ 5.0 MHz operation with main system clock) µPD789314 8 KB µPD789316 16 KB RC oscillation (2.0 to 4.0 MHz) 0.5 µs/2.0 µs (@ 4.0 MHz operation with main system clock) 122 µs (@ 32.768 kHz operation with subsystem clock) General-purpose registers 8 bits × 8 registers Instruction set • 16-bit operation • Bit manipulation (set, reset, test) I/O ports Total: • CMOS I/O: • N-ch open drain: 23 19 4 Timers • • • • 1 channel 2 channels 1 channel 1 channel Serial interface • Switchable between 3-wire serial I/O mode and UART mode: 1 channel • 3-wire serial I/O mode: 1 channel LCD controller/driver • Segment signal outputs: 24 (Max.) • Common signal outputs: 4 (Max.) Vectored interrupt Maskable sources Non-maskable Internal: 9, External: 5 Power supply voltage VDD = 1.8 to 5.5 V Operating ambient temperature TA = –40 to +85°C Package • 64-pin plastic QFP (14 × 14) • 64-pin plastic TQFP (12 × 12) 16-bit timer: 8-bit timer/event counter: Watch timer: Watchdog timer: Internal: 1 Data Sheet U14384EJ1V0DS 5 µPD789304, 789306, 789314, 789316 CONTENTS 1. PIN CONFIGURATION (TOP VIEW) ..................................................................................................................... 7 2. BLOCK DIAGRAM ................................................................................................................................................ 9 3. PIN FUNCTIONS ................................................................................................................................................. 10 3.1 Port Pins ................................................................................................................................................... 10 3.2 Non-Port Pins ........................................................................................................................................... 11 3.3 Pin I/O Circuits and Recommended Connection of Unused Pins ............................................................. 12 4. MEMORY SPACE................................................................................................................................................ 14 5. PERIPHERAL HARDWARE FUNCTIONS .......................................................................................................... 15 5.1 Ports ......................................................................................................................................................... 15 5.2 Clock Generator........................................................................................................................................ 16 5.3 Timer......................................................................................................................................................... 17 5.4 Serial Interface.......................................................................................................................................... 22 5.5 LCD Controller/Driver................................................................................................................................ 25 6. INTERRUPT FUNCTIONS................................................................................................................................... 27 7. STANDBY FUNCTION ........................................................................................................................................ 29 8. RESET FUNCTION.............................................................................................................................................. 29 9. MASK OPTIONS ................................................................................................................................................. 29 10. OVERVIEW OF INSTRUCTION SET .................................................................................................................. 30 10.1 Conventions.............................................................................................................................................. 30 10.2 List of Operations...................................................................................................................................... 32 11. ELECTRICAL SPECIFICATIONS ....................................................................................................................... 37 12. CHARACTERISTICS CURVES OF LCD CONTROLLER/DRIVER (REFERENCE VALUES)............................ 54 13. PACKAGE DRAWINGS ...................................................................................................................................... 56 14. RECOMMENDED SOLDERING CONDITIONS................................................................................................... 58 APPENDIX A. DEVELOPMENT TOOLS ................................................................................................................. 59 APPENDIX B. RELATED DOCUMENTS................................................................................................................. 61 6 Data Sheet U14384EJ1V0DS µPD789304, 789306, 789314, 789316 1. PIN CONFIGURATION (TOP VIEW) 64-pin plastic QFP (14 × 14) 64-pin plastic TQFP (12 × 12) µPD789304GK-×××-9ET µPD789306GC-×××-AB8 µPD789306GK-×××-9ET µPD789314GC-×××-AB8 µPD789314GK-×××-9ET µPD789316GC-×××-AB8 µPD789316GK-×××-9ET P20/SCK10 P21/SO10 P22/SI10 P23/SCK20/ASCK20 P24/SO20/TxD20 P25/SI20/RxD20 P26/TO20 P30/INTP0/CPT20 P31/INTP1/TO30/TMI40 P32/INTP2/TO40 P33/INTP3 P10 P11 P12 P13 S23 µPD789304GC-×××-AB8 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 1 47 2 46 3 45 4 44 5 43 6 42 7 41 8 40 9 39 10 38 11 37 12 36 13 35 14 34 15 33 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 S22 S21 S20 S19 S18 S17 S16 S15 S14 S13 S12 S11 S10 S9 S8 S7 CAPH CAPL VLC0 VLC1 VLC2 COM0 COM1 COM2 COM3 S0 S1 S2 S3 S4 S5 S6 P50 P51 P52 P53 IC XT1 XT2 VDD VSS X1 (CL1) X2 (CL2) RESET P00/KR0 P01/KR1 P02/KR2 P03/KR3 Caution Connect the IC (Internally Connected) pin directly to the VSS pin. Remark Pin names enclosed in parentheses are when using the µPD789314, 789316. Data Sheet U14384EJ1V0DS 7 µPD789304, 789306, 789314, 789316 ASCK20: Asynchronous serial input RESET: Reset CAPH, CAPL: LCD power supply capacitance control RxD20: Receive data CL1, CL2: RC oscillator S0 to S23: Segment output COM0 to COM3: Common output SCK10, SCK20: Serial clock CPT20: Capture trigger input SI10, SI20: Serial input IC: Internally connected SO10, SO20: Serial output INTP0 to INTP3: External interrupt input TMI40: Timer input KR0 to KR3: Key return TO20, TO30, TO40: Timer output P00 to P03: Port 0 TxD20: Transmit data P10 to P13: Port 1 VDD: Port 2 VLC0 P30 to P33: Port 3 VSS: Ground P50 to P53: Port 5 X1, X2: Crystal/ceramic oscillator XT1, XT2: Crystal oscillator P20 to P26: 8 Power supply to Data Sheet U14384EJ1V0DS VLC2: LCD power supply µPD789304, 789306, 789314, 789316 2. BLOCK DIAGRAM TO30/TMI40/P31 TO40/P32 TMI40/TO30/P31 TO20/P26 CPT20/P30 8-bit timer 30 8-bit timer/event counter 40 Cascaded 16-bit timer/event counter 16-bit timer 20 Watch timer 78K/0S CPU core ROM Port 0 P00 to P03 Port 1 P10 to P13 Port 2 P20 to P26 Port 3 P30 to P33 Port 5 P50 to P53 Watchdog timer SCK10/P20 SO10/P21 SI10/P22 Serial interface 10 SCK20/ASCK20/P23 SO20/TxD20/P24 SI20/RxD20/P25 Serial interface 20 RAM RAM space for LCD data System control RESET X1 (CL1) X2 (CL2) XT1 XT2 INTP0/P30 INTP1/P31 Interrupt control INTP2/P32 S0 to S23 COM0 to COM3 VLC0 to VLC2 CAPH CAPL INTP3/P33 KR0/P00 to KR3/P03 LCD controller driver VDD Remark VSS IC Pin names enclosed in parentheses are when using the µPD789314, 789316. Data Sheet U14384EJ1V0DS 9 µPD789304, 789306, 789314, 789316 3. PIN FUNCTIONS 3.1 Port Pins Pin Name I/O Function After Reset P00 to P03 I/O Port 0. 4-bit I/O port. Input/output can be specified in 1-bit units. When used as an input port, an on-chip pull-up resistor can be specified in port units by software. Input P10 to P13 I/O Port 1. 4-bit I/O port. Input/output can be specified in 1-bit units. When used as an input port, an on-chip pull-up resistor can be specified in port units by software. Input P20 I/O Port 2. 7-bit I/O port. Input/output can be specified in 1-bit units. When used as an input port, an on-chip pull-up resistor can be specified in 1-bit units by software. Input P21 P22 P23 Alternate Function KR0 to KR3 – SCK10 SO10 SI10 SCK20/ASCK20 P24 SO20/TxD20 P25 SI20/RxD20 P26 TO20 P30 I/O P31 P32 P33 P50 to P53 10 I/O Port 3. 4-bit I/O port. Input/output can be specified in 1-bit units. When used as an input port, an on-chip pull-up resistor can be specified in 1-bit units by software. Input Port 5. 4-bit I/O port. Input/output can be specified in 1-bit units. An on-chip pull-up resistor can be specified in bit units by the mask option. Input Data Sheet U14384EJ1V0DS INTP0/CPT20 INTP1/TO30/TMI40 INTP2/TO40 INTP3 – µPD789304, 789306, 789314, 789316 3.2 Non-Port Pins Pin Name INTP0 I/O Input INTP1 Function External interrupt input for which the valid edge (rising edge, falling edge, or both rising and falling edges) can be specified After Reset Alternate Function P30/CPT20 Input P31/TO30/TMI40 INTP2 P32/TO40 INTP3 P33 KR0 to KR3 Input Key return signal detection Input P00 to P03 SCK10 I/O Serial clock input/output for serial interface (SIO10) Input P20 SCK20 Serial clock input/output for serial interface (SIO20) Input SI10 SI20 Serial data input for SIO10 serial interface P23/ASCK20 Input P22 Serial data input for SIO20 serial interface Output SO10 SO20 Serial data output for SIO10 serial interface P25/RxD20 Input P21 Serial data output for SIO20 serial interface P24/TxD20 ASCK20 Input Serial clock input for asynchronous serial interface Input P23/SCK20 RxD20 Input Serial data input for asynchronous serial interface Input P25/SI20 TxD20 Output Serial data output for asynchronous serial interface Input P24/SO20 TO20 Output 16-bit timer (TM20) output Input P26 CPT20 Input Capture edge input Input P30/INTP0 TO30 Output 8-bit timer (TM30) output Input P31/INTP1/TMI40 TO40 Output 8-bit timer (TM40) output Input P32/INTP2 TMI40 Input External count clock input to 8-bit timer (TM40) Input P31/INTP1/TO30 S0 to S23 Output Segment signal output for LCD controller/driver Output – COM0 to COM3 Output Common signal output for LCD controller/driver Output – VLC0 to VLC2 – LCD drive voltage – – CAPH – Connection pin for LCD driver’s capacitor – – CAPL – – – – – – – – – – – – – – – Note 1 X1 Input Note 1 X2 Connecting crystal resonator for main system clock oscillation – Note 2 CL1 Input Note 2 CL2 – XT1 Input XT2 Connections to resistor (R) and capacitor (C) for main system clock oscillation Connecting crystal resonator for subsystem clock oscillation – RESET Input System reset input Input – VDD – Positive power supply – – VSS – Ground potential – – IC – Internally connected. Connect directly to VSS. – – Notes 1. µPD789304, 789306 only 2. µPD789314, 789316 only Data Sheet U14384EJ1V0DS 11 µPD789304, 789306, 789314, 789316 3.3 Pin I/O Circuits and Recommended Connection of Unused Pins The I/O circuit type of each pin and recommended connection of unused pins are shown in Table 3-1. For the I/O circuit configuration of each type, refer to Figure 3-1. Table 3-1. Types of Pin I/O Circuits and Recommended Connection of Unused Pins Pin Name I/O Circuit Type P00/KR0 to P03/KR3 8-A P10 to P13 5-A P20/SCK10 8-A I/O Recommended Connection of Unused Pins Input: Independently connect to VDD or VSS via a resistor. Output: Leave open. I/O P21/SO10 P22/SI10 P23/SCK20/ASCK20 P24/SO20/TxD20 P25/SI20/RxD20 P26/TO20 Input: Independently connect to VSS via a resistor. Output: Leave open. P30/INTP0/CPT20 P31/INTP1/TO30/ TMI40 P32/INTP2/TO40 P33/INTP3 P50 to P53 13-W S0 to S23 17 COM0 to COM3 18 VLC0 to VLC2 – CAPH, CAPL – XT1 – XT2 Input: Independently connect to VDD via a resistor. Output: Leave open. Output – Input – RESET 2 Input IC – – 12 Leave open. Connect to VSS. Leave open. – Directly connect to VSS. Data Sheet U14384EJ1V0DS µPD789304, 789306, 789314, 789316 Figure 3-1. Pin I/O Circuits Type 2 Type 13-W VDD Pull-up resistor (mask option) IN/OUT IN Output data Output disable N-ch VSS Schmitt-triggered input with hysteresis characteristics Input enable Middle-voltage input buffer Type 5-A Type 17 VDD VLC0 P-ch Pull-up enable P-ch VLC1 VDD P-ch N-ch P-ch Data P-ch IN/OUT Output disable N-ch SEG data OUT N-ch P-ch VLC2 VSS N-ch N-ch Input enable Type 8-A Type 18 VDD VLC0 Pull-up enable P-ch VLC1 VDD Data P-ch N-ch P-ch N-ch P-ch IN/OUT Output disable P-ch OUT COM data N-ch P-ch P-ch VLC2 VSS N-ch N-ch N-ch Data Sheet U14384EJ1V0DS 13 µPD789304, 789306, 789314, 789316 4. MEMORY SPACE Figure 4-1 shows the memory map of the µPD789304, 789306, 789314, and 789316. Figure 4-1. Memory Map FFFFH Special function registers (SFR) 256 × 8 bits FF00H FEFFH Internal high-speed RAM 512 × 8 bits FD00H FCFFH Reserved FA18H FA17H Data memory space LCD display RAM 24 × 4 bits FA00H F9FFH nnnnH+1 nnnnH nnnnH Reserved Program area Program memory space Internal ROMNote 0080H 007FH CALLT table area 0040H 003FH Program area 0022H 0021H 0000H 0000H Note The internal ROM capacity depends on the product (see the following table). Part Number 14 Last Address of Internal ROM nnnnH µPD789304, 789314 1FFFH µPD789306, 789316 3FFFH Data Sheet U14384EJ1V0DS Vector table area µPD789304, 789306, 789314, 789316 5. PERIPHERAL HARDWARE FUNCTIONS 5.1 Ports The I/O ports are listed below. • CMOS I/O: 19 • N-ch open-drain I/O: 4 Table 5-1. Port Functions Port Name Pin Name Function Port 0 P00 to P03 I/O port. Input/output can be specified in 1-bit units. When used as an input port, an on-chip pull-up resistor can be specified by software. Port 1 P10 to P13 I/O port. Input/output can be specified in 1-bit units. When used as an input port, an on-chip pull-up resistor can be specified by software. Port 2 P20 to P26 I/O port. Input/output can be specified in 1-bit units. When used as an input port, an on-chip pull-up resistor can be specified by software. Port 3 P30 to P33 I/O port. Input/output can be specified in 1-bit units. When used as an input port, an on-chip pull-up resistor can be specified by software. Port 5 P50 to P53 I/O port. Input/output can be specified in 1-bit units. An on-chip pull-up resistor can be specified by the mask option. Data Sheet U14384EJ1V0DS 15 µPD789304, 789306, 789314, 789316 5.2 Clock Generator The specifications of the main system clock generator differ depending on the product as shown below. (1) Main system clock generator • Ceramic/crystal oscillation: µPD789304, 789306 This generator’s oscillation frequency range is 1.0 to 5.0 MHz. The minimum instruction execution time can be changed from 0.4 to 1.6 µs (@ 5.0 MHz operation). • RC oscillation: µPD789314, 789316 This generator’s oscillation frequency range is 2.0 to 4.0 MHz. The minimum instruction execution time can be changed from 0.5 to 2.0 µs (@ 4.0 MHz operation). (2) Subsystem clock generator (crystal oscillation) This generator’s oscillation frequency is 32.768 kHz. The minimum instruction execution time is 122 µs (@ 32.768 kHz operation). Figure 5-1. Block Diagram of Clock Generator Internal bus FRC SCC XT1 XT2 Sub oscillation mode register (SCKM) fXT Subsystem clock oscillator Watch timer LCD controller/driver Prescaler 1/2 X2 (CL2) Main system clock oscillator STOP fXT 2 Prescaler fX (fcc) Clock to peripheral hardware fX 22 ( f2CC2 ) Selector X1 (CL1) MCC PCC1 Standby controller Wait controller CPU clock (fCPU) CLS CSS0 Processor clock control register (PCC) Subsystem clock control register (CSS) Internal bus Remark 16 Pins names enclosed in parentheses are when using the RC oscillation (µPD789314, 789316). Data Sheet U14384EJ1V0DS µPD789304, 789306, 789314, 789316 5.3 Timer Five timer channels are incorporated. • 16-bit timer (TM20): 1 channel • 8-bit timer (TM30, TM40): 2 channels • Watch timer (WT): 1 channel • Watchdog timer (WTM): 1 channel Table 5-2. Timer Operation TM20 TM30 TM40 WT WTM 1 channel 1 channel 1 channel 1 channel 1 channel – 1 channel 1 channel – – 1 output 1 output 1 output – – Square wave output – 1 output 1 output – – Interrupt request 1 1 1 1 1 Operation Interval time mode External event counter Function Timer output Figure 5-2. Block Diagram of 16-Bit Timer (TM20) Internal bus 16-bit timer mode control register 20 (TMC20) P26 output latch TOF20 CPT201 CPT200 TOC20 TCL201 TCL200 TOE20 PM26 TO20/P26 F/F 16-bit compare register 20 (CR20) TOD20 16-bit timer mode control register 20 (TMC20) fCLK fCLK/22 fCLK/25 fCLK/27 CPT20/P30 /INTP0 Selector Match Edge detector INTTM20 OVF 16-bit timer counter 20 (TM20) 16-bit capture register 20 (TCP20) 16-bit counter read buffer Internal bus Remark fCLK: fX or fCC Data Sheet U14384EJ1V0DS 17 18 Figure 5-3. Block Diagram of Timer 30 (TM30) Internal bus 8-bit timer mode control register 30 (TMC30) P30 output latch TCE30 TCL301 TCL300 TMD300 TOE30 PM30 8-bit compare register 30 (CR30) Decoder Selector Match TO30/P31/ INTP1/TMI40 Carrier clock (during carrier generator mode) or timer 40 output signal (during mode other than carrier generator mode) (from Figure 5-4 (C)) Selector 8-bit timer counter 30 (TM30) OVF Clear Internal reset signal From Figure 5-4 (D) Count operation start signal (during cascade connection mode) Selector Cascade connection mode INTTM30 From Figure 5-4 (E) Timer 40 match signal (during cascade connection mode) To Figure 5-4 (G) Timer 30 match signal (during carrier generator mode) To Figure 5-4 (F) Timer 30 match signal (during cascade connection mode) Remark fCLK: fX or fCC µPD789304, 789306, 789314, 789316 Data Sheet U14384EJ1V0DS fCLK/24 fCLK/28 Timer 40 interrupt request signal (from Figure 5-4 (B)) Selector Bit 7 of TM40 (from Figure 5-4 (A)) Figure 5-4. Block Diagram of Timer 40 (TM40) Internal bus Carrier generator output control register 40 (TCA40) 8-bit timer mode control register 40 (TMC40) 8-bit compare register H40 (CRH40) TCE40 TCL402 TCL401 TCL400 TMD401 TMD400 TOE40 8-bit compare register 40 (CR40) RMC40 NRZB40 NRZ40 Decoder From Figure 5-3 (G) Timer counter match signal from timer 30 (during carrier generator mode) Selector TMI/2 Clear Selector Prescaler To Figure 5-3 (C) Carrier clock (during carrier generator mode) or timer 40 output signal (during mode other than carrier generator mode) 8-bit timer counter 40 (TM40) TMI40/P31/ INTP1/TO30 TO40/P32/INTP2 OVF Carrier generator mode PWM mode Reset TMI/22 Cascade connection mode TMI/23 To Figure 5-3 (A) Bit 7 of TM40 (during cascade connection mode) Internal reset signal INTTM40 To Figure 5-3 (D) Count operation start signal to timer 30 (during cascade connection mode) To Figure 5-3 (E) TM40 timer counter match signal (during cascade connection mode) From Figure 5-3 (F) TM30 match signal (during cascade connection mode) Note For details, see Figure 5-5. 19 Remark fCLK: fX or fCC To Figure 5-3 (B) Timer 40 interrupt request signal count clock input signal to TM30 µPD789304, 789306, 789314, 789316 Data Sheet U14384EJ1V0DS fCLK/23 fCLK/27 Output control circuitNote F/F Match µPD789304, 789306, 789314, 789316 Figure 5-5. Block Diagram of Output Controller (Timer 40) TOE40 RMC40 NRZ40 PM32 Selector P32 output latch F/F TO40/P32/ INTP2 Carrier clock (during carrier generator mode) or timer 40 output signal (during mode other than carrier generator mode) Carrier generator mode Figure 5-6. Block Diagram of Watch Timer (WT) fCLK/27 5-bit counter 9-bit prescaler fW fW 24 fW 25 fW 26 fW 27 fW 28 fW 29 WTM7 WTM6 WTM5 WTM4 WTM1 WTM0 Watch timer mode control register (WTM) Internal bus Remark 20 INTWT Clear Selector fXT Selector Clear fCLK: fX or fCC Data Sheet U14384EJ1V0DS INTWTI µPD789304, 789306, 789314, 789316 Figure 5-7. Block Diagram of Watchdog Timer (WTM) Internal bus fCLK 24 WDTMK Prescaler fCLK 26 fCLK 28 fCLK 210 7-bit counter Clear Controller Selector WDTIF INTWDT maskable interrupt request RESET INTWDT non-maskable interrupt request 3 WDCS2 WDCS1 WDCS0 RUN WDTM4 WDTM3 Watchdog timer clock select register (WDCS) Watchdog timer mode register (WDTM) Internal bus Remark fCLK: fX or fCC Data Sheet U14384EJ1V0DS 21 Remark SCK10/P20 SO10/P21 SI10/P22 PM20 fCLK: fX or fCC PM21 CSIE10 TPS101 TPS100 DIR10 CSCK10 Serial operation mode register 10 (CSIM10) Clock controller F/F Serial clock counter TPS101 TPS100 fCLK/22 fCLK/23 fCLK/24 fCLK/25 Interrupt request generator Serial shift register 10 (SIO10) Selector Data Sheet U14384EJ1V0DS Selector 22 Internal bus Figure 5-8. Block Diagram of Serial Interface 10 INTCSI10 µPD789304, 789306, 789314, 789316 5.4 Serial Interface 5.4.1 Serial interface 10 (SIO10) Serial interface 10 (SIO10) has the following two types of modes. • Operation stop mode • 3-wire serial I/O mode Data Sheet U14384EJ1V0DS PM24 PM23 INTSR20/INTCSI20 FE20 OVE20 CSIE20 DIR20 CSCK20 Serial interface mode register 20 (CSIM20) Reception controller Receive shift register 20 (RXS20) PE20 Internal bus Note See Figure 5-10 for the configuration of the baud rate generator. ASCK20/SCK20/ P23 TxD20/SO20/ P24 RxD20/SI20/ P25 Direction controller Receive buffer register 20 (RXB20/SIO20) CSIE20 TXE20 RXE20 Transmission controller Transmit shift register 20 (TXS20/SIO20) Direction controller Asynchronous serial interface status register 20 (ASIS20) Internal bus SL20 fX/2 to fX/28 CSCK20 Note Baud rate generator control register 20 (BRGC20) TPS203 TPS202 TPS201 TPS200 4 Baud rate generator INTST20 SCK20 output controller TXE20 RXE20 PS201 PS200 CL20 Asynchronous serial interface mode register 20 (ASIM20) Figure 5-9. Block Diagram of Serial Interface 20 µPD789304, 789306, 789314, 789316 5.4.2 Serial interface 20 (SIO20) Serial interface 20 (SIO20) has the following three types of modes. • Operation stop mode • Asynchronous serial interface (UART) mode • 3-wire serial I/O mode 23 24 Figure 5-10. Block Diagram of Baud Rate Generator 20 Clock for receive detection 1/2 Selector Selector Receive shift clock 1/2 Transmit clock counter Receive clock counter TXE20 SCK20/ASCK20/P20 RXE20 CSIE20 Receive detection 4 TPS203 TPS202 TPS201 TPS200 Baud rate generator control register 20 (BRGC20) Internal bus µPD789304, 789306, 789314, 789316 Data Sheet U14384EJ1V0DS fXX/2 fXX/22 fXX/23 fXX/24 fXX/25 fXX/26 fXX/27 fXX/28 Selector Transmit shift clock µPD789304, 789306, 789314, 789316 5.5 LCD Controller/Driver The LCD controller/driver has the following functions. (1) Enables automatic output of segment signals and common signals by automatically reading from display data memory. (2) Two types of display modes can be selected: • 1/3 duty (1/3 bias) • 1/4 duty (1/3 bias) (3) Any of four frame frequency settings can be selected for each display mode. (4) There are up to 24 segment signal outputs (S0 to S23) and four common signal outputs (COM0 to COM3). (5) Operation using the subsystem clock is also supported. Data Sheet U14384EJ1V0DS 25 26 Figure 5-11. Block Diagram of LCD Controller/Driver LCD clock control register 0 (LCDC0) LCDC03 LCDC02 LCDC01 LCDC00 2 Display data memory · · · · · · · · · · FA17H 76543210 3 Prescaler fLCD 26 fLCD 27 fLCD 28 fLCD 29 LCD fLCD clock selector 3210 Selector Timing controller LCDON0 3210 Selector LCDON0 Voltage amplifier circuit LCD drive voltage controller Common driver Segment driver COM0 COM1 COM2 COM3 S0 Segment driver · · · · · · · · · · CAPH Remark fCLK: fX or fCC CAPL VLC2 VLC1 VLC0 S23 µPD789304, 789306, 789314, 789316 Data Sheet U14384EJ1V0DS fCLK/25 fCLK/26 fCLK/27 fXT Selector 2 Internal bus LCD voltage amplifier control register 0 (LCDVA0) FA00H LCDON0 VAON0 LIPS0 LCDM02 LCDM01 LCDM00 GAIN 76543210 LCD display mode register 0 (LCDM0) µPD789304, 789306, 789314, 789316 6. INTERRUPT FUNCTIONS A total of 15 interrupt sources divided into the following two types are provided. • Non-maskable: 1 • Maskable: 14 Table 6-1. Interrupt Source List Interrupt Type Note 1 Priority Interrupt Source Name Internal/ External Vector Table Address Basic Configuration Note 2 Type 0004H (A) Trigger Internal Nonmaskable – INTWDT Watchdog timer overflow (with watchdog timer mode 1 selected) Maskable 0 INTWDT Watchdog timer overflow (with interval timer mode selected) 1 INTP0 Pin input edge detection 2 INTP1 0008H 3 INTP2 000AH 4 INTP3 000CH 5 INTSR20 End of serial interface 20 UART reception INTCSI20 End of serial interface 20 3-wire SIO transfer reception 6 INTCSI10 End of serial interface 10 3-wire SIO transfer reception 0010H 7 INTST20 End of serial interface 20 UART transmission 0012H 8 INTWTI Watch timer interval timer interrupt 0014H 9 INTTM20 Generation of match signal of 16-bit timer 20 0016H 10 INTTM30 Generation of match signal of 8-bit timer 30 0018H 11 INTTM40 Generation of match signal of 8-bit timer/event counter 40 001AH 12 INTWT Watch timer interrupt 001EH 13 INTKR00 Key return signal detection Notes 1. (B) External Internal External 0006H 000EH 0020H (C) (B) (C) Default priority is the priority order when several maskable interrupt requests are generated at the same time. 0 is the highest order and 13 is the lowest order. 2. Remark Basic configuration types (A) to (C) correspond to (A) to (C) in Figure 6-1. Two watchdog timer interrupt sources (INTWDT): a non-maskable interrupt and a maskable interrupt (internal), are available, either of which can be selected. Data Sheet U14384EJ1V0DS 27 µPD789304, 789306, 789314, 789316 Figure 6-1. Basic Configuration of Interrupt Function (A) Internal non-maskable interrupt Internal bus Vector table address generator Interrupt request Standby release signal (B) Internal maskable interrupt Internal bus MK Interrupt request IE Vector table address generator IF Standby release signal (C) External maskable interrupt Internal bus INTM0, INTM1, KRM00 Interrupt request Edge detector MK IE Vector table address generator IF Standby release signal INTM0: External interrupt mode register 0 INTM1: External interrupt mode register 1 KRM00: Key return mode register 00 28 IF: Interrupt request flag IE: Interrupt enable flag MK: Interrupt mask flag Data Sheet U14384EJ1V0DS µPD789304, 789306, 789314, 789316 7. STANDBY FUNCTION The following two standby modes are available for further reduction of system current consumption. • HALT mode: In this mode, the CPU operation clock is stopped. The average current consumption can be reduced by intermittent operation by combining this mode with the normal operation. • STOP mode: In this mode, oscillation of the main system clock is stopped. All operations performed on the main system clock are suspended resulting in extremely small power consumption. Figure 7-1. Standby Function System clock operation Interrupt request ( STOP instruction Interrupt request STOP mode Main system clock oscillation stopped HALT instruction ( ( HALT mode Clock supply to CPU halted, oscillation maintained ( 8. RESET FUNCTION The following two reset methods are available. • External reset by RESET pin • Internal reset by watchdog timer program loop time detection 9. MASK OPTIONS The µPD789304, 789306, 789314, and 789316 have the following mask options. • Mask options for P50 to P53 An on-chip pull-up resistor can be selected. <1> Specifies on-chip pull-up resistor in 1-bit units. <2> Does not specify on-chip pull-up resistor. Data Sheet U14384EJ1V0DS 29 µPD789304, 789306, 789314, 789316 10. OVERVIEW OF INSTRUCTION SET This section lists the instruction set for the µPD789304, 789306, 789314, and 789316. 10.1 Conventions 10.1.1 Operand expressions and description methods Operands are described in “Operand” column of each instruction in accordance with the description method of the instruction operand expression (see the assembler specifications for details). When there are two or more description methods, select one of them. Uppercase letters and symbols, #, !, $, and [ ] are key words and are described as they are. The meaning of each symbol is described below. • # : Immediate data specification • $ : Relative address specification • ! : Absolute address specification • [ ] : Indirect address specification For immediate data, enter an appropriate numeric value or a label. When using a label, be sure to enter the #, !, $ and [ ] symbols. For operand register expressions, r and rp, either function names (X, A, C, etc.) or absolute names (names in parenthesis in the table below, R0, R1, R2, etc.) can be used for the description. Table 10-1. Operand Expressions and Description Methods Expression Description Method r rp sfr X (R0), A (R1), C (R2), B (R3), E (R4), D (R5), L (R6), H (R7) AX (RP0), BC (RP1), DE (RP2), HL (RP3) Special function register symbol saddr saddrp FE20H to FF1FH: immediate data or label FE20H to FF1FH: immediate data or label (even addresses only) addr16 addr5 0000H to FFFFH: immediate data or label (even addresses only for 16-bit data transfer instruction) 0040H to 007FH: immediate data or label (even addresses only) word byte bit 16-bit immediate data or label 8-bit immediate data or label 3-bit immediate data or label 30 Data Sheet U14384EJ1V0DS µPD789304, 789306, 789314, 789316 10.1.2 Description of “Operation” column A: A register; 8-bit accumulator X: X register B: B register C: C register D: D register E: E register H: H register L: L register AX: AX register pair; 16-bit accumulator BC: BC register pair DE: DE register pair HL: HL register pair PC: Program counter SP: Stack pointer PSW: Program status word CY: Carry flag AC: Auxiliary carry flag Z: Zero flag IE: Interrupt request enable flag NMIS: Flag indicating non-maskable interrupt servicing in progress ( ): Memory contents indicated by address or register contents in parenthesis XH, XL: Higher 8 bits and lower 8 bits of 16-bit register ∧: Logical product (AND) ∨: Logical sum (OR) ∨: Exclusive logical sum (exclusive OR) : Inverted data addr16: 16-bit immediate data or label jdisp8: Signed 8-bit data (displacement value) 10.1.3 Description of “Flag” column (Blank): Unchanged 0: Cleared to 0 1: Set to 1 ×: Set/cleared according to the result R: Previously saved value is restored Data Sheet U14384EJ1V0DS 31 µPD789304, 789306, 789314, 789316 10.2 List of Operations Mnemonic Operand Bytes Clocks Operation Flags Z MOV r, #byte XCH 3 3 6 (saddr) ← byte sfr, #byte 3 6 sfr ← byte A, r Note 1 2 4 A←r r, A Note 1 2 4 r←A A, saddr 2 4 A ← (saddr) saddr, A 2 4 (saddr) ← A A, sfr 2 4 A ← sfr sfr, A 2 4 sfr ← A A, !addr16 3 8 A ← (addr16) !addr16, A 3 8 (addr16) ← A PSW, #byte 3 6 PSW ← byte A, PSW 2 4 A ← PSW PSW, A 2 4 PSW ← A A, [DE] 1 6 A ← (DE) [DE], A 1 6 (DE) ← A A, [HL] 1 6 A ← (HL) [HL], A 1 6 (HL) ← A A, [HL + byte] 2 6 A ← (HL + byte) [HL + byte], A 2 6 (HL + byte) ← A 1 4 A↔X 2 6 A↔r A, saddr 2 6 A ↔ (saddr) A, sfr 2 6 A ↔ (sfr) A, [DE] 1 8 A ↔ (DE) A, [HL] 1 8 A ↔ (HL) A, [HL + byte] 2 8 A ↔ (HL + byte) rp, #word 3 6 rp ← word A, r XCHW Notes 1. Note 2 AX, saddrp 2 6 AX ← (saddrp) saddrp, AX 2 8 (saddrp) ← AX AX, rp Note 3 1 4 AX ← rp rp, AX Note 3 1 4 rp ← AX AX, rp Note 3 1 8 AX ↔ rp Except r = A, X 3. rp = BC, DE and HL only × × × × × One instruction clock cycle is one CPU clock cycle (fCPU) selected via the processor clock control register (PCC). 32 × Except r = A 2. Remark r ← byte saddr, #byte A, X MOVW 6 AC CY Data Sheet U14384EJ1V0DS µPD789304, 789306, 789314, 789316 Mnemonic Operand Bytes Clocks Operation Flags Z ADD ADDC SUB SUBC AND Remark AC CY A, #byte 2 4 A, CY ← A + byte × × × saddr, #byte 3 6 (saddr), CY ← (saddr) + byte × × × A, r 2 4 A, CY ← A + r × × × A, saddr 2 4 A, CY ← A + (saddr) × × × A, !addr16 3 8 A, CY ← A + (addr16) × × × A, [HL] 1 6 A, CY ← A + (HL) × × × A, [HL + byte] 2 6 A, CY ← A + (HL + byte) × × × A, #byte 2 4 A, CY ← A + byte + CY × × × saddr, #byte 3 6 (saddr), CY ← (saddr) + byte + CY × × × A, r 2 4 A, CY ← A + r + CY × × × A, saddr 2 4 A, CY ← A + (saddr) + CY × × × A, !addr16 3 8 A, CY ← A + (addr16) + CY × × × A, [HL] 1 6 A, CY ← A + (HL) + CY × × × A, [HL + byte] 2 6 A, CY ← A + (HL + byte) + CY × × × A, #byte 2 4 A, CY ← A – byte × × × saddr, #byte 3 6 (saddr), CY ← (saddr) – byte × × × A, r 2 4 A, CY ← A – r × × × A, saddr 2 4 A, CY ← A – (saddr) × × × A, !addr16 3 8 A, CY ← A – (addr16) × × × A, [HL] 1 6 A, CY ← A – (HL) × × × A, [HL + byte] 2 6 A, CY ← A – (HL + byte) × × × A, #byte 2 4 A, CY ← A – byte – CY × × × saddr, #byte 3 6 (saddr), CY ← (saddr) – byte – CY × × × A, r 2 4 A, CY ← A – r – CY × × × A, saddr 2 4 A, CY ← A – (saddr) – CY × × × A, !addr16 3 8 A, CY ← A – (addr16) – CY × × × A, [HL] 1 6 A, CY ← A – (HL) – CY × × × A, [HL + byte] 2 6 A, CY ← A – (HL + byte) – CY × × × A, #byte 2 4 A ← A ∧ byte × saddr, #byte 3 6 (saddr) ← (saddr) ∧ byte × A, r 2 4 A←A∧r × A, saddr 2 4 A ← A ∧ (saddr) × A, !addr16 3 8 A ← A ∧ (addr16) × A, [HL] 1 6 A ← A ∧ (HL) × A, [HL + byte] 2 6 A ← A ∧ (HL + byte) × One instruction clock cycle is one CPU clock cycle (fCPU) selected via the processor clock control register (PCC). Data Sheet U14384EJ1V0DS 33 µPD789304, 789306, 789314, 789316 Mnemonic Operand Bytes Clocks Operation Flags Z AC CY A, #byte 2 4 A ← A ∨ byte × saddr, #byte 3 6 (saddr) ← (saddr) ∨ byte × A, r 2 4 A←A∨r × A, saddr 2 4 A ← A ∨ (saddr) × A, !addr16 3 8 A ← A ∨ (addr16) × A, [HL] 1 6 A ← A ∨ (HL) × A, [HL + byte] 2 6 A ← A ∨ (HL + byte) × A, #byte 2 4 A ← A ∨ byte × saddr, #byte 3 6 (saddr) ← (saddr) ∨ byte × A, r 2 4 A←A∨r × A, saddr 2 4 A ← A ∨ (saddr) × A, !addr16 3 8 A ← A ∨ (addr16) × A, [HL] 1 6 A ← A ∨ (HL) × A, [HL + byte] 2 6 A ← A ∨ (HL + byte) × A, #byte 2 4 A – byte × × × saddr, #byte 3 6 (saddr) – byte × × × A, r 2 4 A–r × × × A, saddr 2 4 A – (saddr) × × × A, !addr16 3 8 A – (addr16) × × × A, [HL] 1 6 A – (HL) × × × A, [HL + byte] 2 6 A – (HL + byte) × × × ADDW AX, #word 3 6 AX, CY ← AX + word × × × SUBW AX, #word 3 6 AX, CY ← AX – word × × × CMPW AX, #word 3 6 AX – word × × × INC r 2 4 r←r+1 × × saddr 2 4 (saddr) ← (saddr) + 1 × × r 2 4 r←r–1 × × saddr 2 4 (saddr) ← (saddr) – 1 × × INCW rp 1 4 rp ← rp + 1 DECW rp 1 4 rp ← rp – 1 ROR A, 1 1 2 (CY, A7 ← A0, Am – 1 ← Am) × 1 time × ROL A, 1 1 2 (CY, A0 ← A7, Am + 1 ← Am) × 1 time × RORC A, 1 1 2 (CY ← A0, A7 ← CY, Am – 1 ← Am) × 1 time × ROLC A, 1 1 2 (CY ← A7, A0 ← CY, Am + 1 ← Am) × 1 time × OR XOR CMP DEC Remark One instruction clock cycle is one CPU clock cycle (fCPU) selected via the processor clock control register (PCC). 34 Data Sheet U14384EJ1V0DS µPD789304, 789306, 789314, 789316 Mnemonic Operand Bytes Clocks Operation Flags Z AC CY saddr. bit 3 6 (saddr. bit) ← 1 sfr. bit 3 6 sfr. bit ← 1 A. bit 2 4 A. bit ← 1 PSW. bit 3 6 PSW. bit ← 1 [HL]. bit 2 10 (HL). bit ← 1 saddr. bit 3 6 (saddr. bit) ← 0 sfr. bit 3 6 sfr. bit ← 0 A. bit 2 4 A. bit ← 0 PSW. bit 3 6 PSW. bit ← 0 [HL]. bit 2 10 (HL). bit ← 0 SET1 CY 1 2 CY ← 1 1 CLR1 CY 1 2 CY ← 0 0 NOT1 CY 1 2 CY ← CY × CALL !addr16 3 6 (SP – 1) ← (PC + 3)H, (SP – 2) ← (PC + 3)L, PC ← addr16, SP ← SP – 2 CALLT [addr5] 1 8 (SP – 1) ← (PC + 1)H, (SP – 2) ← (PC + 1)L, PCH ← (00000000, addr5 + 1), PCL ← (00000000, addr5), SP ← SP – 2 RET 1 6 PCH ← (SP + 1), PCL ← (SP), SP ← SP + 2 RETI 1 8 PCH ← (SP + 1), PCL ← (SP), PSW ← (SP + 2), SP ← SP + 3, NMIS ← 0 PSW 1 2 (SP – 1) ← PSW, SP ← SP – 1 rp 1 4 (SP – 1) ← rpH, (SP – 2) ← rpL, SP ← SP – 2 PSW 1 4 PSW ← (SP), SP ← SP + 1 rp 1 6 rpH ← (SP + 1), rpL ← (SP), SP ← SP + 2 SP, AX 2 8 SP ← AX AX, SP 2 6 AX ← SP !addr16 3 6 PC ← addr16 $addr16 2 6 PC ← PC + 2 + jdisp8 AX 1 6 PCH ← A, PCL ← X SET1 CLR1 PUSH POP MOVW BR Remark × × × × × × R R R R R R One instruction clock cycle is one CPU clock cycle (fCPU) selected via the processor clock control register (PCC). Data Sheet U14384EJ1V0DS 35 µPD789304, 789306, 789314, 789316 Mnemonic Operand Bytes Clocks Operation Flags Z BC $addr16 2 6 PC ← PC + 2 + jdisp8 if CY = 1 BNC $addr16 2 6 PC ← PC + 2 + jdisp8 if CY = 0 BZ $addr16 2 6 PC ← PC + 2 + jdisp8 if Z = 1 BNZ $addr16 2 6 PC ← PC + 2 + jdisp8 if Z = 0 BT saddr. bit, $addr16 4 10 PC ← PC + 4 + jdisp8 if (saddr. bit) = 1 sfr. bit, $addr16 4 10 PC ← PC + 4 + jdisp8 if sfr. bit = 1 A. bit, $addr16 3 8 PC ← PC + 3 + jdisp8 if A. bit = 1 PSW. bit, $addr16 4 10 PC ← PC + 4 + jdisp8 if PSW. bit = 1 saddr. bit, $addr16 4 10 PC ← PC + 4 + jdisp8 if (saddr. bit) = 0 sfr. bit, $addr16 4 10 PC ← PC + 4 + jdisp8 if sfr. bit = 0 A. bit, $addr16 3 8 PC ← PC + 3 + jdisp8 if A. bit = 0 PSW. bit, $addr16 4 10 PC ← PC + 4 + jdisp8 if PSW. bit = 0 B, $addr16 2 6 B ← B – 1, then PC ← PC + 2 + jdisp8 if B ≠ 0 C, $addr16 2 6 C ← C – 1, then PC ← PC + 2 + jdisp8 if C ≠ 0 saddr, $addr16 3 8 (saddr) ← (saddr) – 1, then PC ← PC + 3 + jdisp8 if (saddr) ≠ 0 NOP 1 2 No Operation EI 3 6 IE ← 1 (Enable Interrupt) DI 3 6 IE ← 0 (Disable Interrupt) HALT 1 2 Set HALT Mode STOP 1 2 Set STOP Mode BF DBNZ Remark One instruction clock cycle is one CPU clock cycle (fCPU) selected via the processor clock control register (PCC). 36 AC CY Data Sheet U14384EJ1V0DS µPD789304, 789306, 789314, 789316 11. ELECTRICAL SPECIFICATIONS Absolute Maximum Ratings (TA = 25°°C) Parameter Power supply voltage Input voltage Symbol Conditions VDD P00 to P03, P10 to P13, P20 to P26, P30 to P33, X1 (CL1), X2 (CL2), XT1, XT2, RESET VI2 P50 to P53 N-ch open drain On-chip pull-up resistor VO Output current, high IOH Output current, low IOL Unit –0.3 to +6.5 VI1 Output voltage Ratings V Note –0.3 to VDD + 0.3 –0.3 to +13 V V Note V Note V –0.3 to VDD + 0.3 –0.3 to VDD + 0.3 Per pin –10 mA Total for all pins –30 mA Per pin 30 mA Total for all pins 160 mA Operating ambient temperature TA –40 to +85 °C Storage temperature Tstg –65 to +150 °C Note 6.5 V or less Caution Product quality may suffer if the absolute maximum rating is exceeded even momentarily for any parameter. That is, the absolute maximum ratings are rated values at which the product is on the verge of suffering physical damage, and therefore the product must be used under conditions that ensure that the absolute maximum ratings are not exceeded. Remarks 1. Pin names enclosed in parentheses are when using the µPD789304, 789306. 2. Unless specified otherwise, the characteristics of alternate-function pins are the same as those of port pins. Data Sheet U14384EJ1V0DS 37 µPD789304, 789306, 789314, 789316 Main System Clock Oscillator Characteristics Ceramic/crystal oscillation (µPD789304, 789306) (TA = –40 to +85°C, VDD = 1.8 to 5.5 V) Resonator Recommended Circuit Ceramic resonator IC X2 X1 Parameter Conditions Note Oscillation frequency (fX) MIN. 1.0 TYP. MAX. Unit 5.0 MHz 4 ms 5.0 MHz 10 ms 30 ms 1 C2 IC Crystal resonator X2 C2 External clock X2 X2 Oscillation stabilization Note 2 time C1 X1 Note 1 Oscillation frequency Oscillation stabilization Note 2 time C1 X1 X1 After VDD reaches oscillation voltage range MIN. 1.0 VDD = 4.5 to 5.5 V Note 1 X1 input frequency (fX) 1.0 5.0 MHz X1 input high-/low-level width (tXH, tXL) 85 500 ns Note 1 X1 input frequency (fX) VDD = 2.7 to 5.5 V 1.0 5.0 MHz X1 input high-/low-level width (tXH, tXL) VDD = 2.7 to 5.5 V 85 500 ns OPEN Notes 1. 2. Indicates only oscillator characteristics. Refer to AC Characteristics for instruction execution time. Time required to stabilize oscillation after reset or STOP mode release. Use a resonator whose oscillation stabilizes within the oscillation stabilization wait time. Cautions 1. When using the main system clock oscillator, wire as follows in the area enclosed by the broken lines in the above figures to avoid an adverse effect from wiring capacitance. • Keep the wiring length as short as possible. • Do not cross the wiring with the other signal lines. • Do not route the wiring near a signal line through which a high fluctuating current flows. • Always make the ground point of the oscillator capacitor the same potential as VSS. • Do not ground the capacitor to a ground pattern through which a high current flows. • Do not fetch signals from the oscillator. 2. When the main system clock is stopped and the device is operating on the subsystem clock, wait until the oscillation stabilization time has been secured by the program before switching back to the main system clock. Remark For the resonator selection and oscillator constant, customers are requested to either evaluate the oscillation themselves or apply to the resonator manufacturer for evaluation. 38 Data Sheet U14384EJ1V0DS µPD789304, 789306, 789314, 789316 RC oscillation (µPD789314, 789316) (TA = –40 to +85°C, VDD = 1.8 to 5.5 V) Resonator Recommended Circuit RC resonator CL1 CL2 Parameter Oscillation frequency Note 1 (fCC) Oscillation stabilization Note 2 time External clock CL1 CL1 CL2 CL2 OPEN Notes 1. 2. Conditions MIN. 2.0 VDD = 2.7 to 5.5 V TYP. MAX. Unit 4.0 MHz 32 µs 128 µs CL1 input frequency Note 1 (fCC) 1.0 4.0 MHz CL1 input high-/low-level width (tXH, tXL) 100 500 ns CL1 input frequency Note 1 (fCC) VDD = 2.7 to 5.5 V 1.0 4.0 MHz CL1 input high-/low-level width (tXH, tXL) VDD = 2.7 to 5.5 V 100 500 ns Indicates only oscillator characteristics. Refer to AC Characteristics for instruction execution time. Time required to stabilize oscillation after reset or STOP mode release. Cautions 1. When using the main system clock oscillator, wire as follows in the area enclosed by the broken lines in the above figure to avoid an adverse effect from wiring capacitance. • Keep the wiring length as short as possible. • Do not cross the wiring with the other signal lines. • Do not route the wiring near a signal line through which a high fluctuating current flows. • Always make the ground point of the oscillator capacitor the same potential as VSS. • Do not ground the capacitor to a ground pattern through which a high current flows. • Do not fetch signals from the oscillator. 2. When the main system clock is stopped and the device is operating on the subsystem clock, wait until the oscillation stabilization time has been secured by the program before switching back to the main system clock. Data Sheet U14384EJ1V0DS 39 µPD789304, 789306, 789314, 789316 RC Oscillation Frequency Characteristics (TA = –40 to +85°°C) Parameter Symbol Oscillation frequency fCC1 fCC2 Conditions R = 11.0 kΩ, C = 22 pF Target: 2 MHz fCC3 fCC4 fCC5 R = 6.8 kΩ, C = 22 pF Target: 3 MHz fCC6 fCC7 fCC8 R = 4.7 kΩ, C = 22 pF Target: 4 MHz fCC9 MIN. TYP. MAX. Unit VDD = 2.7 to 5.5 V 1.5 2.0 2.5 MHz VDD = 1.8 to 3.6 V 0.5 2.0 2.5 MHz VDD = 1.8 to 5.5 V 0.5 2.0 2.5 MHz VDD = 2.7 to 5.5 V 2.5 3.0 3.5 MHz VDD = 1.8 to 3.6 V 0.75 3.0 3.5 MHz VDD = 1.8 to 5.5 V 0.75 3.0 3.5 MHz VDD = 2.7 to 5.5 V 3.5 4.0 4.7 MHz VDD = 1.8 to 3.6 V 1.0 4.0 4.7 MHz VDD = 1.8 to 5.5 V 1.0 4.0 4.7 MHz Remarks 1. Set the RC to one of the above nine values so that the typical value of the oscillation frequency is within 2.0 to 4.0 MHz. 2. The resistor (R) and capacitor (C) error is not included. 40 Data Sheet U14384EJ1V0DS µPD789304, 789306, 789314, 789316 Subsystem Clock Oscillator Characteristics (TA = –40 to +85°°C, VDD = 1.8 to 5.5 V) Resonator Recommended Circuit Crystal resonator IC XT1 XT2 R C3 External clock XT1 C4 XT2 Parameter Conditions Oscillation frequency Note 1 (fXT) Oscillation stabilization Note 2 time 2. TYP. MAX. Unit 32 32.768 35 kHz 1.2 2 s VDD = 4.5 to 5.5 V XT1 input frequency Note 1 (fXT) XT1 input high-/low-level width (tXTH, tXTL) Notes 1. MIN. 10 32 35 kHz 14.3 15.6 µs Indicates only oscillator characteristics. Refer to AC Characteristics for instruction execution time. Time required to stabilize oscillation after VDD reaches oscillation voltage range MIN. Cautions 1. When using the subsystem clock oscillator, wire as follows in the area enclosed by the broken lines in the above figure to avoid an adverse effect from wiring capacitance. • Keep the wiring length as short as possible. • Do not cross the wiring with the other signal lines. • Do not route the wiring near a signal line through which a high fluctuating current flows. • Always make the ground point of the oscillator capacitor the same potential as VSS. • Do not ground the capacitor to a ground pattern through which a high current flows. • Do not fetch signals from the oscillator. 2. The subsystem clock oscillator is designed as a low-amplitude circuit for reducing current consumption, and is more prone to malfunction due to noise than the main system clock oscillator. Particular care is therefore required with the wiring method when the subsystem clock is used. Remark For the resonator selection and oscillator constant, customers are requested to either evaluate the oscillation themselves or apply to the resonator manufacturer for evaluation. Data Sheet U14384EJ1V0DS 41 µPD789304, 789306, 789314, 789316 DC Characteristics (TA = –40 to +85°°C, VDD = 1.8 to 5.5 V) (1/4) Parameter Symbol Output current, low IOL Output current, high IOH Input voltage, high VIH1 VIH2 VIH3 VIH4 Input voltage, low VIL1 VIL2 VIL3 VIL4 Output voltage, high Output voltage, low VOH VOL1 VOL2 Conditions MAX. Unit Per pin 10 mA All pins 80 mA Per pin –1 mA All pins –15 mA 0.7VDD VDD V 0.9VDD VDD V 0.7VDD 12 V 0.9VDD 12 V 0.7VDD VDD V 0.9VDD VDD V 0.8VDD VDD V 0.9VDD VDD V VDD – 0.5 VDD V VDD – 0.1 VDD V 0 0.3VDD V 0 0.1VDD V 0 0.3VDD V 0 0.1VDD V 0 0.2VDD V 0 0.1VDD V 0 0.4 V 0 0.1 V P10 to P13 P50 to P53 VDD = 2.7 to 5.5 V N-ch open drain VDD = 2.7 to 5.5 V On-chip pullup resistor VDD = 2.7 to 5.5 V RESET, P00 to P03, P20 to P26, P30 to P33 VDD = 2.7 to 5.5 V X1 (CL1), X2 (CL2), XT1, XT2 VDD = 4.5 to 5.5 V P10 to P13 VDD = 2.7 to 5.5 V P50 to P53 VDD = 2.7 to 5.5 V RESET, P00 to P03, P20 to P26, P30 to P33 VDD = 2.7 to 5.5 V X1 (CL1), X2 (CL2), XT1, XT2 VDD = 4.5 to 5.5 V MIN. TYP. VDD = 4.5 to 5.5 V, IOH = –1 mA VDD – 1.0 V VDD = 1.8 to 5.5 V, IOH = –100 µA VDD – 0.5 V P00 to P03, P10 to P13, P20 to P26, P30 to P33 P50 to P53 4.5 ≤ VDD ≤ 5.5 V, IOL = 10 mA 1.0 V 1.8 ≤ VDD < 4.5 V, IOL = 400 µA 0.5 V 4.5 ≤ VDD < 5.5 V, IOL = 10 mA 1.0 V 1.8 ≤ VDD < 4.5 V, IOL = 1.6 mA 0.4 V Remarks 1. Pin names enclosed in parentheses are when using the µPD789314, 789316. 2. Unless specified otherwise, the characteristics of alternate-function pins are the same as those of port pins. 42 Data Sheet U14384EJ1V0DS µPD789304, 789306, 789314, 789316 DC Characteristics (TA = –40 to +85°°C, VDD = 1.8 to 5.5 V) (2/4) Parameter Symbol Input leakage current, high ILIH1 Conditions VIN = VDD ILIH2 Input leakage current, low MIN. TYP. MAX. Unit P00 to P03, P10 to P13, P20 to P26, P30 to P33, RESET 3 µA X1 (CL1), X2 (CL2), XT1, XT2 20 µA ILIH3 VIN = 12 V P50 to P53 (N-ch open drain) 20 µA ILIL1 VIN = 0 V P00 to P03, P10 to P13, P20 to P26, P30 to P33, RESET –3 µA ILIL2 X1 (CL1), X2 (CL2), XT1, XT2 –20 µA ILIL3 P50 to P53 (N-ch open drain) Note µA –3 Output leakage current, ILOH high VOUT = VDD 3 µA Output leakage current, ILOL low VOUT = 0 V –3 µA Software pull-up resistor R1 VIN = 0 V P00 to P03, P10 to P13, P20 to P26, P30 to P33 50 100 200 kΩ Mask option pull-up resistor R2 VIN = 0 V P50 to P53 10 30 60 kΩ Note If there is no on-chip pull-up resistor for P50 to P53 (specified by the mask option), if P50 to P53 have been set to input mode when a read instruction is executed to read from P50 to P53, a low-level input leakage current of up to –30 µA flows during only one cycle. At all other times, the maximum leakage current is –3 µA. Remarks 1. Pin names enclosed in parentheses are when using the µPD789314, 789316. 2. Unless specified otherwise, the characteristics of alternate-function pins are the same as those of port pins. Data Sheet U14384EJ1V0DS 43 µPD789304, 789306, 789314, 789316 DC Characteristics (TA = –40 to +85°°C, VDD = 1.8 to 5.5 V) (3/4) Parameter Symbol Power supply Note 1 current IDD1 (Ceramic/crystal oscillation) IDD2 IDD3 IDD4 Conditions 5.0 MHz crystal oscillation operation mode (C1 = C2 = 22 pF) 5.0 MHz crystal oscillation HALT mode (C1 = C2 = 22 pF) Notes 1. MIN. MAX. Unit VDD = 5.0 V ±10% 1.8 2.9 mA VDD = 3.0 V ±10% Note 3 0.36 0.9 mA VDD = 2.0 V ±10% Note 3 0.16 0.45 mA VDD = 5.0 V ±10% Note 2 0.96 1.92 mA VDD = 3.0 V ±10% Note 3 0.26 0.76 mA VDD = 2.0 V ±10% Note 3 0.1 0.34 mA 32.768 kHz crystal oscillation operation Note 4 mode VDD = 5.0 V ±10% 30 58 µA VDD = 3.0 V ±10% 9 26 µA (C3 = C4 = 22 pF, R1 = 220 kΩ) VDD = 2.0 V ±10% 4 12 µA LCD VDD = 5.0 V ±10% not VDD = 3.0 V ±10% operating VDD = 2.0 V ±10% 25 48 µA 7 20 µA 4 10 µA LCD VDD = 5.0 V ±10% operating VDD = 3.0 V ±10% Note 5 28 57 µA 9.6 27.8 µA VDD = 2.0 V ±10% 6 16 µA VDD = 5.0 V ±10% 0.1 10 µA VDD = 3.0 V ±10% 0.05 5.0 µA VDD = 2.0 V ±10% 0.05 3.0 µA 32.768 kHz crystal oscillation HALT Note 4 mode (C3 = C4 = 22 pF, R1 = 220 kΩ) IDD5 TYP. Note 2 Note 6 STOP mode The port current (including the current that flows to the on-chip pull-up resistor) is not included. 2. High-speed mode operation (when processor clock control register (PCC) is set to 00H) 3. Low-speed mode operation (when PCC is set to 02H) 4. When the main system clock is stopped 5. This is the total current that flows when the LCD controller/driver is operating (LCDON0 = 1, VAON0 = 1, LIPS0 = 1). The power supply current when the LCD is not operating (LCDON0 = 0, VAON0 = 1, LIPS0 = 0) is included in IDD2. 6. Remark This is the current when the LCD voltage booster circuit is stopped (LCDON0 = 0, VAON0 = 1). Unless specified otherwise, the characteristics of alternate-function pins are the same as those of port pins. 44 Data Sheet U14384EJ1V0DS µPD789304, 789306, 789314, 789316 DC Characteristics (TA = –40 to +85°°C, VDD = 1.8 to 5.5 V) (4/4) Parameter Symbol Power supply Note 1 current IDD1 (RC oscillation) IDD2 IDD3 IDD4 Conditions 4.0 MHz RC oscillation operation mode (R = 4.7 kΩ, C = 22 pF) 4.0 MHz RC oscillation HALT mode (R = 4.7 kΩ, C = 22 pF) Notes 1. MIN. MAX. Unit VDD = 5.0 V ±10% 1.65 3.0 mA VDD = 3.0 V ±10% Note 3 0.65 1.44 mA VDD = 2.0 V ±10% Note 3 0.38 1.05 mA VDD = 5.0 V ±10% Note 2 1.1 2.29 mA VDD = 3.0 V ±10% Note 3 0.6 1.28 mA VDD = 2.0 V ±10% Note 3 0.35 0.82 mA 32.768 kHz crystal oscillation operation Note 4 mode VDD = 5.0 V ±10% 30 58 µA VDD = 3.0 V ±10% 9 26 µA (C3 = C4 = 22 pF, R1 = 220 kΩ) VDD = 2.0 V ±10% 4 12 µA LCD VDD = 5.0 V ±10% not VDD = 3.0 V ±10% operating VDD = 2.0 V ±10% 25 48 µA 7 20 µA 4 10 µA LCD VDD = 5.0 V ±10% operating VDD = 3.0 V ±10% Note 5 28 57 µA 9.6 27.8 µA VDD = 2.0 V ±10% 6 16 µA VDD = 5.0 V ±10% 0.1 10 µA VDD = 3.0 V ±10% 0.05 5.0 µA VDD = 2.0 V ±10% 0.05 3.0 µA 32.768 kHz crystal oscillation HALT Note 4 mode (C3 = C4 = 22 pF, R1 = 220 kΩ) IDD5 TYP. Note 2 Note 6 STOP mode The port current (including the current that flows to the on-chip pull-up resistor) is not included. 2. High-speed mode operation (when processor clock control register (PCC) is set to 00H) 3. Low-speed mode operation (when PCC is set to 02H) 4. When the main system clock is stopped 5. This is the total current that flows when the LCD controller/driver is operating (LCDON0 = 1, VAON0 = 1, LIPS0 = 1). The power supply current when the LCD is not operating (LCDON0 = 0, VAON0 = 1, LIPS0 = 0) is included in IDD2. 6. Remark This is the current when the LCD voltage booster circuit is stopped (LCDON0 = 0, VAON0 = 1). Unless specified otherwise, the characteristics of alternate-function pins are the same as those of port pins. Data Sheet U14384EJ1V0DS 45 µPD789304, 789306, 789314, 789316 AC Characteristics (1) Basic operation (TA = –40 to +85°°C, VDD = 1.8 to 5.5 V) Parameter Cycle time (minimum instruction execution time) Symbol TCY1 Conditions Operating with main system clock MIN. VDD = 2.7 to 5.5 V Operating with subsystem clock TMI40 input frequency TMI40 input high-/lowlevel width fTMI tTIMH, VDD = 2.7 to 5.5 V tINTH, Key return input lowlevel width tKRL RESET low-level width tRSL 0.4 8.0 µs 1.6 8.0 µs 125 µs 0 4 MHz 0 275 kHz 122 µs 1.8 µs INTP0 to INTP3 10 µs KR00 to KR03 10 µs 10 µs tINTL TCY vs. VDD (main system clock) 60 20 Cycle time TCY [ µ s] 10 Guaranteed operation range 2.0 1.0 0.5 0.4 0.1 1 2 3 4 5 Power supply voltage VDD (V) 46 Unit 0.1 VDD = 2.7 to 5.5 V tTIML Interrupt input high/low-level width MAX. 114 TYP. Data Sheet U14384EJ1V0DS 6 µPD789304, 789306, 789314, 789316 (2) Serial interface 10, 20 (SIO10, SIO20) (TA = –40 to +85°°C, VDD = 1.8 to 5.5 V) (a) 3-wire serial I/O mode (internal clock output) Parameter SCKn0 cycle time Symbol tKCY1 SCKn0 high-/low-level width tKH1, SIn0 setup time (to SCKn0↑) tSIK1 SIn0 hold time (from SCKn0↑) tSI1 Delay time from SCKn0↓ to SOn0 output Conditions VDD = 2.7 to 5.5 V VDD = 2.7 to 5.5 V tKL1 tSO1 VDD = 2.7 to 5.5 V VDD = 2.7 to 5.5 V R = 1 kΩ, C = 100 pF Note VDD = 2.7 to 5.5 V MIN. TYP. MAX. Unit 800 ns 3200 ns tKCY1/2–50 ns tKCY1/2–150 ns 150 ns 500 ns 400 ns 600 ns 0 250 ns 0 1000 ns MAX. Unit Note R and C are the load resistance and load capacitance of the SOn0 output lines. Remark n = 1, 2 (b) 3-wire serial I/O mode (external clock input) Parameter SCKn0 cycle time Symbol tKCY2 SCKn0 high-/low-level width tKH2, SIn0 setup time (to SCKn0↑) tSIK2 SIn0 hold time (from SCKn0↑) tSI2 Delay time from SCKn0↓ to SOn0 output Conditions VDD = 2.7 to 5.5 V VDD = 2.7 to 5.5 V tKL2 tSO2 VDD = 2.7 to 5.5 V VDD = 2.7 to 5.5 V R = 1 kΩ, C = 100 pF Note VDD = 2.7 to 5.5 V MIN. TYP. 800 ns 3200 ns 400 ns 1600 ns 100 ns 150 ns 400 ns 600 ns 0 300 ns 0 1000 ns Note R and C are the load resistance and load capacitance of the SOn0 output lines. Remark n = 1, 2 Data Sheet U14384EJ1V0DS 47 µPD789304, 789306, 789314, 789316 (c) UART mode (SIO20 only) (dedicated baud rate generator output) Parameter Symbol Transfer rate Conditions MIN. TYP. VDD = 2.7 to 5.5 V MAX. Unit 78125 bps 19531 bps MAX. Unit (d) UART mode (SIO20 only) (external clock input) Parameter ASCK20 cycle time ASCK20 high-/lowlevel width Symbol tKCY3 tKH3, tKL3 Transfer rate ASCK20 rise/fall time 48 Conditions VDD = 2.7 to 5.5 V VDD = 2.7 to 5.5 V VDD = 2.7 to 5.5 V tR, tF Data Sheet U14384EJ1V0DS MIN. TYP. 800 ns 3200 ns 400 ns 1600 ns 39063 bps 9766 bps 1 µs µPD789304, 789306, 789314, 789316 AC Timing Test Points (excluding X1 (CL1) and XT1 inputs) 0.8VDD 0.2VDD 0.8VDD Test points 0.2VDD Clock Timing 1/fCLK tXL tXH VIH4 (MIN.) X1 (CL1) input VIL4 (MAX.) 1/fXT tXTL tXTH VIH5 (MIN.) XT1 input Remark VIL5 (MAX.) fCLK: fX or fCC TMI Timing 1/fTMI tTIL tTIH TMI40 input Interrupt Input Timing tINTL tINTH INTP0 to INTP3 Key Return Input Timing tKRL KR00 to KR03 Data Sheet U14384EJ1V0DS 49 µPD789304, 789306, 789314, 789316 RESET Input Timing tRSL RESET Serial Transfer Timing 3-wire serial I/O mode: tKCYm tKLm tKHm SCKn0 tSIKm SIn0 tKSIm Input data tKSOm Output data SOn0 Remark n, m = 1, 2 UART mode (external clock input): tKCY3 tKL3 tKH3 tR ASCK20 50 Data Sheet U14384EJ1V0DS tF µPD789304, 789306, 789314, 789316 LCD Characteristics (TA = –40 to +85°°C, VDD = 1.8 to 5.5 V) Parameter Symbol Conditions c1 to c4 = 0.47 µF MIN. TYP. MAX. Unit GAIN = 1 0.84 1.0 1.165 V GAIN = 0 1.26 1.5 1.74 V LCD output voltage variation range VLCD2 Doubler output VLCD1 c1 to c4 = 0.47 µF 2VLCD2 – 0.1 2.0VLCD2 2.0VLCD2 V Tripler output VLCD0 c1 to c4 = 0.47 µF 3VLCD2 – 0.15 3.0VLCD2 3.0VLCD2 V Voltage boost wait Note 1 time tVAWAIT GAIN = 0 GAIN = 1 0.5 s 5.0 ≤ VDD ≤ 5.5 V 2.0 s 4.5 ≤ VDD < 5.0 V 1.0 s 1.8 ≤ VDD < 4.5 V 0.5 s LCD output voltage Note 2 differential (common) VODC IO = ±5 µA 0 ±0.2 V LCD output voltage Note 2 (segment) differential VODS IO = ±1 µA 0 ±0.2 V Notes 1. This is the wait time from when voltage boosting is started (VAON0 = 1) until display is enabled (LCDON0 = 0). 2. The voltage differential is the difference between the segment and common signal output’s actual and ideal output voltages. Remark c1: Capacitor connected between CAPH and CAPL c2: Capacitor connected between VLC0 and ground c3: Capacitor connected between VLC1 and ground c4: Capacitor connected between VLC2 and ground Data Memory STOP Mode Low Supply Voltage Data Retention Characteristics (TA = –40 to +85°°C) Parameter Symbol Conditions MIN. Data retention power supply voltage VDDDR 1.8 Release signal set time tSREL 0 Data Sheet U14384EJ1V0DS TYP. MAX. Unit 5.5 V µs 51 µPD789304, 789306, 789314, 789316 Data Retention Timing Internal reset operation HALT mode STOP mode Operation mode Data retention mode VDD VDDDR tSREL STOP instruction execution RESET tWAIT HALT mode STOP mode Operation mode Data retention mode VDD VDDDR tSREL STOP instruction execution Standby release signal (interrupt request) tWAIT 52 Data Sheet U14384EJ1V0DS µPD789304, 789306, 789314, 789316 Oscillation Stabilization Wait Time (TA = –40 to +85°°C, VDD = 1.8 to 5.5 V) Parameter Oscillation stabilization wait Note 1 time (ceramic/crystal Symbol tWAIT oscillation) Oscillation stabilization wait time (RC oscillation) Notes 1. 2. tWAIT Conditions MIN. TYP. MAX. 15 Unit Release by RESET 2 /fX s Release by interrupt Note 2 s Release by RESET 2 /fCC Release by interrupt 7 7 2 /fCC s s Use a resonator whose oscillation stabilizes within the oscillation stabilization wait time. 12 15 17 Selection of 2 /fX, 2 /fX, or 2 /fX is possible with bits 0 to 2 (OSTS0 to OSTS2) of the oscillation stabilization time select register (OSTS). Remarks 1. fX: Main system clock oscillation frequency (ceramic/crystal oscillation) 2. fCC: Main system clock oscillation frequency (RC oscillation) Data Sheet U14384EJ1V0DS 53 µPD789304, 789306, 789314, 789316 12. CHARACTERISTICS CURVES OF LCD CONTROLLER/DRIVER (REFERENCE VALUES) (1) Characteristics curves of voltage boost stabilization time The following shows the characteristics curves of the time from the start of voltage boost (VAON0 = 1) and the changes in the LCD output voltage (when GAIN is set to 1 (using the 3 V display panel)) LCD Output Voltage/Voltage Boost Time 5.5 VDD = 4.5 V 5 VDD = 5 V VDD = 5.5 V 4.5 LCD output voltage [V] 4 3.5 VLCD0 3 2.5 VLCD1 2 1.5 VLCD2 1 0.5 0 0 500 1000 1500 2000 Voltage boost time [ms] 54 Data Sheet U14384EJ1V0DS 2500 3000 3500 4000 µPD789304, 789306, 789314, 789316 (2) Temperature characteristics of LCD output voltage The following shows the temperature characteristics curves of LCD output voltage. LCD Output Voltage/Temperature (When GAIN = 1) VLCD2 5 VLCD1 VLCD0 LCD output voltage [V] 4 3 2 1 0 −40 −30 −20 −10 0 10 20 30 40 50 60 70 80 Temperature [°C] LCD Output Voltage/Temperature (When GAIN = 0) VLCD2 5 VLCD1 VLCD0 LCD output voltage [V] 4 3 2 1 0 −40 −30 −20 −10 0 10 20 30 40 50 60 70 80 Temperature [°C] Data Sheet U14384EJ1V0DS 55 µPD789304, 789306, 789314, 789316 13. PACKAGE DRAWINGS 64-PIN PLASTIC QFP (14x14) A B 33 32 48 49 detail of lead end S C D Q 64 1 R 17 16 F J G H I M P K S N S L M NOTE ITEM Each lead centerline is located within 0.15 mm of its true position (T.P.) at maximum material condition. MILLIMETERS A 17.6±0.4 B 14.0±0.2 C 14.0±0.2 D 17.6±0.4 F 1.0 G 1.0 H 0.37 +0.08 −0.07 I J 0.15 0.8 (T.P.) K 1.8±0.2 L 0.8±0.2 M 0.17 +0.08 −0.07 N 0.10 P 2.55±0.1 Q 0.1±0.1 R 5°±5° S 2.85 MAX. P64GC-80-AB8-5 56 Data Sheet U14384EJ1V0DS µPD789304, 789306, 789314, 789316 64-PIN PLASTIC TQFP (12x12) A B 48 detail of lead end 33 32 49 S P T C D R L U 64 Q 17 16 1 F G J H I M ITEM K S M N S NOTE Each lead centerline is located within 0.13 mm of its true position (T.P.) at maximum material condition. MILLIMETERS A B 14.0±0.2 12.0±0.2 C 12.0±0.2 D F 14.0±0.2 1.125 G 1.125 H 0.32 +0.06 −0.10 I 0.13 J 0.65 (T.P.) K 1.0±0.2 L 0.5 M 0.17 +0.03 −0.07 N 0.10 P 1.0 Q 0.1±0.05 R 3° +4° −3° S 1.1±0.1 T 0.25 U 0.6±0.15 P64GK-65-9ET-2 Data Sheet U14384EJ1V0DS 57 µPD789304, 789306, 789314, 789316 14. RECOMMENDED SOLDERING CONDITIONS The µPD789304, 789306, 789314, and µPD789316 should be soldered and mounted under the following recommended conditions. For the details of the recommended soldering conditions, refer to the document Semiconductor Device Mounting Technology Manual (C10535E). For soldering methods and conditions other than those recommended below, contact an NEC sales representative. Table 14-1. Surface Mounting Type Soldering Conditions 64-pin plastic QFP (14 × 14) ×××-AB8: ××× µPD789304GC-××× ×××-AB8: 64-pin plastic QFP (14 × 14) ××× µPD789306GC-××× 64-pin plastic QFP (14 × 14) ×××-AB8: ××× µPD789314GC-××× ×××-AB8: 64-pin plastic QFP (14 × 14) ××× µPD789316GC-××× Soldering Method Soldering Conditions Recommended Condition Symbol Infrared reflow Package peak temperature: 235°C, Time: 30 seconds max. (at 210°C or higher), Count: three times or less IR35-00-3 VPS Package peak temperature: 215°C, Time: 40 seconds max. (at 200°C or higher), Count: three times or less VP15-00-3 Wave soldering Solder bath temperature: 260°C max., Time: 10 seconds max., Count: Once, Preheating temperature: 120°C max. (package surface temperature) WS60-00-1 Partial heating Pin temperature: 300°C max. Time: 3 seconds max. (per pin row) — Caution Do not use different soldering method together (except for partial heating). 64-pin plastic TQFP (fine pitch) (12 × 12) ×××-9ET: ××× µPD789304GK-××× ×××-9ET: 64-pin plastic TQFP (fine pitch) (12 × 12) ××× µPD789306GK-××× 64-pin plastic TQFP (fine pitch) (12 × 12) ×××-9ET: ××× µPD789314GK-××× 64-pin plastic TQFP (fine pitch) (12 × 12) ×××-9ET: ××× µPD789316GK-××× Soldering Method Soldering Conditions Recommended Condition Symbol Infrared reflow Package peak temperature: 235°C, Time: 30 seconds max. (at 210°C or Note higher), Count: two times or less, Exposure limit: 7 days (after that, prebake at 125°C for 10 hours) IR35-107-2 VPS Package peak temperature: 215°C, Time: 40 seconds max. (at 200°C or Note (after that, higher), Count: two times or less, Exposure limit: 7 days prebake at 125°C for 10 hours) VP15-107-2 Partial heating Pin temperature: 300°C max. Time: 3 seconds max. (per pin row) — Note After opening the dry pack, store it at 25°C or less and 65% RH or less for the allowable storage period. Caution Do not use different soldering method together (except for partial heating). 58 Data Sheet U14384EJ1V0DS µPD789304, 789306, 789314, 789316 APPENDIX A. DEVELOPMENT TOOLS The following development tools are available for system development using the µPD789304, 789306, 789314, and 789316. Language Processing Software RA78K0S Notes 1, 2, 3 Assembler package common to 78K/0S Series Notes 1, 2, 3 C compiler package common to 78K/0S Series CC78K0S Notes 1, 2, 3 DF789306 Notes 1, 2, 3 CC78K0S-L Device file for µPD789306, 789316 Subseries C compiler library source file common to 78K/0S Series Flash Memory Writing Tools Flashpro III Note 4 (Part No. FL-PR3 , PG-FP3) Note 4 Flash memory writing adapter for 64-pin plastic QFP (GC-AB8 type) Note 4 Flash memory writing adapter for 64-pin plastic TQFP (fine pitch) (GK-9ET type) FA-64GC FA-64GK Flash programmer dedicated to on-chip flash memory microcontroller Debugging Tools IE-78K0S-NS In-circuit emulator This is an in-circuit emulator for debugging hardware and software of application system using the 78K/0S Series. It supports the integrated debugger (ID78K0S-NS). It is used with an AC adapter, emulation probe, and interface adapter for connecting the host machine. IE-70000-MC-PS-B AC adapter This is the adapter for supplying power from an AC-100 to 240 V outlet. IE-70000-98-IF-C Interface adapter This adapter is needed when PC-9800 series PC (except notebook type) is used as the host machine for an IE-78K0S-NS (supports C bus). IE-70000-CD-IF-A PC card interface This PC card and interface cable are needed when a PC-9800 series notebook-type PC is used as the host machine for an IE-78K0S-NS (supports PCMCIA socket). IE-70000-PC-IF-C Interface adapter This adapter is needed when an IBM PC/AT™ or compatible PC is used as the host machine for an IE-78K0S-NS (supports ISA bus). IE-70000-PCI-IF-A Interface adapter This adapter is needed when a PC that includes a PCI bus is used as the host machine for an IE-78K0S-NS. IE-789306-NS-EM1 Emulation board This is an emulation board for emulating the peripheral hardware inherent to the device. It is used with an in-circuit emulator. Note 4 This is a board that is used to connect an in-circuit emulator to the target system. It is for 64-pin plastic QFP (GC-AB8 type). Note 4 This is a board that is used to connect an in-circuit emulator to the target system. It is for 64-pin plastic TQFP (GK-9ET type). NP-64GC NP-64GK SM78K0S Notes 1, 2 ID78K0S-NS Notes 1, 2 Notes 1, 2 DF789306 System simulator common to 78K/0S Series Integrated debugger common to 78K/0S Series Device file for µPD789306, 789316 Subseries Real-Time OS MX78K0S Notes 1, 2 OS for 78K/0S Series Data Sheet U14384EJ1V0DS 59 µPD789304, 789306, 789314, 789316 Notes 1. Based on PC-9800 series (Japanese Windows) 2. Based on IBM PC/AT compatible (Japanese/English Windows) 3. Based on HP9000 series 700™ (HP-UX™), SPARCstation™ (SunOS™, Solaris™), or NEWS™ (NEWS-OS™) 4. Remark 60 This product is manufactured by Naito Densei Machida Mfg. Co., Ltd. (TEL +81-44-822-3813). The RA78K0S, CC78K0S, and SM78K0S are used in combination with the DF789306. Data Sheet U14384EJ1V0DS µPD789304, 789306, 789314, 789316 APPENDIX B. RELATED DOCUMENTS Documents Related to Devices Document Name Document No. µPD789304, 789306, 789314, 789316 Data Sheet This manual µPD78F9306, 78F9316 Data Sheet To be prepared µPD789306, 789316 Subseries User’s Manual U14800E 78K/0S Series User’s Manual Instructions U11047E Documents Related to Development Tools (User’s Manuals) Document Name RA78K0S Assembler Package Document No. Operation U11622E Language U11599E Structured Assembly Language U11623E Operation U11816E Language U11817E SM78K0S, SM78K0 System Simulator Ver. 2.10 or Later Windows Based Operation U14611E SM78K Series System Simulator Ver. 2.10 or Later External Part User Open Interface Specifications U15006E ID-78K0-NS, ID78K0S-NS Integrated Debugger Ver. 2.20 or Later Windows Based Operation U14910E CC78K0S C Compiler IE-78K0S-NS In-Circuit Emulator U13549E IE-789306-NS-EM1 Emulation Board To be prepared Documents Related to Embedded Software (User’s Manual) Document Name 78K/0S Series OS MX78K0S Document No. Fundamental U12938E Other Related Documents Document Name Document No. SEMICONDUCTOR SELECTION GUIDE Products & Packages (CD-ROM) X13769X Semiconductor Device Mounting Technology Manual C10535E Quality Grades on NEC Semiconductor Devices C11531E NEC Semiconductor Device Reliability/Quality Control System C10983E Guide to Prevent Damage for Semiconductor Devices by Electrostatic Discharge (ESD) C11892E Caution The related documents listed above are subject to change without notice. Be sure to use the latest version of each document for designing. Data Sheet U14384EJ1V0DS 61 µPD789304, 789306, 789314, 789316 NOTES FOR CMOS DEVICES 1 PRECAUTION AGAINST ESD FOR SEMICONDUCTORS Note: Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. Environmental control must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using insulators that easily build static electricity. Semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. All test and measurement tools including work bench and floor should be grounded. The operator should be grounded using wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need to be taken for PW boards with semiconductor devices on it. 2 HANDLING OF UNUSED INPUT PINS FOR CMOS Note: No connection for CMOS device inputs can be cause of malfunction. If no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused pin should be connected to V DD or GND with a resistor, if it is considered to have a possibility of being an output pin. All handling related to the unused pins must be judged device by device and related specifications governing the devices. 3 STATUS BEFORE INITIALIZATION OF MOS DEVICES Note: Power-on does not necessarily define initial status of MOS device. Production process of MOS does not define the initial operation status of the device. Immediately after the power source is turned ON, the devices with reset function have not yet been initialized. Hence, power-on does not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the reset signal is received. Reset operation must be executed immediately after power-on for devices having reset function. EEPROM is a trademark of NEC Corporation. Windows is either a registered trademark or a trademark of Microsoft Corporation in the United States and/or other countries. PC/AT is a trademark of International Business Machines Corporation. HP9000 series 700 and HP-UX are trademarks of Hewlett-Packard Company. SPARCstation is a trademark of SPARC International, Inc. Solaris and SunOS are trademarks of Sun Microsystems, Inc. NEWS and NEWS-OS are trademarks of Sony Corporation. 62 Data Sheet U14384EJ1V0DS µPD789304, 789306, 789314, 789316 Regional Information Some information contained in this document may vary from country to country. Before using any NEC product in your application, pIease contact the NEC office in your country to obtain a list of authorized representatives and distributors. They will verify: • Device availability • Ordering information • Product release schedule • Availability of related technical literature • Development environment specifications (for example, specifications for third-party tools and components, host computers, power plugs, AC supply voltages, and so forth) • Network requirements In addition, trademarks, registered trademarks, export restrictions, and other legal issues may also vary from country to country. NEC Electronics Inc. (U.S.) NEC Electronics (Germany) GmbH NEC Electronics Hong Kong Ltd. Santa Clara, California Tel: 408-588-6000 800-366-9782 Fax: 408-588-6130 800-729-9288 Benelux Office Eindhoven, The Netherlands Tel: 040-2445845 Fax: 040-2444580 Hong Kong Tel: 2886-9318 Fax: 2886-9022/9044 NEC Electronics Hong Kong Ltd. Velizy-Villacoublay, France Tel: 01-3067-5800 Fax: 01-3067-5899 Seoul Branch Seoul, Korea Tel: 02-528-0303 Fax: 02-528-4411 NEC Electronics (France) S.A. NEC Electronics Singapore Pte. Ltd. Milton Keynes, UK Tel: 01908-691-133 Fax: 01908-670-290 Madrid Office Madrid, Spain Tel: 091-504-2787 Fax: 091-504-2860 Novena Square, Singapore Tel: 253-8311 Fax: 250-3583 NEC Electronics Italiana s.r.l. NEC Electronics (Germany) GmbH Milano, Italy Tel: 02-66 75 41 Fax: 02-66 75 42 99 Scandinavia Office Taeby, Sweden Tel: 08-63 80 820 Fax: 08-63 80 388 NEC Electronics (France) S.A. NEC Electronics (Germany) GmbH Duesseldorf, Germany Tel: 0211-65 03 02 Fax: 0211-65 03 490 NEC Electronics (UK) Ltd. NEC Electronics Taiwan Ltd. Taipei, Taiwan Tel: 02-2719-2377 Fax: 02-2719-5951 NEC do Brasil S.A. Electron Devices Division Guarulhos-SP, Brasil Tel: 11-6462-6810 Fax: 11-6462-6829 J01.2 Data Sheet U14384EJ1V0DS 63 µPD789304, 789306, 789314, 789316 The export of this product from Japan is regulated by the Japanese government. To export this product may be prohibited without governmental license, the need for which must be judged by the customer. The export or re-export of this product from a country other than Japan may also be prohibited without a license from that country. Please call an NEC sales representative. • The information in this document is current as of December, 2000. The information is subject to change without notice. For actual design-in, refer to the latest publications of NEC's data sheets or data books, etc., for the most up-to-date specifications of NEC semiconductor products. Not all products and/or types are available in every country. Please check with an NEC sales representative for availability and additional information. • No part of this document may be copied or reproduced in any form or by any means without prior written consent of NEC. NEC assumes no responsibility for any errors that may appear in this document. • NEC does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from the use of NEC semiconductor products listed in this document or any other liability arising from the use of such products. No license, express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of NEC or others. • Descriptions of circuits, software and other related information in this document are provided for illustrative purposes in semiconductor product operation and application examples. The incorporation of these circuits, software and information in the design of customer's equipment shall be done under the full responsibility of customer. NEC assumes no responsibility for any losses incurred by customers or third parties arising from the use of these circuits, software and information. • While NEC endeavours to enhance the quality, reliability and safety of NEC semiconductor products, customers agree and acknowledge that the possibility of defects thereof cannot be eliminated entirely. To minimize risks of damage to property or injury (including death) to persons arising from defects in NEC semiconductor products, customers must incorporate sufficient safety measures in their design, such as redundancy, fire-containment, and anti-failure features. • NEC semiconductor products are classified into the following three quality grades: "Standard", "Special" and "Specific". The "Specific" quality grade applies only to semiconductor products developed based on a customer-designated "quality assurance program" for a specific application. The recommended applications of a semiconductor product depend on its quality grade, as indicated below. Customers must check the quality grade of each semiconductor product before using it in a particular application. "Standard": Computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots "Special": Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support) "Specific": Aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems and medical equipment for life support, etc. The quality grade of NEC semiconductor products is "Standard" unless otherwise expressly specified in NEC's data sheets or data books, etc. If customers wish to use NEC semiconductor products in applications not intended by NEC, they must contact an NEC sales representative in advance to determine NEC's willingness to support a given application. (Note) (1) "NEC" as used in this statement means NEC Corporation and also includes its majority-owned subsidiaries. (2) "NEC semiconductor products" means any semiconductor product developed or manufactured by or for NEC (as defined above). M8E 00.4