ETC UPD780078GK-XXX-9ET

PRELIMINARY
INFORMATION
DATA PRODUCT
SHEET
MOS INTEGRATED CIRCUIT
µPD780076, 780078, 780076Y, 780078Y
8-BIT SINGLE-CHIP MICROCONTROLLERS
DESCRIPTION
The µPD780076 and 780078 are products in the µPD780078 Subseries within the 78K/0 Series. They are based
on the existing µPD780034A Subseries, with an enhanced timer and serial interface and greater ROM and RAM
capacities.
The µPD780076Y and 780078Y are products based on the µPD780078 Subseries, with an I2C bus interface
supporting multimaster.
A flash memory version, the µPD78F0078 and 78F0078Y, and various development tools are available.
Detailed function descriptions are provided in the following user’s manuals. Be sure to read them before
designing.
µPD780076, 780078, 780076Y, 780078Y Subseries User’s Manual: U14260E
78K/0 Series User’s Manual – Instructions: U12326E
FEATURES
• Internal large capacity ROM and RAM
Item Program Memory
Internal ROM
Part Number
µPD780076, 780076Y
µPD780078, 780078Y
Data Memory
Package
Internal High-
Internal Expansion
Speed RAM
RAM
1024 bytes
1024 bytes
48 KB
• 64-pin plastic QFP (14 × 14)
• 64-pin plastic TQFP (12 × 12)
60 KB
• Minimum instruction execution time: 0.24 µs (at fX = 8.38 MHz operation)
• I/O ports: 52 (N-ch open-drain 5 V withstand voltage: 4)
• 10-bit resolution A/D converter: 8 channels
• Serial interface: 3 channels (µPD780078 Subseries)
4 channels (µPD780078Y Subseries)
• Timer: 6 channels
• Power supply voltage: VDD = 1.8 to 5.5 V
APPLICATIONS
Personal computers, air conditioners, dash boards, air bags, car audios, etc.
The information in this document is subject to change without notice. Before using this document, please
confirm that this is the latest version.
Not all devices/types available in every country. Please check with local NEC representative for
availability and additional information.
Document No. U14259EJ1V0DS00 (1st edition)
Date Published April 2001 N CP(K)
Printed in Japan
The mark
shows major revised points.
©
1999
µPD780076, 780078, 780076Y, 780078Y
ORDERING INFORMATION
Part Number
Package
µPD780076GC-×××-AB8
64-pin plastic QFP (14 × 14)
µPD780076GK-×××-9ET
64-pin plastic TQFP (12 × 12)
µPD780078GC-×××-AB8
64-pin plastic QFP (14 × 14)
µPD780078GK-×××-9ET
64-pin plastic TQFP (12 × 12)
µPD780076YGC-×××-AB8
64-pin plastic QFP (14 × 14)
µPD780076YGK-×××-9ET
64-pin plastic TQFP (12 × 12)
µPD780078YGC-×××-AB8
64-pin plastic QFP (14 × 14)
µPD780078YGK-×××-9ET
64-pin plastic TQFP (12 × 12)
Remark ××× indicates ROM code suffix.
2
Data Sheet U14259EJ1V0DS
µPD780076, 780078, 780076Y, 780078Y
78K/0 SERIES LINEUP
The products in the 78K/0 Series are listed below. The names enclosed in boxes are subseries names.
Products in mass production
Products under development
Y subseries products are compatible with I2C bus.
Control
100-pin
100-pin
100-pin
µ PD78075B
µ PD78078
µ PD78070A
100-pin
80-pin
80-pin
µ PD780058
µ PD78058F
EMI-noise reduced version of the µPD78078
µPD78078Y
µPD78054 with added timer and enhanced external interface
µ PD78070AY
ROM-less version of the µPD78078
µ PD78078Y with enhanced serial I/O and limited function
µ PD780018AY
µ PD780058Y
µ PD78058FY
µPD78054
µPD780065
µ PD78054Y
80-pin
64-pin
µ PD780078
64-pin
64-pin
64-pin
µ PD780034A
µ PD780024A
µPD78014H
µ PD780078Y
µ PD780034AY
µ PD780024AY
64-pin
42-/44-pin
µPD78018F
µ PD78083
64-pin
µPD780988
80-pin
µ PD78018FY
µ PD78054 with enhanced serial I/O
EMI-noise reduced version of the µ PD78054
µPD78018F with enhanced UART and D/A converter and enhanced I/O
RAM capacity of the µ PD780024A increased.
µPD780034A with added timer and enhanced serial I/O
µ PD780024A with enhanced A/D converter
µ PD78018F with enhanced serial I/O
EMI-noise reduced version of the µPD78018F
Basic subseries for control
On-chip UART, capable of operating at low voltage (1.8 V)
Inverter control
On-chip inverter controller and UART. EMI-noise reduced.
VFD drive
78K/0
Series
100-pin
µ PD780208
µ PD78044F with enhanced I/O and VFD C/D. Display output total: 53
80-pin
For panel control. On-chip VFD and C/D. Display output total: 53
80-pin
µ PD780232
µPD78044H
80-pin
µPD78044F
Basic subseries for VFD drive. Display output total: 34
µ PD78044F with added N-ch open-drain I/O. Display output total: 34
LCD drive
120-pin
µ PD780338
120-pin
µ PD780328
µPD780318
µ PD780308
µPD78064B
µPD78064
120-pin
100-pin
100-pin
100-pin
µ PD780308 with enhanced display function and timer. Segment signal output: 40 pins max.
µ PD780308 with enhanced display function and timer. Segment signal output: 32 pins max.
µ PD780308 with enhanced display function and timer. Segment signal output: 24 pins max.
µPD780308Y
µ PD78064 with enhanced SIO, and increased ROM, RAM capacity
EMI-noise reduced version of the µ PD78064
µ PD78064Y
Basic subseries for LCD drive, on-chip UART
Bus interface supported
100-pin
80-pin
µ PD780948
µ PD78098B
On-chip D-CAN controller
µPD78054 with added IEBusTM controller.
80-pin
µPD780702Y
On-chip IEBus controller
80-pin
µPD780703Y
µPD780833Y
On-chip D-CAN controller
80-pin
64-pin
µPD780816
On-chip controller compliant with J1850 (Class 2)
Specialized for D-CAN controller function
Meter control
100-pin
µPD780958
For industrial meter control
80-pin
µPD780852
µPD780828B
On-chip automobile meter controller/driver
For automobile meter driver. On-chip D-CAN controller
80-pin
Remark VFD (Vacuum Fluorescent Display) is referred to as FIPTM (Fluorescent Indicator Panel) in some
documents, but the functions of the two are the same.
Data Sheet U14259EJ1V0DS
3
µPD780076, 780078, 780076Y, 780078Y
The major functional differences among the subseries are shown below.
•
Non Y Subseries
Function
Subseries Name
ROM
Capacity
(Bytes)
Timer
8-Bit 16-Bit Watch WDT A/D
µPD78075B 32 K to 40 K 4 ch
Control
µPD78078
µPD78070A
8-Bit 10-Bit 8-Bit
1 ch
1 ch
1 ch
8 ch
A/D
–
Serial Interface
I/O
VDD External
MIN.
Expansion
Value
88
1.8 V
61
2.7 V
D/A
2 ch 3 ch (UART: 1 ch)
48 K to 60 K
–
µPD780058 24 K to 60 K 2 ch
3 ch (time-division UART: 1 ch)
68
1.8 V
µPD78058F 48 K to 60 K
3 ch (UART: 1 ch)
69
2.7 V
µPD78054
√
16 K to 60 K
2.0 V
µPD780065 40 K to 48 K
–
µPD780078 48 K to 60 K
2 ch
µPD780034A 8 K to 32 K
1 ch
–
µPD780024A
8 ch
8 ch
4 ch (UART: 1 ch)
60
2.7 V
3 ch (UART: 2 ch)
52
1.8 V
3 ch (UART: 1 ch)
51
2 ch
53
1 ch (UART: 1 ch)
33
–
µPD78014H
µPD78018F 8 K to 60 K
µPD78083
Inverter
8 K to 16 K
–
µPD780988 16 K to 60 K 3 ch Note
–
–
–
1 ch
–
8 ch
–
3 ch (UART: 2 ch)
47
4.0 V
√
1 ch
8 ch
–
–
2 ch
74
2.7 V
–
40
4.5 V
68
2.7 V
54
1.8 V
control
VFD
drive
µPD780208 32 K to 60 K 2 ch
1 ch
1 ch
µPD780232 16 K to 24 K 3 ch
–
–
4 ch
µPD78044H 32 K to 48 K 2 ch
1 ch
1 ch
8 ch
1 ch
µPD78044F 16 K to 40 K
LCD
drive
µPD780338 48 K to 60 K 3 ch
2 ch
2 ch
1 ch
1 ch
–
10 ch 1 ch 2 ch (UART: 1 ch)
µPD780328
62
µPD780318
70
µPD780308 48 K to 60 K 2 ch
1 ch
8 ch
–
–
µPD78064B 32 K
µPD78064
2.0 V
79
4.0 V
√
69
2.7 V
–
2 ch (UART: 1 ch)
2 ch
1 ch
1 ch
8 ch
–
1 ch
–
3 ch (UART: 1 ch)
2 ch
µPD780816 32 K to 64 K
2 ch
Meter
control
µPD780958 48 K to 60 K 4 ch
2 ch
–
1 ch
–
Dash
board
control
µPD780852 32 K to 40 K 3 ch
1 ch
1 ch
1 ch
5 ch
12 ch
–
2 ch (UART: 1 ch)
46
4.0 V
–
–
2 ch (UART: 1 ch)
69
2.2 V
–
–
–
3 ch (UART: 1 ch)
56
4.0 V
–
2 ch (UART: 1 ch)
59
µPD780828B 32 K to 60 K
16-bit timer: 2 channels
10-bit timer: 1 channel
4
57
16 K to 32 K
Bus
µPD780948 60 K
2 ch
interface
supported µPD78098B 40 K to 60 K
Note
3 ch (time-division UART: 1 ch)
–
Data Sheet U14259EJ1V0DS
µPD780076, 780078, 780076Y, 780078Y
•
Y Subseries
Function
Subseries Name
Control
µPD78078Y
ROM
Capacity
(Bytes)
Timer
8-Bit 16-Bit Watch WDT A/D
48 K to 60 K 4 ch
µPD78070AY
8-Bit 10-Bit 8-Bit
1 ch
1 ch
1 ch
8 ch
A/D
–
2 ch 3 ch (UART: 1 ch,
–
–
µPD780058Y
24 K to 60 K 2 ch
µPD78058FY
I/O
VDD
External
MIN.
Expansion
Value
88
1.8 V
61
2.7 V
D/A
I2C: 1 ch)
µPD780018AY 48 K to 60 K
3 ch
(I2C:
1 ch)
1.8 V
48 K to 60 K
3 ch (UART: 1 ch,
2.7 V
µPD78054Y
16 K to 60 K
I2C: 1 ch)
µPD780078Y
48 K to 60 K
2 ch
µPD780034AY 8 K to 32 K
1 ch
–
8 ch
µPD78018FY
8 K to 60 K
µPD780308Y
48 K to 60 K 2 ch
µPD78064Y
16 K to 32 K
For bus µPD780702Y
60 K
8 ch
–
1 ch
1 ch
8 ch
2.0 V
52
3 ch (UART: 1 ch,
51
1.8 V
I2C: 1 ch)
–
–
69
4 ch (UART: 2 ch,
I2C: 1 ch)
2 ch (I2C: 1 ch)
1 ch
√
88
2 ch 3 ch (time division
68
UART: 1 ch, I2C: 1 ch)
µPD780024AY
LCD
drive
Serial Interface
–
53
3 ch (time division
57
UART: 1 ch, I2C: 1 ch)
2.0 V
–
67
3.5 V
–
65
4.5 V
2 ch (UART: 1 ch,
I2C: 1 ch)
3 ch
2 ch
1 ch
1 ch 16 ch
–
–
4 ch (UART: 1 ch,
I2C:
interface µPD780703Y
µPD780833Y
1 ch)
Remark The functions of non Y subseries and Y subseries products are the same, except for the serial interface.
Data Sheet U14259EJ1V0DS
5
µPD780076, 780078, 780076Y, 780078Y
FUNCTION OVERVIEW
µPD780076
µPD780076Y
Part Number
Item
Internal
ROM
48 KB
memory
High-speed RAM
1024 bytes
Expansion RAM
1024 bytes
µPD780078
µPD780078Y
60 KB
Memory space
64 KB
General-purpose registers
8 bits × 32 registers (8 bits × 8 registers × 4 banks)
Minimum instruction execution time
On-chip variable function of minimum instruction execution time
When main system 0.24 µs/0.48 µs/0.95 µs/1.91 µs/3.81 µs (at 8.38 MHz operation)
clock selected
When subsystem
clock selected
122 µs (at 32.768 kHz operation)
Instruction set
•
•
•
•
16-bit operation
Multiply/divide (8 bits × 8 bits,16 bits ÷ 8 bits)
Bit manipulate (set, reset, test, Boolean operation)
BCD adjust, etc.
I/O ports
Total:
52
• CMOS input:
• CMOS I/O:
• N-ch open-drain I/O:
8
40
4
A/D converter
• 10-bit resolution × 8 channels
• Low-voltage operation available: AVDD = 2.2 to 5.5 V
Serial interface
• 3-wire serial I/O mode:
• UART mode:
1 channel
1 channel
• 3-wire serial I/O/UART mode selectableNote: 1 channel
• I2C bus mode (µPD780078Y Subseries only): 1 channel
Timer
• 16-bit timer/event counter:
• 8-bit timer/event counter:
2 channels
2 channels
• Watch timer:
• Watchdog timer:
1 channel
1 channel
Timer output
4 (8-bit PWM output capable: 2)
Clock output
• 65.5 kHz, 131 kHz, 262 kHz, 524 kHz, 1.05 MHz, 2.10 MHz, 4.19 MHz, 8.38 MHz
(at 8.38 MHz operation with main system clock)
• 32.768 kHz (at 32.768 kHz operation with subsystem clock)
Buzzer output
1.02 kHz, 2.05 kHz, 4.10 kHz, 8.19 kHz (at 8.38 MHz operation with main system clock)
Vectored
interrupt
source
External:
18 (µPD780078 Subseries)
19 (µPD780078Y Subseries)
5
Non-maskable
Internal:
1
Software
1
Maskable
Internal:
Power supply voltage
VDD = 1.8 to 5.5 V
Operating ambient temperature
TA = –40 to +85°C
Package
• 64-pin plastic QFP (14 × 14)
• 64-pin plastic TQFP (12 × 12)
Note Pins are multiplexed. Select either of these interfaces.
6
Data Sheet U14259EJ1V0DS
µPD780076, 780078, 780076Y, 780078Y
CONTENTS
1. PIN CONFIGURATION (TOP VIEW) ................................................................................................... 8
2. BLOCK DIAGRAM .............................................................................................................................10
3. PIN FUNCTIONS ................................................................................................................................ 11
3.1
Port Pins .................................................................................................................................................... 11
3.2
Non-Port Pins ............................................................................................................................................ 12
3.3
Pin I/O Circuits and Recommended Connection of Unused Pins ..................................................... 14
4. MEMORY SPACE ................................................................................................................................16
5. PERIPHERAL HARDWARE FUNCTION FEATURES .......................................................................17
5.1
Ports ........................................................................................................................................................... 17
5.2
Clock Generator ........................................................................................................................................ 18
5.3
Timer/Event Counter ................................................................................................................................ 18
5.4
Clock Output/Buzzer Output Controller ................................................................................................ 22
5.5
A/D Converter ........................................................................................................................................... 23
5.6
Serial Interface .......................................................................................................................................... 24
6. INTERRUPT FUNCTIONS .................................................................................................................29
7. EXTERNAL DEVICE EXPANSION FUNCTIONS .............................................................................33
8. STANDBY FUNCTION .......................................................................................................................33
9. RESET FUNCTION ............................................................................................................................34
10. MASK OPTION ...................................................................................................................................34
11. INSTRUCTION SET ...........................................................................................................................35
12. ELECTRICAL SPECIFICATIONS ......................................................................................................37
13. PACKAGE DRAWINGS .....................................................................................................................61
14. RECOMMENDED SOLDERING CONDITIONS ................................................................................63
APPENDIX A. DEVELOPMENT TOOLS ................................................................................................65
APPENDIX B. RELATED DOCUMENTS ...............................................................................................68
Data Sheet U14259EJ1V0DS
7
µPD780076, 780078, 780076Y, 780078Y
1. PIN CONFIGURATION (TOP VIEW)
• 64-pin plastic QFP (14 × 14)
µPD780076GC-×××-AB8, 780078GC-×××-AB8, 780076YGC-×××-AB8, 780078YGC-×××-AB8
• 64-pin plastic TQFP (12 × 12)
P47/AD7
P46/AD6
P45/AD5
P44/AD4
P43/AD3
P42/AD2
P41/AD1
P40/AD0
P67/ASTB
P66/WAIT
P65/WR
P64/RD
P75/BUZ/TI001/TO01
P74/PCL/TI011
P73/TI51/TO51
P72/TI50/TO50
µPD780076GK-×××-9ET, 780078GK-×××-9ET, 780076YGK-×××-9ET, 780078YGK-×××-9ET
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
P71/TI010
P70/TI000/TO00
P03/INTP3/ADTRG
P02/INTP2
P01/INTP1
P00/INTP0
VSS1
X1
X2
IC
XT1
XT2
RESET
P80/SS1
AVREF
P10/ANI0
P36/SCK3/ASCK2
P20/SI1
P21/SO1
P22/SCK1
P23/RxD0
P24/TxD0
P25/ASCK0
VDD1
AVSS
P17/ANI7
P16/ANI6
P15/ANI5
P14/ANI4
P13/ANI3
P12/ANI2
P11/ANI1
P50/A8
P51/A9
P52/A10
P53/A11
P54/A12
P55/A13
P56/A14
P57/A15
VSS0
VDD0
P30
P31
P32/SDA0Note
P33/SCL0Note
P34/SI3/TxD2
P35/SO3/RxD2
Note SDA0 and SCL0 are only provided on the µPD780078Y Subseries.
Cautions 1. Connect the IC (Internally Connected) pin directly to VSS0 or VSS1.
2. Connect the AVSS pin to VSS0.
Remark When used in applications where the noise generated inside the microcontroller needs to be reduced,
the implementation of noise reduction measures, such as supplying voltage to VDD0 and VDD1 individually
and connecting VSS0 and VSS1 to different ground lines, is recommended.
8
Data Sheet U14259EJ1V0DS
µPD780076, 780078, 780076Y, 780078Y
Address bus
PCL:
AD0 to AD7:
Address/data bus
RD:
Read strobe
ADTRG:
AD trigger input
RESET:
Reset
ANI0 to ANI7:
Analog input
RxD0, RxD2:
Receive data
ASCK0, ASCK2:
Asynchronous serial clock
SCK1, SCK3, SCL0:
Serial clock
ASTB:
Address strobe
SDA0:
Serial data
AVREF:
Analog reference voltage
SI1, SI3:
Serial input
AVSS:
Analog ground
SO1, SO3:
Serial output
BUZ:
Buzzer output
SS1:
Serial interface chip select input
IC:
Internally connected
TI000, TI010, TI001,
INTP0 to INTP3:
External interrupt input
TI011, TI50, TI51:
P00 to P03:
Port 0
TO00, TO01, TO50, TO51: Timer output
P10 to P17:
Port 1
TxD0, TxD2:
Transmit data
P20 to P25:
Port 2
VDD0, VDD1:
Power supply
P30 to P36:
Port 3
VSS0, VSS1:
Ground
P40 to P47:
Port 4
WAIT:
Wait
P50 to P57:
Port 5
WR:
Write strobe
P64 to P67:
Port 6
X1, X2:
Crystal (main system clock)
P70 to P75:
Port 7
XT1, XT2:
Crystal (subsystem clock)
P80:
Port 8
A8 to A15:
Data Sheet U14259EJ1V0DS
Programmable clock
Timer input
9
µPD780076, 780078, 780076Y, 780078Y
2. BLOCK DIAGRAM
TI000/TO00/P70
TI010/P71
16-bit timer/event
counter 00
TI001/TO01/BUZ/P75
TI011/PCL/P74
16-bit timer/event
counter 01
TI50/TO50/P72
8-bit timer/event
counter 50
TI51/TO51/P73
8-bit timer/event
counter 51
Watch timer
78K/0
CPU
core
ROM
Port 0
4
P00 to P03
Port 1
8
P10 to P17
Port 2
6
P20 to P25
Port 3
7
P30 to P36
Port 4
8
P40 to P47
Port 5
8
P50 to P57
Port 6
4
P64 to P67
Port 7
6
P70 to P75
Watchdog timer
RxD0/P23
TxD0/P24
ASCK0/P25
Serial interface
UART0
RxD2/SO3/P35
TxD2/SI3/P34
ASCK2/SCK3/P36
Serial interface
UART2
Serial interface
SIO3
SI1/P20
SO1/P21
SCK1/P22
SS1/P80
Serial interface
CSI1
SDA0/P32
8
Clock/buzzer
output control
8
AD0/P40 to
AD7/P47
A8/P50 to
A15/P57
RD/P64
WR/P65
WAIT/P66
ASTB/P67
PCL/TI011/P74
BUZ/TI001/TO01/P75
8
A/D converter
System
control
4
Interrupt control
VDD0 VDD1 VSS0 VSS1
IC
Note I2C bus is only provided on the µPD780078Y Subseries.
Remark The internal ROM capacity depends on the product.
10
P80
I2C busNote
SCL0/P33
INTP0/P00 to
INTP3/P03
Internal
expansion
RAM
1024 bytes
External
access
SI3/TxD2/P34
SO3/RxD2/P35
SCK3/ASCK2/P36
ANI0/P10 to
ANI7/P17
ADTRG/INTP3/P03
AVREF
AVSS
Port 8
Internal
high-speed
RAM
1024 bytes
Data Sheet U14259EJ1V0DS
RESET
X1
X2
X1
X2
µPD780076, 780078, 780076Y, 780078Y
3. PIN FUNCTIONS
3.1 Port Pins (1/2)
Pin Name
P00
I/O
I/O
P01
P02
Function
Port 0
4-bit input/output port.
Input/output can be specified in 1-bit units.
An on-chip pull-up resistor can be specified by a software setting.
After
Alternate
Reset
Function
Input
INTP0
INTP1
INTP2
P03
INTP3/ADTRG
P10 to P17
P20
Input
I/O
P21
P22
Port 1
8-bit input only port.
Input
ANI0 to ANI7
Port 2
6-bit input/output port.
Input/output can be specified in 1-bit units.
An on-chip pull-up resistor can be specified by a software setting.
Input
SI1
SO1
SCK1
P23
RxD0
P24
TxD0
P25
ASCK0
P30, P31
I/O
P32
P33
Port 3
7-bit input/output port.
Input/output can be specified
in 1-bit units.
P34
N-ch open-drain input/output port.
On-chip pull-up resistors can be specified
by the mask optionNote 1.
LEDs can be driven directly.
Input
SDA0Note 2
SCL0Note 2
SI3/TxD2
An on-chip pull-up resistor can be
specified by a software setting.
P35
—
SO3/RxD2
P36
SCK3/ASCK2
P40 to P47
I/O
Port 4
8-bit input/output port.
Input/output can be specified in 1-bit units.
An on-chip pull-up resistor can be specified by a software setting.
Interrupt request flag (KRIF) is set to 1 by falling edge detection.
Input
AD0 to AD7
P50 to P57
I/O
Port 5
8-bit input/output port.
LEDs can be driven directly.
Input/output can be specified in 1-bit units.
An on-chip pull-up resistor can be specified by a software setting.
Input
A8 to A15
P64
I/O
Port 6
4-bit input/output port.
Input/output can be specified in 1-bit units.
An on-chip pull-up resistor can be specified by a software setting.
Input
RD
P65
P66
P67
WR
WAIT
ASTB
Notes 1. With the µPD780078Y Subseries, on-chip pull-up resistors can be specified using a mask option for P30
and P31.
2. These pins are only provided on the µPD780078Y Subseries.
Data Sheet U14259EJ1V0DS
11
µPD780076, 780078, 780076Y, 780078Y
3.1 Port Pins (2/2)
Pin Name
P70
I/O
I/O
P71
P72
Function
Port 7
6-bit input/output port.
Input/output can be specified in 1-bit units.
An on-chip pull-up resistor can be specified by a software setting.
After
Alternate
Reset
Function
Input
TI000/TO00
TI010
TI50/TO50
P73
TI51/TO51
P74
TI011/PCL
P75
TI001/TO01/
BUZ
P80
I/O
Port 8
1-bit input/output port.
Input/output can be specified in 1-bit units.
On-chip pull-up resistor can be specified by a software setting.
Input
SS1
3.2 Non-Port Pins (1/2)
Pin Name
I/O
Function
INTP0 to INTP2 Input
External interrupt request input for which the valid edge (rising edge,
INTP3
falling edge, or both rising edge and falling edge) can be specified.
SI1
Input
Serial interface serial data input.
After
Alternate
Reset
Function
Input
P00 to P02
P03/ADTRG
Input
SI3
SO1
P20
P34/TxD2
Output
Serial interface serial data output.
Input
SO3
P21
P35/RxD2
SDA0Note
I/O
Serial interface serial data input/output.
Input
P32
SCK1
I/O
Serial interface serial clock input/output.
Input
P22
SCK3
P36/ASCK2
SCL0Note
P33
SS1
Input
Serial interface chip select input.
Input
P80
RxD0
Input
Serial data input for asynchronous serial interface.
Input
P23
RxD2
TxD0
P35/SO3
Output
Serial data output for asynchronous serial interface.
Input
TxD2
ASCK0
P34/SI3
Input
Serial clock input for asynchronous serial interface.
Input
ASCK2
TI000
P24
P25
P36/SCK3
Input
External count clock input to 16-bit timer/event counter 00.
Input
P70/TO00
Capture trigger input to capture register 000, 010 of 16-bit timer/event counter 00.
TI010
Capture trigger input to capture register 000 of 16-bit timer/event counter 00.
P71
TI001
External count clock input to 16-bit timer/event counter 01.
Capture trigger input to capture register 001, 011 of 16-bit timer/event counter 01.
P75/TO01/
BUZ
TI011
Capture trigger input to capture register 001 of 16-bit timer/event counter 01.
P74/PCL
TI50
External count clock input to 8-bit timer/event counter 50.
P72/TO50
TI51
External count clock input to 8-bit timer/event counter 51.
P73/TO51
Note These pins are only provided on the µPD780078Y Subseries.
12
Data Sheet U14259EJ1V0DS
µPD780076, 780078, 780076Y, 780078Y
3.2 Non-Port Pins (2/2)
Pin Name
TO00
I/O
Output
Function
16-bit timer/event counter 00.
After
Alternate
Reset
Function
Input
P70/TI000
TO01
16-bit timer/event counter 01.
P75/TI001/
BUZ
TO50
8-bit timer/event counter 50.
P72/TI50
TO51
8-bit timer/event counter 51.
P73/TI51
PCL
Output
Clock output (for trimming of main system clock and subsystem clock).
Input
BUZ
Output
Buzzer output.
Input
P74/TI011
P75/TI001/
TO01
AD0 to AD7
I/O
Lower address/data bus for extending memory externally.
Input
P40 to P47
A8 to A15
Output
Higher address bus for extending memory externally.
Input
P50 to P57
RD
Output
Strobe signal output for read operation of external memory.
Input
P64
WR
Strobe signal output for write operation of external memory.
WAIT
Input
ASTB
Output
P65
Inserting wait for accessing external memory.
Input
P66
Strobe output which externally latches address information output to
Input
P67
port 4 and port 5 to access external memory.
ANI0 to ANI7
Input
A/D converter analog input.
Input
P10 to P17
ADTRG
Input
A/D converter trigger signal input.
Input
P03/INTP3
AVREF
Input
A/D converter reference voltage and analog power supply.
—
—
AVSS
—
A/D converter ground potential. Set the same potential as that of VSS0 or VSS1.
—
—
Connecting crystal resonator for main system clock oscillation.
—
—
—
—
—
—
—
—
Input
—
X1
Input
X2
—
XT1
Input
XT2
—
RESET
Input
Connecting crystal resonator for subsystem clock oscillation.
System reset input.
VDD0
—
Positive power supply for ports.
—
—
VDD1
—
Positive power supply (except ports).
—
—
VSS0
—
Ground potential of ports.
—
—
VSS1
—
Ground potential (except ports).
—
—
IC
—
Internally connected. Connect directly to VSS0 or VSS1.
—
—
Data Sheet U14259EJ1V0DS
13
µPD780076, 780078, 780076Y, 780078Y
3.3 Pin I/O Circuits and Recommended Connection of Unused Pins
The I/O circuit type of each pin and recommended connection of unused pins are shown in Table 3-1.
For the I/O circuit configuration of each type, see Figure 3-1.
Table 3-1. Types of Pin I/O Circuits
Pin Name
P00/INTP0 to P02/INTP2
I/O
Circuit Type
I/O
8-C
I/O
P03/INTP3/ADTRG
Recommended Connection of Unused Pins
Input: Independently connect to VSS0 via a resistor.
Output: Leave open.
P10/ANI0 to P17/ANI7
25
Input
P20/SI1
8-C
I/O
P21/SO1
5-H
P22/SCK1
8-C
Connect to VDD0 or VSS0.
Input: Independently connect to VDD0 or VSS0 via a resistor.
Output: Leave open.
P23/RxD0
P24/TxD0
5-H
P25/ASCK0
8-C
P30, P31
13-Q
Input: Independently connect to VDD0 via a resistor.
P32, P33
(µPD780078 Subseries only)
P32/SDA0
(µPD780078Y Subseries only)
Output: Leave open.
13-R
P33/SCL0
(µPD780078Y Subseries only)
P34/SI3/TxD2
8-C
Input: Independently connect to VDD0 or VSS0 via a resistor.
P35/SO3/RxD2
Output: Leave open.
P36/SCK3/ASCK2
P40/AD0 to P47/AD7
5-H
Input: Independently connect to VDD0 via a resistor.
Output: Leave open.
P50/A8 to P57/A15
Input: Independently connect to VDD0 or VSS0 via a resistor.
P64/RD
Output: Leave open.
P65/WR
P66/WAIT
P67/ASTB
P70/TI000/TO00
8-C
P71/TI010
P72/TI50/TO50
P73/TI51/TO51
P74/TI011/PCL
P75/TI001/TO01/BUZ
P80/SS1
Input: Independently connect to VSS0 via a resistor.
Output: Leave open.
RESET
2
XT1
16
XT2
AVREF
Input
—
—
—
Connect to VDD0.
Leave open.
Connect to VSS0.
AVSS
IC
14
Connect directly to VSS0 or VSS1.
Data Sheet U14259EJ1V0DS
µPD780076, 780078, 780076Y, 780078Y
Figure 3-1. Pin I/O Circuits
TYPE 2
TYPE 13-R
IN/OUT
Data
Output disable
N-ch
IN
VSS0
Schmitt-triggered input with hysteresis characteristics
TYPE 5-H
Pull-up
enable
Data
TYPE 16
VDD0
Feedback
cut-off
P-ch
VDD0
P-ch
P-ch
IN/OUT
Output
disable
N-ch
VSS0
XT1
Input
enable
XT2
TYPE 25
TYPE 8-C
VDD0
Pull-up
enable
Data
P-ch
P-ch
Comparator
VDD0
–
N-ch
VSS0
VREF (threshold voltage)
P-ch
IN/OUT
Output
disable
+
N-ch
Input
enable
VSS0
TYPE 13-Q
IN
VDD0
 Mask 


 option 
IN/OUT
Data
Output disable
N-ch
VSS0
Input
enable
Data Sheet U14259EJ1V0DS
15
µPD780076, 780078, 780076Y, 780078Y
4. MEMORY SPACE
Figure 4-1 shows the memory map of the µPD780076, 780078, 780076Y, and 780078Y.
Figure 4-1. Memory Map
FFFFH
Special function registers
(SFR) 256 × 8 bits
FF00H
FEFFH
FEE0H
FEDFH
General-purpose
registers
32 × 8 bits
Internal high-speed RAM
1024 × 8 bits
FB00H
FAFFH
F800H
F7FFH
Reserved
nnnnH
Internal expansion RAM
1024 × 8 bits
Data memory
space
F400H
F3FFH
Program area
1000H
0FFFH
CALLF entry area
External memory
0800H
07FFH
nnnnH+1
nnnnH
Program area
Program memory
space
0080H
007FH
CALLT table area
Internal ROMNote
0040H
003FH
Vector table area
0000H
0000H
Note The internal ROM capacity depends on the products (see the following table).
Part Number
16
Internal ROM Last Address
nnnnH
Internal ROM Capacity
µPD780076, 780076Y
BFFFH
49152 × 8 bits
µPD780078, 780078Y
EFFFH
61440 × 8 bits
Data Sheet U14259EJ1V0DS
µPD780076, 780078, 780076Y, 780078Y
5. PERIPHERAL HARDWARE FUNCTION FEATURES
5.1 Ports
The following 3 types of I/O ports are available.
•
CMOS input (Port 1):
8
•
CMOS input/output (Port 0, 2, P34 to P36, Port 4 to 8):
40
•
N-channel open-drain input/output (P30 to P33):
4
Total:
52
Table 5-1. Port Functions
Name
Pin Name
Function
Port 0
P00 to P03
Input/output port pins. Input/output can be specified in 1-bit units.
An on-chip pull-up resistor can be specified by a software setting.
Port 1
P10 to P17
Input-only port pins.
Port 2
P20 to P25
Input/output port pins. Input/output can be specified in 1-bit units.
An on-chip pull-up resistor can be specified by a software setting.
Port 3
Port 4
P30 to P33
N-ch open-drain input/output port pins. Input/output can be specified in 1-bit units.
An on-chip pull-up resistor can be specified by a mask optionNote.
LEDs can be driven directly.
P34 to P36
Input/output port pins. Input/output can be specified in 1-bit units.
An on-chip pull-up resistor can be specified by a software setting.
P40 to P47
Input/output port pins. Input/output can be specified in 1-bit units.
An on-chip pull-up resistor can be specified by a software setting.
Test input flag (KRIF) is set to 1 by falling edge detection.
Port 5
P50 to P57
Input/output port pins. Input/output can be specified in 1-bit units.
An on-chip pull-up resistor can be specified by a software setting.
LEDs can be driven directly.
Port 6
P64 to P67
Input/output port pins. Input/output can be specified in 1-bit units.
An on-chip pull-up resistor can be specified by a software setting.
Port 7
P70 to P75
Input/output port pins. Input/output can be specified in 1-bit units.
An on-chip pull-up resistor can be specified by a software setting.
Port 8
P80
Input/output port pins. Input/output can be specified in 1-bit units.
An on-chip pull-up resistor can be specified by a software setting.
Note With the µPD780078Y Subseries, on-chip pull-up resistors can be specified using a mask option for P30
and P31.
Data Sheet U14259EJ1V0DS
17
µPD780076, 780078, 780076Y, 780078Y
5.2 Clock Generator
A system clock generator is incorporated.
The minimum instruction execution time can be changed.
• 0.24 µs/0.48 µs/0.95 µs/1.91 µs/3.81 µs (at 8.38 MHz operation with main system clock)
• 122 µs (at 32.768 kHz operation with subsystem clock)
Figure 5-1. Block Diagram of Clock Generator
XT1
Subsystem
clock
oscillator
XT2
fXT
Watch timer, clock
output function
Prescaler
1
X1
Main system
clock
oscillator
X2
Prescaler
fX
fX
2
fX
22
fX
23
2
fXT
2
Clock to peripheral
hardware
fX
24
STOP
Selector
Standby
controller
Wait
controller
CPU clock
(fCPU)
5.3 Timer/Event Counter
Six timer/event counter channels are incorporated.
•
16-bit timer/event counter:
2 channels
•
8-bit timer/event counter:
2 channels
•
Watch timer:
1 channel
•
Watchdog timer:
1 channel
Table 5-2. Operations of Timer/Event Counter
16-Bit Timer/Event
Counter 00, 01
8-Bit Timer/Event
Counter 50, 51
Watch Timer
Watchdog Timer
Operation
Interval timer
2 channels
2 channels
1 channelNote 1
1 channelNote 2
mode
External event counter
2 channels
2 channels
—
—
Function
Timer output
2 outputs
2 outputs
—
—
PWM output
—
2 outputs
—
—
PPG output
2 outputs
—
—
—
4 inputs
—
—
—
2 outputs
2 outputs
—
—
4
2
2
1
Pulse width measurement
Square wave output
Interrupt source
Notes 1. The watch timer can perform both watch timer and interval timer functions at the same time.
2. The watchdog timer has the watchdog timer and interval timer functions. However, use the watchdog
timer by selecting either the watchdog timer function or the interval timer function.
18
Data Sheet U14259EJ1V0DS
µPD780076, 780078, 780076Y, 780078Y
Figure 5-2. Block Diagram of 16-Bit Timer/Event Counter 00
TI010/P71
Selector
Noise
eliminator
Selector
Internal bus
16-bit timer capture/
compare register 000 (CR000)
INTTM000
Match
Selector
fX
fX/22
fX/26
16-bit timer counter 00
(TM00)
Output
controller
TO00/TI000/P70
Match
Noise
eliminator
Noise
eliminator
TI000/TO00/P70
16-bit timer capture/
compare register 010 (CR010)
Selector
fX/23
Clear
INTTM010
Internal bus
Figure 5-3. Block Diagram of 16-Bit Timer/Event Counter 01
Noise
eliminator
TI011/PCL/P74
Selector
Selector
Internal bus
INTTM001
16-bit timer capture/
compare register 001 (CR001)
fX/2
fX/23
fX/29
Selector
Match
16-bit timer counter 01
(TM01)
Clear
Output
controller
Match
fX/23
Noise
eliminator
Noise
eliminator
16-bit timer capture/
compare register 011 (CR011)
Selector
TI001/TO01/
BUZ/P75
TO01/TI001/
BUZ/P75
INTTM011
Internal bus
Remark 16-bit timer/event counter 01 shares pins with the clock output (PCL) and buzzer output (BUZ) functions,
in addition to the port function.
Data Sheet U14259EJ1V0DS
19
µPD780076, 780078, 780076Y, 780078Y
Figure 5-4. Block Diagram of 8-Bit Timer/Event Counter 50
Internal bus
Selector
INTTM50
S
Q
INV
8-bit timer counter OVF
50 (TM50)
R
Selector
Match
Selector
TI50/TO50/P72
fX
fX/22
fX/24
fX/26
fX/28
fX/210
Mask circuit
8-bit timer compare
register 50 (CR50)
TO50/TI50/P72
Clear
S
3
R
Selector
Level
inversion
TCE50 TMC506 TMC504 LVS50 LVR50 TMC501 TOE50
TCL502 TCL501 TCL500
8-bit timer mode control
register 50 (TMC50)
Timer clock selection
register 50 (TCL50)
Internal bus
Figure 5-5. Block Diagram of 8-Bit Timer/Event Counter 51
Internal bus
8-bit timer
counter 51
(TM51)
Selector
S
Q
INV
OVF
R
INTTM51
Selector
Match
Selector
TI51/TO51/P73
fX/2
fX/23
fX/25
fX/27
fX/29
fX/211
Mask circuit
8-bit timer
compare register
51 (CR51)
Clear
S
3
R
Selector
TCL512 TCL511 TCL510
Timer clock selection
register 51 (TCL51)
TCE51 TMC516 TMC514 LVS51 LVR51 TMC511 TOE51
8-bit timer mode control
register 51 (TMC51)
Internal bus
20
Level
inversion
Data Sheet U14259EJ1V0DS
TO51/TI51/P73
µPD780076, 780078, 780076Y, 780078Y
Selector
Figure 5-6. Block Diagram of Watch Timer
fX/27
5-bit counter
Clear
9-bit prescaler
fW
fW
24
fW
25
fW
26
fW
27
INTWT
fW
28
fW
29
Selector
fXT
Selector
Clear
INTWTI
WTM7 WTM6 WTM5 WTM4 WTM3 WTM1 WTM0
Watch timer operation
mode register (WTM)
Internal bus
Remark fX: Main system clock oscillation frequency
fXT: Subsystem clock oscillation frequency
fW: Watch timer clock frequency
Figure 5-7. Block Diagram of Watchdog Timer
fX
fX/28
Clock
input
controller
Division
circuit
Divided
clock
selector
Output
controller
INTWDT
RESET
RUN
Division mode
selector
3
WDT mode signal
OSTS2 OSTS1 OSTS0
Oscillation
stabilization time
selection register
(OSTS)
WDCS2 WDCS1 WDCS0
Watchdog timer
clock selection
register (WDCS)
RUN WDTM4 WDTM3
Watchdog timer
mode register
(WDTM)
Internal bus
Data Sheet U14259EJ1V0DS
21
µPD780076, 780078, 780076Y, 780078Y
5.4 Clock Output/Buzzer Output Controller
A clock output/buzzer output control circuit (CKU) is incorporated.
Clocks with the following frequencies can be output as clock output.
• 65.5 kHz/131 kHz/262 kHz/524 kHz/1.05 MHz/2.10 MHz/4.19 MHz/8.38 MHz (at 8.38 MHz operation with main
system clock)
• 32.768 kHz (at 32.768 kHz operation with subsystem clock)
Clocks with the following frequencies can be output as buzzer output.
• 1.02 kHz/2.05 kHz/4.10 kHz/8.19 kHz (at 8.38 MHz operation with main system clock)
Figure 5-8. Block Diagram of Clock Output/Buzzer Output Controller
Prescaler
8
4
fX/210 to fX/213
Selector
fX
BZOE
BUZ/TO01/TI001/P75
BCS0, BCS1
Selector
fX to fX/27
fXT
Clock
controller
PCL/TI011/P74
CLOE
BZOE
BCS1
BCS0
CLOE
CCS3
CCS2
CCS1
CCS0
Clock output selection register (CKS)
Internal bus
Remark The clock output/buzzer output controller shares pins with 16-bit timer/event counter 01, in addition to
the port function.
22
Data Sheet U14259EJ1V0DS
µPD780076, 780078, 780076Y, 780078Y
5.5 A/D Converter
An A/D converter of 10-bit resolution × 8 channels is incorporated.
The following two A/D conversion operation start-up methods are available.
• Hardware start
• Software start
Figure 5-9. Block Diagram of A/D Converter
Series resistor string
Sample & hold circuit
ANI0/P10
ANI1/P11
AVREF
(shared with analog
power supply)
Voltage comparator
ANI2/P12
Tap
selector
ANI3/P13
ANI4/P14
Selector
ANI5/P15
ANI6/P16
Successive approximation
register (SAR)
ANI7/P17
INTP3/ADTRG/P03
Edge
detector
Edge
detector
AVSS
INTAD0
Controller
A/D conversion
result register 0 (ADCR0)
INTP3
Internal bus
Data Sheet U14259EJ1V0DS
23
µPD780076, 780078, 780076Y, 780078Y
5.6 Serial Interface
Three channels of the serial interface are incorporated (four channels for the µPD780078Y Subseries).
•
Serial interface UART0
•
Serial interface UART2/SIO3
•
Serial interface CSI1
•
Serial interface IIC0 (µPD780078Y Subseries only)
(1) Serial interface UART0
The serial interface UART0 has two modes, asynchronous serial interface (UART) mode and infrared data
transfer mode.
• Asynchronous serial interface (UART) mode
This mode enables full-duplex operation wherein one byte of data is transmitted and received after the start
bit.
The on-chip dedicated UART baud rate generator enables communication using a wide range of selectable
baud rates.
In addition, a baud rate can be also defined by dividing the clock input to the ASCK0 pin.
The dedicated UART baud rate generator can also be used to generate a MIDI-standard baud rate (31.25
Kbps).
• Infrared data transfer mode
This mode enables pulse output and pulse reception in an IrDA specification data formatNote.
This mode can be used for office equipment applications such as personal computers.
Note Transfer rate differs with that of IrDA standard.
Figure 5-10. Block Diagram of Serial Interface UART0
Internal bus
Asynchronous serial
interface mode
register 0 (ASIM0)
Receive
buffer
RXB0 register 0
TXE0 RXE0 PS01 PS00 CL0
SL0 ISRM0 IRDAM0
Asynchronous serial
interface status
register 0 (ASIS0)
RxD0/P23
RX0 Receive
shift
register 0
PE0 FE0 OVE0
TXS0 Transmit
shift
register 0
TxD0/P24
Receive
control
parity
check
Transmit
INTSER0 control
INTSR0
parity
addition
INTST0
Baud rate
generator
24
Data Sheet U14259EJ1V0DS
ASCK0/P25
fX/2 to fX/27
µPD780076, 780078, 780076Y, 780078Y
(2) Serial interface UART2/SIO3
The serial interface UART2/SIO3 has two modes, asynchronous serial (UART) interface mode and 3-wire
serial I/O mode.
Caution Do not enable UART2 and SIO3 at the same time.
(a) Serial interface UART2
The serial interface UART2 has three modes, asynchronous serial interface (UART) mode, multiprocessor
transfer mode, and infrared data transfer mode.
• Asynchronous serial interface (UART) mode
This mode enables full-duplex operation wherein one byte of data is transmitted and received after the
start bit.
The on-chip dedicated UART baud rate generator enables communication using a wide range of
selectable baud rates.
In addition, a baud rate can be also defined by dividing the clock input to the ASCK2 pin.
The dedicated UART baud rate generator can also be used to generate a MIDI-standard baud rate
(31.25 Kbps).
• Multiprocessor transfer mode
This mode enables multiprocessor compatible data transmission/reception.
• Infrared data transfer (IrDA) mode
This mode enables pulse output and pulse reception in an IrDA specification data format.
This mode can be used for office equipment applications such as personal computers.
Figure 5-11. Block Diagram of Serial Interface UART2
Internal bus
Asynchronous serial interface
mode register 2 (ASIM2)
RXB2
RxD2/SO3/P35
Receive buffer
register 2
RX2 Receive
shift
register 2
TXB2
Transmit buffer
register 2
SL2 ISEM2
Asynchronous serial interface
status register 2 (ASIS2)
TXS2 Transmit
shift
MPR2 PE2 FE2 OVE2
register 2
Transmit
control
parity
addition
TxD2/SI3/P34
Receive
control
parity check
POWER2 TXE2 RXE2 PS21 PS20 CL2
INTST2
INTSER2
INTSR2
Baud rate
generator
Data Sheet U14259EJ1V0DS
ASCK2/SCK3/P36
fX/2 to fX/27
25
µPD780076, 780078, 780076Y, 780078Y
(b) Serial interface SIO3
The serial interface SIO3 has the 3-wire serial I/O mode.
• 3-wire serial I/O mode (fixed as MSB first)
This is an 8-bit data transfer mode using three lines: serial clock line (SCK3), serial output line (SO3),
and serial input line (SI3).
Since simultaneous transmit and receive operations are available in the 3-wire serial I/O mode, the
processing time for data transfer is reduced.
The first bit in 8-bit data in the serial transfer is fixed as MSB.
The 3-wire serial I/O mode is useful for connection to a peripheral I/O device that includes a clocked
serial interface, a display controller, etc.
Figure 5-12. Block Diagram of Serial Interface SIO3
Internal bus
8
Serial I/O shift register
3 (SIO3)
SI3/TxD2/P34
SO3/RxD2/P35
SCK3/ASCK2/P36
Serial clock
counter
Serial clock
controller
26
Data Sheet U14259EJ1V0DS
Interrupt request
signal generator
Selector
INTCSI3
fX/23
fX/24
fX/25
µPD780076, 780078, 780076Y, 780078Y
(3) Serial interface CSI1
The serial interface CSI1 has the 3-wire serial I/O mode.
• 3-wire serial I/O mode (MSB/LSB first selectable)
This is an 8-bit data transfer mode using three lines: serial clock line (SCK1), serial output line (SO1), and
serial input line (SI1).
Since simultaneous transmit and receive operations are available in the 3-wire serial I/O mode, the
processing time for data transfer is reduced.
The serial transfer of 8-bit data can be switched between MSB or LSB first, enabling the chip to be connected
to devices using either mode.
The 3-wire serial I/O mode is useful for connection to a peripheral I/O device that includes a clocked serial
interface, a display controller, etc.
Figure 5-13. Block Diagram of Serial Interface CSI1
Internal bus
SI1/P20
8
8
Serial I/O shift
register 1 (SIO1)
Transmit buffer
register 1 (SOTB1)
Transmit data
controller
Output
selector
SO1/P21
Output latch
Transmit controller
fX/2 to fX/27
SCK1/P22
Selector
Clock start/stop controller &
clock phase controller
INTCSI1
SS1/P80
Data Sheet U14259EJ1V0DS
27
µPD780076, 780078, 780076Y, 780078Y
(4) Serial interface IIC0 (µPD780078Y Subseries only)
The serial interface IIC0 has the I2C (Inter IC) bus mode (multimaster supported).
• I2C bus mode (multimaster supported)
This is an 8-bit data transfer mode using two lines: serial clock line (SCL0) and serial data bus line (SDA0).
This mode complies with the I2C bus format, and can output “start condition”, “data”, and “stop condition”
during transmission via the serial data bus. These data are automatically detected by hardware during
reception.
Since the SCL0 and SDA0 are open-drain outputs in IIC0, pull-up resistors for the serial clock line and the
serial data bus line are required.
Figure 5-14. Block Diagram of Serial Interface IIC0
Internal bus
IIC status register 0
(IICS0)
MSTS0 ALD0 EXC0 COI0 TRC0 ACKD0 STD0 SPD0
IIC control register 0
(IICC0)
Slave address
register 0 (SVA0)
SDA0/P32
Noise
eliminator
IICE0 LREL0 WREL0 SPIE0 WTIM0 ACKE0 STT0
Matched
signal
IIC shift register
0 (IIC0)
SPT0
CLEAR
SET
SO0 latch
D
CL00
Data hold
time correction
circuit
N-ch opendrain output
Acknowledge
detector
Wake-up controller
Acknowledge detector
Start condition
detector
Stop condition
detector
SCL0/P33
Noise
eliminator
Interrupt request
signal generator
Serial clock counter
Serial clock wait
controller
Serial clock controller
N-ch opendrain output
fX
Prescaler
CLD0 DAD0 SMC0 DFC0 CL00
IIC transfer clock selection
register 0 (IICCL0)
Internal bus
28
Data Sheet U14259EJ1V0DS
INTIIC0
µPD780076, 780078, 780076Y, 780078Y
6. INTERRUPT FUNCTIONS
A total of 25 interrupt sources (26 sources for the µPD780078Y Subseries) are provided, divided into the following
three types.
•
Non-maskable: 1
•
Maskable:
23 (24 for the µPD780078Y Subseries)
•
Software:
1
Table 6-1. Interrupt Source List (1/2)
Interrupt
Default
Interrupt Source
Type
PriorityNote 1
Name
Nonmaskable
—
INTWDT
Maskable
0
INTWDT
Trigger
Watchdog timer overflow (non-maskable
interrupt selected)
Internal/
Vector Table
External
Address
Internal
0004H
Watchdog timer overflow (interval timer mode
Basic
Configuration
TypeNote 2
(A)
(B)
selected)
1
INTP0
Pin input edge detection
External
2
INTP1
0008H
3
INTP2
000AH
4
INTP3
000CH
5
INTSER0
Generation of serial interface UART0 reception error
6
INTSR0
End of serial interface UART0 reception
0010H
7
INTST0
End of serial interface UART0 transmission
0012H
8
INTCSI1
End of serial interface CSI1 transfer
0014H
9
INTCSI3
End of serial interface SIO3 transfer
0016H
10
INTIIC0Note 3
End of serial interface IIC0 transfer
0018H
11
INTWTI
Reference time interval signal from watch timer
001AH
12
INTTM000
Coincidence of TM00 and CR000 (when
compare register is specified) or detection of
valid edge of TI010 (when capture register is
specified)
001CH
13
INTTM010
Coincidence of TM00 and CR010 (when
compare register is specified) or detection of
valid edge of TI000 (when capture register is
specified)
001EH
14
INTTM50
Coincidence of TM50 and CR50
0020H
15
INTTM51
Coincidence of TM51 and CR51
0022H
16
INTAD0
End of conversion by A/D converter
0024H
17
INTWT
Watch timer overflow
0026H
18
INTKR
Falling edge detection of port 4
Internal
External
0006H
000EH
0028H
(C)
(B)
(D)
Notes 1. The default priority is a priority order when two or more maskable interrupt requests are generated
simultaneously. 0 is the highest order and 23, the lowest.
2. Basic configuration types (A) to (E) correspond to (A) to (E) in Figure 6-1, respectively.
3. µPD780078Y Subseries only.
Remark As the watchdog timer interrupt source (INTWDT), a non-maskable interrupt or maskable interrupt
(internal) can be selected.
Data Sheet U14259EJ1V0DS
29
µPD780076, 780078, 780076Y, 780078Y
Table 6-1. Interrupt Source List (2/2)
Interrupt
Default
Type
PriorityNote 1
Name
Maskable
19
INTSER2
Generation of UART2 reception error
20
INTSR2
End of UART2 reception
Software
Interrupt Source
Trigger
Internal/
Vector Table
External
Address
Internal
002AH
Basic
Configuration
TypeNote 2
(B)
002CH
transferNote 3
21
INTST2
End of UART2 transmission/data
002EH
22
INTTM001
Coincidence of TM01 and CR001 (when
compare register specified) or detection of
TI011 valid edge (when capture register
specified)
0030H
23
INTTM011
Coincidence of TM01 and CR011 (when
compare register specified) or detection of
TI001 valid edge (when capture register
specified)
0032H
—
BRK
BRK instruction execution
—
003EH
(E)
Notes 1. The default priority is a priority order when two or more maskable interrupt requests are generated
simultaneously. 0 is the highest order and 23, the lowest.
2. Basic configuration types (A) to (E) correspond to (A) to (E) in Figure 6-1, respectively.
3. This source generates an interrupt request signal during data transfer from the transmit buffer register
2 (TXB2) to the transmit shift register. Interrupt sources can be selected by the transmit interrupt signal
select flag (ISMD).
30
Data Sheet U14259EJ1V0DS
µPD780076, 780078, 780076Y, 780078Y
Figure 6-1. Basic Configuration of Interrupt Function (1/2)
(A) Internal non-maskable interrupt
Internal bus
Interrupt
request
Vector table
address
generator
Priority
controller
Standby release
signal
(B) Internal maskable interrupt
Internal bus
MK
Interrupt
request
PR
IE
ISP
Vector table
address
generator
Priority
controller
IF
Standby release
signal
(C) External maskable interrupt (INTP0 to INTP3)
Internal bus
External interrupt
edge enable register
(EGP, EGN)
Interrupt
request
Edge
detector
MK
IE
IF
PR
Priority
controller
ISP
Vector table
address
generator
Standby release
signal
Data Sheet U14259EJ1V0DS
31
µPD780076, 780078, 780076Y, 780078Y
Figure 6-1. Basic Configuration of Interrupt Function (2/2)
(D) External maskable interrupt (INTKR)
Internal bus
MK
Interrupt
request
Falling edge
detector
IE
PR
ISP
Priority
controller
IF
Vector table
address
generator
Standby release
signal
(E) Software interrupt
Internal bus
Priority
controller
Interrupt
request
IF:
32
Interrupt request flag
IE:
Interrupt enable flag
ISP:
In-service priority flag
MK:
Interrupt mask flag
PR:
Priority specification flag
Data Sheet U14259EJ1V0DS
Vector table
address
generator
µPD780076, 780078, 780076Y, 780078Y
7. EXTERNAL DEVICE EXPANSION FUNCTIONS
The external device expansion functions connect external devices to areas other than the internal ROM, RAM and
SFR. Ports 4 to 6 are used for external device connection.
8. STANDBY FUNCTION
There are the following two standby functions to reduce the consumption current.
• HALT mode: The CPU operating clock is stopped. The average consumption current can be reduced by
intermittent operation in combination with the normal operating mode.
• STOP mode: The main system clock oscillation is stopped. The whole operation by the main system clock is
stopped, so that the system operates with ultra-low power consumption. This mode can be used
only when the main system clock is operating (it cannot be used to stop the subsystem clock).
Figure 8-1. Standby Function
CSS = 1
Main system
clock operation
Interrupt
request
CSS = 0
HALT
instruction
STOP
instruction
Interrupt
request
STOP mode
(Main system clock
oscillation stopped)
HALT mode
(Clock supply to CPU halted,
oscillation maintained)
Subsystem clock
operationNote
HALT
instruction
Interrupt
request
HALT modeNote
(Clock supply to CPU halted,
oscillation maintained)
Note The current consumption can be reduced by stopping the main system clock.
When the CPU is operating on the subsystem clock, set bit 7 (MCC) of the processor clock control register
(PCC) to stop the main system clock. The STOP instruction cannot be used.
Caution When the main system clock is stopped and the device is operating on the subsystem clock, wait
until the oscillation stabilization time has been secured by the program before switching back
to the main system clock.
Data Sheet U14259EJ1V0DS
33
µPD780076, 780078, 780076Y, 780078Y
9. RESET FUNCTION
The following two reset methods are available.
• External reset by RESET pin
• Internal reset by watchdog timer inadvertent program loop time detection
10. MASK OPTION
Table 10-1. Selection of Pin Mask Options
Subseries
Pin
µPD780078 Subseries
P30 to P33
µPD780078Y Subseries
P30, P31
Mask Option
An on-chip pull-up resistor can be specified in 1-bit
units.
P30 to P33Note on-chip pull-up resistor can be specified by mask option. The mask option can be specified in
1-bit units.
Note Only P30 and P31 can be specified on the µPD780078Y Subseries.
34
Data Sheet U14259EJ1V0DS
µPD780076, 780078, 780076Y, 780078Y
11. INSTRUCTION SET
(1) 8-bit instructions
MOV, XCH, ADD, ADDC, SUB, SUBC, AND, OR, XOR, CMP, MULU, DIVUW, INC, DEC, ROR,
ROL, RORC, ROLC, ROR4, ROL4, PUSH, POP, DBNZ
Second
operand
First
operand
A
r
[HL + byte]
#byte
A
Note
r
sfr
saddr
!addr16
PSW
[DE]
[HL]
[HL + B]
$addr16
1
None
[HL + C]
ADD
MOV
MOV
MOV
MOV
ADDC
XCH
XCH
XCH
XCH
SUB
ADD
ADD
ADD
SUBC
ADDC
ADDC
ADDC
AND
SUB
SUB
MOV
MOV
MOV
ROR
XCH
XCH
ROL
ADD
ADD
RORC
ADDC
ADDC
ROLC
SUB
SUB
SUB
SUBC
XCH
MOV
OR
SUBC
SUBC
SUBC
SUBC
XOR
AND
AND
AND
AND
AND
CMP
OR
OR
OR
OR
OR
XOR
XOR
XOR
XOR
XOR
CMP
CMP
CMP
CMP
CMP
MOV
MOV
ADD
INC
DEC
ADDC
SUB
SUBC
AND
OR
XOR
CMP
DBNZ
B, C
sfr
MOV
MOV
saddr
MOV
MOV
DBNZ
ADD
INC
DEC
ADDC
SUB
SUBC
AND
OR
XOR
CMP
!addr16
PSW
MOV
MOV
MOV
PUSH
POP
[DE]
MOV
[HL]
MOV
ROR4
ROL4
[HL + byte]
MOV
[HL + B]
[HL + C]
X
MULU
C
DIVUW
Note Except r = A
Data Sheet U14259EJ1V0DS
35
µPD780076, 780078, 780076Y, 780078Y
(2) 16-bit instructions
MOVW, XCHW, ADDW, SUBW, CMPW, PUSH, POP, INCW, DECW
Second operand
First operand
AX
#word
rpNote
AX
MOVW
ADDW
SUBW
CMPW
MOVW
saddrp
!addr16
MOVW
MOVW
SP
None
MOVW
XCHW
rp
MOVW
MOVWNote
sfrp
MOVW
MOVW
saddrp
MOVW
MOVW
!addr16
SP
sfrp
INCW, DECW
PUSH, POP
MOVW
MOVW
MOVW
Note Only when rp = BC, DE or HL
(3) Bit manipulation instructions
MOV1, AND1, OR1, XOR1, SET1, CLR1, NOT1, BT, BF, BTCLR
Second operand
First operand
A.bit
sfr.bit
saddr.bit
PSW.bit
[HL].bit
CY
$addr16
None
A.bit
MOV1
BT
BF
BTCLR
SET1
CLR1
sfr.bit
MOV1
BT
BF
BTCLR
SET1
CLR1
saddr.bit
MOV1
BT
BF
BTCLR
SET1
CLR1
PSW.bit
MOV1
BT
BF
BTCLR
SET1
CLR1
[HL].bit
MOV1
BT
BF
BTCLR
SET1
CLR1
CY
MOV1
AND1
MOV1
AND1
MOV1
AND1
MOV1
AND1
MOV1
AND1
SET1
CLR1
OR1
XOR1
OR1
XOR1
OR1
XOR1
OR1
XOR1
OR1
XOR1
NOT1
(4) Call instructions/branch instructions
CALL, CALLF, CALLT, BR, BC, BNC, BZ, BNZ, BT, BF, BTCLR, DBNZ
Second operand
First operand
Basic instruction
AX
BR
!addr16
CALL
BR
!addr11
CALLF
[addr5]
CALLT
$addr16
BR, BC, BNC
BZ, BNZ
BT, BF
BTCLR
DBNZ
Compound
instruction
(5) Other instructions
ADJBA, ADJBS, BRK, RET, RETI, RETB, SEL, NOP, EI, DI, HALT, STOP
36
Data Sheet U14259EJ1V0DS
µPD780076, 780078, 780076Y, 780078Y
12. ELECTRICAL SPECIFICATIONS
Absolute Maximum Ratings (TA = 25°C)
Parameter
Supply voltage
Symbol
Conditions
VDD
AVREF
Unit
–0.3 to +6.5
V
–0.3 to VDD +
AVSS
Input voltage
Ratings
–0.3 to
0.3Note
+0.3Note
V
V
0.3Note
V
VI1
P00 to P03, P10 to P17, P20 to P25, P34 to P36,
P40 to P47, P50 to P57, P64 to P67, P70 to P75, P80,
X1, X2, XT1, XT2, RESET
–0.3 to VDD +
VI2
P30 to P33
–0.3 to VDD + 0.3Note
V
0.3Note
V
Output voltage
VO
Analog input
voltage
VAN
P10 to P17
Output current,
IOH
high
Output current, low IOL
N-ch open-drain
–0.3 to VDD +
Analog input pin
AV SS – 0.3 to AVREF + 0.3
and –0.3 to VDD + 0.3
V
Per pin
–10
mA
Total for P00 to P03, P40 to P47, P50 to P57, P64 to P67,
P70 to P75, P80
–15
mA
Total for P20 to P25, P30 to P36
–15
mA
Per pin for P00 to P03, P20 to P25, P34 to P36,
P40 to P47, P64 to P67, P70 to P75, P80
20
mA
Per pin for P30 to P33, P50 to P57
30
mA
Total for P00 to P03, P40 to P47, P64 to P67,
50
mA
Total for P20 to P25
20
mA
Total for P30 to P36
100
mA
Total for P50 to P57
100
mA
P70 to P75, P80
Operating ambient
temperature
TA
–40 to +85
°C
Storage
Tstg
–40 to +150
°C
temperature
Note 6.5 V or below.
Caution Product quality may suffer if the absolute maximum rating is exceeded for even single parameter
or even momentarily. That is, the absolute maximum ratings are rated values at which the product
is on the verge of suffering physical damage, and therefore the product must be used under
conditions ensuring that the absolute maximum ratings are not exceeded.
Data Sheet U14259EJ1V0DS
37
µPD780076, 780078, 780076Y, 780078Y
Capacitance (TA = 25°C, VDD = VSS = 0 V)
Parameter
Symbol
Conditions
Input
capacitance
CIN
f = 1 MHz
Unmeasured pins returned to 0 V.
I/O
CIO
f = 1 MHz
Unmeasured pins
returned to 0 V.
capacitance
P00
P34
P50
P70
to
to
to
to
P03,
P36,
P57,
P75,
MIN.
TYP.
P20 to P25,
P40 to P47,
P64 to P67,
P80
P30 to P33
MAX.
Unit
15
pF
15
pF
20
pF
Remark Unless specified otherwise, alternate-function pin characteristics are the same as port pin
characteristics.
Main System Clock Oscillator Characteristics (TA = –40 to 85°C, VDD = 1.8 to 5.5 V)
Resonator
Ceramic
Recommended Circuit
X1
X2 IC
C1
X1
C2
X2 IC
C1
C2
External
clock
Oscillation
Conditions
VDD = 4.0 to 5.5 V
MIN.
TYP.
MAX.
Unit
1.0
8.38
MHz
1.0
5.0
MHz
4
ms
1.0
8.38
MHz
1.0
5.0
MHz
10
ms
30
ms
8.38
MHz
5.0
MHz
50
500
ns
85
500
ns
frequency (fX)Note 1
resonator
Crystal
resonator
Parameter
Oscillation
After VDD reaches oscilstabilization timeNote 2 lation voltage range MIN.
Oscillation
frequency (fX)Note 1
Oscillation
VDD = 4.0 to 5.5 V
stabilization timeNote 2
X1 input
X1
X2
µ PD74HCU04
VDD = 4.0 to 5.5 V
VDD = 4.0 to 5.5 V
1.0
frequency (fX)Note 1
X1 input
high-/low-level width
(tXH, tXL)
VDD = 4.0 to 5.5 V
Notes 1. Indicates only oscillator characteristics.
2. Time required to stabilize oscillation after reset or STOP mode release.
Cautions 1. When using the main system clock oscillator, wiring in the area enclosed with the broken line
in the above figures should be carried out as follows to avoid an adverse effect from wiring
capacitance.
• Keep the wiring length as short as possible.
• Do not cross the wiring with the other signal lines.
• Do not route the wiring near a line through which a high fluctuating current flows.
• Always keep the ground point of the oscillator to the same potential as VSS1.
• Do not ground the capacitor to a ground pattern in which a high current flows.
• Do not fetch signals from the oscillator.
2. When the main system clock is stopped and the system is operated by the subsystem clock,
the subsystem clock should be switched again to the main system clock after the oscillation
stabilization time is secured by the program.
38
Data Sheet U14259EJ1V0DS
µPD780076, 780078, 780076Y, 780078Y
Subsystem Clock Oscillator Characteristics (TA = –40 to +85°C, VDD = 1.8 to 5.5 V)
Resonator
Crystal
resonator
Recommended Circuit
XT2
R
C4
External
XT1 IC
C3
XT2
Parameter
Conditions
Oscillation
frequency (fXT)Note 1
MIN.
TYP.
MAX.
Unit
32
32.768
35
kHz
1.2
2
s
10
s
32
38.5
kHz
5
15
µs
Oscillation
VDD = 4.0 to 5.5 V
stabilization timeNote 2
XT1
XT1 input frequency
(fXT)Note 1
clock
µPD74HCU04
XT1 input high-/low- level width (tXTH, tXTL)
Notes 1. Indicates only oscillator characteristics.
2. Time required to stabilize oscillation after VDD reaches oscillation voltage MIN.
Cautions 1. When using the subsystem clock oscillator, wiring in the area enclosed with the broken line
in the above figures should be carried out as follows to avoid an adverse effect from wiring
capacitance.
• Keep the wiring length as short as possible.
• Do not cross the wiring with the other signal lines.
• Do not route the wiring near a line through which a high fluctuating current flows.
• Always keep the ground point of the oscillator to the same potential as VSS1.
• Do not ground the capacitor to a ground pattern in which a high current flows.
• Do not fetch signals from the oscillator.
2. The subsystem clock oscillator is a low-amplitude circuit in order to achieve a low consumption current, and is more prone to malfunction due to noise than the main system clock
oscillator. Particular care is therefore required with the wiring method when the subsystem
clock is used.
Data Sheet U14259EJ1V0DS
39
µPD780076, 780078, 780076Y, 780078Y
Recommended Oscillator Constant
Main system clock: Ceramic resonator (TA = –45 to +85°C)
Manufacturer
Part Number
Murata Mfg.
CSB1000J
Co., Ltd.
CSBF1000J
CSA2.00MG040
Frequency Recommended Circuit Constant
(MHz)
C1 (pF)
C2 (pF)
MIN. (V)
MAX. (V)
1.00
150
150
1.8
5.5
2.00
100
100
On-chip
On-chip
2.0
5.5
1.8
5.5
2.0
5.5
1.8
5.5
2.0
5.5
1.8
5.5
2.0
5.5
1.8
5.5
2.0
5.5
1.8
5.5
2.0
5.5
4.0
5.5
1.8
5.5
4.0
5.5
CST2.00MG040
CSTCC2.00MG0H6
CSA3.58MG
3.58
CST3.58MGW
30
30
On-chip
On-chip
CSTCC3.58MG0H6
CSA4.00MG
4.00
CSTS0400MH06
30
30
On-chip
On-chip
CSTCC4.0MG0H6
CSA4.19MG
4.19
CSTS0419MG06
30
30
On-chip
On-chip
CSTCC4.19MG0H6
CSA4.91MG
4.91
CSTS0491MG03
30
30
On-chip
On-chip
CSTCC4.91MG0H6
CSA5.00MG
5.00
CSTS0500MG03
30
30
On-chip
On-chip
CSTCC5.00MG0H6
CSA8.00MTZ
Oscillation Voltage Range
8.00
CSTS0800MG03
30
30
On-chip
On-chip
30
30
On-chip
On-chip
On-chip
On-chip
Remarks
–
CSTCC8.00MG
CSA8.38MTZ
8.38
CSTS0838MG03
CSTCC8.38MG
TDK
CCR3.58MC3
3.58
CCR4.0MC3
4.00
CCR4.19MC3
4.19
CCR5.0MC3
5.00
CCR6.0MC3
6.00
CCR8.0MC5
8.00
CCR8.38MC5
8.38
Caution The oscillator constant and oscillation voltage range indicate conditions of stable oscillation.
Oscillation frequency precision is not guaranteed. For applications requiring oscillation
frequency precision, the oscillation frequency must be adjusted on the implementation circuit.
For details please contact directly the manufacturer of the resonator you will use.
40
Data Sheet U14259EJ1V0DS
µPD780076, 780078, 780076Y, 780078Y
Main system clock: Crystal resonator (TA = –10 to +70°C)
Manufacturer
Kinseki, Ltd.
Part Number
HC-49/U-SNote
Frequency Recommended Circuit Constant
Oscillation Voltage Range
Remarks
(MHz)
C1 (pF)
C2 (pF)
MIN. (V)
MAX. (V)
4.19
18
18
1.9
5.5
R = 4.7 kΩ
8.38
27
27
4.0
5.5
–
Note A limiting resistor (R = 4.7 kΩ) is required when the HU-49/U-S manufactured by Kinseki, Ltd. is used as
the ceramic resonator (see the figure below) at fX = 4.19 MHz.
X1
X2
HC-49/U-S
(4.19 MHz)
R
C2
C1
Subsystem clock: Crystal resonator (TA = –40 to +85°C)
Manufacturer
Seiko
Epson Inc.
Part Number
C-002RXNote
MC-206Note
MC-306Note
Frequency Recommended Circuit Constant
Oscillation Voltage Range
(MHz)
C1 (pF)
C2 (pF)
MIN. (V)
32.768
15
15
1.8
Remarks
MAX. (V)
5.5
R = 330 kΩ
Note A limiting resistor (R = 330 kΩ) is required when the C-002RX, MC-206, or MC-306 manufactured by Seiko
Epson Inc. is used as the ceramic resonator (see the figure below).
XT2
R
C4
XT1
C-002RX
MC-206
MC-306
C3
Caution The oscillator constant and oscillation voltage range indicate conditions of stable oscillation.
Oscillation frequency precision is not guaranteed. For applications requiring oscillation
frequency precision, the oscillation frequency must be adjusted on the implementation circuit.
For details please contact directly the manufacturer of the resonator you will use.
Data Sheet U14259EJ1V0DS
41
µPD780076, 780078, 780076Y, 780078Y
DC Characteristics (TA = –40 to +85°C, VDD = 1.8 to 5.5 V)
Parameter
Symbol
Output current,
high
IOH
Output current,
low
IOL
Input voltage,
high
VIH1
MIN.
MAX.
Unit
Per pin
–1
mA
All pins
–15
mA
Per pin for P00 to P03, P20 to P25, P34 to P36,
P40 to P47, P64 to P67, P70 to P75, P80
10
mA
Per pin for P30 to P33, P50 to P57
15
mA
Total for P00 to P03, P40 to P47, P64 to P67,
P70 to P75, P80
20
mA
Total for P20 to P25
10
mA
Total for P30 to P36
70
mA
Total for P50 to P57
70
mA
0.7VDD
VDD
V
0.8VDD
VDD
V
P10 to P17, P21, P24, P40 to P47,
P50 to P57, P64 to P67
VDD = 2.7 to 5.5 V
P00 to P03, P20, P22, P23, P25,
P34 to P36, P70 to P75, P80,
RESET
VDD = 2.7 to 5.5 V
VIH3
P30 to P33 (N-ch open-drain)
VIH4
X1, X2
VIH2
Input voltage,
low
Conditions
TYP.
0.8VDD
VDD
V
0.85VDD
VDD
V
VDD = 2.7 to 5.5 V
0.7VDD
VDD
V
0.8VDD
VDD
V
VDD = 2.7 to 5.5 V
VDD – 0.5
VDD
V
VDD – 0.2
VDD
V
0.8VDD
VDD
V
0.9VDD
VDD
V
0
0.3VDD
V
0
0.2VDD
V
0
0.2VDD
V
0
0.15VDD
V
VIH5
XT1, XT2
VDD = 4.0 to 5.5 V
VIL1
P10 to P17, P21, P24, P40 to P47,
P50 to P57, P64 to P67
VDD = 2.7 to 5.5 V
P00 to P03, P20, P22, P23, P25,
P34 to P36, P70 to P75, P80,
RESET
VDD = 2.7 to 5.5 V
P30 to P33 (N-ch open-drain)
4.0 V ≤ VDD ≤ 5.5 V
0
0.3VDD
V
2.7 V ≤ VDD < 4.0 V
0
0.2VDD
V
1.8 V ≤ VDD < 2.7 V
0
0.1VDD
V
VDD = 2.7 to 5.5 V
0
0.4
V
0
0.2
V
0
0.2VDD
V
0
0.1VDD
V
VIL2
VIL3
VIL4
VIL5
Output voltage,
high
VOH1
Output voltage,
low
X1, X2
XT1, XT2
VDD = 4.0 to 5.5 V
IOH = –1 mA
VDD = 4.0 to 5.5 V
VDD – 1.0
VDD
V
IOH = –100 µA
VDD = 1.8 to 5.5 V
VDD – 0.5
VDD
V
VOL1
P30 to P33
VDD = 4.0 to 5.5 V,
IOL = 15 mA
2.0
V
VOL2
P50 to P57
VDD = 4.0 to 5.5 V,
IOL = 15 mA
2.0
V
VOL3
P00 to P03, P20 to P25,
P34 to P36, P40 to P47,
P64 to P67, P70 to P75, P80
VDD = 4.0 to 5.5 V,
IOL = 1.6 mA
0.4
V
VOL4
IOL = 400 µA
0.5
V
0.4
Remark Unless specified otherwise, alternate-function pin characteristics are the same as port pin
characteristics.
42
Data Sheet U14259EJ1V0DS
µPD780076, 780078, 780076Y, 780078Y
DC Characteristics (TA = –40 to +85°C, VDD = 1.8 to 5.5 V)
Parameter
Input leakage
current, high
Symbol
ILIH1
Conditions
VIN = VDD
ILIH2
Input leakage
current, low
P00 to P03,
P20 to P25,
P40 to P47,
P64 to P67,
RESET
MIN.
P10
P34
P50
P70
to
to
to
to
TYP.
P17,
P36,
P57,
P75, P80,
X1, X2, XT1, XT2
Unit
3
µA
20
µA
3
µA
–3
µA
X1, X2, XT1, XT2
–20
µA
P30 to P33
ILIH3
VIN = 5.5 V
P30 to P33
ILIL1
VIN = 0 V
P00 to P03,
P20 to P25,
P40 to P47,
P64 to P67,
RESET
ILIL2
MAX.
P10
P34
P50
P70
to
to
to
to
P17,
P36,
P57,
P75, P80,
–3
µA
Output leakage
current, high
ILOH
VOUT = VDD
3
µA
Output leakage
ILOL
VOUT = 0 V
–3
µA
Mask option
pull-up resistor
R1
VIN = 0 V, P30, P31, P32Note, P33Note
15
30
90
kΩ
Software pull-up
resistor
R2
VIN = 0 V, P00 to P03, P20 to P25, P34 to P36,
P40 to P47, P50 to P57, P64 to P67, P70 to P75, P80
15
30
90
kΩ
ILIL3
current, low
Note µPD780078 Subseries only.
Remark Unless specified otherwise, alternate-function pin characteristics are the same as port pin
characteristics.
Data Sheet U14259EJ1V0DS
43
µPD780076, 780078, 780076Y, 780078Y
DC Characteristics (TA = –40 to +85°C, VDD = 1.8 to 5.5 V)
Parameter Symbol
Power
supply
currentNote 1
IDD1Note 2
Conditions
8.38 MHz crystal
VDD = 5.0 V
oscillation operating
mode
5.0 MHz crystal
±10%Note 3
VDD = 3.0 V ±10%Note 3
oscillation operating
mode
IDD2
8.38 MHz crystal
VDD = 2.0 V
±10%Note 4
VDD = 5.0 V
±10%Note 3
VDD = 3.0 V
±10%Note 3
VDD = 2.0 V
±10%Note 4
oscillation HALT mode
5.0 MHz crystal
When A/D converter stopped
5.5
11.0
mA
When A/D converter is operating
6.5
13.0
mA
When A/D converter stopped
2.0
4.0
mA
When A/D converter is operating
3.0
6.0
mA
When A/D converter stopped
0.4
1.5
mA
When A/D converter is operating
1.4
4.2
mA
When peripheral function stopped
1.1
2.2
mA
4.7
mA
0.7
mA
1.7
mA
0.4
mA
1.1
mA
When peripheral function is operating
oscillation HALT
mode
MIN. TYP. MAX. Unit
When peripheral function stopped
0.35
When peripheral function is operating
When peripheral function stopped
0.15
When peripheral function is operating
IDD3
IDD4
VDD = 5.0 V ±10%
40
80
µA
oscillation operating VDD = 3.0 V ±10%
modeNote 5
VDD = 2.0 V ±10%
20
40
µA
10
20
µA
32.768 kHz crystal
VDD = 5.0 V ±10%
30
60
µA
oscillation HALT
VDD = 3.0 V ±10%
6
18
µA
VDD = 2.0 V ±10%
2
10
µA
VDD = 5.0 V ±10%
0.1
30
µA
VDD = 3.0 V ±10%
0.05
10
µA
VDD = 2.0 V ±10%
0.05
10
µA
32.768 kHz crystal
modeNote 5
IDD5
STOP mode
Notes 1. Total current flowing in the internal power supply (VDD0, VDD1).
2. Includes the peripheral operating current. However, the pull-up resistor on the port and the current
flowing in the AVREF pin are not included.
3. When the processor clock control register (PCC) is set to 00H.
4. When PCC is set to 02H.
5. When the main system clock has been stopped.
44
Data Sheet U14259EJ1V0DS
µPD780076, 780078, 780076Y, 780078Y
AC Characteristics
(1) Basic operation (TA = –40 to +85°C, VDD = 1.8 to 5.5 V)
Parameter
Cycle time
Symbol
TCY
(Min. instruction
Conditions
0.24
16
µs
2.7 V ≤ VDD < 4.0 V
0.4
16
µs
1.8 V ≤ VDD < 2.7 V
1.6
16
µs
125
µs
tTIH0
3.5 V ≤ VDD ≤ 5.5 V
TI001, TI011 input
tTIL0
2.7 V ≤ VDD < 3.5 V
high-/low-level width
1.8 V ≤ VDD < 2.7 V
VDD = 2.7 to 5.5 V
frequency
tTIH5
high-/low-level width
tTIL5
Unit
4.0 V ≤ VDD ≤ 5.5 V
TI000, TI010,
TI50, TI51 input
MAX.
system clock
Operating with subsystem clock
fTI5
TYP.
Operating with main
execution time)
TI50, TI51 input
MIN.
VDD = 2.7 to 5.5 V
VDD = 2.7 to 5.5 V
103.9Note 1
2/fsam +
µs
Note2
µs
0.5Note2
µs
2/fsam + 0.2
2/fsam +
122
0.1Note2
0
4
MHz
0
275
kHz
100
ns
1.8
µs
1
µs
Interrupt request input
tINTH
INTP0 to INTP3,
high-/low-level width
tINTL
P40 to P47
2
µs
RESET
tRSL
VDD = 2.7 to 5.5 V
10
µs
20
µs
low-level width
Notes 1. Value when using the external clock. When using a crystal resonator, the value becomes 114 µs (MIN.).
2. Selection of fsam = f X, fX/4, fX/64 is available with bits 0 and 1 (PRM0n0, PRM0n1) of prescaler mode
register 0n (PRM0n). However, if the TI00n valid edge is selected as the count clock, the value
becomes fsam = fX/8 (n = 0, 1).
Data Sheet U14259EJ1V0DS
45
µPD780076, 780078, 780076Y, 780078Y
TCY vs VDD (at main system clock operation)
16.0
Cycle time TCY [ µ s]
10.0
5.0
Operation
Guaranteed
Range
2.0
1.6
1.0
0.4
0.24
0.1
0
1.0
2.0
1.8
3.0
4.0
2.7
Supply voltage VDD [V]
46
Data Sheet U14259EJ1V0DS
5.0 5.5 6.0
µPD780076, 780078, 780076Y, 780078Y
(2) Read/write operation (TA = –40 to + 85°C, VDD = 4.0 to 5.5 V) (1/3)
Parameter
Symbol
Conditions
MIN.
MAX.
Unit
ASTB high-level width
tASTH
0.3tCY
ns
Address setup time
tADS
20
ns
Address hold time
tADH
6
ns
Data input time from address
tADD1
(2 + 2n)tCY – 54
ns
tADD2
(3 + 2n)tCY – 60
ns
100
ns
Address output time from RD↓
tRDAD
0
Data input time from RD↓
tRDD1
(2 + 2n)tCY – 87
ns
tRDD2
(3 + 2n)tCY – 93
ns
Read data hold time
tRDH
0
ns
RD low-level width
tRDL1
(1.5 + 2n)tCY – 33
ns
tRDL2
(2.5 + 2n)tCY – 33
ns
WAIT↓ input time from RD↓
WAIT↓ input time from WR↓
tRDWT1
tCY – 43
ns
tRDWT2
tCY – 43
ns
tWRWT
tCY – 25
ns
(2 + 2n)tCY
ns
WAIT low-level width
tWTL
(0.5 + 2n)tCY + 10
Write data setup time
tWDS
60
ns
Write data hold time
tWDH
6
ns
WR low-level width
tWRL1
(1.5 + 2n)tCY – 15
ns
RD↓ delay time from ASTB↓
tASTRD
6
ns
WR↓ delay time from ASTB↓
tASTWR
2tCY – 15
ns
ASTB↑ delay time from
tRDAST
0.8tCY – 15
1.2tCY
ns
Address hold time from
RD↑ in external fetch
tRDADH
0.8tCY – 15
1.2tCY + 30
ns
Write data output time from RD↑
tRDWD
40
Write data output time from WR↓
tWRWD
10
60
ns
Address hold time from WR↑
tWRADH
0.8tCY – 15
1.2tCY + 30
ns
RD↑ delay time from WAIT↑
tWTRD
0.8tCY
2.5tCY + 25
ns
WR↑ delay time from WAIT↑
tWTWR
0.8tCY
2.5tCY + 25
ns
RD↑ in external fetch
ns
Remarks 1. tCY = TCY/4
2. n indicates the number of waits.
3. CL = 100 pF (CL is the load capacitance of AD0 to AD7, A8 to A15, RD, WR, WAIT, and ASTB pins)
Data Sheet U14259EJ1V0DS
47
µPD780076, 780078, 780076Y, 780078Y
(2) Read/write operation (TA = –40 to + 85°C, VDD = 2.7 to 4.0 V) (2/3)
Parameter
Symbol
Conditions
MIN.
MAX.
Unit
ASTB high-level width
tASTH
0.3tCY
ns
Address setup time
tADS
30
ns
Address hold time
tADH
10
ns
Data input time from address
tADD1
(2 + 2n)tCY – 108
ns
tADD2
(3 + 2n)tCY – 120
ns
200
ns
Address output time from RD↓
tRDAD
0
Data input time from RD↓
tRDD1
(2 + 2n)tCY – 148
ns
tRDD2
(3 + 2n)tCY – 162
ns
Read data hold time
tRDH
0
ns
RD low-level width
tRDL1
(1.5 + 2n)tCY – 40
ns
tRDL2
(2.5 + 2n)tCY – 40
ns
WAIT↓ input time from RD↓
WAIT↓ input time from WR↓
tRDWT1
tCY – 75
ns
tRDWT2
tCY – 75
ns
tWRWT
tCY – 50
ns
(2 + 2n)tCY
ns
WAIT low-level width
tWTL
(0.5 + 2n)tCY + 10
Write data setup time
tWDS
60
ns
Write data hold time
tWDH
10
ns
WR low-level width
tWRL1
(1.5 + 2n)tCY – 30
ns
RD↓ delay time from ASTB↓
tASTRD
10
ns
WR↓ delay time from ASTB↓
tASTWR
2tCY – 30
ns
ASTB↑ delay time from
RD↑ in external fetch
tRDAST
0.8tCY – 30
1.2tCY
ns
Address hold time from
RD↑ in external fetch
tRDADH
0.8tCY – 30
1.2tCY + 60
ns
Write data output time from RD↑
tRDWD
40
Write data output time from WR↓
tWRWD
20
120
ns
Address hold time from WR↑
tWRADH
0.8tCY – 30
1.2tCY + 60
ns
RD↑ delay time from WAIT↑
tWTRD
0.5tCY
2.5tCY + 50
ns
WR↑ delay time from WAIT↑
tWTWR
0.5tCY
2.5tCY + 50
ns
ns
Remarks 1. tCY = TCY/4
2. n indicates the number of waits.
3. CL = 100 pF (CL is the load capacitance of AD0 to AD7, A8 to A15, RD, WR, WAIT, and ASTB pins)
48
Data Sheet U14259EJ1V0DS
µPD780076, 780078, 780076Y, 780078Y
(2) Read/write operation (TA = –40 to + 85°C, VDD = 1.8 to 2.7 V) (3/3)
Parameter
Symbol
Conditions
MIN.
MAX.
Unit
ASTB high-level width
tASTH
0.3tCY
ns
Address setup time
tADS
120
ns
Address hold time
tADH
20
ns
Data input time from address
tADD1
(2 + 2n)tCY – 233
ns
tADD2
(3 + 2n)tCY – 240
ns
400
ns
Address output time from RD↓
tRDAD
0
Data input time from RD↓
tRDD1
(2 + 2n)tCY – 325
ns
tRDD2
(3 + 2n)tCY – 332
ns
Read data hold time
tRDH
0
ns
RD low-level width
tRDL1
(1.5 + 2n)tCY – 92
ns
tRDL2
(2.5 + 2n)tCY – 92
ns
WAIT↓ input time from RD↓
WAIT↓ input time from WR↓
tRDWT1
tCY – 350
ns
tRDWT2
tCY – 350
ns
tWRWT
tCY – 100
ns
(2 + 2n)tCY
ns
WAIT low-level width
tWTL
(0.5 + 2n)tCY + 10
Write data setup time
tWDS
60
ns
Write data hold time
tWDH
20
ns
WR low-level width
tWRL1
(1.5 + 2n)tCY – 60
ns
RD↓ delay time from ASTB↓
tASTRD
20
ns
WR↓ delay time from ASTB↓
tASTWR
2tCY – 60
ns
ASTB↑ delay time from
RD↑ in external fetch
tRDAST
0.8tCY – 60
1.2tCY
ns
Address hold time from
RD↑ in external fetch
tRDADH
0.8tCY – 60
1.2tCY + 120
ns
Write data output time from RD↑
tRDWD
40
Write data output time from WR↓
tWRWD
40
240
ns
Address hold time from WR↑
tWRADH
0.8tCY – 60
1.2tCY + 120
ns
RD↑ delay time from WAIT↑
tWTRD
0.5tCY
2.5tCY + 100
ns
WR↑ delay time from WAIT↑
tWTWR
0.5tCY
2.5tCY + 100
ns
ns
Remarks 1. tCY = TCY/4
2. n indicates the number of waits.
3. CL = 100 pF (CL is the load capacitance of AD0 to AD7, A8 to A15, RD, WR, WAIT, and ASTB pins)
Data Sheet U14259EJ1V0DS
49
µPD780076, 780078, 780076Y, 780078Y
(3) Serial interface (TA = –40 to +85°C, VDD = 1.8 to 5.5 V)
(a) SIO3 3-wire serial I/O mode (SCK3 ... Internal clock output)
Parameter
SCK3 cycle time
Symbol
tKCY1
SCK3 high-/low-level
tKH1
width
tKL1
SI3 setup time
tSIK1
(to SCK3↑)
SI3 hold time
Conditions
MIN.
TYP.
MAX.
Unit
4.0 V ≤ VDD ≤ 5.5 V
954
ns
2.7 V ≤ VDD < 4.0 V
1600
ns
1.8 V ≤ VDD < 2.7 V
3200
ns
tKCY1/2 – 50
ns
tKCY1/2 – 100
ns
4.0 V ≤ VDD ≤ 5.5 V
100
ns
2.7 V ≤ VDD < 4.0 V
150
ns
1.8 V ≤ VDD < 2.7 V
300
ns
400
ns
VDD = 4.0 to 5.5 V
tKSI1
(from SCK3↑)
Delay time from SCK3↓
to SO3 output
tKSO1
C = 100 pFNote
300
ns
MAX.
Unit
Note C is the load capacitance of the SCK3 and SO3 output lines.
(b) SIO3 3-wire serial I/O mode (SCK3 ... External clock input)
Parameter
SCK3 cycle time
Symbol
tKCY2
Conditions
MIN.
TYP.
4.0 V ≤ VDD ≤ 5.5 V
800
ns
2.7 V ≤ VDD < 4.0 V
1600
ns
1.8 V ≤ VDD < 2.7 V
3200
ns
SCK3 high-/low-level
tKH2
4.0 V ≤ VDD ≤ 5.5 V
400
ns
width
tKL2
2.7 V ≤ VDD < 4.0 V
800
ns
1.8 V ≤ VDD < 2.7 V
1600
ns
SI3 setup time
(to SCK3↑)
tSIK2
100
ns
SI3 hold time
(from SCK3↑)
tKSI2
400
ns
Delay time from SCK3↓
to SO3 output
tKSO2
C = 100 pFNote
Note C is the load capacitance of the SO3 output line.
50
Data Sheet U14259EJ1V0DS
300
ns
µPD780076, 780078, 780076Y, 780078Y
(c) CSI1 3-wire serial I/O mode (SCK1 ... Internal clock output)
Parameter
SCK1 cycle time
Symbol
tKCY3
Conditions
MIN.
TYP.
MAX.
Unit
4.0 V ≤ VDD ≤ 5.5 V
240
ns
2.7 V ≤ VDD < 4.0 V
500
ns
1.8 V ≤ VDD < 2.7 V
1
µs
SCK1 high-/low-level
tKH3
4.0 V ≤ VDD ≤ 5.5 V
tKCY3/2–5
ns
width
tKL3
2.7 V ≤ VDD < 4.0 V
tKCY3/2–20
ns
1.8 V ≤ VDD < 2.7 V
tKCY3/2–30
ns
SI1 setup time
(to SCK1↑)
tSIK3
25
ns
SI1 hold time
(to SCK1↑)
tKSI3
110
ns
Delay time from SCK1↓
to SO1 output
tKSO3
C = 100 pFNote
150
ns
MAX.
Unit
Note C is the load capacitance of the SCK1 and SO1 output lines.
(d) CSI1 3-wire serial I/O mode (SCK1 ... External clock input)
Parameter
SCK1 cycle time
Symbol
tKCY4
Conditions
MIN.
TYP.
4.0 V ≤ VDD ≤ 5.5 V
200
ns
2.7 V ≤ VDD < 4.0 V
500
ns
1.8 V ≤ VDD < 2.7 V
1
µs
SCK1 high-/low-level
tKH4
4.0 V ≤ VDD ≤ 5.5 V
100
ns
width
tKL4
2.7 V ≤ VDD < 4.0 V
250
ns
1.8 V ≤ VDD < 2.7 V
500
ns
SI1 setup time
(to SCK1↑)
tSIK4
25
ns
SI1 hold time
(to SCK1↑)
tKSI4
110
ns
Delay time from SCK1↓
to SO1 output
tKSO4
C = 100 pFNote
150
ns
MAX.
Unit
4.0 V ≤ VDD ≤ 5.5 V
131031
bps
2.7 V ≤ VDD < 4.0 V
78125
bps
1.8 V ≤ VDD < 2.7 V
39063
bps
Note C is the load capacitance of the SO1 output line.
(e) UART0 mode (Dedicated baud rate generator output)
Parameter
Transfer rate
Symbol
Conditions
Data Sheet U14259EJ1V0DS
MIN.
TYP.
51
µPD780076, 780078, 780076Y, 780078Y
(f)
UART0 mode (External clock input)
Parameter
ASCK0 cycle time
Symbol
tKCY5
Conditions
MIN.
TYP.
MAX.
Unit
4.0 V ≤ VDD ≤ 5.5 V
800
ns
2.7 V ≤ VDD < 4.0 V
1600
ns
1.8 V ≤ VDD < 2.7 V
3200
ns
ASCK0 high-/low-level
tKH5
4.0 V ≤ VDD ≤ 5.5 V
400
ns
width
tKL5
2.7 V ≤ VDD < 4.0 V
800
ns
1.8 V ≤ VDD < 2.7 V
1600
ns
Transfer rate
4.0 V ≤ VDD ≤ 5.5 V
39063
bps
2.7 V ≤ VDD < 4.0 V
19531
bps
1.8 V ≤ VDD < 2.7 V
9766
bps
MAX.
Unit
(g) UART0 mode (Infrared data transfer mode)
Parameter
Symbol
Conditions
MIN.
TYP.
Transfer rate
VDD = 4.0 to 5.5 V
131031
bps
Bit rate allowable error
VDD = 4.0 to 5.5 V
±0.87
%
Output pulse width
VDD = 4.0 to 5.5 V
1.2
0.24/fbrNote
µs
Input pulse width
VDD = 4.0 to 5.5 V
4/fX
µs
Note fbr: Specified baud rate
(h) UART2 (Dedicated baud rate generator output)
Parameter
Symbol
Transfer rate
(i)
Conditions
MIN.
TYP.
MAX.
Unit
4.0 V ≤ VDD ≤ 5.5 V
262062
bps
2.7 V ≤ VDD < 4.0 V
156250
bps
1.8 V ≤ VDD < 2.7 V
62500
bps
MAX.
Unit
UART2 (External clock input)
Parameter
ASCK2 cycle time
Symbol
tKCY6
Conditions
MIN.
TYP.
4.0 V ≤ VDD ≤ 5.5 V
800
ns
2.7 V ≤ VDD < 4.0 V
1600
ns
1.8 V ≤ VDD < 2.7 V
3200
ns
ASCK2 high-/low-level
tKH6
4.0 V ≤ VDD ≤ 5.5 V
400
ns
width
tKL6
2.7 V ≤ VDD < 4.0 V
800
ns
1.8 V ≤ VDD < 2.7 V
1600
ns
Transfer rate
52
4.0 V ≤ VDD ≤ 5.5 V
78125
bps
2.7 V ≤ VDD < 4.0 V
39063
bps
1.8 V ≤ VDD < 2.7 V
19531
bps
Data Sheet U14259EJ1V0DS
µPD780076, 780078, 780076Y, 780078Y
(j)
UART2 (Infrared data transfer mode)
Parameter
Symbol
Conditions
MIN.
TYP.
MAX.
Unit
Transfer rate
4.0 V ≤ VDD ≤ 5.5 V
262062
bps
Bit rate allowable error
4.0 V ≤ VDD ≤ 5.5 V
±0.87
%
Output pulse width
4.0 V ≤ VDD ≤ 5.5 V
1.2
0.24/fbrNote
µs
Input pulse width
4.0 V ≤ VDD ≤ 5.5 V
4/fX
µs
Note fbr: Specified baud rate
(k) I2C bus mode
Standard Mode
Parameter
Symbol
High-speed Mode
MIN.
MAX.
MIN.
MAX.
Unit
SCL0 clock frequency
fSCL
0
100
0
400
kHz
Bus free time
(between stop and start condition)
tBUF
4.7
—
1.3
—
µs
Hold timeNote 1
tHD:STA
4.0
—
0.6
—
µs
SCL0 clock low-level width
tLOW
4.7
—
1.3
—
µs
SCL0 clock high-level width
tHIGH
4.0
—
0.6
—
µs
Start/restart condition setup time
tSU:STA
4.7
—
0.6
—
µs
Data hold time
tHD:DAT
5.0
—
—
—
µs
—
0Note 2
0.9Note 3
µs
CBUS compatible master
I2C
0Note 2
bus
Data setup time
tSU:DAT
SDA0 and SCL0 signal rise time
tR
250
—
—
1000
100
Note 4
—
ns
Note 5
300
ns
0.1CbNote 5
300
ns
20 + 0.1Cb
SDA0 and SCL0 signal fall time
tF
—
300
20 +
Stop condition setup time
tSU:STO
4.0
—
0.6
—
µs
Capacitive load per each bus line
Cb
—
400
—
400
pF
Spike pulse width controlled by input filter
tSP
—
—
0
50
ns
Notes 1. On start condition, the first clock pulse is generated after hold period.
2. To fulfill undefined area of the SCL0 falling edge, it is necessary for the device to provide internally SDA0
signal (on VIHmin. of SCL0 signal) with at least 300 ns of hold time.
3. If the device does not extend the SCL0 signal low hold time (tLOW), only maximum data hold time tHD:DAT
needs to be fulfilled.
4. The high-speed mode I2C bus is available in the standard mode I2C bus system. At this time, the
conditions described below must be satisfied.
• If the device does not extend the SCL0 signal low state hold time
tSU:DAT ≥ 250 ns
• If the device extends the SCL0 signal low state hold time
Be sure to transmit the next data bit to the SDA0 line before the SCL0 line is released (tRmax. + tSU:DAT
= 1000 + 250 = 1250 ns by standard mode I2C bus specification).
5. Cb : total capacitance per one bus line (unit : pF)
Data Sheet U14259EJ1V0DS
53
µPD780076, 780078, 780076Y, 780078Y
AC Timing Test Points (excluding X1, XT1 Inputs)
0.8VDD
0.8VDD
Test points
0.2VDD
0.2VDD
Clock Timing
1/fX
tXL
tXH
VIH4 (MIN.)
VIL4 (MAX.)
X1 input
1/fXT
tXTL
tXTH
VIH5 (MIN.)
VIL5 (MAX.)
XT1 input
TI Timing
tTIH0
tTIL0
TI000, TI010, TI001, TI011
1/fT5
tTIL5
TI50, TI51
54
Data Sheet U14259EJ1V0DS
tTIH5
µPD780076, 780078, 780076Y, 780078Y
Read/Write Operation
External fetch (no wait):
A8 to A15
Higher 8-bit address
tADD1
Lower 8-bit
address
AD0 to AD7
tADS
tADH
Hi-Z
Operation
code
tRDAD
tRDD1
tRDADH
tASTH
tRDAST
ASTB
RD
tASTRD
tRDL1
tRDH
External fetch (wait insertion):
A8 to A15
Higher 8-bit address
tADD1
AD0 to AD7
Hi-Z
Lower 8-bit
address
tADS
tADH
tRDAD
Operation
code
tRDADH
tRDD1
tASTH
tRDAST
ASTB
RD
tASTRD
tRDL1
tRDH
WAIT
tRDWT1
tWTL
Data Sheet U14259EJ1V0DS
tWTRD
55
µPD780076, 780078, 780076Y, 780078Y
External data access (no wait):
A8 to A15
AD0 to AD7
Higher 8-bit address
tADD2
Lower 8-bit
address
tADS
Hi-Z
tRDAD
tRDD2
tADH
Read data
tASTH
Hi-Z
Write data
tRDH
ASTB
RD
tASTRD
tRDWD
tRDL2
tWDS
tWDH
tWRADH
tWRWD
WR
tASTWR
tWRL1
External data access (wait insertion):
A8 to A15
Higher 8-bit address
tADD2
AD0 to AD7
Lower 8-bit
address
tADS tADH
tASTH
Hi-Z
Read data
Hi-Z
Write data
tRDAD
tRDH
tRDD2
ASTB
tASTRD
RD
tRDWD
tRDL2
tWDS
tWDH
tWRWD
WR
tASTWR
tWRL1
tWRADH
WAIT
tRDWT2
tWTL
tWTRD
tWTL
tWRWT
56
Data Sheet U14259EJ1V0DS
tWTWR
µPD780076, 780078, 780076Y, 780078Y
Serial Transfer Timing
3-wire serial I/O mode:
tKCYn
tKLn
tKHn
SCK1, SCK3
tSIKn
SI1, SI3
tKSIn
Input data
tKSOn
SO1, SO3
Output data
n = 1 to 4
UART mode (external clock input):
t KCYn
t KLn
t KHn
ASCK0, ASCK2
n = 5, 6
I2C bus mode:
tLOW
tR
SCL0
tHD:DAT
tHD:STA
tHIGH
tSU:DAT
tF
tSU:STA
tHD:STA
tSP
tSU:STO
SDA0
tBUF
Stop
condition
Start
condition
Restart
condition
Data Sheet U14259EJ1V0DS
Stop
condition
57
µPD780076, 780078, 780076Y, 780078Y
A/D Converter Characteristics (TA = –40 to +85°C, VDD = AVREF = 2.2 to 5.5 V, AVSS = VSS = 0 V)
Parameter
Symbol
Conditions
MIN.
TYP.
MAX.
Unit
10
10
10
bit
4.0 V ≤ AVREF ≤ 5.5 V
±0.2
±0.4
%FSR
2.7 V ≤ AVREF < 4.0 V
±0.3
±0.6
%FSR
2.2 V ≤ AVREF < 2.7 V
±0.6
±1.2
%FSR
Resolution
Overall
errorNote
Conversion time
Zero-scale
Full-scale
tCONV
errorNote
errorNote
Integral linear error
Differential linear error
Analog input impedance
4.0 V ≤ AVREF ≤ 5.5 V
14
100
µs
2.7 V ≤ AVREF < 4.0 V
19
100
µs
2.2 V ≤ AVREF < 2.7 V
28
100
µs
4.0 V ≤ AVREF ≤ 5.5 V
±0.4
%FSR
2.7 V ≤ AVREF < 4.0 V
±0.6
%FSR
2.2 V ≤ AVREF < 2.7 V
±1.2
%FSR
4.0 V ≤ AVREF ≤ 5.5 V
±0.4
%FSR
2.7 V ≤ AVREF < 4.0 V
±0.6
%FSR
2.2 V ≤ AVREF < 2.7 V
±1.2
%FSR
4.0 V ≤ AVREF ≤ 5.5 V
±2.5
LSB
2.7 V ≤ AVREF < 4.0 V
±4.5
LSB
2.2 V ≤ AVREF < 2.7 V
±8.5
LSB
4.0 V ≤ AVREF ≤ 5.5 V
±1.5
LSB
2.7 V ≤ AVREF < 4.0 V
±2.0
LSB
2.2 V ≤ AVREF < 2.7 V
±3.5
LSB
During sampling
100
kΩ
Other than during sampling
Analog input voltage
VIAN
AVREF resistance
RAIREF
10
0
During A/D conversion
20
MΩ
AVREF
40
V
kΩ
Note Overall error excluding quantization error (±1/2 LSB). It is indicated as a ratio to the full-scale value.
Remark FSR: Full-scale range
58
Data Sheet U14259EJ1V0DS
µPD780076, 780078, 780076Y, 780078Y
Data Memory STOP Mode Low Supply Voltage Data Retention Characteristics (TA = –40 to +85°C)
Parameter
Data retention power
Symbol
Conditions
MIN.
VDDDR
TYP.
1.6
MAX.
Unit
5.5
V
30
µA
supply voltage
Data retention
power supply current
IDDDR
Release signal set time
tSREL
Oscillation stabilization
wait time
tWAIT
Subsystem clock is not used (XT1 = VDD)
and feed-back resistor disconnected
0.1
µs
0
Release by RESET
217/fx
ms
Release by interrupt request
Note
ms
Note Selection of 212/fX and 214/f X to 217/fX is possible with bits 0 to 2 (OSTS0 to OSTS2) of the oscillation
stabilization time select register (OSTS).
Data Retention Timing (STOP Mode Release by RESET)
Internal reset operation
HALT mode
Operating mode
STOP mode
Data retention mode
VDD
VDDDR
tSREL
STOP instruction execution
RESET
tWAIT
Data Retention Timing (Standby Release Signal: STOP Mode Release by Interrupt Request Signal)
HALT mode
Operating mode
STOP mode
Data retention mode
VDD
VDDDR
tSREL
STOP instruction execution
Standby release signal
(interrupt request)
tWAIT
Data Sheet U14259EJ1V0DS
59
µPD780076, 780078, 780076Y, 780078Y
Interrupt Request Input Timing
tINTL
INTP0 to INTP3
RESET Input Timing
tRSL
RESET
60
Data Sheet U14259EJ1V0DS
tINTH
µPD780076, 780078, 780076Y, 780078Y
13. PACKAGE DRAWINGS
64-PIN PLASTIC QFP (14x14)
A
B
48
49
33
32
detail of lead end
S
C D
Q
64
1
R
17
16
F
J
G
H
I
M
P
K
S
N
S
L
M
NOTE
ITEM
Each lead centerline is located within 0.15 mm of
its true position (T.P.) at maximum material condition.
MILLIMETERS
A
17.6±0.4
B
14.0±0.2
C
14.0±0.2
D
17.6±0.4
F
1.0
G
1.0
H
0.37 +0.08
−0.07
I
J
0.15
0.8 (T.P.)
K
1.8±0.2
L
0.8±0.2
M
0.17 +0.08
−0.07
N
0.10
P
2.55±0.1
Q
0.1±0.1
R
5°±5°
S
2.85 MAX.
P64GC-80-AB8-5
Remark The external dimensions and material of the ES version are the same as those of the mass-produced
version.
Data Sheet U14259EJ1V0DS
61
µPD780076, 780078, 780076Y, 780078Y
64-PIN PLASTIC TQFP (12x12)
A
B
48
detail of lead end
33
32
49
S
P
T
C
D
R
L
U
64
Q
17
16
1
F
G
J
H
I
M
ITEM
K
S
M
N
S
NOTE
Each lead centerline is located within 0.13 mm of
its true position (T.P.) at maximum material condition.
MILLIMETERS
A
B
14.0±0.2
12.0±0.2
C
12.0±0.2
D
F
14.0±0.2
1.125
G
1.125
H
0.32 +0.06
−0.10
I
0.13
J
0.65 (T.P.)
K
1.0±0.2
L
0.5
M
0.17 +0.03
−0.07
N
0.10
P
1.0
Q
0.1±0.05
R
3° +4°
−3°
S
1.1±0.1
T
0.25
U
0.6±0.15
P64GK-65-9ET-3
Remark The external dimensions and material of the ES version are the same as those of the mass-produced
version.
62
Data Sheet U14259EJ1V0DS
µPD780076, 780078, 780076Y, 780078Y
14. RECOMMENDED SOLDERING CONDITIONS
The µPD780078, 780078Y Subseries should be soldered and mounted under the following recommended
conditions.
For details of the recommended soldering conditions, refer to the document Semiconductor Device Mounting
Technology Manual (C10535E).
For soldering methods and conditions other than those recommended below, contact an NEC sales representative.
Table 14-1. Surface Mounting Type Soldering Conditions
(1) µPD780076GC-×××-AB8:
64-pin plastic QFP (14 × 14)
µPD780078GC-×××-AB8:
64-pin plastic QFP (14 × 14)
µPD780076YGC-×××-AB8: 64-pin plastic QFP (14 × 14)
µPD780078YGC-×××-AB8: 64-pin plastic QFP (14 × 14)
Soldering
Soldering Conditions
Recommended Method
Condition Symbol
Infrared reflow
Package peak temperature: 235°C, Time: 30 sec. max. (at 210°C or higher),
Count: two times or less
IR35-00-2
VPS
Package peak temperature: 215°C, Time: 40 sec. max. (at 200°C or higher),
Count: two times or less
VP15-00-2
Solder bath temperature: 260°C max., Time: 10 sec. max., Count: once,
WS60-00-1
Wave soldering
Preheating temperature: 120°C max. (package surface temperature)
Partial heating
Pin temperature: 300°C max., Time: 3 sec. max. (per pin row)
—
Caution Do not use different soldering methods together (except for partial heating).
Data Sheet U14259EJ1V0DS
63
µPD780076, 780078, 780076Y, 780078Y
(2) µPD780076GK-×××-9ET:
64-pin plastic TQFP (12 × 12)
µPD780078GK-×××-9ET:
64-pin plastic TQFP (12 × 12)
µPD780076YGK-×××-9ET: 64-pin plastic TQFP (12 × 12)
µPD780078YGK-×××-9ET: 64-pin plastic TQFP (12 × 12)
Soldering
Infrared reflow
Soldering Conditions
Package peak temperature: 235°C, Time: 30 sec. max. (at 210°C or higher),
Count: two times or less, Exposure limit: 7 daysNote (after that, prebake at
Recommended Method
Condition Symbol
IR35-107-2
125°C for 10 hours)
VPS
Package peak temperature: 215°C, Time: 40 sec. max. (at 200°C or higher),
Count: two times or less, Exposure limit: 7 daysNote (after that, prebake at
125°C for 10 hours)
VP15-107-2
Wave soldering
Solder bath temperature: 260°C max., Time: 10 sec. max., Count: once,
Preheating temperature: 120°C max. (package surface temperature),
Exposure limit: 7 daysNote (after that, prebake at 125°C for 10 hours)
WS60-107-1
Partial heating
Pin temperature: 300°C max., Time: 3 sec. max. (per pin row)
—
Note After opening the dry pack, store it at 25°C or less and 65% RH or less for the allowable storage period.
Caution Do not use different soldering methods together (except for partial heating).
64
Data Sheet U14259EJ1V0DS
µPD780076, 780078, 780076Y, 780078Y
APPENDIX A. DEVELOPMENT TOOLS
The following development tools are available for system development using the µPD780078, 780078Y Subseries.
Also refer to (6) Cautions on using development tools.
(1) Software package
SP78K0
Software package common to 78K/0 Series
(2) Language processing software
RA78K0
Assembler package common to 78K/0 Series
CC78K0
C compiler package common to 78K/0 Series
DF780078
Device file for µPD780078, 780078Y Subseries
CC78K0-L
C compiler library source file common to 78K/0 Series
(3) Flash memory writing tools
Flashpro III (FL-PR3,
PG-FP3)
Flash programmer dedicated to on-chip flash memory microcontroller
FA-64GC
FA-64GK-9ET
Adapter for flash memory writing
• FA-64GC: For 64-pin plastic QFP (GC-AB8 type)
• FA-64GK-9ET: For 64-pin plastic TQFP (GK-9ET type)
(4) Debugging tool
• When using in-circuit emulator IE-78K0-NS(–A)
IE-78K0-NS(–A)
In-circuit emulator common to 78K/0 Series
IE-70000-MC-PS-B
Power supply unit for IE-78K0-NS
IE-78K0-NS-PA
Performance board to enhance/expand functions of IE-78K0-NS
IE-70000-98-IF-C
Adapter when using PC-9800 series as host machine (excluding notebook PCs) (C bus compatible)
IE-70000-CD-IF-A
PC card and interface cable when using notebook PC as host machine (PCMCIA socket compatible)
IE-70000-PC-IF-C
Adapter when using IBM PC/ATTM compatible as host machine (ISA bus compatible)
IE-70000-PCI-IF-A
Adapter necessary when using on-chip PCI bus PC as host machine
IE-780078-NS-EM1
Emulation board to emulate µPD780078, 780078Y Subseries
NP-64GC
NP-64GC-TQ
Emulation probe for 64-pin plastic QFP (GC-AB8 type)
NP-64GK
Emulation probe for 64-pin plastic TQFP (GK-9ET type)
EV-9200GC-64
Conversion socket for connecting target system designed to mount a 64-pin plastic QFP (GC-AB8 type)
and NP-64GC
TGC-064SAP
Conversion adapter for connecting target system designed to mount a 64-pin plastic QFP (GC-AB8
type) and NP-64GC-TQ
TGK-064SBP
Conversion adapter for connecting target system board designed to mount a 64-pin plastic TQFP
(GK-9ET type) and NP-64GK
ID78K0-NS
Integrated debugger for IE-78K0-NS
SM78K0
System simulator common to 78K/0 Series
DF780078
Device file common to µPD780078, 780078Y Subseries
Data Sheet U14259EJ1V0DS
65
µPD780076, 780078, 780076Y, 780078Y
• When using in-circuit emulator IE-78001-R-A
IE-78001-R-A
In-circuit emulator common to 78K/0 Series
IE-70000-98-IF-C
Interface adapter when using PC-9800 series as host machine (excluding notebook PCs) (C bus
compatible)
IE-70000-PC-IF-C
Interface adapter when using IBM PC/AT compatible as host machine (ISA bus compatible)
IE-70000-PCI-IF-A
Adapter necessary when using on-chip PCI bus PC as host machine
IE-78000-R-SV3
Interface adapter and cable when using EWS as host machine
IE-780078-NS-EM1
Emulation board to emulate µPD780078, 780078Y Subseries
IE-78K0-R-EX1
Emulation probe conversion board necessary to use IE-780078-NS-EM1 on IE-78001-R-A
EP-78240GC-R
Emulation probe for 64-pin plastic QFP (GC-AB8 type)
EP-78012GK-R
Emulation probe for 64-pin plastic TQFP (GK-9ET type)
EV-9200GC-64
Socket to be mounted on target system board manufactured for 64-pin plastic QFP (GC-AB8 type)
TGK-064SBP
Conversion adapter for connecting target system board designed to mount a 64-pin plastic TQFP (GK9ET) and EP-78012GK-R.
ID78K0
Integrated debugger for IE-78001-R-A
SM78K0
System simulator common to 78K/0 Series
DF780078
Device file common to µPD780078, 780078Y Subseries
(5) Real-time OS
RX78K0
Real-time OS for 78K/0 Series
MX78K0
OS for 78K/0 Series
66
Data Sheet U14259EJ1V0DS
µPD780076, 780078, 780076Y, 780078Y
(6) Cautions on using development tools
• The ID78K0-NS, ID78K0, and SM78K0 are used in combination with the DF780078.
• The CC78K0 and RX78K0 are used in combination with the RA78K0 and the DF780078.
• The FL-PR3, FA-64GC, FA64GK, NP-64GC, NP-64GC-TQ, and NP-64GK-9ET are products made by Naito
Densei Machida Mfg. Co., Ltd. (+81-44-822-3813).
• The TGC-064SAP and TGK-064SBP are products made by Tokyo Eletech Corp.
Refer to: Daimaru Kogyo, Ltd.
Electronics Dept.
(TEL: Tokyo +81-3-3820-7112)
Electronics 2nd Dept. (TEL: Osaka +81-6-6244-6672)
• For third party development tools, see the Single-Chip Microcontroller Development Tools Selection
Guide (U11069E).
• The host machines and OSs supporting each software are as follows.
Host Machine
[OS]
Software
PC
EWS
WindowsTM]
PC-9800 series [Japanese
IBM PC/AT compatible
[Japanese/English Windows]
HP9000 series 700TM [HP-UXTM]
SPARCstationTM [SunOSTM, SolarisTM]
RA78K0
√ Note
√
CC78K0
√
√
Note
ID78K0-NS
√
—
ID78K0
√
—
√
—
SM78K0
RX78K0
√
Note
MX78K0
√
Note
√
√
Note DOS-based software
Data Sheet U14259EJ1V0DS
67
µPD780076, 780078, 780076Y, 780078Y
APPENDIX B. RELATED DOCUMENTS
The related documents indicated in this publication may include preliminary versions. However, preliminary
versions are not marked as such.
Documents Related to Devices
Document Name
Document No.
µPD780078, 780078Y Subseries User’s Manual
U14260E
µPD780076, 780078, 780076Y, 780078Y Data Sheet
This document
µPD78F0078, 78F0078Y Data Sheet
U14258E
78K/0 Series User’s Manual — Instructions
U12326E
Documents Related to Development Tools (User’s Manuals)
Document Name
RA78K0 Assembler Package
CC78K0 C Compiler
Document No.
Operation
U14445E
Language
U14446E
Structured Assembly Language
U11789E
Operation
U14297E
Language
U14298E
IE-78K0-NS In-Circuit Emulator
U13731E
IE-78001-R-A In-Circuit Emulator
U14142E
IE-78K0-R-EX1 In-Circuit Emulator
To be prepared
IE-780078-NS-EM1 Emulation Board
To be prepared
EP-78012GK-R Emulation Probe
EEU-1538
EP-78240 Emulation Probe
U10332E
SM78K0S, SM78K0 System Simulator Ver. 2.10 or Later
Windows Based
Operation
U14611E
SM78K Series System Simulator Ver. 2.10 or Later
External Part User Open
Interface Specifications
U15006E
ID78K0-NS Integrated Debugger Ver. 2.00 or Later Windows Based
Operation
U14379E
ID78K0 Integrated Debugger Ver. 2.00 or Later EWS Based
Reference
U11151E
ID78K0 Integrated Debugger Ver. 2.00 or Later Windows Based
Reference
U11539E
Guide
U11649E
Caution The related documents listed above are subject to change without notice. Be sure to use the
latest version of each document for designing.
68
Data Sheet U14259EJ1V0DS
µPD780076, 780078, 780076Y, 780078Y
Documents Related to Embedded Software (User’s Manuals)
Document Name
78K/0 Series Real-time OS
78K/0 Series OS MX78K0
Document No.
Fundamentals
U11537E
Installation
U11536E
Fundamental
U12257E
Other Documents
Document Name
Document No.
SEMICONDUCTOR SELECTION GUIDE - Programs & Packages - (CD-ROM)
X13769E
Semiconductor Device Mounting Technology Manual
C10535E
Quality Grades on NEC Semiconductor Devices
C11531E
NEC Semiconductor Device Reliability/Quality Control System
C10983E
Guide to Prevent Damage for Semiconductor Devices by Electrostatic Discharge (ESD)
C11892E
Caution The related documents listed above are subject to change without notice. Be sure to use the
latest version of each document for designing.
Data Sheet U14259EJ1V0DS
69
µPD780076, 780078, 780076Y, 780078Y
NOTES FOR CMOS DEVICES
1
PRECAUTION AGAINST ESD FOR SEMICONDUCTORS
Note:
Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and
ultimately degrade the device operation. Steps must be taken to stop generation of static electricity
as much as possible, and quickly dissipate it once, when it has occurred. Environmental control
must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using
insulators that easily build static electricity. Semiconductor devices must be stored and transported
in an anti-static container, static shielding bag or conductive material. All test and measurement
tools including work bench and floor should be grounded. The operator should be grounded using
wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need
to be taken for PW boards with semiconductor devices on it.
2
HANDLING OF UNUSED INPUT PINS FOR CMOS
Note:
No connection for CMOS device inputs can be cause of malfunction. If no connection is provided
to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence
causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels
of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused
pin should be connected to V DD or GND with a resistor, if it is considered to have a possibility of
being an output pin. All handling related to the unused pins must be judged device by device and
related specifications governing the devices.
3
STATUS BEFORE INITIALIZATION OF MOS DEVICES
Note:
Power-on does not necessarily define initial status of MOS device. Production process of MOS
does not define the initial operation status of the device. Immediately after the power source is
turned ON, the devices with reset function have not yet been initialized. Hence, power-on does
not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the
reset signal is received. Reset operation must be executed immediately after power-on for devices
having reset function.
Purchase of NEC I 2C components conveys a license under the Philips I 2C Patent Rights to use
these components in an I 2C system, provided that the system conforms to the I 2C Standard
Specification as defined by Philips.
FIP and IEBus are trademarks of NEC Corporation.
Windows is either a registered trademark or a trademark of Microsoft Corporation in the United
States and/or other countries.
PC/AT is a trademark of International Business Machines Corporation.
HP9000 series 700 and HP-UX are trademarks of Hewlett-Packard Company.
SPARCstation is a trademark of SPARC International, Inc.
Solaris and SunOS are trademarks of Sun Microsystems, Inc.
70
Data Sheet U14259EJ1V0DS
µPD780076, 780078, 780076Y, 780078Y
Regional Information
Some information contained in this document may vary from country to country. Before using any NEC
product in your application, pIease contact the NEC office in your country to obtain a list of authorized
representatives and distributors. They will verify:
•
Device availability
•
Ordering information
•
Product release schedule
•
Availability of related technical literature
•
Development environment specifications (for example, specifications for third-party tools and
components, host computers, power plugs, AC supply voltages, and so forth)
•
Network requirements
In addition, trademarks, registered trademarks, export restrictions, and other legal issues may also vary
from country to country.
NEC Electronics Inc. (U.S.)
NEC Electronics (Germany) GmbH
NEC Electronics Hong Kong Ltd.
Santa Clara, California
Tel: 408-588-6000
800-366-9782
Fax: 408-588-6130
800-729-9288
Benelux Office
Eindhoven, The Netherlands
Tel: 040-2445845
Fax: 040-2444580
Hong Kong
Tel: 2886-9318
Fax: 2886-9022/9044
NEC Electronics Hong Kong Ltd.
Velizy-Villacoublay, France
Tel: 01-3067-5800
Fax: 01-3067-5899
Seoul Branch
Seoul, Korea
Tel: 02-528-0303
Fax: 02-528-4411
NEC Electronics (France) S.A.
NEC Electronics Singapore Pte. Ltd.
Madrid Office
Madrid, Spain
Tel: 091-504-2787
Fax: 091-504-2860
Novena Square, Singapore
Tel: 253-8311
Fax: 250-3583
NEC Electronics (France) S.A.
NEC Electronics (Germany) GmbH
Duesseldorf, Germany
Tel: 0211-65 03 02
Fax: 0211-65 03 490
NEC Electronics (UK) Ltd.
Milton Keynes, UK
Tel: 01908-691-133
Fax: 01908-670-290
NEC Electronics Taiwan Ltd.
NEC Electronics Italiana s.r.l.
NEC Electronics (Germany) GmbH
Milano, Italy
Tel: 02-66 75 41
Fax: 02-66 75 42 99
Scandinavia Office
Taeby, Sweden
Tel: 08-63 80 820
Fax: 08-63 80 388
Taipei, Taiwan
Tel: 02-2719-2377
Fax: 02-2719-5951
NEC do Brasil S.A.
Electron Devices Division
Guarulhos-SP, Brasil
Tel: 11-6462-6810
Fax: 11-6462-6829
J01.2
Data Sheet U14259EJ1V0DS
71
µPD780076, 780078, 780076Y, 780078Y
The export of this product from Japan is regulated by the Japanese government. To export this product may be prohibited
without governmental license, the need for which must be judged by the customer. The export or re-export of this product
from a country other than Japan may also be prohibited without a license from that country. Please call an NEC sales
representative.
• The information in this document is current as of March, 2001. The information is subject to change
without notice. For actual design-in, refer to the latest publications of NEC's data sheets or data
books, etc., for the most up-to-date specifications of NEC semiconductor products. Not all products
and/or types are available in every country. Please check with an NEC sales representative for
availability and additional information.
• No part of this document may be copied or reproduced in any form or by any means without prior
written consent of NEC. NEC assumes no responsibility for any errors that may appear in this document.
• NEC does not assume any liability for infringement of patents, copyrights or other intellectual property rights of
third parties by or arising from the use of NEC semiconductor products listed in this document or any other
liability arising from the use of such products. No license, express, implied or otherwise, is granted under any
patents, copyrights or other intellectual property rights of NEC or others.
• Descriptions of circuits, software and other related information in this document are provided for illustrative
purposes in semiconductor product operation and application examples. The incorporation of these
circuits, software and information in the design of customer's equipment shall be done under the full
responsibility of customer. NEC assumes no responsibility for any losses incurred by customers or third
parties arising from the use of these circuits, software and information.
• While NEC endeavours to enhance the quality, reliability and safety of NEC semiconductor products, customers
agree and acknowledge that the possibility of defects thereof cannot be eliminated entirely. To minimize
risks of damage to property or injury (including death) to persons arising from defects in NEC
semiconductor products, customers must incorporate sufficient safety measures in their design, such as
redundancy, fire-containment, and anti-failure features.
• NEC semiconductor products are classified into the following three quality grades:
"Standard", "Special" and "Specific". The "Specific" quality grade applies only to semiconductor products
developed based on a customer-designated "quality assurance program" for a specific application. The
recommended applications of a semiconductor product depend on its quality grade, as indicated below.
Customers must check the quality grade of each semiconductor product before using it in a particular
application.
"Standard": Computers, office equipment, communications equipment, test and measurement equipment, audio
and visual equipment, home electronic appliances, machine tools, personal electronic equipment
and industrial robots
"Special": Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster
systems, anti-crime systems, safety equipment and medical equipment (not specifically designed
for life support)
"Specific": Aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life
support systems and medical equipment for life support, etc.
The quality grade of NEC semiconductor products is "Standard" unless otherwise expressly specified in NEC's
data sheets or data books, etc. If customers wish to use NEC semiconductor products in applications not
intended by NEC, they must contact an NEC sales representative in advance to determine NEC's willingness
to support a given application.
(Note)
(1) "NEC" as used in this statement means NEC Corporation and also includes its majority-owned subsidiaries.
(2) "NEC semiconductor products" means any semiconductor product developed or manufactured by or for
NEC (as defined above).
M8E 00.4