NEC UPD78083

DATA SHEET
MOS INTEGRATED CIRCUIT
µPD78001B(A), 78002B(A)
8-BIT SINGLE-CHIP MICROCOMPUTER
DESCRIPTION
The µPD78001B(A)/78002B(A) are products in the µPD78002 subseries within the 78K/0 series.
The µPD78001B(A)/78002B(A) have various peripheral hardware such as timer, serial interface and interrupt
function.
A one-time PROM or EPROM product, the µPD78P014, capable of operating in the same power supply voltage
range as that of the mask ROM product and other development tools is provided.
Functions are described in detail in the following User's Manual, which should be read when carrying out design
work.
µPD78002, 78002Y Series User's Manual: IEU-1334
FEATURES
• The µPD78001B, in comparison with the 78002B, is a higher reliability device, as a result of a more comprehensive
quality assurance program (Refer to Quality Grade on NEC Semiconductor Devices (IEI-1209))
• Large on-chip ROM & RAM
Item
Program Memory
Data Memory
Product Name
(ROM)
(Internal High-Speed RAM)
Package
µPD78001B(A)
8K bytes
256 bytes
• 64-pin plastic shrink DIP (750 mil)
µPD78002B(A)
16K byte
384 bytes
• 64-pin plastic QFP ( 14 mm)
• External memory expansion space: 64K bytes
• Instruction execution time can be varied from high-speed (0.4 µs) to ultra-low-speed (122 µs)
• I/O ports: 53 (N-ch open-drain : 4)
• Serial interface : 1 channel
• Timer: 4 channels
• Operating voltage range : 2.7 to 6.0 V
APPLICATION
Transmission equipment control device, gas detector circuit breaker, safety devices, etc.
The information in this document is subject to change without notice.
Document No. IC-3599
(O.D. No. IC-9078)
Date Published February 1995 P
Printed in Japan
©
1995
µPD78001B(A), 78002B(A)
ORDERING INFORMATION
Part Number
Package
Quality Grade
µPD78001BCW (A)-×××
64-pin plastic shrink DIP (750 mil)
Special
µPD78001BGC (A)-×××-AB8
64-pin plastic QFP (■
■ 14 mm)
Special
µPD78002BCW (A)-×××
64-pin plastic shrink DIP (750 mil)
Special
µPD78002BGC (A)-×××-AB8
64-pin plastic QFP (■
■ 14 mm)
Special
Remark ××× indicates ROM code No.
Please refer to "Quality grade on NEC Semiconductor Devices" (Document number IEI-1209) published by
NEC Corporation to know the specification of quality grade on the devices and its recommended applications.
Difference between the µPD78001B(A), 78002B(A) and the µPD78001B, 78002B.
Product Name
Item
Quality Grade
2
µPD78001B(A), 78002B(A)
µPD78001B, 78002B
Special
Standard
µPD78001B(A), 78002B(A)
78K/0 SERIES PRODUCT DEVELOPMENT
These products are a further development in the 78K/0 Series. The designations appearing inside the boxes
are subseries names.
Products in Volume Production
Products under Development
2
Y series products are compatible with I C bus.
For control
100-pin
80-pin
64-pin
64-pin
64-pin
42/44-pin
µ PD78078
µ PD78054
µ PD78018F
µ PD78014
µ PD78002
µ PD78083
µ PD78078Y
µ PD78054Y
µPD78018FY
µ PD78014Y
µ PD78002Y
Timer added to the µ PD78054, external interface functions
UART and D/A added to the µ PD78014, I/O enhanced
Low-voltage (1.8 V) operation version of the µ PD78014, with enhanced ROM and RAM variations
A/D and 16-bit timer added to the µ PD78002
Basic subseries for control
Internal UART, low-voltage (1.8 V) operation possible
78K/0
Series
For FIP® driving
I/O, FIP C/D of the µPD78044A enhanced, display output total: 53
6-bit U/D counter added to the µPD78024, display output total: 34
Basic subseries for FIP driving, display output total: 26
100-pin µ PD780208
80-pin µPD78044A
64-pin
µ PD78024
For LCD driving
µ PD78064
100-pin
For IEBus
80-pin
µ PD78064Y
Subseries for LCD driving, internal UART
TM
IEBus controller added to the µPD78054
µ PD78098
The major functional differences among the subseries are shown below.
Function
Timer
A/D
Name
For Control
8-bit
16-bit
Watch
Watchdog
µPD78078
4ch
1ch
1ch
1ch
µPD78054
2ch
8-bit × 8ch
µPD78018F
D/A
Serial
Interface
8-bit × 2ch 3ch (UART: 1ch)
—
2ch
I/O
VDD
MIN.
Value
External
Expansion
88
1.8 V
C
69
2.0 V
53
1.8 V
µPD78014
2.7 V
µPD78002
—
µPD78083
For FIP 
driving
µPD780208
—
2ch
1ch
1ch
1ch
—
1ch
8-bit × 8ch
1ch (UART: 1ch)
8-bit × 8ch
—
2ch
33
1.8 V
—
74
2.7 V
—
µPD78044A
68
µPD78024
54
For LCD
driving
µPD78064
2ch
1ch
1ch
1ch
8-bit × 8ch
For IEBusTM
µPD78098
2ch
1ch
1ch
1ch
8-bit × 8ch
—
2ch (UART: 1ch)
57
2.0 V
—
8-bit × 2ch 3ch (UART: 1ch)
69
2.7 V
C
3
µPD78001B(A), 78002B(A)
OVERVIEW OF FUNCTION
Product Name
µPD78001B(A)
Item
Internal
memory
ROM
Internal highspeed RAM
16K bytes
384 bytes
64K bytes
General registers
8 bits × 32 registers (8 bits × 8 registers × 4 banks)
Instruction cycle
On-chip instruction execution time cycle modification function
0.4 µs/0.8 µs/1.6 µs/3.2 µs/6.4 µs (at 10.0 MHz operation)
122 µs (at 32.768 kHz operation)
Instruction set
• 16-bit operation
• Bit manipulation (set, reset, test, boolean operation)
• BCD correction, etc.
I/O ports
Total
• CMOS input
• CMOS I/O
• N-channel open-drain I/O
(15 V withstand voltage)
Serial interface
: 53
: 02
: 47
: 04
• 3-wire/SBI/2-wire mode selectable
• 8-bit timer/event counter
• Watch timer
• Watchdog timer
Timer
: 2 channels
: 1 channel
: 1 channel
Timer output
2
Clock output
39.1 kHz, 78.1 kHz, 156 kHz, 313 kHz, 625 kHz, 1.25 MHz (at main system clock 10.0 MHz operation),
32.768 kHz (at subsystem clock 32.768 kHz operation)
Buzzer output
2.4 kHz, 4.9 kHz, 9.8 kHz (at main system clock 10.0 MHz operation)
Vectored
Maskable
interrupts
Internal : 5
External : 4
Non-maskable
interrupt
Internal : 1
Software
interrupt
Internal : 1
interrupts
4
8K bytes
256 bytes
Memory space
When main system
clock selected
When subsystem
clock selected
µPD78002B(A)
Test input
Internal : 1
External : 1
Operating voltage range
VDD = 2.7 to 6.0 V
Operating ambient
temperature range
–40 to +85°C
Package
• 64-pin plastic shrink DIP (750 mil)
• 64-pin plastic QFP (■
■ 14 mm)
µPD78001B(A), 78002B(A)
CONTENTS
1.
PIN CONFIGURATION (TOP VIEW) .....................................................................................................
6
2.
BLOCK DIAGRAM ...................................................................................................................................
9
3.
PIN FUNCTIONS ..................................................................................................................................... 10
3.1
PORT PINS ...................................................................................................................................................... 10
3.2
OTHER PINS ................................................................................................................................................... 12
3.3
PIN I/O CIRCUIT AND RECOMMENDED CONNECTION OF UNUSED PINS ...................................... 13
4.
MEMORY SPACE .................................................................................................................................... 15
5.
PERIPHERAL HARDWARE FUNCTION FEATURES ............................................................................ 16
6.
5.1
PORTS .............................................................................................................................................................. 16
5.2
CLOCK GENERATOR ...................................................................................................................................... 17
5.3
TIMER/EVENT COUNTER .............................................................................................................................. 18
5.4
CLOCK OUTPUT CONTROL CIRCUIT ......................................................................................................... 20
5.5
BUZZER OUTPUT CONTROL CIRCUIT ....................................................................................................... 20
5.6
SERIAL INTERFACES ..................................................................................................................................... 21
INTERRUPT FUNCTIONS AND TEST FUNCTIONS .......................................................................... 22
6.1
INTERRUPT FUNCTIONS ............................................................................................................................... 22
6.2
TEST FUNCTIONS .......................................................................................................................................... 25
7.
EXTERNAL DEVICE EXPANSION FUNCTIONS ................................................................................. 26
8.
STANDBY FUNCTIONS ......................................................................................................................... 26
9.
RESET FUNCTION .................................................................................................................................. 26
10. INSTRUCTION SET ................................................................................................................................ 27
11. ELECTRICAL SPECIFICATIONS ............................................................................................................. 30
12. CHARACTERISTIC CURVE (REFERENCE VALUES) ........................................................................... 48
13. PACKAGE DRAWINGS ........................................................................................................................... 52
14. RECOMMENDED SOLDERING CONDITIONS ..................................................................................... 56
APPENDIX A. DEVELOPMENT TOOLS ...................................................................................................... 57
APPENDIX B. RELATED DOCUMENTS ...................................................................................................... 59
5
µPD78001B(A), 78002B(A)
1. PIN CONFIGURATION (TOP VIEW)
64-Pin Plastic Shrink DIP (750 mil)
1
64
IC3
P21
2
63
IC2
P22
3
62
P17
P23
4
61
P16
P24
5
60
P15
P25/SI0/SB0
6
59
P14
P26/SO0/SB1
7
58
P13
P27/SCK0
8
57
P12
P30
9
56
P11
P31/TO1
10
55
P10
P32/TO2
11
54
IC1
P33/TI1
12
53
P04/XT1
P34/TI2
13
52
XT2
51
IC0
50
X1
49
X2
48
V DD
47
P03/INTP3
46
P02/INTP2
45
P01/INTP1
P35/PCL
14
P36/BUZ
15
P37
16
V SS
17
P40/AD0
18
P41/AD1
19
P42/AD2
20
P43/AD3
21
44
P00/INTP0
P44/AD4
22
43
RESET
P45/AD5
23
42
P67/ASTB
P46/AD6
24
41
P66/WAIT
P47/AD7
25
40
P65/WR
P50/A8
26
39
P64/RD
P51/A9
27
38
P63
P52/A10
28
37
P62
P53/A11
29
36
P61
P54/A12
30
35
P60
P55/A13
31
34
P57/A15
V SS
32
33
P56/A14
Always connect the IC0, IC1 and IC3 (Internally Connected) pins to VSS directly.
Always connect the IC2 pin to VDD directly.
6
µPD78001BCW(A)– × × ×
µPD78002BCW(A)– × × ×
Remark
P20
µPD78001B(A), 78002B(A)
P12
P13
P14
P15
P16
P17
IC2
IC3
P20
P21
P22
P23
P24
P25/SI0/SB0
P30
1
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
48
P11
P31/TO1
2
47
P10
P32/TO2
3
46
IC1
P33/TI1
4
45
P04/XT1
P34/TI2
5
44
XT2
43
IC0
42
X1
41
X2
40
V DD
39
P03/INTP3
38
P02/INTP2
37
P01/INTP1
P35/PCL
6
P36/BUZ
7
P37
8
V SS
9
µPD78001BGC(A)– × × × –AB8
µPD78002BGC(A)– × × × –AB8
P65/WR
P66/WAIT
P64/RD
P67/ASTB
P63
34
33
16
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
P62
15
P46/AD6
P61
P45/AD5
P60
RESET
P57/A15
P00/INTP0
35
P56/A14
36
14
V SS
13
P44/AD4
P55/A13
P43/AD3
P54/A12
12
P53/A11
P42/AD2
P52/A10
11
P51/A9
10
P41/AD1
P50/A8
P40/AD0
P47/AD7
Remark
P26/SO0/SB1
P27/SCK0
64-Pin Plastic QFP (■
■ 14 mm)
Always connect the IC0, IC1 and IC3 (Internally Connected) pins to VSS directly.
Always connect the IC2 pin to VDD directly.
7
µPD78001B(A), 78002B(A)
P00 to P04
P10 to P17
P20 to P27
P30 to P37
P40 to P47
P50 to P57
P60 to P67
INTP0 to INTP3
TI1, TI2
TO1, TO2
SB0, SB1
SI0
SO0
SCK0
8
:
:
:
:
:
:
:
:
:
:
:
:
:
:
Port 0
Port 1
Port 2
Port 3
Port 4
Port 5
Port 6
Interrupt From Peripherals
Timer Input
Timer Output
Serial Bus
Serial Input
Serial Output
Serial Clock
PCL
BUZ
AD0 to AD7
A8 to A15
RD
WR
WAIT
ASTB
X1, X2
XT1, XT2
RESET
VDD
VSS
IC0 to IC3
:
:
:
:
:
:
:
:
:
:
:
:
:
:
Programmable Clock
Buzzer Clock
Address/Data Bus
Address Bus
Read Strobe
Write Strobe
Wait
Address Strobe
Crystal (Main System Clock)
Crystal (Subsystem Clock)
Reset
Power Supply
Ground
Internally Connected
µPD78001B(A), 78002B(A)
2. BLOCK DIAGRAM
TO1/P31
TI1/P33
TO2/P32
TI2/P34
8-bit TIMER/
EVENT COUNTER 1
PORT0
P00
P01-P03
P04
8-bit TIMER/
EVENT COUNTER 2
PORT1
P10-P17
PORT2
P20-P27
WATCH TIMER
PORT3
P30-P37
SERIAL
INTERFACE 0
PORT4
P40-P47
INTERRUPT
CONTROL
PORT5
P50-P57
PORT6
P60-P67
WATCHDOG TIMER
78K/0
CPU CORE
SI0/SB0/P25
SO0/SB1/P26
SCK0/P27
INTP0/P00 –
INTP3/P03
ROM
RAM
BUZ/P36
BUZZER OUTPUT
PCL/P35
CLOCK OUTPUT
CONTROL
AD0/P40AD7/P47
EXTERNAL
ACCESS
VDD
Remark
VSS
IC0IC3
SYSTEM
CONTROL
A8/P50A15/P57
RD/P64
WR/P65
WAIT/P66
ASTB/P67
RESET
X1
X2
XT1/P04
XT2
Internal ROM & RAM capacity varies depending on the product.
9
µPD78001B(A), 78002B(A)
3. PIN FUNCTIONS
3.1
PORT PINS (1/2)
Pin Name
I/O
P00
Input
P01
Input/
output
P02
Reset
DualFunction Pin
Input only
Input
INTP0
Input/output can be specified bit-wise.
When used as an input port, pull-up resistor can
be used by software.
Input
INTP1
Function
Port 0
5-bit I/O port
After
INTP2
P03
INTP3
Input only
P04*
Input
P10 to P17
Input/
output
Port 1
8-bit input/output port.
Input/output can be specified bit-wise.
When used as an input port, pull-up resistor can be used by software.
P20
Input/
output
Port 2
8-bit input/output port.
Input/output can be specified bit-wise.
When used as an input port, pull-up resistor can be used by software.
P21
P22
Input
XT1
–
Input
–
–
–
P23
–
P24
–
P25
SI0/SB0
P26
SO0/SB1
P27
SCK0
P30
P31
Input/
output
P32
Port 3
8-bit input/output port.
Input/output can be specified in bit-wise.
When used as an input port, pull-up resistor can be used by software.
Input
–
TO1
TO2
P33
TI1
P34
TI2
P35
PCL
P36
BUZ
P37
–
P40 to P47
Input/
output
Port 4
8-bit input/output port.
Input/output can be specified in 8-bit unit.
When used as an input port, pull-up resistor can be used by software.
Test input flag (KRIF) is set to 1 by falling edge detection.
Input
AD0 to AD7
* When using the P04/XT1 pins as an input port, set 1 to bit 6 (FRC) of the processor control register. (Do not use
the on-chip feedback register of the subsystem clock oscillator.)
10
µPD78001B(A), 78002B(A)
3.1
PORT PINS (2/2)
Pin Name
I/O
P50 to P57
Input/
output
Port 5
8-bit input/output port.
LED can be driven directly.
Input/output can be specified bit-wise.
When used as an input port, pull-up resistor can be used by software.
P60
Input/
output
Port 6
8-bit input/output port.
Input/output can be specified
bit-wise.
P61
P62
Function
N-ch open-drain input/output port. Onchip pull-up resistor can be specified by
mask option.
LED can be driven directly.
After
Dual-
Reset
Function Pin
Input
A8 to A15
Input
P63
When used as an input port, pull-up
resistor can be used by software.
P64
P65
RD
WR
P66
WAIT
P67
ASTB
Caution
When pull-up resistors are not used (specified by mask option), the low-level input leak current
increases with -200 µA (MAX.) under either of the following conditions.
1 When the external device expansion function is used and a low-level is input to the pin.
2 During the 3-clock period when a read instruction is executed on port 6 (P6) and the port mode
register (PM6).
11
µPD78001B(A), 78002B(A)
3.2
OTHER PINS
Pin Name
INTP0
I/O
Input
Function
Effective edge (rising edge, falling edge, or both rising edge and falling edge)
After
Dual-
Reset
Function Pin
Input
P00
INTP1
can be specified.
P01
INTP2
External interrupt input.
P02
INTP3
Falling edge detection external interrupt input.
P03
SI0
Input
SO0
Output
SB0
Input
SB1
/output
SCK0
Input
Serial interface serial data input.
Input
P25/SB0
Serial interface serial data output.
Input
P26/SB1
Serial interface serial data input/output.
Input
P25/SI0
P26/SO0
Serial interface serial clock input/output.
Input
P27
External count clock input to 8-bit timer (TM1).
Input
P33
/output
TI1
Input
TI2
TO1
External count clock input to 8-bit timer (TM2).
Output
TO2
8-bit timer (TM1) output.
P34
Input
8-bit timer (TM2) output.
P31
P32
PCL
Output
Clock output (for main system clock, subsystem clock trimming).
Input
P35
BUZ
Output
Buzzer output.
Input
P36
Low-order address/data bus at external memory expansion.
Input
P40 to P47
AD0 to AD7
Input
/output
A8 to A15
Output
High-order address bus at external memory expansion.
Input
P50 to P57
RD
Output
External memory read operation strobe signal output.
Input
P64
WR
External memory write operation strobe signal output.
WAIT
Input
ASTB
Output
P65
Wait insertion at external memory access.
Input
P66
Strobe output which latches the address information output at port 4 and
Input
P67
port 5 to access external memory.
RESET
Input
System reset input.
—
—
X1
Input
Main system clock oscillation crystal connection.
—
—
X2
—
—
—
Input
P04
—
—
XT1
Input
Subsystem clock oscillation crystal connection.
XT2
—
VDD
—
Positive power supply.
—
—
VSS
—
Ground potential.
—
—
IC0 to IC3
—
Internal connection. IC0/IC1/IC3 and IC2 should be connected directly to VSS
—
—
VDD, respecitively.
12
µPD78001B(A), 78002B(A)
3.3 PIN I/O CIRCUIT AND RECOMMENDED CONNECTION OF UNUSED PINS
The input/output circuit type of each pin and recommended connection of unused pins are shown in Table 3-1.
For the input/output circuit configuration of each type, see Fig. 3-1.
Table 3-1 Input/Output Circuit Type of Each Pin
Pin Name
Input/Output
I/O
Circuit Type
Recommended Connection when Not Used
Input
Connected to VSS .
8-A
Input/output
Connected to VSS through resistor independently.
P04/XT1
16
Input
Connected to VDD or VSS .
P10 to P17
5-A
Input/output
Connected to VDD or VSS through resistor independently.
P00/INTP0
2
P01/INTP1
P02/INTP2
P03/INTP3
P20 to P24
P25/SI0/SB0
10-A
P26/SO0/SB1
P27/SCK0
P30
5-A
P31/TO1
P32/TO2
P33/TI1
8-A
P34/TI2
P35/PCL
5-A
P36/BUZ
P37
P40/AD0 to P47/AD7
5-E
Connected to VDD through resistor independently.
P50/A8 to P57/A15
5-A
Connected to VDD or VSS through resistor independently.
P60 to P63
13-B
Connected to VDD through resistor independently.
P64/RD
5-A
Connected to VDD or VSS through resistor independently.
P65/WR
P66/WAIT
P67/ASTB
RESET
2
Input
—
XT2
16
—
Leave open.
IC0, IC1, IC3
—
IC2
Connected to VSS directly.
Connected to VDD directly.
13
µPD78001B(A), 78002B(A)
Fig. 3-1 Pin Input/Output Circuits
V DD
Type 10-A
Type 2
pullup
enable
P-ch
V DD
IN
data
P-ch
IN / OUT
open drain
output disable
N-ch
Schmitt-Triggered Input with Hysteresis Characteristic
Type 5-A
Type 13-B
V DD
pullup
enable
V DD
Mask
Option
P-ch
data
output disable
V DD
data
IN / OUT
N-ch
P-ch
V DD
IN / OUT
output
disable
N-ch
input
enable
Middle-High Voltage Input Buffer
Type 5-E
pullup
enable
data
P-ch
RD
Type 16
V DD
feedback
cut-off
P-ch
P-ch
V DD
P-ch
IN / OUT
output
disable
N-ch
XT1
V DD
Type 8-A
pullup
enable
P-ch
V DD
data
P-ch
IN / OUT
output
disable
14
N-ch
XT2
µPD78001B(A), 78002B(A)
4. MEMORY SPACE
The memory map of µPD78001B(A)/78002B(A) is shown in Fig. 4-1.
Fig. 4-1 Memory Map
FFFFH
Special Function Registers
(SFR) 256 × 8 Bits
FF00H
FEFFH
FEE0H
FEDFH
General Registers
32 × 8 Bits
Internal High-Speed RAM*
mmmmH
nnnnH
mmmmH–1
Program Area
Data
Memory
Use Prohibited
1000H
0FFFH
Space
CALLF Entry Area
0800H
07FFH
FA80H
FA7FH
Program Area
Program
Memory
External Memory
0080H
007FH
Space
nnnnH+1
CALLT Table Area
nnnnH
0040H
003FH
Internal ROM*
0000H
0000H
Remark
Vector Table Area
Shaded area indicates internal memory.
* Intermal ROM and internal high-speed RAM capacities vary depending on the product (see the table below).
Product Name
Internal ROM
Internal High-Speed
End Address
RAM Start Address
nnnnH
mmmmH
µPD78001B(A)
1FFFH
FE00H
µPD78002B(A)
3FFFH
FD80H
15
µPD78001B(A), 78002B(A)
5
PERIPHERAL HARDWARE FUNCTION FEATURES
5.1 PORTS
The I/O port has the following three types.
• CMOS input (P00, P04)
• CMOS input/output (P01 to P03,
port 1 to port 5, P64 to P67)
• N-ch open-drain input/output
(15V withstand voltage) (P60 to P63)
:
: 47
Total
: 53
:
2
4
Table 5-1 Functions of Ports
Port Name
Port 0
Pin Name
P00, P04
Dedicated Input port
P01 to P03
Input/output ports. Input/output can be specified bit-wise.
When used as an input port, pull-up resistor can be used by software.
Input/output ports. Input/output can be specified bit-wise.
When used as an input port, pull-up resistor can be used by software.
Input/output ports. Input/output can be specified bit-wise.
When used as an input port, pull-up resistor can be used by software.
Input/output ports. Input/output can be specified bit-wise.
When used as an input port, pull-up resistor can be used by software.
Input/output ports. Input/output can be specified in 8-bit units.
When used as an input port, pull-up resistor can be used by software.
Test input flag (KRIF) is set to 1 by falling edge detection.
Input/output ports. Input/output can be specified bit-wise.
When used as an input port, pull-up resistor can be used by software.
LED can be driven directly.
N-ch open-drain input/output port. Input/output can be specified bit-wise.
On-chip pull-up resistor can be specified by mask option.
LED can be driven directly.
Input/output ports. Input/output can be specified bit-wise.
When used as an input port, pull-up resistor can be used by software.
Port 1
P10 to P17
Port 2
P20 to P27
Port 3
P30 to P37
Port 4
P40 to P47
Port 5
P50 to P57
Port 6
P60 to P63
P64 to P67
Caution
Function
When pull-up resistors are not used (specified by mask option), low-level input leak current increases
with –200 µA (MAX.) under either of the following conditions.
1 When the external device expansion function is used and a low-level is input to the pin.
2 During the 3-clock period when a read instruction is executed on port 6 (P6) and the port mode
register (PM6).
16
µPD78001B(A), 78002B(A)
5.2 CLOCK GENERATOR
There are two types of clock generator: main system clock and subsystem clock.
The instruction exection time can be changed.
• 0.4 µs/0.8 µs/1.6 µs/3.2 µs/6.4 µs (mainsystem clock: at 10.0 MHz operation)
• 122 µs (subsystem clock: at 32.768 KHz operation)
Fig. 5-1 Clock Generator Block Diagram
XT1/P04
XT2
Watch Timer
Clock Output
Function
Subsystem fXT
Clock
Osicillator
Prescaler
X1
X2
Main
System
Clock
Osicillator
fX
Clock to
Peripheral
Hardware
Prescaler
fX
2
fX
22
fX
23
fX
24
STOP
Selector
Standby
Control
Circuit
Wait
Control
Circuit
CPU Clock
(fCPU)
INTP0
Sampling Clock
17
µPD78001B(A), 78002B(A)
5.3 TIMER/EVENT COUNTER
The following four channels are incorporated in the timer/event counter.
• 8-bit timer/event counter
• Watch timer
• Watchdog timer
: 2 channels
: 1 channel
: 1 channel
Table 5-2 Types and Features of Timer/Event Counter
Type
Functions
8-bit Timer/Event Counter
Watch Timer
Watchdog Timer
Interval timer
2 channels
1 channel
1 channel
External event counter
2 channels
–
–
Timer output
2 outputs
–
–
Sqare wave output
2 outputs
–
–
2
2
1
Interrupt request
Fig. 5-2 8-Bit Timer/Enent Counter Block Diagram
Internal Bus
INTTM1
8-Bit Compare
Register (CR10)
8-Bit Compare
Register (CR20)
Selector
Match
Match
Output
Control
Circuit
INTTM2
fX/2 – fX/210
fX/212
TO2/P32
Selector
8-Bit Timer
Register 1 (TM1)
Selector
TI1/P33
Clear
8-Bit Timer
Register 2 (TM2)
Clear
fX/2 – fX/210
fX/212
Selector
Selector
TI1/P34
Output
Control
Circuit
Internal Bus
18
TO1/P31
µPD78001B(A), 78002B(A)
Fig. 5-3 Watch Timer Block Diagram
Selector
fX/2 8
Selector
fW
5-Bit Counter
fW
214
Selector
Prescaler
fXT
fW
24
fW
25
fW
26
fW
27
fW
28
INTWT
fW
213
fW
29
INTTM3
Selector
Fig. 5-4 Watchdog Timer Block Diagram
fW
24
Prescaler
fW
25
fW
26
fW
27
fW
28
fW
29
fW fW
210 212
INTWDT
Maskable
Interrupt Request
Selector
8-Bit Counter
Control
Circuit
RESET
INTWDT
Non-Maskable
Interrupt Request
19
µPD78001B(A), 78002B(A)
5.4 CLOCK OUTPUT CONTROL CIRCUIT
The clock with the following frequencies can be output for clock output.
• 39.1 kHz/78.1 kHz/156 kHz/313 kHz/625 kHz/1.25 MHz (Main system clock: at 10.0 MHz operation)
• 32.768 kHz (Subsystem clock: at 32.768 kHz operation)
Fig. 5-5 Clock Output Control Block Diagram
fX/2 3
fX/2 4
fX/2 5
fX/2 6
Selector
Synchronization
Circuit
Output Control
Circuit
fX/2 7
fX/2 8
fXT
5.5 BUZZER OUTPUT CONTROL CIRCUIT
The clock with the following frequencies can be output for buzzer output.
• 2.4 kHz/4.9 kHz/9.8 kHz (Main system clock: at 10.0 MHz operation)
Fig. 5-6 Buzzer Output Control Block Diagram
fX/210
fX/211
fX/212
20
Selector
Output Control
Circuit
BUZ/P36
PCL/P35
µPD78001B(A), 78002B(A)
5.6 SERIAL INTERFACES
There is one on-chip clocked serial interface.
Serial Interface channel 0 has the following three modes.
• 3-wire serial I/O mode
• SBI (Serial Bus Interface) mode
• 2-wire serial I/O mode
: MSB/LSB-first switchable
: MSB-first
: MSB-first
Fig. 5-7 Serial Interface Channel 0 Block Diagram
Internal Bus
SI0/SB0/P25
Selector
Serial I/O Shift
Register 0 (SIO0)
Output
Latch
SO0/SB1/P26
Selector
SCK0/P27
Bus Release/Command/
Acknowledge Detection
Circuit
Serial Counter
Busy/Acknowledge
Output Circuit
Interrupt
Request
Signal
Generator
INTCSI0
fX/22 – fX/2 9
Serial Clock
Control Circuit
Selector
TO2
21
µPD78001B(A), 78002B(A)
6. INTERRUPT FUNCTIONS AND DEST FUNCTIONS
6.1 INTERRUPT FUNCTIONS
There are 11 interrupt functions of 3 different kinds as shown below.
• Non-maskable interrupt
• Maskable interrupt
• Software interrupt
:
:
:
1
9
1
Table 6-1 Interrrupt Source List
Interrupt
Type
Default
Priority *1
Nonmaskable
Maskable
Software
Interrupt Source
Name
Trigger
INTWDT
Watchdog timer overflow (with nonmaskable interrupt selected)
0
INTWDT
Watchdog timer overflow (with interval
timer selected)
1
INTP0
2
Pin input edge detection
Internal/
External
Vector Table
Adress
Basic
Configuration
Type *2
Internal
0004H
A
B
0006H
C
INTP1
0008H
D
3
INTP2
000AH
4
INTP3
000CH
5
INTCSI0
Serial interface channel 0 transfer end
6
INTTM3
Reference time interval signal from
watch timer
0012H
7
INTTM1
8-bit timer/event counter 1 match signal
generation
0016H
8
INTTM2
8-bit timer/event counter 2 match signal
generation
0018H
BRK
BRK instruction execution
External
Internal
Internal
000EH
003EH
B
E
* 1. The default priority is the priority applicable when more priority than one maskable interrupt is generated.
0 is the highest and 11, the lowest.
2. Basic configuration types A to E correspond to (A) to (E) on the next page.
22
µPD78001B(A), 78002B(A)
Fig. 6-1 Interrupt Function Basic Configuration (1/2)
(A) Internal Non-Maskable Interrupt
Internal Bus
Interrupt
Request
Vector Table
Address
Generator
Priority Control
Circuit
Standby Release
Signal
(B) Internal Maskable Interrupt
Internal Bus
MK
Interrupt
Request
PR
IE
ISP
Priority Control
Circuit
IF
Vector Table
Address
Generator
Standby Release
Signal
(C) External Maskable Interrupt (INTP0)
Internal Bus
Sampling Clock
Select Register
(SCS)
Interrupt
Request
Sampling
Clock
External Interrupt
Mode Register
(INTM0)
Edge
Detector
MK
IF
IE
PR
Priority Control
Circuit
ISP
Vector Table
Address
Generator
Standby Release
Signal
23
µPD78001B(A), 78002B(A)
Fig. 6-1 Interrupt Function Basic Configuration (2/2)
(D) External Maskable Interrupt (Except INTP0)
Internal Bus
External Interrupt
Mode Register
(INTM0)
Interrupt
Request
Edge
Detector
MK
IE
PR
Priority Control
Circuit
IF
ISP
Vector Table
Address
Generator
Standby Release
Signal
(E) Software Interrupt
Internal Bus
Interrupt
Request
Remarks
24
1.
IF
2.
3.
IE : Interrupt enable flag
ISP : In-service priority flag
: Interrupt request flag
4.
5.
MK : Interrupt mask flag
PR : Priority spcification flag
Priority Control
Circuit
Vector Table
Address
Generator
µPD78001B(A), 78002B(A)
6.2 TEST FUNCTIONS
There are two test functions as shown in Table 6-2.
Table 6-2 Test Source List
Test Source
Internal/External
Name
Trigger
INTWT
Watch timer overflow
Internal
NTPT4
Port 4 falling edge detection
External
Fig. 6-2 Test Function Basic Configuration
Internal Bus
MK
Test Input
Remarks
1.
IF
2.
MK : Test mask flag
IF
Standby Release
Signal
: Test input flag
25
µPD78001B(A), 78002B(A)
7. EXTERNAL DEVICE EXPANSION FUNCTIONS
The external device expansion function is used to connect external devices to areas other than the internal ROM,
RAM and SFR.
Ports 4 to 6 are used for connection with external devices.
8. STANDBY FUNCTIONS
There are the following two standby functions to reduce the current dissipation.
• HALT mode
: The CPU operating clock is stopped. The average consumption current can be reduced by
intermittent operation in combination with the normal operating mode.
• STOP mode
: The main system clock oscillation is stopped. The whole operation by the main system clock is
stopped, so that the system operates with ultra-low power consumption using only the subsystem clock.
Fig. 8-1 Standby Functions
CSS=1
Main System
Clock Operation
Interrupt
Request
CSS=0
HALT
Instruction
STOP
Instruction
Interrupt
Request
STOP Mode
(Main system clock
oscillation stopped)
*
HALT Mode
(Clock supply to CPU is
stopped, oscillation)
Interrupt
Request
HALT
Instruction
HALT Mode*
(Clock supply to CPU is
stopped, oscillation)
The power consumption can be reduced by stopping the main system clock. When the CPU is operating on the
subsystem clock, set the MCC to stop the main system clock. The STOP instruction cannot be used.
Caution
When the main system clock is stopped and the system is operated by the subsystem clock, the
subsystem clock should be switched again to the main system clock after the oscillation stabilization
time is secured by the program by the program.
9. RESET FUNCTION
There are the following two reset methods.
• External reset input by RESET pin.
• Internal reset by watchdog timer runaway time detection.
26
Subsystem Clock
Operation*
µPD78001B(A), 78002B(A)
10. INSTRUCTION SET
(1) 8-Bit Instruction
MOV, XCH, ADD, ADDC, SUB, SUBC, AND, OR, XOR, CMP, INC, DEC, ROR, ROL, RORC, ROLC, ROR4, ROL4, PUSH,
POP, DBNZ
2nd
Operand
[HL+byte]
#byte
A
r*
sfr
saddr
!addr16
PSW
[DE]
[HL]
1st
Operand
A
r
[HL+B]
$addr16
1
None
[HL+C]
ADD
MOV
MOV
MOV
MOV
ADDC
XCH
XCH
XCH
XCH
SUB
ADD
ADD
ADD
MOV
MOV
MOV
MOV
XCH
XCH
XCH
ROL
ADD
ADD
RORC
ROLC
SUBC
ADDC
ADDC
ADDC
ADDC
ADDC
AND
SUB
SUB
SUB
SUB
SUB
OR
SUBC
SUBC
SUBC
SUBC
SUBC
XOR
AND
AND
AND
AND
AND
CMP
OR
OR
OR
OR
OR
XOR
XOR
XOR
XOR
XOR
CMP
CMP
CMP
CMP
CMP
MOV
ROR
MOV
INC
ADD
DEC
ADDC
SUB
SUBC
AND
OR
XOR
CMP
r1
DBNZ
sfr
MOV
MOV
saddr
MOV
MOV
ADD
DBNZ
INC
DEC
ADDC
SUB
SUBC
AND
OR
XOR
CMP
!addr16
PSW
MOV
MOV
MOV
PUSH
POP
[DE]
MOV
[HL]
MOV
ROR4
ROL4
[HL+byte]
MOV
[HL+B]
[HL+C]
* Except r = A
27
µPD78001B(A), 78002B(A)
(2) 16-Bit Instruction
MOVW, XCHW ADDW, SUBW, CMPW, PUSH, POP, INCW, DECW
2nd Operand
#word
AX
rp*
sfrp
ADDW
MOVW
MOVW
SUBW
XCHW
saddrp
!addr16
SP
None
1st Operand
AX
MOVW
MOVW
MOVW
CMPW
rp
MOVW
MOVW*
INCW, DECW
PUSH, POP
sfrp
MOVW
MOVW
saddrp
MOVW
MOVW
!addr16
SP
MOVW
MOVW
MOVW
* Only when rp = BC, DE, HL.
(3) Bit Operation Instruction
MOV1, AND1, OR1, XOR1, SET1, CLR1, NOT1, BT, BF, BTCLR
2nd Operand
A.bit
sfr.bit
saddr.bit
PWS.bit
[HL].bit
CY
$addr16
None
1st Operand
A.bit
MOV1
BT
SET1
BF
CLR1
BTCLR
sfr.bit
MOV1
BT
SET1
BF
CLR1
BTCLR
saddr.bit
MOV1
BT
SET1
BF
CLR1
BTCLR
PSW.bit
MOV1
BT
SET1
BF
CLR1
BTCLR
[HL].bit
MOV1
BT
SET1
BF
CLR1
BTCLR
CY
28
MOV1
MOV1
MOV1
MOV1
MOV1
SET1
AND1
AND1
AND1
AND1
AND1
CLR1
OR1
OR1
OR1
OR1
OR1
NOT1
XOR1
XOR1
XOR1
XOR1
XOR1
µPD78001B(A), 78002B(A)
(4) Call Instruction/Branch Instruction
CALL, CALLF, CALLT, BR, BC, BNC, BZ, BNZ, BT, BF,BTCLR, DBNZ
2nd Operand
AX
!addr16
!addr11
[addr5]
BR
CALL, BR
CALLF
CALLT
$addr16
1st Operand
Basic instruction
Compound instruction
BR, BC, BNC, BZ, BNZ
BT, BF, BTCLR, DBNZ
(5) Other Instruction
ADJBA, ADJBS, BRK, RET, RETI, RETB, SEL, NOP, EI, DI, HALT, STOP
29
µPD78001B(A), 78002B(A)
11. ELECTRICAL SPECIFICATIONS
Absolute Maximum Ratings (TA = 25 °C)
Parameter
Supply voltage
Input voltage
Symbol
Test Conditions
Rating
Unit
–0.3 to + 7.0
V
–0.3 to VDD + 0.3
V
–0.3 to +16
V
–0.3 to VDD + 0.3
V
1 pin
–10
mA
P10 to P17, P20 to P27, P30 to P37 total
–15
mA
P01 to P03, P40 to P47, P50 to P57, P60 to P67 total
–15
mA
Peak value
30
mA
Effective value
15
mA
Peak value
100
mA
Effective value
70
mA
P01 to P03, P56, P57,
Peak value
100
mA
P60 to P67 total
Effective value
70
mA
P01 to P03,
Peak value
50
mA
P64 to P67 total
Effective value
20
mA
P10 to P17, P20 to P27, P30 to P37
Peak value
50
mA
total
Effective value
20
mA
TA
–40 to +85
°C
Tstg
–65 to +150
°C
VDD
VI1
P00 to P04, P10 to P17, P20 to P27, P30 toP37
P40 to P47, P50 to P57, P64 to P67, X1, X2, XT2
VI2
Output voltage
IOH
Output
1 pin
current low
P40 to P47, P50 to P55 total
IOL*
Operating ambient
temperature
Storage
temperature
*
Open-drain
VO
Output
current high
P60 to P67
Effective value should be calculated as follows:
[Effective value] = [Peak value] × √duty
Caution
Product quality may suffer if the absolute maximum rating is exceeded for even a single parameter or even
momentarily. That is, the absolute maximuam ratings are rated values at which the product is on the verge of suffering
physical damage, and therefore the product must be used under conditions which ensure that the absolute maximum
ratings are not exceeded.
30
µPD78001B(A), 78002B(A)
Capacitance (TA = 25 °C, VDD = VSS = 0 V)
Parameter
Symbol
Input capacitance
CIN
Test Conditions
MIN.
TYP.
f=1 MHz Unmeasured pins returned to 0 V
I/O capacitance
MAX.
Unit
15
pF
15
pF
20
pF
P01 to P03, P10 to P17,
f=1 MHz Unmeasured
CIO
pins returned to 0 V
P20 to P27, P30 to P37,
P40 toP47, P50 to P57,
P64 to P67
P60 to P63
Remark
The characteristics of a dual-function pin and a port pin are the same unless specified otherwise.
Main System Clock Oscillation Circuit Characteristics (TA = –40 to +85 °C, VDD = 2.7 to 6.0 V)
Recommended
Circuit
Resonator
Ceramic
X1
resonator
X2 VSS
Parameter
Test Conditions
Oscillator
VDD = Oscillator
frequency (fX) *1
voltage range
MIN.
TYP.
1
MAX.
Unit
10
MHz
4
ms
10
MHz
R1
C1
C2
Crystal
After VDD reaches oscil-
stabilization time *2
lator voltage range MIN.
Oscillator
X1
resonator
C1
X2 VSS
C2
External
clock
Oscillation
1
frequency (fX) *1
Oscillation
8.38
10
VDD = 4.5 to 6.0 V
ms
stabilization time *2
30
X1 input
X2
X1
µPD74HCU04
frequency (fX) *1
1.0
10.0
MHz
42.5
500
ns
X1 input
high/low level width
(tXH , tXL)
*
1. Indicates only oscillation circuit characteristics. Refer to “AC Characteristics” for instruction execution time.
2. Time required to stabilize oscillation after reset or STOP mode release.
Cautions
1.
When using the main system clock oscillator, wiring the area enclosed with the broken line should be carried
out as follows to avoid an adverse effect from wiring capacitance.
2.
•
Wiring should be as short as possible.
•
Wiring should not cross other signal lines.
•
Wiring should not be placed close to a varying high current.
•
The potential of the oscillator capacitor ground should be the same as VSS.
•
Do not ground wiring to a ground pattern in which a high current flows.
•
Do not fetch a signal from the oscillator.
When the main system clock is stopped and the system is operated by the subsystem clock, the subsystem
clock should be switched again to the main system clock after the oscillation stabilization time is secured by
the program.
31
µPD78001B(A), 78002B(A)
Subsystem Clock Oscillation Circuit Characteristics (TA = –40 to +85 °C, VDD = 2.7 to 6.0 V)
Recommended
Circuit
Resonator
Crystal
XT1
XT2 VSS
resonator
Test Conditions
Parameter
MIN.
TYP.
MAX.
Unit
32
32.768
35
kHz
1.2
2
Oscillator
frequency (fXT) *1
R2
C3
C4
Oscillation
VDD = 4.5 to 6.0 V
s
stabilization time *2
External
10
XT1 input
clock
XT1
XT2
frequency (fXT) *1
32
100
kHz
5
15
µs
XT1 input
high/low level width
(tXTH , tXTL)
*
1. Indicates only oscillation circuit characteristics. Refer to “AC Characteristics” for instruction execution time.
2. Time required to stabilize oscillation after VDD reaches oscillator voltage MIN.
Cautions
1.
When using the subsystem clock oscillator, wiring in the area enclosed with the broken line should be carried
out as follows to avoid an adverse effect from wiring capacitance.
2.
•
Wiring should be as short as possible.
•
Wiring should not cross other signal lines.
•
Wiring should not be placed close to a varying high current.
•
The potential of the oscillator capacitor ground should be the same as VSS.
•
Do not ground wiring to a ground pattern in which a high current flows.
•
Do not fetch a signal from the oscillator.
The subsystem clock oscillation circuit is a circuit with a low amplification level, more prone to misoperation
due to noise than the main system clock. When using the subsystem clock, special care is needed regarding
the wiring method.
32
µPD78001B(A), 78002B(A)
RECOMMENDED OSCILLATION CIRCUIT CONSTANT
Main System Clock Ceramic Resonator (TA = –40 to +85 °C)
Manufacturer
Murata m.f.g.
Products
Recommended Oscillation Constant
Frequency (MHz)
Oscillation Voltage Range
C1 (pF)
C2 (pF)
R1 (kΩ)
MIN. (V)
MAX. (V)
1.00
100
100
6.8
2.9
6.0
CSB × × × × J
1.01-1.25
100
100
4.7
2.7
6.0
CSA × . × × × MK
1.26-1.79
100
100
0
2.7
6.0
100
100
0
2.7
6.0
On-chip
On-chip
0
2.7
6.0
30
30
0
2.7
6.0
On-chip
On-chip
0
2.7
6.0
30
30
0
2.7
6.0
On-chip
On-chip
0
2.7
6.0
30
30
0
2.9
6.0
On-chip
On-chip
0
2.9
6.0
4.19
–
–
–
2.7
6.0
4.19
33
33
–
2.7
6.0
10.0
33
33
–
2.8
6.0
1.00
100
100
2.2
2.7
6.0
CSB1000J
CSA × . × × MG
CST × . × × MG
1.80-2.44
CSA× . × × MG
CST× . × × MGW
2.45-4.18
CSA× . × × MG
CST× . × × MGW
4.19-6.00
CSA× . × × MT
CST× . × × MTW
6.01-10.0
KBR-4.19MWS
Kyocera
KBR-4.19MKS
KBR-4.19MSA
PBRC4.19A
KBR-10.0M
KBR-1000F
KBR-1000Y
Remark × × × × , × . × × × , × . × × indicates frequency.
Subsystem Clock: Crystal Resonator (TA = –40 to +60 °C)
Manufacturer
Daishinku corp.
Caution
Products
DT-38 (1TA632E00,
Load capacitance 6.3pF)
Frequency (MHz)
32.768
Recommended Circuit Constant
Oscillation Voltage Range
C3 (pF)
C4 (pF)
R2 (kΩ)
MIN. (V)
MAX. (V)
8
8
100
2.7
6.0
Regarding the oscillator circuit constant, operation is guaranteed, but reliability is not guaranteed. Customers who
require high reliability should directly consult the resonator manufacturer.
33
µPD78001B(A), 78002B(A)
DC Characteristics (TA = –40 to +85 °C, VDD = 2.7 to 6.0 V)
Parameter
Input voltage
Symbol
VIH1
high
Test Conditions
MIN.
P10 to P17, P21, P23, P30 to P32, P35 to P37,
TYP.
MAX.
Unit
0.7 VDD
VDD
V
P40 to P47, P50 to P57, P64 to P67
Input voltage
VIH2
P00 to P03, P20, P22, P24 to P27, P33, P34, RESET
0.8 VDD
VDD
V
VIH3
P60 to P63
0.7 VDD
15
V
VIH4
X1, X2
VDD-0.5
VDD
V
VIH5
XT1/P04, XT2
VDD-0.5
VDD
V
VDD-0.3
VDD
V
0
0.3 VDD
V
0
0.2 VDD
V
0
0.3 VDD
V
0
0.2 VDD
V
0
0.4
V
0
0.4
V
0
0.3
V
VIL1
low
Open-drain
VDD = 4.5 to 6.0 V
P10 to P17, P21, P23, P30 to P32, P35 to P37
P40 to P47, P50 to P57, P64 to P67
VIL2
P00 to P03, P20, P22, P24 to P27, P33, P34, RESET
VIL3
P60 to P63
VIL4
VIL5
Output voltage
VOH1
high
VDD = 4.5 to 6.0 V
X1, X2
XT1/P04, XT2
VDD = 4.5 to 6.0 V
VDD = 4.5 to 6.0 V,IOH = –1 mA
IOH = –100 µA
Output voltage
low
P50 to P57, P60 to P63
VDD = 4.5 to 6.0 V,
VDD-1.0
V
VDD-0.5
V
0.4
2.0
V
0.4
V
0.2 VDD
V
0.5
V
3
µA
X1, X2, XT1/P04, XT2
20
µA
P60 to P63
80
µA
–3
µA
–20
µA
–200
µA
IOL = 15 mA
VOL1
P01 to P03, P10 to P17, P20 to P27,
VDD = 4.5 to 6.0 V,
P30 to P37, P40 to P47, P64 to P67
IOL = 1.6 mA
VDD = 4.5 to 6.0 V,
VOL2
SB0, SB1, SCK0
open-drain
pulled-up (R = 1 KΩ )
VOL3
IOL = 400 µA
Input leakage
current high
P00 to P03, P10 to P17,
P20 to P27, P30 to P37,
ILIH1
VIN = VDD
P40 to P47, P50 to P57,
P60 to P67, RESET
ILIH2
ILIH3
VIN = 15 V
Input leakage
current high
P00 to P03, P10 to P17,
P20 to P27, P30 to P37,
ILIL1
P40 to P47, P50 to P57,
VIN = 0 V
*
X1, X2, XT1/P04, XT2
ILIL3
P60 to
P63
*1
Other than above
–3
*2
µA
1. When memory expansion mode is used by the memory expansion mode register (MM) with no on-chip pull-up resistor
by mask option.
2. When pull-up resistors are not used (specified by mask option), the low-level input leakage current increases with –200
µA (MAX.) under either of the following conditions.
q
w
Remark
34
P64 to P67, RESET
ILIL2
When the external device expansion function is used and a low level is input to the pin.
During the 3-clock period when a read instruction is executed on port 6 (P6) and the port mode registor (PM6).
The characteristics of a dual-function pin and a port pin are the same unless specified otherwise.
µPD78001B(A), 78002B(A)
DC Characteristics (TA = –40 to +85 °C, VDD = 2.7 to 6.0 V)
Parameter
Output leakage
current high
Output leakage
current low
Mask option pullup resister
Symbol
Test Conditions
Unit
3
µA
ILOL
VOUT = 0 V
–3
µA
R1
VIN = 0 V, P60 to P63
VIN = 0 V, P01 to P03,
P10 to P17, P20 to P27,
R2
P30 to P37, P40 to P47,
P50 to P57, P64 to P67
20
40
90
kΩ
4.5 V ≤ VDD < 6.0 V
15
40
90
kΩ
2.7 V ≤ VDD < 4.5 V
20
500
kΩ
8.38 MHz
Crystal oscillation
operating mode
VDD = 5.0 V ± 10 % *1
7.5
22.5
mA
VDD = 3.0 V ± 10 %
0.8
2.4
mA
8.38 MHz
Crystal oscillation
HALT mode
VDD = 5.0 V ± 10 %
1.4
4.2
mA
IDD2
VDD = 3.0 V ± 10 %
550
1650
µA
VDD = 5.0 V ± 10 %
60
120
µA
IDD3
32.768 kHz
Crystal oscillation
operating mode
VDD = 3.0 V ± 10 %
35
70
µA
32.768 kHz
Crystal oscillation
HALT mode
VDD = 5.0 V ± 10 %
25
50
µA
IDD4
VDD = 3.0 V ± 10 %
5
10
µA
XT1 = 0 V STOP mode
When feedback resister
is used
VDD = 5.0 V ± 10 %
1
20
µA
VDD = 3.0 V ± 10 %
0.5
10
µA
XT1 = 0 V STOP mode
When feedback
resister is unused
VDD = 5.0 V ± 10 %
0.1
20
µA
VDD = 3.0 V ± 10 %
0.05
10
µA
Power supply
IDD1
IDD5
IDD6
*
MAX.
VOUT = VDD
up resister
current
TYP.
ILOH1
Software pull-
*3
MIN.
*2
1. Operating in high-speed mode (when set the processor clock control register to 00H).
2. Operating in low-speed mode (when set the processor clock control register to 04H).
3. Port current are excluded.
Remark
The characteristics of a dual-function pin and a port pin are the same unless specified otherwise.
35
µPD78001B(A), 78002B(A)
AC Characteristics (TA = –40 to +85 °C, VDD = 2.7 to 6.0 V)
(1) Basic Operation
Parameter
Symbol
Cycle time
Test Conditions
Operating on main
(Min. instruction
TCY
VDD = 4.5 to 6.0 V
fTI
tTIH
low-level width
tTIL
Interrupt input
tINTH
high/low-level
tINTL
width
RESET low
*
64
µs
µs
µs
0
4
MHz
0
275
kHz
VDD = 4.5 to 6.0 V
122
100
ns
1.8
µs
8/fsam*
µs
INTP1 to INTP3
10
µs
KR0 to KR7
10
µs
10
µs
INTP0
tRSL
level width
Unit
64
40
VDD = 4.5 to 6.0 V
MAX.
125
0.96
Operationg on subsystem clock
frequency
TI input high/
TYP.
0.4
system clock
execution time)
TI input
MIN.
In combination with bits 0 (SCS0) and 1 (SCS1) of sampling clock select register, selection of fsam is possible between fX/2N+1,
µPD78001B(A), 78002B(A)
µPD78P014 (Reference)
TCY vs VDD (At main system clock operation)
TCY vs VDD (At main system clock operation)
60
60
10
10
Operation Guaranteed
Range
2.0
Cycle Time TCY [µs]
Cycle Time TCY [µs]
fX/64 and fx/128 (when N = 0 to 4).
Operation Guaranteed
Range
2.0
1.0
1.0
0.5
0.4
0.5
0.4
0
0
1
2
3
4
5
6
1
Supply Voltage VDD [V]
36
3
4
5
6
Supply Voltage VDD [V]
Remark
Caution
2
indicates TA=–40 to +40 °C
indicates TA=–40 to +85 °C
The operation guaranteed range of the µPD78001B(A), and 78002B(A) differs from that of the
µPD78P014.
µPD78001B(A), 78002B(A)
(2) Read/Write Operation (TA = –40 to +85 °C, VDD = 2.7 to 6.0 V)
Parameter
Symbol
Test Conditions
MIN.
MAX.
Unit
ASTB high-level width
tASTH
0.5tCY
ns
Address setup time
tADS
0.5tCY–30
ns
Address hold time
tADH
10
ns
Data input time from address
tADD1
Load resistor ≥ 5 kΩ
tADD2
Data input time from RD↓
5
(2+2n)tCY–50
ns
(3+2n)tCY–100
ns
tRDD1
(1+2n)tCY–25
ns
tRDD2
(2.5+2n)tCY–100
ns
Read data hold time
tRDH
0
ns
RD low-level width
tRDL1
(1.5+2n)tCY–20
ns
tRDL2
(2.5+2n)tCY–20
WAIT↓ input time from RD↓
WAIT↓ input time from WR↓
WAIT low-level width
ns
tRDWT1
0.5tCY
ns
tRDWT2
1.5tCY
ns
tWRWT
0.5tCY
ns
(2+2n)tCY
ns
tWTL
(0.5+2n)tCY +10
Write data setup time
tWDS
100
ns
Write data hold time
tWDH
5
ns
WR low-level width
tWRL1
(2.5+2n)tCY –20
ns
RD↓ delay time from ASTB↓
tASTRD
0.5tCY–30
ns
WR↓ delay time from ASTB↓
tASTWR
1.5tCY –30
ns
tRDAST
tCY-10
tCY+40
ns
tRDADH
tCY
tCY+50
ns
tRDWD
10
ASTB↑ delay time from
RD↑ in external fetch
Address hold time from
RD↑ in external fetch
Write data output time from RD↑
WR↓ delay time from write data
VDD = 4.5 to 6.0 V
0.5tCY–120
ns
0.5tCY
ns
0.5tCY–170
0.5tCY
ns
tCY
tCY+60
ns
tCY
tCY+100
ns
tWDWR
Address hold time from WR↑
VDD =4.5 to 6.0 V
tWRADH
RD↑ delay time from WAIT↑
tWTRD
0.5tCY
2.5tCY+80
ns
WR↑ delay time from WAIT↑
tWTWR
0.5tCY
2.5tCY+80
ns
Remarks
1.
tCY = TCY/4
2.
n indicates number of waits.
3.
CL = 100 pF (CL indicates load capacitance of P40/AD0 to P47/AD7, P50/A8 to P57/A15, P64/RD, P65/WR,
P66/WAIT,P67/ASTB pins).
37
µPD78001B(A), 78002B(A)
(3) Serial Interface (TA = –40 to +85 °C, VDD = 2.7 to 6.0 V)
(a) 3-wire serial I/O mode (SCK... Internal clock output)
Parameter
Symbol
SCK cycle time
Test Conditions
VDD = 4.5 to 6.0 V
MIN.
TYP.
MAX.
Unit
800
ns
3200
ns
tKCY1/2-50
ns
tKL1
tKCY1/2-150
ns
SI setup time (to SCK↑)
tSIK1
100
ns
SI hold time (from SCK↑)
tKSI1
tKCY1
SCK high/low-level width
tKH1
VDD = 4.5 to 6.0 V
400
SO output delay time from
ns
VDD = 4.5 to 6.0 V
tKSO1
ns
1000
ns
MAX.
Unit
C = 100 pF*
SCK↓
*
300
C is the load capacitance of SO output line.
(b) 3-wire serial I/O mode (SCK... External clock input)
Parameter
Symbol
SCK cycle time
Test Conditions
VDD = 4.5 to 6.0 V
MIN.
TYP.
800
ns
3200
ns
400
ns
tKCY2
SCK high/low-level width
tKH2
VDD = 4.5 to 6.0 V
tKL2
1600
ns
SI setup time (to SCK↑)
tSIK2
100
ns
SI hold time (from SCK↑)
tKSI2
400
SO output delay time from
VDD = 4.5 to 6.0 V
tKSO2
1000
tR2
tF2
*
38
ns
C = 100 pF*
SCK↓
SCK rise, fall time
ns
300
When external device expansion
160
ns
1000
ns
function is used
When external device expansion
function is not used
C is the load capacitance of SO output line.
µPD78001B(A), 78002B(A)
(c) SBI mode (SCK... Internal clock output)
Parameter
SCK cycle time
SCK high/low-level width
Symbol
tKCY3
tKH3
Test Conditions
TYP.
MAX.
Unit
VDD = 4.5 to 6.0 V
800
ns
3200
ns
VDD = 4.5 to 6.0 V
tKCY3/2-50
ns
tKCY3/2-150
ns
100
ns
300
ns
tKCY3/2
ns
tKL3
SB0, SB1 setup time
MIN.
VDD = 4.5 to 6.0 V
tSIK3
(to SCK↑)
SB0, SB1 hold time
tKSI3
from SCK↓
SB0, SB1 output delay time
R = 1 kΩ ,
VDD = 4.5 to 6.0 V
0
250
ns
0
1000
ns
tKSO3
(from SCK↑)
*
C = 100 pF*
SB0, SB1↓ from SCK↑
tKSB
tKCY3
ns
SCK↓ from SB0, SB1↓
tSBK
tKCY3
ns
SB0, SB1 high-level width
tSBH
tKCY3
ns
SB0, SB1 low-level width
tSBL
tKCY3
ns
R and C are the load resistors and load capacitance of the SB0 and SB1 output line.
(d) SBI mode (SCK... External clock input)
Parameter
Symbol
SCK cycle time
Test Conditions
VDD = 4.5 to 6.0 V
MIN.
TYP.
MAX.
Unit
800
ns
3200
ns
400
ns
1600
ns
100
ns
300
ns
tKCY4/2
ns
tKCY4
SCK high/low-level width
tKH4
VDD = 4.5 to 6.0 V
tKL4
SB0, SB1 setup time
VDD = 4.5 to 6.0 V
tSIK4
(to SCK↑)
SB0, SB1 hold time
tKSI4
(from SCK↓)
SB0, SB1 output delay time
R = 1 kΩ ,
VDD = 4.5 to 6.0 V
0
300
ns
0
1000
ns
tKSO4
from SCK↑
C = 100 pF*
SB0, SB1↓ from SCK↑
tKSB
tKCY4
ns
SCK↓ from SB0, SB1↓
tSBK
tKCY4
ns
SB0, SB1 high-level width
tSBH
tKCY4
ns
SB0, SB1 low-level width
tSBL
SCK rise, fall time
tR4
tF4
tKCY4
When external device expansion
ns
160
ns
1000
ns
function is used
When external device expansion
function is not used
*
R and C are the load resistors and load capacitance of the SB0 and SB1 output line.
39
µPD78001B(A), 78002B(A)
(e) 2-wire serial I/O mode (SCK... Internal clock output)
Parameter
Symbol
SCK cycle time
Test Conditions
VDD = 4.5 to 6.0 V
MIN.
TYP.
MAX.
Unit
1600
ns
3800
ns
tKCY5
SCK high-level width
tKH5
tKCY5/2-50
ns
SCK low-level width
tKL5
R = 1 kΩ, C = 100 pF*
tKCY5/2-50
ns
tSIK5
300
ns
tKSI5
600
ns
SB0, SB1 setup time
(to SCK↑)
SB0, SB1 hold time
(from SCK↑)
SB0, SB1 output delay time
R = 1 kΩ,
VDD = 4.5 to 6.0 V
0
250
ns
0
1000
ns
MAX.
Unit
tKSO5
from SCK↓
*
C = 100 pF*
R and C are the load resistors and load capacitance of the SCK0, SB0 and SB1 output line.
(f) 2-wire serial I/O mode (SCK... External clock input)
Parameter
Symbol
SCK cycle time
Test Conditions
VDD = 4.5 to 6.0 V
MIN.
TYP.
1600
ns
tKCY6
3800
ns
SCK high-level width
tKH6
650
ns
SCK low-level width
tKL6
800
ns
tSIK6
100
ns
tKSI6
tKCY6/2
ns
SB0, SB1 setup time
(to SCK↑)
SB0, SB1 hold time
(from SCK↑)
SB0, SB1 output delay time
R = 1 kΩ,
VDD = 4.5 to 6.0 V
0
300
ns
0
1000
ns
160
ns
1000
ns
tKSO6
from SCK↓
C = 100 pF*
SCK rise, fall time
When external device expansion
tR6
function is used
tF6
When external device expansion
function is not used
*
40
R and C are the load resistors and load capacitance of the SCK0, SB0 and SB1 output line.
µPD78001B(A), 78002B(A)
AC Timing Test Point (Excluding X1, XT1 Input)
0.8 VDD
0.2 VDD
0.8 VDD
0.2 VDD
Test Points
Clock Timing
1/fX
tXL
tXH
VDD - 0.5 V
0.4V
X1 Input
1/fXT
tXTL
tXTH
VDD - 0.5 V
0.4V
XT1 Input
TI Timing
1/fTI
tTIL
tTIH
TI1, TI2
41
µPD78001B(A), 78002B(A)
Read/Write Operation
External fetch (no wait):
A8-A15
Upper 8-Bit Address
Lower 8-Bit
Address
tADD1
Hi-z
AD0-AD7
tADS
tASTH
Operation
Code
tRDADH
tRDD1
tADH
tRDAST
ASTB
RD
tRDL1
tASTRD
tRDH
External fetch (wait insertion):
A8-A15
Upper 8-Bit Address
Lower 8-Bit
Address
tADD1
Hi-z
AD0-AD7
Operation
Code
tRDADH
tRDD1
tADS
tASTH
tADH
tRDAST
ASTB
RD
tASTRD
tRDL1
tRDH
WAIT
tRDWT1
42
tWTL
tWTRD
µPD78001B(A), 78002B(A)
External data access (No wait):
A8-A15
Upper 8-Bit Address
Lower
8-Bit
Address
tADD2
Hi-z
AD0-AD7
Read Data
tADS
Hi-z
Write Data
tRDD2
tADH
tRDH
tASTH
ASTB
RD
tRDWD
tWDS
tRDL2
tASTRD
tWDH
tWDWR
tWRADH
WR
tASTWR
tWRL1
External data access (Wait insertion):
A8-A15
Upper 8-Bit Address
Lower
8-Bit
Address
tADD2
Hi-z
AD0-AD7
Read Data
Hi-z
Write Data
tRDD2
tADS
tADH
tRDH
tASTH
ASTB
tASTRD
RD
tRDL2
tWDH
tWDS
tRDWD
tWDWR
WR
tASTWR
tWRL1
tWRADH
WAIT
tRDWT2
tWTRD
tWTL
tWRWT
tWTL
tWTWR
43
µPD78001B(A), 78002B(A)
Serial Transfer Timing
3-wire serial I/O mode:
tKCY 1,2
tKL1,2
tKH1,2
tR2
tF2
SCK
tSIK1,2
SI
tKSI1,2
Input Data
tKSO1,2
SO
Output Data
SBI mode (Bus release signal transfer):
tKCY3,4
tKL3,4
tKH3,4
tR4
tF4
SCK
tKSB
tSBL
tSBK
tSBH
tSIK3,4
tKSI3,4
tSIK3,4
tKSI3,4
SB0, SB1
tKSO3,4
SBI mode (Command signal transfer):
tKCY3,4
tKL3,4
tKH3,4
tR4
tF4
SCK
tKSB
tSBK
SB0, SB1
tKSO3,4
44
µPD78001B(A), 78002B(A)
2-wire serial I/O mode:
tKCY5,6
tKL5,6
tKH5,6
tR6
tF6
SCK
tSIK5,6
tKSI5,6
tKSO5,6
SB0, SB1
45
µPD78001B(A), 78002B(A)
Data Memory Stop Mode Low Supply Voltage Data Retention Characteristics (TA = –40 to +85 °C)
Parameter
Symbol
Test Conditions
MIN.
TYP.
MAX.
Unit
6.0
V
10
µA
Data retention
VDDDR
2.0
supply voltage
Data retention
supply
current
IDDDR
Release signal set time
tSREL
Oscillation stabilization
VDDDR = 2.0 V
Subsystem clock stop and
feed-back resister disconnected
0.1
µs
0
Release by RESET
218/fx
µs
*
µs
tWAIT
wait time
Release by interrupt
* In combination with bits 0 to 2 (OSTS0 to OSTS2) of oscillation stabilization time select register, selection of 213/fx and 215/fx
to 218/fx is possible.
Data Retention Timing (STOP Mode Release by RESET)
HALT Mode
Operating Mode
STOP Mode
Data Retension Mode
VDD
VDDDR
tSREL
STOP Instruction Execution
Standby Release Signal
(Interrupt Request)
tWAIT
Data Retention Timing (Standby Release Signal: STOP Mode Release by Interrupt Signal)
Internal Reset Operation
HALT Mode
Operating Mode
STOP Mode
Data Retension Mode
VDD
VDDDR
tSREL
STOP Instruction Execution
RESET
tWAIT
46
µPD78001B(A), 78002B(A)
Interrupt Input Timing
tINTL
tINTH
INTP0-INTP2
tINTL
INTP3
RESET Input Timing
tRSL
RESET
47
µPD78001B(A), 78002B(A)
12. CHARACTERISTIC CURVE (REFERENCE VALUES)
IDD vs VDD (Main System Clock : 8.38 MHz)
(TA=25°C)
10.0
PCC=00H
PCC=01H
5.0
PCC=02H
PCC=03H
PCC=04H
PCC=30H
HALT (X1 Oscillation,
XT1 Oscillation)
1.0
Supply Current IDD [mA]
0.5
0.1
PCC=B0H
0.05
HALT (X1 Stop,
XT1 Oscillation)
STOP (X1 Stop,
XT1 Oscillation)
0.01
f X =8.38MHz
f XT=32.768kHz
0.005
0.001
0
2
3
4
5
Supply Voltage VDD [V]
48
6
7
8
µPD78001B(A), 78002B(A)
IDD vs VDD (Main System Clock : 4.19 MHz)
(TA=25°C)
10.0
5.0
PCC=00H
PCC=01H
PCC=02H
PCC=03H
PCC=04H
PCC=30H
HALT (X1 Oscillation,
XT1 Oscillation)
1.0
Supply Current IDD [mA]
0.5
0.1
PCC=B0H
0.05
HALT (X1 Stop,
XT1 Oscillation)
STOP (X1 Stop,
XT1 Oscillation)
0.01
f X =4.19MHz
f XT=32.768kHz
0.005
0.001
0
2
3
4
5
6
7
8
Supply Voltage VDD [V]
49
µPD78001B(A), 78002B(A)
IDD vs fX
(VDD = 3 V, TA = 25 °C)
5
Supply Current IDD [mA]
PCC=00H
4
3
PCC=01H
2
PCC=02H
PCC=03H
PCC=04H
HALT
(X1 Oscillation)
1
0
0
1
2
3
4
5
6
7
8
9
10
11
12
Clock Oscillator Frequency fX [MHz]
IDD vs fX
(VDD = 5 V, TA = 25 °C)
12
11
10
9
Supply Current IDD [mA]
PCC=00H
8
7
6
PCC=01H
5
4
PCC=02H
PCC=03H
PCC=04H
HALT
(X1 Oscillation)
3
2
1
0
0
1
2
3
4
5
6
7
8
9
Clock Oscillator Frequency fX [MHz]
50
10
11
12
µPD78001B(A), 78002B(A)
VOL vs IOL (Port 0, 2 to 5, P64 to P67)
VOL vs IOL (P60 to P63)
(TA=25 °C)
(TA=25 °C)
VDD=5 V
VDD= 6 V VDD=4 V VDD=3 V
20
10
0
VDD=6 V
30
Output Current Low IOL [mA]
Output Current Low IOL [mA]
30
0
0.5
VDD=5 V
VDD=4 V
VDD=3 V
20
10
1.0
Output Voltage Low VOL [V]
0
0
0.5
1.0
Output Voltage Low VOL [V]
VOL vs IOL (Port 1)
VOH vs IOH (Port 0 to 5, P64 to P67)
(TA=25 °C)
(TA=25 °C)
Output Current Low IOL [mA]
VDD=4 V
VDD=3 V
20
10
Output Current High IOH [mA]
VDD=6 V VDD=5 V
30
VDD=5 V VDD=4 V
-10
VDD=6 V
VDD=3 V
-5
0
0
0
0
0.5
0.5
1.0
1.0
Output Voltage Low VOL [V]
Output Voltage High VDD – VOH [V]
51
µPD78001B(A), 78002B(A)
13. PACKAGE DRAWINGS
DRAWINGS OF MASS-PRODUCTION PRODUCT PACKAGES (1/2)
64-PIN PLASTIC SHRINK DIP (750 mil)
64
33
1
32
A
K
F
D
H
G
J
I
L
N
M
NOTE
B
C
M
R
ITEM
MILLIMETERS
INCHES
1) Each lead centerline is located within 0.17 mm (0.007 inch) of
its true position (T.P.) at maximum material condition.
A
58.68 MAX.
2.311 MAX.
B
1.78 MAX.
0.070 MAX.
2) Item "K" to center of leads when formed parallel.
C
1.778 (T.P.)
0.070 (T.P.)
D
0.50±0.10
0.020 +0.004
–0.005
F
0.9 MIN.
0.035 MIN.
G
3.2±0.3
0.126±0.012
H
0.51 MIN.
0.020 MIN.
I
4.31 MAX.
0.170 MAX.
J
5.08 MAX.
0.200 MAX.
K
19.05 (T.P.)
0.750 (T.P.)
L
17.0
0.669
M
0.25 +0.10
–0.05
0.010 +0.004
–0.003
N
0.17
0.007
R
0~15°
0~15°
P64C-70-750A,C-1
Caution
Dimensions and materials of ES products are different from those of mass-production products. Refer
to DRAWINGS OF ES PRODUCT PACKAGES (1/2).
52
µPD78001B(A), 78002B(A)
DRAWINGS OF MASS-PRODUCTION PRODUCT PACKAGES (2/2)
64-PIN PLASTIC QFP (■
■ 14)
A
B
48
49
33
32
F
Q
5°±5°
S
D
C
detail of lead end
64
1
G
17
16
H
I M
J
M
P
K
N
L
P64GC-80-AB8-3
NOTE
Each lead centerline is located within 0.15
mm (0.006 inch) of its true position (T.P.) at
maximum material condition.
Caution
ITEM
MILLIMETERS
INCHES
A
17.6 ± 0.4
0.693 ± 0.016
B
14.0 ± 0.2
0.551+0.009
–0.008
C
14.0 ± 0.2
0.551+0.009
–0.008
D
17.6 ± 0.4
0.693 ± 0.016
F
1.0
0.039
G
1.0
0.039
H
0.35 ± 0.10
0.014 +0.004
–0.005
I
0.15
0.006
J
0.8 (T.P.)
0.031 (T.P.)
K
1.8 ± 0.2
0.071 ± 0.008
L
0.8 ± 0.2
0.031+0.009
–0.008
M
0.15+0.10
–0.05
0.006+0.004
–0.003
N
0.10
0.004
P
2.55
0.100
Q
0.1 ± 0.1
0.004 ± 0.004
S
2.85 MAX.
0.112 MAX.
Dimensions and materials are different from those of mass-production products. Refer to DRAWINGS
OF ES PRODUCT PACKAGES (2/2).
53
µPD78001B(A), 78002B(A)
DRAWINGS OF ES PRODUCT PACKAGES (1/2)
64PIN CERAMIC SHRINK DIP (SEAM WELD) (750 mil)
64
33
1
32
K
A
H
G
J
I
L
F
D
B
N M
M
C
0~15°
P64D-70-750A1
NOTES
1) Each lead centerline is located within 0.25
mm (0.01 inch) of its true position (T.P.) at
maximum material condition.
2)
54
Item "K" to center of leads when formed
parallel.
ITEM
MILLIMETERS
INCHES
A
58.16 MAX.
2.290 MAX.
B
1.521 MAX.
0.060 MAX.
C
1.778 (T.P.)
0.070 (T.P.)
D
0.46 ± 0.05
0.018 ± 0.002
F
0.8 MIN.
0.031 MIN.
G
3.5 ± 0.3
0.138 ± 0.012
H
1.02 MIN.
0.040 MIN.
I
3.14
0.124
J
5.08 MAX.
0.200 MAX.
K
19.05 (T.P.)
0.750 (T.P.)
L
18.8
0.740
M
0.25 ± 0.05
0.010 –0.003
N
0.25
0.01
+0.002
µPD78001B(A), 78002B(A)
DRAWINGS OF ES PRODUCT PACKAGES (2/2)
64 PIN CERAMIC QFP (14 × 14) (FOR ES)
A
33
32
64
1
17
16
F
C
48
49
G
H
D
B
J
T
(Bottom View)
U
V
M
Q
K
ITEM
MILLIMETERS
X64B-80A-1
INCHES
A
22.0 ± 0.4
0.866 ± 0.016
B
14.0
0.551
C
14.0
0.551
D
22.0 ± 0.4
0.866 ± 0.016
F
1.0
0.039
G
1.0
0.039
H
0.32
0.013
J
0.8 (T.P.)
0.031 (T.P.)
K
4.0 ± 0.15
0.157+0.007
–0.006
M
0.25
0.01
Q
3.0 MAX.
0.119 MAX.
T
0.55
0.022
U
1.0
0.039
V
1.2
0.047
55
µPD78001B(A), 78002B(A)
14. RECOMMENDED SOLDERING CONDITIONS
The µPD78001B(A)/78002B(A) should be soldered and mounted under the conditions recommended in the table
below.
For detail of recommended soldering conditions, refer to the information document “Semiconductor Device
Mounting Technology Manual” (IEI-1207).
For soldering methods and conditions other than those recommended below, contact our sales personnel.
Table 14-1 Surface Mounting Type Soldering Conditions
µPD78001BGC(A)-×××-AB8 :
µPD78002BGC(A)-×××-AB8 :
64-Pin Plastic QFP (■
■ 14 mm)
64-Pin Plastic QFP (■
■ 14 mm)
Soldering
Method
Infrared reflow
Soldering Conditions
Package peak temperature: 235°C, Duration: 30 sec. max. (at 210°C or above),
Number of times: Twice max.
Recommended
Condition Symbol
IR35-00-2
< Points to note >
(1) Start the second reflow after the device temprature by the first reflow returns to normal.
(2) Flux washing by the water after the first reflow should be avoided.
VPS
Package peak temperature: 215°C, Duration: 40 sec. max. (at 200°C or above)
Number of times: Twice max.
VP15-00-2
< Points to note >
(1) Start the second reflow after the device temprature by the first reflow returns to normal.
(2) Flux washing by the water after the first reflow should be avoided.
Pin part heating Pin temperature: 300°C max., Duration: 3 sec. max. (per device side)
Caution
—
Use of more than one soldering method should be avoided (except in the case of pin part heating).
Table 14-2 Insertion Type Soldering Conditions
µPD78001BCW(A)-××× :
µPD78002BCW(A)-××× :
Soldering Method
Soldering Conditions
Wave soldering
(Pin only)
Solder bath temperature: 260°C max., Duration: 10 sec. max.
Pin part heating
Pin temperature: 300°C max., Duration: 3 sec. max. (per pin)
Caution
Wave soldering is only for the pins in order that jet solder can not contact with the chip
directly.
56
64-Pin Plastic Shrink DIP (750 mil)
64-Pin Plastic Shrink DIP (750 mil)
µPD78001B(A), 78002B(A)
APPENDIX A. DEVEROPMENT TOOLS
The following development tools are available for system development using the µPD78001B(A), 78002B(A).
Language Processing Software
RA78K/0*1, 2, 3
78K/0 series common assembler package
CC78K/0*1, 2, 3
78K/0 series common C compiler package
DF78002*1, 2, 3
µPD78002 subseries device file
*1, 2, 3
CC78K/0-L
78K/0 series common C compiler library source file
PROM Programming Tools
PG-1500
PROM programmer
PA-78P014CW
PA-78P014GC
Programmer adapter connected to PG-1500
PG-1500 controller*1, 2
PG-1500 control program
Debugging Tools
IE-78000-R
78K/0 series common in-circuit emulator
IE-78000-R-BK
78K/0 series common break board
IE-78014-R-EM
µPD78002/78014 subseries evaluation emulation board
EP-78240CW-R
EP-78240GC-R
Emulation probe common to µPD78244 subseries
EV-9200GC-64
Socket to be mounted on user system board created for the 64-pin plastic QFP
SD78K/0*1, 2
IE-78000-R screen debugger
SM78K/0
*4, 5, 6
78K/0 series common system simulator
µPD78002 subseries device file
*1, 2, 4, 5
DF78002
Enbedded OS
MX78K/0*1, 2, 3, 6
78K/0 series common enbedded OS
Fuzzy Inference Development Support System
FE9000*1/FE9200*5
*1
*2
Fuzzy knowledge data creation tool
FT9080 /FT9085
Translator
FI78K0*1, 2
Fuzzy inference module
FD78K0*1, 2
Fuzzy inference debugger
* 1. PC-9800 series (MS-DOSTM) based.
2. IBM PC/ATTM (PC DOSTM) based.
3. HP9000 series 300TM, HP9000 series 700TM (HP-UXTM) based, SPARCstationTM, (Sun OSTM) based, EWS-4800
series (EWS-UX/V) based.
4. PC-9800 series (MS-DOS + WindowsTM) based.
57
µPD78001B(A), 78002B(A)
5. IBM PC/AT (PC DOS + Windows) based.
6. Under development.
Remarks 1. For development tools manufactured by a third party, see the "78K/0 Series Selection Guide" (IF1185).
2. RA78K/0, CC78K/0, SD78K/0, and SM78K/0 are used in combination with DF78002.
58
µPD78001B(A), 78002B(A)
APPENDIX B. RELATED DOCUMENTS
Device Related Documents
Document Name
Document No. (Japanese)
Document No. (Engligh)
User's Manual
IEU-788
IEU-1334
78K/0 Series User's Manual - Instruction
IEU-849
IEU-1372
Basic I
IEA-715
IEA-1288
Basic II
IEA-740
IEA-1299
Document No. (Japanese)
Document No. (Engligh)
Operation
EEU-809
EEU-1399
Language
EEU-815
EEU-1404
EEU-817
EEU-1402
Operation
EEU-656
EEU-1280
Language
EEU-655
EEU-1284
PG-1500 PROM Programmer
EEU-651
EEU-1335
PG-1500 Controller
EEU-704
EEU-1291
IE-78000-R
EEU-810
EEU-1398
IE-78000-R-BK
EEU-867
EEU-1427
IE-78014-R-EM
EEU-805
EEU-1400
EP-78240
EEU-986
In preparation
Beginner's guide
EEU-852
EEU-1414
Reference
EEU-816
EEU-1413
Document No. (Japanese)
Document No. (Engligh)
Fuzzy Knowledge Data Creation Tool
EEU-892
EEU-1438
78K/0, 78K/II, 87AD Series
Fuzzy Inference Development Support System - Translator
EEU-862
EEU-1444
Application Note
Development Tools Documents (User's Manual)
Document Name
RA78K Series Assembler Package
RA78K Series Structured Assembler Preprocessor
CC78K Series C Compiler
SD78K/0 Screen Debugger
Embedded Software Documents (User's Manual)
Document Name
Caution
These documents above are subject to change without notice. Besure to use the latest document for
designing your system.
59
µPD78001B(A), 78002B(A)
Other Documents
Document Name
Document No. (Japanese)
Document No. (Engligh)
Package Manual
IEI-635
IEI-1213
Semiconductor Device Mounting Technology Manual
IEI-616
IEI-1207
Quality Grade on NEC Semiconductor Devices
IEI-620
IEI-1209
MEI-603
MEI-1202
Semiconductor Device Quality Guarantee Guide
Caution
60
These documents above are subject to change without notice. Besure to use the latest document for
designing your system.
µPD78001B(A), 78002B(A)
NOTES FOR CMOS DEVICES
1 PRECAUTION AGAINST ESD FOR SEMICONDUCTORS
Note: Strong electric field, when exposed to a MOS device, can cause destruction of
the gate oxide and ultimately degrade the device operation. Steps must be
taken to stop generation of static electricity as much as possible, and quickly
dissipate it once, when it has occurred.
Environmental control must be
adequate. When it is dry, humidifier should be used. It is recommended to
avoid using insulators that easily build static electricity.
Semiconductor
devices must be stored and transported in an anti-static container, static
shielding bag or conductive material. All test and measurement tools including
work bench and floor should be grounded. The operator should be grounded
using wrist strap. Semiconductor devices must not be touched with bare
hands. Similar precautions need to be taken for PW boards with semiconductor
devices on it.
2 HANDLING OF UNUSED INPUT PINS FOR CMOS
Note: No connection for CMOS device inputs can be cause of malfunction. If no
connection is provided to the input pins, it is possible that an internal input
level may be generated due to noise, etc., hence causing malfunction. CMOS
device behave differently than Bipolar or NMOS devices. Input levels of CMOS
devices must be fixed high or low by using a pull-up or pull-down circuitry. Each
unused pin should be connected to VDD or GND with a resistor, if it is considered
to have a possibility of being an output pin. All handling related to the unused
pins must be judged device by device and related specifications governing the
devices.
3 STATUS BEFORE INITIALIZATION OF MOS DEVICES
Note: Power-on does not necessarily define initial status of MOS device. Production
process of MOS does not define the initial operation status of the device.
Immediately after the power source is turned ON, the devices with reset
function have not yet been initialized. Hence, power-on does not guarantee
out-pin levels, I/O settings or contents of registers. Device is not initialized
until the reset signal is received. Reset operation must be executed immediately after power-on for devices having reset function.
61
µPD78001B(A), 78002B(A)
[MEMO]
The export of this product from Japan is regulated by the Japanese government. To export this product may be
prohibited without governmental license, the need for which must be judged by the customer. The export or reexport of this product from a country other than Japan may also be prohibited without a license from that country.
Please call an NEC sales representative.
No part of this document may be copied or reproduced in any form or by any means without the prior written
consent of NEC Corporation. NEC Corporation assumes no responsibility for any errors which may appear in this
document.
NEC Corporation does not assume any liability for infringement of patents, copyrights or other intellectual
property rights of third parties by or arising from use of a device described herein or any other liability arising
from use of such device. No license, either express, implied or otherwise, is granted under any patents,
copyrights or other intellectual property rights of NEC Corporation or others.
While NEC Corporation has been making continuous effort to enhance the reliability of its semiconductor devices,
the possibility of defects cannot be eliminated entirely. To minimize risks of damage or injury to persons or
property arising from a defect in an NEC semiconductor device, customer must incorporate sufficient safety
measures in its design, such as redundancy, fire-containment, and anti-failure features.
NEC devices are classified into the following three quality grades:
“Standard“, “Special“, and “Specific“. The Specific quality grade applies only to devices developed based on
a customer designated “quality assurance program“ for a specific application. The recommended applications
of a device depend on its quality grade, as indicated below. Customers must check the quality grade of each
device before using it in a particular application.
Standard: Computers, office equipment, communications equipment, test and measurement equipment,
audio and visual equipment, home electronic appliances, machine tools, personal electronic
equipment and industrial robots
Special: Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster
systems, anti-crime systems, safety equipment and medical equipment (not specifically designed
for life support)
Specific: Aircrafts, aerospace equipment, submersible repeaters, nuclear reactor control systems, life
support systems or medical equipment for life support, etc.
The quality grade of NEC devices in “Standard“ unless otherwise specified in NEC's Data Sheets or Data Books.
If customers intend to use NEC devices for applications other than those specified for Standard quality grade,
they should contact NEC Sales Representative in advance.
Anti-radioactive design is not implemented in this product.
FIP is a registered trademark of NEC Corporation.
M4 94.11
IEBus is a trademark of NEC Corporation.
MS-DOS and Windows are trademarks of Microsoft Corporation.
PC/AT and PC DOS are trademarks of IBM Corporation.
HP9000 Series 300, HP9000 Series 700, and HP-UX are trademarks of Hewlett-Packard Company.
SPARCstation is a trademark of SPARC International, Inc.
SunOS is a trademark of Sun Microsystems, Inc.