DATA SHEET MOS INTEGRATED CIRCUIT m PD784020, 784021 16/8-BIT SINGLE-CHIP MICROCOMPUTER The mPD784021 is a product of the m PD784026 sub-series in the 78K/IV series. It contains various peripheral hardware such as RAM, I/O ports, 8-bit resolution A/D and D/A converters, timers, serial interface, and interrupt functions, as well as a high-speed, high-performance CPU. The m PD784021 is a ROM-less product of the m PD784025 or mPD784026. The mPD784020 differs from the mPD784021 only in its RAM size: 512 bytes are allocated for the mPD784020, while 2048 bytes are allocated for the mPD784021. For specific functions and other detailed information, consult the following user’s manual. This manual is required reading for design work. mPD784026 Sub-Series User’s Manual, Hardware : U10898E 78K/IV Series User’s Manual, Instruction : U10905E FEATURES • 78K/IV series • Pin-compatible with the mPD78234 sub-series • Minimum instruction execution time: 160 ns (at 25 MHz) • Number of I/O ports: 46 • Timer/counters: 16-bit timer/counter ¥ 3 units 16-bit timer ¥ 1 unit • Serial interface: 3 channels UART/IOE (3-wire serial I/O) • PWM outputs: 2 • Standby function HALT/STOP/IDLE mode • • • • • Clock frequency division function Watchdog timer : 1 channel A/D converter : 8-bit resolution ¥ 8 channels D/A converter : 8-bit resolution ¥ 2 channels Supply voltage : VDD = 2.7 to 5.5 V :2 channels CSI (3-wire serial I/O, SBI) : 1 channel APPLICATIONS LBP, automatic-focusing camera, PPC, printer, electronic typewriter, air conditioner, electronic musical instruments, cellular telephone, etc. This manual describes the mPD784021 unless otherwise specified. The information in this document is subject to change without notice. Document No. U11514EJ1V0DS00 (1st edition) (Previous No. IP-3234) Date Published July 1996 P Printed in Japan The mark H shows major revised points. © 1990 1996 m PD784020, 784021 ORDERING INFORMATION Part number H Package Internal ROM Internal RAM (bytes) (bytes) mPD784020GC-3B9 80-pin plastic QFP (14 ¥ 14 mm) None 512 mPD784021GC-3B9 80-pin plastic QFP (14 ¥ 14 mm) None 2048 H mPD784021GK-BE9 80-pin plastic TQFP (fine pitch) (12 ¥ 12 mm) None 2048 H 78K/IV SERIES PRODUCT DEVELOPMENT DIAGRAM : Product under mass production : Product under development : Product under planning Standard Products Development µ PD784038Y sub-series Product containing for an I2C bus interface circuit µ PD784038 sub-series 80-pin, 8-bit A/D, 8-bit D/A ROM: 48K/64K/96K/128K µPD784216Y sub-series Product containing for two I2C bus interface circuits µ PD784026 sub-series 80-pin, 8-bit A/D, 8-bit D/A ROM: none/48K/64K µ PD784216 sub-series 100-pin, 8-bit A/D, 8-bit D/A ROM: 96K/128K µPD784054 80-pin, 10-bit A/D ROM: 32K µPD784046 sub-series sub-set µ PD784046 sub-series 80-pin, 10-bit A/D ROM: 32K/64K ASSP Development µ PD784915 sub-series VTR servo, 100-pin, built-in analog amplifier ROM: 48K/62K 2 µ PD784908 sub-series 100-pin, built-in IEBusTM ROM: 96K/128K µ PD784943 sub-series 80-pin, for CD-ROM ROM: 56K m PD784020, 784021 FUNCTIONS Product mPD784020 Item mPD784021 Number of basic instructions (mnemonics) 113 General-purpose register 8 bits ¥ 16 registers ¥ 8 banks, or 16 bits ¥ 8 registers ¥ 8 banks (memory mapping) Minimum instruction execution time 160 ns/320 ns/640 ns/1280 ns (at 25 MHz) Internal memory ROM None RAM 512 bytes Memory space I/O ports Additional function pinsNote 2048 bytes Program and data: 1M byte Total 46 Input 8 Input/output 34 Output 4 Pins with pull- 32 up resistor LED direct drive outputs 8 Transistor direct drive 8 Real-time output ports 4 bits ¥ 2, or 8 bits ¥ 1 Timer/counter Timer/counter 0: (16 bits) Timer register ¥ 1 Capture register ¥ 1 Compare register ¥ 2 Pulse output capability Ý Toggle output Ý PWM/PPG output Ý One-shot pulse output Timer/counter 1: (8/16 bits) Timer register ¥ 1 Capture register ¥ 1 Capture/compare register ¥ 1 Compare register ¥ 1 Pulse output capability Ý Real-time output (4 bits ¥ 2) Timer/counter 2: (8/16 bits) Timer register ¥ 1 Capture register ¥ 1 Capture/compare register ¥ 1 Compare register ¥ 1 Pulse output capability Ý Toggle output Ý PWM/PPG output Timer 3 (8/16 bits) Timer register ¥ 1 Compare register ¥ 1 : PWM outputs 12-bit resolution ¥ 2 channels Serial interface UART/IOE (3-wire serial I/O) : 2 channels (incorporating baud rate generator) CSI (3-wire serial I/O, SBI) : 1 channel A/D converter 8-bit resolution ¥ 8 channels D/A converter 8-bit resolution ¥ 2 channels Watchdog timer 1 channel Standby HALT/STOP/IDLE mode Interrupt Source 23 (16 internal, 7 external (sampling clock variable input: 1)) + BRK instruction Software BRK instruction Nonmaskable 1 internal, 1 external Maskable 15 internal, 6 external Ý 4-level programmable priority Ý 3 operation statuses: vectored interrupt, macro service, context switching Supply voltage VDD = 2.7 to 5.5 V H Package 80-pin plastic QFP (14 ¥ 14 mm) 80-pin plastic TQFP (fine pitch) (12 ¥ 12 mm): for the mPD784021 only H Note Additional function pins are included in the I/O pins. 3 m PD784020, 784021 CONTENTS 1. DIFFERENCES BETWEEN mPD784026 SUB-SERIES ........................................................... 6 2. MAIN DIFFERENCES BETWEEN mPD784026 AND mPD78234 SUB-SERIES ..................... 7 3. PIN CONFIGURATION (TOP VIEW) ........................................................................................ 8 4. SYSTEM CONFIGURATION EXAMPLE (PPC) ....................................................................... 10 5. BLOCK DIAGRAM ..................................................................................................................... 11 6. LIST OF PIN FUNCTIONS ........................................................................................................ 12 7. 6.1 PORT PINS ...................................................................................................................................... 12 6.2 NON-PORT PINS ............................................................................................................................ 13 6.3 I/O CIRCUITS FOR PINS AND HANDLING OF UNUSED PINS ................................................. 15 CPU ARCHITECTURE .............................................................................................................. 18 7.1 MEMORY SPACE ........................................................................................................................... 18 7.2 8. 9. 4 CPU REGISTERS ............................................................................................................................ 21 7.2.1 General-Purpose Registers .......................................................................................... 21 7.2.2 Control Registers ........................................................................................................... 22 7.2.3 Special Function Registers (SFRs) ............................................................................. 23 PERIPHERAL HARDWARE FUNCTIONS ............................................................................... 28 8.1 PORTS ............................................................................................................................................. 28 8.2 CLOCK GENERATOR .................................................................................................................... 29 8.3 REAL-TIME OUTPUT PORT .......................................................................................................... 31 8.4 TIMERS/COUNTERS ...................................................................................................................... 32 8.5 PWM OUTPUT (PWM0, PWM1) ..................................................................................................... 34 8.6 A/D CONVERTER ........................................................................................................................... 35 8.7 D/A CONVERTER ........................................................................................................................... 36 8.8 SERIAL INTERFACE ...................................................................................................................... 37 8.8.1 Asynchronous Serial Interface/Three-Wire Serial I/O (UART/IOE) ......................... 38 8.8.2 Synchronous Serial Interface (CSI) ............................................................................. 40 8.9 EDGE DETECTION FUNCTION ..................................................................................................... 41 8.10 WATCHDOG TIMER ....................................................................................................................... 42 INTERRUPT FUNCTION ........................................................................................................... 43 9.1 INTERRUPT SOURCE .................................................................................................................... 43 9.2 VECTORED INTERRUPT ............................................................................................................... 45 9.3 CONTEXT SWITCHING .................................................................................................................. 46 9.4 MACRO SERVICE ........................................................................................................................... 46 9.5 EXAMPLES OF MACRO SERVICE APPLICATIONS .................................................................. 47 m PD784020, 784021 10. LOCAL BUS INTERFACE ......................................................................................................... 49 10.1 MEMORY EXPANSION .................................................................................................................. 49 10.2 MEMORY SPACE ........................................................................................................................... 50 10.3 PROGRAMMABLE WAIT ............................................................................................................... 51 10.4 PSEUDO-STATIC RAM REFRESH FUNCTION ........................................................................... 51 10.5 BUS HOLD FUNCTION .................................................................................................................. 51 11. STANDBY FUNCTION .............................................................................................................. 52 12. RESET FUNCTION .................................................................................................................... 53 13. INSTRUCTION SET ................................................................................................................... 54 14. ELECTRICAL CHARACTERISTICS ......................................................................................... 59 15. PACKAGE DRAWINGS ............................................................................................................ 80 16. RECOMMENDED SOLDERING CONDITIONS ........................................................................ 82 APPENDIX A DEVELOPMENT TOOLS ........................................................................................ 83 APPENDIX B RELATED DOCUMENTS ....................................................................................... 85 5 H H m PD784020, 784021 H 1. DIFFERENCES BETWEEN m PD784026 SUB-SERIES The only difference between the mPD784020, mPD784021, mPD784025, and mPD784026 is their capacity of internal memory, port functions, and part of their packages. The mPD78P4026 is produced by replacing the masked ROM in the mPD784025 or m PD784026 with 64K-byte onetime PROM or EPROM. Table 1-1 shows the differences between these products. Table 1-1 Differences between the mPD784026 Sub-Series Product Item mPD784020 mPD784021 mPD784025 mPD784026 mPD78P4026 48K bytes (masked ROM) 64K bytes (masked ROM) 64K bytes (one-time PROM or EPROM) Internal ROM None Internal RAM 512 bytes P40-P47 Functions only as an address/data bus Can be switched to a general-purpose port or address/data bus, by using software P50-P57 Functions only as an address bus P60-P63 Can be switched to an output-only port or address bus in units of 2 bits, by using software Can be switched to a general-purpose port or address bus in units of 2 bits, by using software P64, P65 Functions only as the RD or WR pin Functions as the RD or WR pin when the local bus interface is used. Functions as a general-purpose port in other cases. Package 80-pin plastic QFP (14 ¥ 14 mm) 80-pin plastic QFP (14 ¥ 14 mm) 2048 bytes 80-pin plastic QFP (14 ¥ 14 mm) 80-pin plastic TQFP (fine pitch) (12 ¥ 12 mm) 6 80-pin plastic QFP (14 ¥ 14 mm) 80-pin ceramic WQFN (14 ¥ 14 mm) m PD784020, 784021 2. MAIN DIFFERENCES BETWEEN m PD784026 AND mPD78234 SUB-SERIES Series mPD784026 sub-series Item mPD78234 sub-series Number of basic instructions (mnemonics) 113 65 Minimum instruction execution time 160 ns (at 25 MHz) 333 ns (at 12 MHz) Memory space (program/data) 1M byte in total 64K bytes/1M byte Timer/counter 16-bit timer/counter ¥ 1 8/16-bit timer/counter ¥ 2 8/16-bit timer ¥ 1 16-bit timer/counter ¥ 1 8-bit timer/counter ¥ 2 8-bit timer ¥ 1 Clock output function Available Unavailable Watchdog timer Available Unavailable Serial interface UART/IOE (3-wire serial I/O) ¥ 2 channels CSI (3-wire serial I/O, SBI) ¥ 1 channel UART ¥ 1 channel CSI (3-wire serial I/O, SBI) ¥ 1 channel Interrupt Context switching Available Unavailable Priority 4 levels 2 levels Standby function 3 modes (HALT, STOP, IDLE) 2 modes (HALT, STOP) Operation clock switching Selectable from fXX/2, fXX /4, fXX/8, or f XX /16 Fixed to f XX/2 Pin functions MODE pin Unavailable To specify ROM-less mode (always in the high level for the mPD78233 or mPD78237) TEST pin Pin for testing the device Low level during ordinary use Unavailable 80-pin plastic QFP (14 ¥ 14 mm) 80-pin plastic TQFP (fine pitch) (12 ¥ 12 mm): for the mPD784021 only 80-pin ceramic WQFN (14 ¥ 14 mm): for the mPD78P4026 only 80-pin plastic QFP (14 ¥ 14 mm) 94-pin plastic QFP (20 ¥ 20 mm) Package 84-pin plastic QFJ (1150 ¥ 1150 mil) 94-pin ceramic WQFN (20 ¥ 20 mm): for the mPD78P238 only 7 m PD784020, 784021 3. PIN CONFIGURATION (TOP VIEW) • 80-pin plastic QFP (14 ¥ 14 mm) H mPD784020GC-3B9, mPD784021GC-3B9 • 80-pin plastic TQFP (fine pitch) (12 ¥ 12 mm) H 8 P75/ANI5 P76/ANI6 P77/ANI7 AVREF1 AVDD AVSS ANO0 ANO1 AVREF3 AVREF2 P20/NMI P21/INTP0 P22/INTP1 P23/INTP2/CI P24/INTP3 P25/INTP4/ASCK/SCK1 P26/INTP5 P27/SI0 Note Connect the TEST pin to VSS directly. AD3 AD4 AD5 AD6 AD7 A8 A9 A10 A11 A12 A13 A14 A15 P60/A16 P61/A17 P62/A18 P63/A19 RD WR 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 1 60 2 59 3 58 4 57 5 56 6 55 7 54 8 53 9 52 10 51 11 50 12 49 13 48 14 47 15 46 16 45 17 44 18 43 19 42 20 41 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 P66/WAIT/HLDRQ P32/SCK0 P33/SO0/SB0 P34/ TO0 P35/ TO1 P36/ TO2 P37/ TO3 RESET VDD X2 X1 VSS P00 P01 P02 P03 P04 P05 P06 P07 P67/REFRQ/HLDAK P30/RxD/SI1 P31/TxD/SO1 mPD784021GK-BE9 P74/ANI4 P73/ANI3 P72/ANI2 P71/ANI1 P70/ANI0 VDD P17 P16 P15 P14/TXD2/SO2 P13/RXD2/SI2 P12/ASCK2/SCK2 P11/PWM1 P10/PWM0 TESTNote VSS ASTB AD0 AD1 AD2 m PD784020, 784021 P00-P07 : Port 0 A8-A19 : Address bus P10-P17 : Port 1 RD : Read strobe P20-P27 : Port 2 WR : Write strobe P30-P37 : Port 3 WAIT : Wait P60-P63, P66, P67 : Port 6 HLDRQ : Hold request P70-P77 : Port 7 HLDAK : Hold acknowledge TO0-TO3 : Timer output ASTB : Address strobe CI : Clock input REFRQ : Refresh request RxD, RxD2 : Receive data RESET : Reset TxD, TxD2 : Transmit data X1, X2 : Crystal SCK0-SCK2 : Serial clock ANI0-ANI7 : Analog input ASCK, ASCK2 : Asynchronous serial clock ANO0, ANO1 : Analog output SI0-SI2 : Serial input AVREF1-AVREF3 : Reference voltage SO0-SO2 : Serial output AVDD : Analog power supply SB0 : Serial bus AV SS : Analog ground PWM0, PWM1 : Pulse width modulation output VDD : Power supply NMI : Non-maskable interrupt VSS : Ground INTP0-INTP5 : Interrupt from peripherals TEST : Test AD0-AD7 : Address/data bus 9 m PD784020, 784021 4. SYSTEM CONFIGURATION EXAMPLE (PPC) µ PD784021 Serial communication P11 RxD TxD µ PD27C1001A OE RD CE A17 A8-A16 Sensing paper Sensing paper feed P16 P17 Sensing paper ejection Sensing the position of the scanner station SCK1 SI1 SO1 Operator panel P04 P06 High-voltage control circuit Drum, toner, and charge for transfer P07 Fusing heater control circuit Fusing roller P66 Lamp regulator A8-A16 µ PD74HC573 Latch O0-O7 P15 A0-A7 AD0-AD7 ASTB Sensing paper transport INTP0 Temperature of the fusing heater ANI0 (DC stepping motor) PWM0 Brightness of the lamp Lever for adjusting the tone of the copy ANI1 M P00-P03 Clutch for stopping the scanner station SL Clutch for forwarding the scanner station SL Clutch for the resist shutter SL Clutch for manual feeding SL Clutch for cassette feeding P33 ANI3 Driver P35 P36 Reset circuit 10 RESET P37 Main motor SL ANI2 P34 Lever for compensating the tone of the copy Lamp for lighting the original Lamp for discharging Solenoid m PD784020, 784021 5. BLOCK DIAGRAM NMI INTP0-INTP5 INTP3 TO0 TO1 INTP0 INTP1 INTP2/CI TO2 TO3 UART/IOE2 Programmable interrupt controller Baud-rate generator UART/IOE1 Timer/counter 0 (16 bits) Baud-rate generator RxD/SI1 TxD/SO1 ASCK/SCK1 RxD2/SI2 TxD2/SO2 ASCK2/SCK2 SCK0 Timer/counter 1 (16 bits) Clocked serial interface SO0/SB0 SI0 Timer/counter 2 (16 bits) ASTB 78K /IV CPU core AD0-AD7 A8-A15 Bus interface Timer 3 (16 bits) P00-P03 Real-time output port A16-A19 RD WR WAIT/HLDRQ REFRQ/HLDAK Port 0 P00-P07 Port 1 P10-P17 Port 2 P20-P27 Port 3 P30-P37 P04-P07 RAM PWM0 PWM PWM1 ANO0 ANO1 AVREF2 AVREF3 P60-P63 D /A converter Port 6 Port 7 ANI0-ANI7 AVDD AVREF1 System control A /D converter AVSS INTP5 Watchdog timer P60, P67 P70-P77 RESET TEST X1 X2 VDD VSS Remark The internal ROM or RAM capacity differs for each product. 11 m PD784020, 784021 6. LIST OF PIN FUNCTIONS 6.1 PORT PINS Pin I/O Dual-function P00-P07 I/O — Function Port 0 (P0): Ý 8-bit I/O port Ý Functions as a real-time output port (4 bits ¥ 2). Ý Inputs and outputs can be specified bit by bit. Ý The use of the pull-up resistors can be specified by software for the pins in the input mode together. Ý Can drive a transistor. P10 I/O PWM0 Port 1 (P1): P11 PWM1 Ý 8-bit I/O port P12 ASCK2/SCK2 Ý Inputs and outputs can be specified bit by bit. P13 RxD2/SI2 P14 TxD2/SO2 Ý The use of the pull-up resistors can be specified by software for the pins in the input mode together. P15-P17 — Ý Can drive LED. NMI Port 2 (P2): P21 INTP0 Ý 8-bit input-only port P22 INTP1 P23 INTP2/CI Ý P20 does not function as a general-purpose port (nonmaskable interrupt). However, the input level can be checked by an interrupt service routine. P24 INTP3 P25 INTP4/ASCK/SCK1 P26 INTP5 P27 SI0 Ý The P25/INTP4/ASCK/SCK1 pin functions as the SCK1 output pin by CSIM1. RxD/SI1 Port 3 (P3): P31 TxD/SO1 Ý 8-bit I/O port P32 SCK0 Ý Inputs and outputs can be specified bit by bit. P33 SO0/SB0 P34-P37 TO0-TO3 Ý The use of the pull-up resistors can be specified by software for the pins in the input mode together. P20 P30 P60-P63 Input I/O I/O A16-A19 Ý The use of the pull-up resistors can be specified by software for pins P22 to P27 (in units of 6 bits). Port 6 (P6): Ý P60 to P63 are an output-only port. P66 WAIT/HLDRQ Ý Inputs and outputs can be specified bit by bit for pins P66 and P67. P67 P70-P77 I/O REFRQ/HLDAK Ý The use of the pull-up resistors can be specified by software for the pins in the input mode together. ANI0-ANI7 Port 7 (P7): Ý 8-bit I/O port Ý Inputs and outputs can be specified bit by bit. 12 m PD784020, 784021 6.2 NON-PORT PINS (1/2) Pin TO0-TO3 I/O Output Dual-function Function P34-P37 Timer output CI Input P23/INTP2 Input of a count clock for timer/counter 2 RX D Input P30/SI1 Serial data input (UART0) P13/SI2 Serial data input (UART2) P31/SO1 Serial data output (UART0) P14/SO2 Serial data output (UART2) RX D2 T XD Output TXD2 ASCK Input P25/INTP4/SCK1 Baud rate clock input (UART0) P12/SCK2 Baud rate clock input (UART2) P33/SO0 Serial data I/O (SBI) P27 Serial data input (3-wire serial I/O0) P30/RX D Serial data input (3-wire serial I/O1) P13/RX D2 Serial data input (3-wire serial I/O2) P33/SB0 Serial data output (3-wire serial I/O0) SO1 P31/TXD Serial data output (3-wire serial I/O1) SO2 P14/TXD2 Serial data output (3-wire serial I/O2) ASCK2 SB0 I/O SI0 Input SI1 SI2 SO0 SCK0 Output P32 Serial clock I/O (3-wire serial I/O0, SBI) SCK1 P25/INTP4/ASCK Serial clock I/O (3-wire serial I/O1) SCK2 P12/ASCK2 Serial clock I/O (3-wire serial I/O2) P20 External interrupt request NMI I/O Input — INTP0 P21 Ý Input of a count clock for timer/counter 1 Ý Capture/trigger signal for CR11 or CR12 INTP1 P22 Ý Input of a count clock for timer/counter 2 Ý Capture/trigger signal for CR22 INTP2 P23/CI Ý Input of a count clock for timer/counter 2 Ý Capture/trigger signal for CR21 INTP3 P24 Ý Input of a count clock for timer/counter 0 Ý Capture/trigger signal for CR02 INTP4 P25/ASCK/SCK1 INTP5 P26 AD0-AD7 — Input of a conversion start trigger for A/D converter I/O — Time multiplexing address/data bus (for connecting external memory) A8-A15 Output — High-order address bus (for connecting external memory) A16-A19 Output RD Output — Strobe signal output for reading the contents of external memory WR Output — Strobe signal output for writing on external memory WAIT P60-P63 High-order address bus during address expansion (for connecting external memory) Input P66/HLDRQ Wait signal insertion REFRQ Output P67/HLDAK Refresh pulse output to external pseudo static memory HLDRQ Input P66/WAIT Input of bus hold request HLDAK Output P67/REFRQ Output of bus hold response ASTB Output — Latch timing output of time multiplexing address (A0-A7) (for connecting external memory) 13 m PD784020, 784021 6.2 NON-PORT PINS (2/2) Pin I/O Dual-function RESET Input — Chip reset X1 Input — Crystal input for system clock oscillation (A clock pulse can also be X2 — ANI0-ANI7 ANO0, ANO1 AVREF1 Input Function input to the X1 pin.) P70-P77 Analog voltage inputs for the A/D converter Output — Analog voltage inputs for the D/A converter — — Application of A/D converter reference voltage AVREF2, AVREF3 Application of D/A converter reference voltage AVDD Positive power supply for the A/D converter AVSS Ground for the A/D converter VDD Positive power supply VSS Ground TEST Directly connect to VSS . (The TEST pin is for the IC test.) 14 m PD784020, 784021 6.3 I/O CIRCUITS FOR PINS AND HANDLING OF UNUSED PINS Table 6-1 describes the types of I/O circuits for pins and the handling of unused pins. Fig. 6-1 shows the configuration of these various types of I/O circuits. Table 6-1 Types of I/O Circuits for Pins and Handling of Unused Pins (1/2) Pin P00-P07 I/O circuit type 5-A I/O I/O P10/PWM0 Recommended connection method for unused pins Input state : To be connected to VDD Output state: To be left open P11/PWM1 P12/ASCK2/SCK2 8-A P13/RxD2/SI2 5-A P14/TxD2/SO2 P15-P17 P20/NMI 2 Input To be connected to VDD or V SS P21/INTP0 P22/INTP1 2-A To be connected to V DD P23/INTP2/CI P24/INTP3 P25/INTP4/ASCK/SCK1 8-A I/O Input state : To be connected to VDD Output state: To be left open P26/INTP5 2-A Input 5-A I/O To be connected to V DD P27/SI0 P30/RxD/SI1 P31/TxD/SO1 Input state : To be connected to VDD Output state: To be left open P32/SCK0 8-A P33/SO0/SB0 10-A P34/TO0-P37/TO3 5-A AD0-AD7 OutputNote A8-A15 To be left open P60/A16-P63/A19 RD WR P66/WAIT/HLDRQ I/O P67/REFRQ/HLDAK P70/ANI0-P77/ANI7 Input state : To be connected to VDD Output state: To be left open Input state : To be connected to VDD or VSS 20 Output state: To be left open ANO0, ANO1 12 ASTB 4 Output To be left open Note These pins function as output-only pins depending on the internal circuit, though their I/O type is 5-A. 15 m PD784020, 784021 Table 6-1 Types of I/O Circuits for Pins and Handling of Unused Pins (2/2) Pin I/O circuit type RESET 2 TEST 1 AVREF1-AVREF3 I/O Recommended connection method for unused pins Input — To be connected to VSS directly — To be connected to VSS AVSS AVDD To be connected to V DD Caution When the I/O mode of an I/O dual-function pin is unpredictable, connect the pin to VDD through a resistor of 10 to 100 kilohms (particularly when the voltage of the reset input pin becomes higher than that of the low level input at power-on or when I/O is switched by software). Remark Since type numbers are consistent in the 78K series, those numbers are not always serial in each product. (Some circuits are not included.) 16 m PD784020, 784021 Fig. 6-1 I/O Circuits for Pins Type 1 Type 2-A VDD VDD P Pull-up enable P IN N IN Type 2 Schmitt trigger input with hysteresis characteristics IN Type 5-A VDD Schmitt trigger input with hysteresis characteristics VDD Type 4 Data Pull-up enable P P VDD Data P OUT Output disable IN/OUT Output disable N Push-pull output which can output high impedance (both the positive and negative channels are off.) Type 8-A N Input enable Type 12 VDD Pull-up enable Data P VDD P Analog output voltage OUT N IN/OUT Output disable P N Type 10-A Type 20 VDD VDD Data Pull-up enable IN/OUT P Output disable VDD Data Open drain Output disable P N P Comparator IN/OUT + – N P N VREF (Threshold voltage) Input enable 17 m PD784020, 784021 7. CPU ARCHITECTURE 7.1 MEMORY SPACE A 1M-byte memory space can be accessed. By using a LOCATION instruction, the mode for mapping internal data areas (special function registers and internal RAM) can be selected. A LOCATION instruction must always be executed after a reset, and can be used only once. (1) When the LOCATION 0 instruction is executed Internal data areas are mapped to 0FD00H-0FFFFH for themPD784020 and 0F700H-0FFFFH for the mPD784021. (2) When the LOCATION 0FH instruction is executed Internal data areas are mapped to FFD00H-FFFFFH for themPD784020 and FF700H-FFFFFH for themPD784021. 18 External memory (960K bytes) External memory (64,768 bytes) Note General-purpose registers (128 bytes) 00000H 00040H 0003FH Vector table area (64 bytes) 00080H 0007FH CALLT table area (64 bytes) 00080H 0007FH 00FFFH FFD00H 00800H 007FFH CALLF entry area (2K bytes) Data area (512 bytes) FFE06H FFE2FH FFE80H FFE7FH FFEFFH 00800H 007FFH 00FFFH 0FD00H Macro service control 0 F E 0 6 H word area (42 bytes) 0FE2FH 0FE80H 0FE7FH 0FEFFH 00000H 10000H 0FFFFH FFD00H FFCFFH External memory (1,047,808 bytes) Internal RAM (512 bytes) Note When the LOCATION 0FH F F F F F H instruction is executed FFFDFH Special function registers (SFRs) FFFD0H (256 bytes) FFF00H FFEFFH Note Base area, or entry area based on a reset or interrupt. Internal RAM is excluded in the case of a reset. 00000H 0FD00H 0FCFFH Internal RAM (512 bytes) 10000H 0 F F F F H Special function registers (SFRs) 0FFDFH 0FFD0H (256 bytes) 0FF00H 0FEFFH FFFFFH When the LOCATION 0 instruction is executed Fig. 7-1 mPD784020 Memory MapH H m PD784020, 784021 19 20 External memory (960K bytes) Note General-purpose registers (128 bytes) 00000H 00040H 0003FH Vector table area (64 bytes) 00000H 00080H 0007FH CALLT table area (64 bytes) 00080H 0007FH 00FFFH FF700H FFD00H FFCFFH 00800H 10000H 007FFH 0FFFFH CALLF entry area (2K bytes) Program/data area (1,536 bytes) Data area (512 bytes) FFE06H FFE2FH FFE80H FF700H FFE7FH FF6FFH 00800H 007FFH 00FFFH 0F700H 0FD00H 0FCFFH Macro service control 0 F E 0 6 H word area (42 bytes) 0FE2FH 0FE80H 0FE7FH 0FEFFH External memory (1,046,272 bytes) Note When the LOCATION 0FH F F F F F H instruction is executed FFFDFH Special function registers (SFRs) FFFD0H (256 bytes) FFF00H FFEFFH FFEFFH Internal RAM (2,048 bytes) Note Base area, or entry area based on a reset or interrupt. Internal RAM is excluded in the case of a reset. 00000H External memory (63,232 bytes) 10000H 0 F F F F H Special function registers (SFRs) 0FFDFH 0FFD0H (256 bytes) 0FF00H 0FEFFH 0FD00H 0FCFFH Internal RAM (2,048 bytes) 0F700H 0F6FFH FFFFFH When the LOCATION 0 instruction is executed Fig. 7-2 mPD784021 Memory Map m PD784020, 784021 m PD784020, 784021 7.2 7.2.1 CPU REGISTERS General-Purpose Registers A set of general-purpose registers consists of sixteen general-purpose 8-bit registers. Two 8-bit general-purpose registers can be combined to form a 16-bit general-purpose register. Moreover, four 16-bit general-purpose registers, when combined with an 8-bit register for address extension, can be used as 24-bit address specification registers. Eight banks of this register set are provided. The user can switch between banks by software or the context switching function. General-purpose registers other than the V, U, T, and W registers used for address extension are mapped onto internal RAM. Fig. 7-3 General-Purpose Register Format A (R1) X (R0) AX (RP0) B (R3) C (R2) BC (RP1) R5 R4 RP2 R7 R6 RP3 V R9 VVP (RG4) R8 VP (RP4) U R11 R10 UUP (RG5) UP (RP5) T D (R13) E (R12) TDE (RG6) DE (RP6) W H (R15) L (R14) WHL (RG7) HL (RP7) 8 banks The character strings enclosed in parentheses represent absolute names. Caution By setting the RSS bit of PSW to 1, R4, R5, R6, R7, RP2, and RP3 can be used as the X, A, C, B, AX, and BC registers, respectively. However, this function must be used only when using programs for the 78K/III series. 21 m PD784020, 784021 7.2.2 Control Registers (1) Program counter (PC) This register is a 20-bit program counter. The program counter is automatically updated by program execution. Fig. 7-4 Format of Program Counter (PC) 19 0 PC (2) Program Status Word (PSW) This register holds the CPU state. The program status word is automatically updated by program execution. Fig. 7-5 Format of Program Status Word (PSW) PSWH 15 14 13 12 11 10 9 8 UF RBS2 RBS1 RBS0 7 6 5 4 3 2 1 0 S Z RSSNote AC IE P/V 0 CY PSW PSWL Note This flag is used to maintain compatibility with the 78K/III series. This flag must be set to 0 when programs for the 78K/III series are being used. (3) Stack pointer (SP) This register is a 24-bit pointer for holding the start address of the stack. The high-order 4 bits must be set to 0. Fig. 7-6 Format of Stack Pointer (SP) 23 PC 22 0 20 0 0 0 0 m PD784020, 784021 7.2.3 H Special Function Registers (SFRs) The special function registers are registers with special functions such as mode registers and control registers for built-in peripheral hardware. The special function registers are mapped onto the 256-byte space between 0FF00H and 0FFFFHNote. Note Applicable when the LOCATION 0 instruction is executed. FFF00H-FFFFFH when the LOCATION 0FH instruction is executed. Caution Never attempt to access addresses in this area where no SFR is allocated. Otherwise, the mPD784021 may be placed in the deadlock state. The deadlock state can be cleared only by a reset. Table 7-1 lists the special function registers (SFRs). The titles of the table columns are explained below. • Abbreviation ................... Symbol used to represent a built-in SFR. The abbreviations listed in the table are reserved words for the NEC assembler (RA78K4). The C compiler (CC78K4) allows the abbreviations to be used as sfr variables of bit type with the #pragma sfr command. • R/W ................................. Indicates whether each SFR allows read and/or write operations. R/W : Allows both read and write operations. R : Allows read operations only. W : Allows write operations only. • Manipulatable bits .......... Indicates the maximum number of bits that can be manipulated whenever an SFR is manipulated. An SFR that supports 16-bit manipulation can be described in the sfr operand. For address specification, an even-numbered address must be specified. An SFR that supports 1-bit manipulation can be described in a bit manipulation instruction. • When reset ..................... Indicates the state of each register when RESET is applied. 23 m PD784020, 784021 Table 7-1 Special Function Registers (SFRs) (1/4) Manipulatable bits AddressNote Special function register (SFR) name Abbreviation R/W When reset 1 bit l l – l l – R l l – R/W l l – P6 l l – 00H P7 l l – Undefined Port 0 buffer register L P0L l l – 0FF00H Port 0 P0 0FF01H Port 1 P1 0FF02H Port 2 P2 0FF03H Port 3 P3 0FF06H Port 6 0FF07H Port 7 0FF0EH 8 bits 16 bits R/W Undefined 0FF0FH Port 0 buffer register H P0H l l – 0FF10H Compare register (timer/counter 0) CR00 – – l 0FF12H Capture/compare register (timer/counter 0) CR01 – – l 0FF14H Compare register L (timer/counter 1) CR10 CR10W – l l 0FF15H Compare register H (timer/counter 1) – – 0FF16H Capture/compare register L (timer/counter 1) – l 0FF17H Capture/compare register H (timer/counter 1) – – 0FF18H Compare register L (timer/counter 2) – l 0FF19H Compare register H (timer/counter 2) – – 0FF1AH Capture/compare register L (timer/counter 2) – l 0FF1BH Capture/compare register H (timer/counter 2) – – 0FF1CH Compare register L (timer 3) – l 0FF1DH Compare register H (timer 3) – – – 0FF20H Port 0 mode register PM0 l l – 0FF21H Port 1 mode register PM1 l l – 0FF23H Port 3 mode register PM3 l l – 0FF26H Port 6 mode register PM6 l l – 0FF27H Port 7 mode register PM7 l l – 0FF2EH Real-time output port control register RTPC l l – 00H 0FF30H Capture/compare control register 0 CRC0 – l – 10H 0FF31H Timer output control register TOC l l – 00H 0FF32H Capture/compare control register 1 CRC1 – l – 0FF33H Capture/compare control register 2 CRC2 – l – – CR11 CR11W – CR20 CR20W – CR21 CR21W – CR30 CR30W l l l l FFH 10H Note Applicable when the LOCATION 0 instruction is executed. When the LOCATION 0FH instruction is executed, F0000H is added to each address. 24 m PD784020, 784021 Table 7-1 Special Function Registers (SFRs) (2/4) AddressNote Manipulatable bits Special function register (SFR) name Abbreviation R/W When reset 1 bit – – l – l l – – – l – – l l – PMC3 l l – Register for optional pull-up resistor PUO l l – Timer register 0 TM0 – – l – – – l – – – l – – – l – – – l – 11H 0FF36H Capture register (timer/counter 0) CR02 0FF38H Capture register L (timer/counter 1) CR12 CR12W 0FF39H Capture register H (timer/counter 1) 0FF3AH Capture register L (timer/counter 2) 0FF3BH Capture register H (timer/counter 2) 0FF41H Port 1 mode control register PMC1 0FF43H Port 3 mode control register 0FF4EH 0FF50H R – CR22 CR22W – R/W R 0FF51H 0FF52H Timer register 1 0FF53H 0FF54H TM1 TM1W – Timer register 2 0FF55H 0FF56H 8 bits 16 bits TM2 TM2W – Timer register 3 0FF57H TM3 TM3W – R/W 0000H l 00H 0000H l l l 0FF5CH Prescaler mode register 0 PRM0 0FF5DH Timer control register 0 TMC0 l l – 00H 0FF5EH Prescaler mode register 1 PRM1 – l – 11H 0FF5FH Timer control register 1 TMC1 l l – 00H 0FF60H D/A conversion value setting register 0 DACS0 – l – 0FF61H D/A conversion value setting register 1 DACS1 – l – 0FF62H D/A converter mode register DAM l l – 03H 0FF68H A/D converter mode register ADM l l – 00H 0FF6AH A/D conversion result register ADCR R – l – Undefined 0FF70H PWM control register PWMC R/W l l – 05H 0FF71H PWM prescaler register PWPR – l – 00H 0FF72H PWM modulo register 0 PWM0 – – l Undefined 0FF74H PWM modulo register 1 PWM1 – – l 0FF7DH One-shot pulse output control register OSPC l l – 0FF80H Serial bus interface control register SBIC l l – 0FF82H Synchronous serial interface mode register CSIM l l – 00H Note Applicable when the LOCATION 0 instruction is executed. When the LOCATION 0FH instruction is executed, F0000H is added to each address. 25 m PD784020, 784021 Table 7-1 Special Function Registers (SFRs) (3/4) Manipulatable bits AddressNote 1 Special function register (SFR) name Abbreviation R/W When reset 1 bit 8 bits 16 bits l l – CSIM2 l l – Serial shift register SIO – l – 0FF88H Asynchronous serial interface mode register ASIM l l – 0FF89H Asynchronous serial interface mode register 2 ASIM2 l l – 0FF8AH Asynchronous serial interface status register ASIS l l – 0FF8BH Asynchronous serial interface status register 2 ASIS2 l l – 0FF8CH Serial receive buffer: UART0 RXB – l – Serial transmission shift register: UART0 TXS W – l – Serial shift register: IOE1 SIO1 R/W – l – Serial receive buffer: UART2 RXB2 R – l – Serial transmission shift register: UART2 TXS2 W – l – Serial shift register: IOE2 SIO2 R/W – l – 0FF90H Baud rate generator control register BRGC – l – 0FF91H Baud rate generator control register 2 BRGC2 – l – 0FFA0H External interrupt mode register 0 INTM0 l l – 0FFA1H External interrupt mode register 1 INTM1 l l – 0FFA4H Sampling clock selection register SCS0 – l – 0FFA8H In-service priority register ISPR R l l – 0FFAAH Interrupt mode control register IMC R/W l l – 80H 0FFACH Interrupt mask register 0L MK0L MK0 l l l FFFFH 0FFADH Interrupt mask register 0H MK0H l l 0FFAEH Interrupt mask register 1L MK1L l l – FFH 0FFC0H Standby control register STBC – lNote 2 – 30H 0FFC2H Watchdog timer mode register WDM – lNote 2 – 00H 0FFC4H Memory expansion mode register MM l l – 20H 0FFC5H Hold mode register HLDM l l – 00H 0FFC6H Clock output mode register CLOM l l – 0FFC7H Programmable wait control register 1 PWC1 – l – AAH 0FFC8H Programmable wait control register 2 PWC2 – – l AAAAH 0FF84H Synchronous serial interface mode register 1 CSIM1 0FF85H Synchronous serial interface mode register 2 0FF86H 0FF8DH R/W R 00H Undefined 00H Notes 1. Applicable when the LOCATION 0 instruction is executed. When the LOCATION 0FH instruction is executed, F0000H is added to each address. 2. A write operation can be performed only with special instructions MOV STBC,#byte and MOV WDM,#byte. Other instructions cannot perform a write operation. 26 m PD784020, 784021 Table 7-1 Special Function Registers (SFRs) (4/4) Manipulatable bits AddressNote Special function register (SFR) name Abbreviation R/W When reset 1 bit 8 bits 16 bits l l – RFA l l – OSTS – l – l l – 0FFCCH Refresh mode register RFM 0FFCDH Refresh area specification register 0FFCFH Oscillation settling time specification register 0FFD0H- External SFR area R/W – 00H – 0FFDFH 0FFE0H Interrupt control register (INTP0) PIC0 l l – 0FFE1H Interrupt control register (INTP1) PIC1 l l – 0FFE2H Interrupt control register (INTP2) PIC2 l l – 0FFE3H Interrupt control register (INTP3) PIC3 l l – 0FFE4H Interrupt control register (INTC00) CIC00 l l – 0FFE5H Interrupt control register (INTC01) CIC01 l l – 0FFE6H Interrupt control register (INTC10) CIC10 l l – 0FFE7H Interrupt control register (INTC11) CIC11 l l – 0FFE8H Interrupt control register (INTC20) CIC20 l l – 0FFE9H Interrupt control register (INTC21) CIC21 l l – 0FFEAH Interrupt control register (INTC30) CIC30 l l – 0FFEBH Interrupt control register (INTP4) PIC4 l l – 0FFECH Interrupt control register (INTP5) PIC5 l l – 0FFEDH Interrupt control register (INTAD) ADIC l l – 0FFEEH Interrupt control register (INTSER) SERIC l l – 0FFEFH Interrupt control register (INTSR) SRIC l l – Interrupt control register (INTCSI1) CSIIC1 l l – 0FFF0H Interrupt control register (INTST) STIC l l – 0FFF1H Interrupt control register (INTCSI) CSIIC l l – 0FFF2H Interrupt control register (INTSER2) SERIC2 l l – 0FFF3H Interrupt control register (INTSR2) SRIC2 l l – Interrupt control register (INTCSI2) CSIIC2 l l – Interrupt control register (INTST2) STIC2 l l – 0FFF4H 43H Note Applicable when the LOCATION 0 instruction is executed. When the LOCATION 0FH instruction is executed, F0000H is added to each address. 27 m PD784020, 784021 8. PERIPHERAL HARDWARE FUNCTIONS 8.1 PORTS The ports shown in Fig. 8-1 are provided to enable the application of wide-ranging control. Table 8-1 lists the functions of the ports. For the inputs to port 0 to port 6, a built-in pull-up resistor can be specified by software. Fig. 8-1 Port Configuration P00 Port 0 P07 P10 Port 1 P17 P20-P27 8 Port 2 P30 Port 3 P37 P60 P63 P66 P67 P70 Port 6 Port 7 P77 28 m PD784020, 784021 Table 8-1 Port Functions Port name Pin Function Pull-up specification by software Port 0 P00-P07 • Bit-by-bit input/output setting supported • Operable as 4-bit real-time outputs (P00-P03, P04-P07) • Capable of driving transistors Specified as a batch for all pins placed in input mode. Port 1 P10-P17 • Bit-by-bit input/output setting supported • Capable of driving LEDs Specified as a batch for all pins placed in input mode. Port 2 P20-P27 • Input port Specified for the 6 bits (P22-P27) as a batch. Port 3 P30-P37 • Bit-by-bit input/output setting supported Specified as a batch for all pins placed in input mode. Port 6 P60-P63 • Output-only port P66, P67 • Bit-by-bit input/output setting supported Specified as a batch for all pins placed in input mode. P70-P77 • Bit-by-bit input/output setting supported Port 7 8.2 — CLOCK GENERATOR A circuit for generating the clock signal required for operation is provided. The clock generator includes a frequency divider; low current consumption can be achieved by operating at a lower internal frequency when high-speed operation is not necessary. Fig. 8-2 Block Diagram of Clock Generator X1 fXX 1/2 1/2 1/2 1/2 Selector Oscillator X2 fCLK CPU Peripheral circuits fXX/2 UART/IOE INTP0 noise eliminator Oscillation settling timer Remark fXX : Oscillator frequency or external clock input fCLK : Internal operating frequency 29 m PD784020, 784021 Fig. 8-3 Examples of Using Oscillator (1) Crystal/ceramic oscillation µ PD784021 VSS X1 X2 H (2) External clock • When EXTC bit of OSTS = 1 • When EXTC bit of OSTS = 0 µ PD784021 µ PD784021 X1 µ PD74HC04, etc. X2 X1 Open X2 Caution When using the clock generator, to avoid problems caused by influences such as stray capacitance, run all wiring within the area indicated by the dotted lines according to the following rules: • • • • Minimize the wiring length. Wires must never cross other signal lines. Wires must never run near a line carrying a large varying current. The grounding point of the capacitor of the oscillator circuit must always be at the same potential as VSS. Never connect the capacitor to a ground pattern carrying a large current. • Never extract a signal from the oscillator circuit. 30 m PD784020, 784021 8.3 REAL-TIME OUTPUT PORT The real-time output port outputs data stored in the buffer, synchronized with a timer/counter 1 match interrupt or external interrupt. Thus, pulse output that is free of jitter can be obtained. Therefore, the real-time output port is best suited to applications (such as open-loop control over stepping motors) where an arbitrary pattern is output at arbitrary intervals. As shown in Fig. 8-4, the real-time output port is built around port 0 and the port 0 buffer register (P0H, P0L). Fig. 8-4 Block Diagram of Real-Time Output Port Internal bus INTP0 (externally) INTC10 (from timer/counter 1) INTC11 (from timer/counter 1) 4 8 4 Real-time output port control register (RTPC) P0H P0L 4 4 Buffer register Output trigger control circuit 8 Output latch (P0) P07 P00 31 m PD784020, 784021 8.4 TIMERS/COUNTERS Three timer/counter units and one timer unit are incorporated. Moreover, seven interrupt requests are supported, allowing these units to function as seven timer/counter units. Table 8-2 Timer/Counter Operation Name Timer/counter 0 Timer/counter 1 Timer/counter 2 Timer 3 8 bits – l l l 16 bits l l l l 2ch 2ch 2ch 1ch External event counter l l l – One-shot timer – – l – 2ch – 2ch – Toggle output l – l – PWM/PPG output l – l – One-shot pulse outputNote l – – – – l – – 1 input 1 input 2 inputs – 2 2 2 1 Item Count pulse width H Operating mode Function Interval timer Timer output Real-time output Pulse width measurement Number of interrupt requests Note The one-shot pulse output function makes the level of a pulse output active by software, and makes the level of a pulse output inactive by hardware (interrupt request signal). Note that this function differs from the one-shot timer function of timer/counter 2. 32 m PD784020, 784021 H Fig. 8-5 Timer/Counter Block Diagram Timer/counter 0 Software trigger Prescaler Timer register 0 (TM0) Compare register (CR00) Compare register (CR01) Match Match Capture register (CR02) Edge detection INTP3 OVF Pulse output control fxx/8 Selector Clear information TO0 TO1 INTC00 INTC01 INTP3 Timer/counter 1 fxx/8 Prescaler Selector Clear information Event input Compare register (CR10/CR10W) Edge detection INTP0 Timer register 1 (TM1/TM1M) Capture/compare register (CR11/CR11W) OVF Match Match INTC10 To real-time output port INTC11 INTP0 Capture register (CR12/CR12W) Timer/counter 2 INTP2/C1 Prescaler Compare register (CR20/CR20W) Edge detection INTP2 Capture/compare register (CR21/CR21W) OVF Match Match Capture register (CR22/CR22W) Edge detection INTP1 Timer register 2 (TM2/TM2W) Pulse output control fxx/8 Selector Clear information TO2 TO3 INTC20 INTP1 INTC21 Timer 3 fxx/8 Prescaler Timer register 3 (TM3/TM3W) Clear Compare register (CR30/CR30W) Match CSI INTC30 Remark OVF: Overflow flag 33 m PD784020, 784021 8.5 PWM OUTPUT (PWM0, PWM1) Two channels of PWM (pulse width modulation) output circuitry with a resolution of 12 bits and a repetition frequency of 48.8 kHz (fCLK = 12.5 MHz) are incorporated. Low or high active level can be selected for the PWM output channels, independently of each other. This output is best suited to DC motor speed control. Fig. 8-6 Block Diagram of PWM Output Unit Internal bus 16 8 PWM modulo register 8 7 PWMn 15 8 4 3 0 PWM control register (PWMC) 4 Reload control fCLK Prescaler 8-bit down-counter Pulse control circuit 4-bit counter 1/256 Remark n = 0, 1 34 Output control PWMn (output pin) m PD784020, 784021 8.6 A/D CONVERTER An analog/digital (A/D) converter having 8 multiplexed analog inputs (ANI0-ANI7) is incorporated. The successive approximation system is used for conversion. The result of conversion is held in the 8-bit A/D conversion result register (ADCR). Thus, speedy high-precision conversion can be achieved. (The conversion time is about 10 ms at fCLK = 12.5 MHz.) A/D conversion can be started in any of the following modes: • Hardware start : Conversion is started by means of trigger input (INTP5). • Software start : Conversion is started by means of bit setting the A/D converter mode register (ADM). After conversion has started, one of the following modes can be selected: • Scan mode : Multiple analog inputs are selected sequentially to obtain conversion data from all pins. • Select mode : A single analog input is selected at all times to enable conversion data to be obtained continuously. ADM is used to specify the above modes, as well as the termination of conversion. When the result of conversion is transferred to ADCR, an interrupt request (INTAD) is generated. Using this feature, the results of conversion can be continuously transferred to memory by the macro service. Fig. 8-7 Block Diagram of A/D Converter Series resistor string Sample-and-hold circuit Input selector AVREF1 R Successive conversion register (SAR) INTP5 R/2 Voltage comparator Conversion trigger Edge detector Tap selector ANI0 ANI1 ANI2 ANI3 ANI4 ANI5 ANI6 ANI7 INTAD Control circuit R/2 AVSS Trigger enable 8 A/ D converter mode register (ADM) A/ D conversion result register (ADCR) 8 8 Internal bus 35 m PD784020, 784021 8.7 D/A CONVERTER Two digital/analog (D/A) converter channels of voltage output type, having a resolution of 8 bits, are incorporated. A resistor string system is used for conversion. By writing the value to be subject to D/A conversion in the 8-bit D/A conversion value setting register (DACSn: n = 0, 1), the resulting analog value is output on ANOn (n = 0, 1). The range of the output voltages is determined by the voltages applied to the AVREF2 and AVREF3 pins. Because of its high output impedance, no current can be obtained from an output pin. When the load impedance is low, insert a buffer amplifier between the load and the converter. The impedance of the ANOn pin goes high while the RESET signal is low. DACSn is set to 0 after a reset is released. Fig. 8-8 Block Diagram of D/A Converter AVREF2 R Tap selector R R ANOn R AVREF3 RESET DACSn DACEn 8 8 Internal bus Remark 36 n = 0, 1 m PD784020, 784021 8.8 SERIAL INTERFACE Three independent serial interface channels are incorporated. • Asynchronous serial interface (UART)/three-wire serial I/O (IOE) ¥ 2 • Synchronous serial interface (CSI) ¥ 1 • Three-wire serial I/O (IOE) • Serial bus interface (SBI) So, communication with points external to the system and local communication within the system can be performed at the same time. (See Fig. 8-9.) Fig. 8-9 Example Serial Interfaces (a) UART + SBI µ PD784021 (master) µ PD4711A VDD µ PD75402A (slave) (UART) RxD TxD RS-232-C driver/ receiver (SBI) SB0 SCK0 SB0 SCK Port µ PD75328 (slave) SB0 µ PD4711A SCK (UART) LCD RxD2 TxD2 RS-232-C driver/ receiver Port (b) UART + Three-wire serial I/O µ PD784021 (master) µ PD4711A SO0 SI0 (UART) RS-232-C driver/ receiver µ PD75108 (slave) [Three-wire serial I/O] RxD TxD SCK0 INTPm Port Note Port SI SO SCK Port INT µ PD78014 (slave) SO1 SI1 SCK1 INTPn Port Note SI SO SCK Port INT Note Handshake line 37 m PD784020, 784021 8.8.1 Asynchronous Serial Interface/Three-Wire Serial I/O (UART/IOE) Two serial interface channels are available; for each channel, asynchronous serial interface mode or three-wire serial I/O mode can be selected. (1) Asynchronous serial interface mode In this mode, 1-byte data is transferred after a start bit. A baud rate generator is incorporated to enable communication at a wide range of baud rates. Moreover, the frequency of a clock signal applied to the ASCK pin can be divided to define a baud rate. With the baud rate generator, the baud rate conforming to the MIDI standard (31.25 kbps) can be obtained. Fig. 8-10 Block Diagram of Asynchronous Serial Interface Mode Internal bus Receive buffer RXB, RXB2 Transmission shift register Receive shift register RxD, RxD2 TXS, TXS2 TxD, TxD2 Reception control parity check Baud rate generator ASCK, ASCK2 Selector 1/2m fXX/2 1/2 n+1 1/2m Remark fXX: Oscillator frequency or external clock input n = 0 to 11 m = 16 to 30 38 INTSR, INTSR2 INTSER, INTSER2 Transmission control parity bit addition INTST, INTST2 m PD784020, 784021 (2) Three-wire serial I/O mode In this mode, the master device makes the serial clock active to start transmission, then transfers 1-byte data in phase with the clock. This mode is designed for communication with a device incorporating a conventional synchronous serial interface. Basically, three lines are used for communication: the serial clock line (SCK) and the two serial data lines (SI and SO). In general, a handshake line is required to check the state of communication. Fig. 8-11 Block Diagram of Three-Wire Serial I/O Mode Internal bus Direction control circuit SIO1, SIO2 SI1, SI2 Shift register Output latch SO1, SO2 Interrupt signal generator Serial clock counter Serial clock control circuit Selector SCK1, SCK2 1/m INTCSI1, INTCSI2 1/2n+1 fXX/2 Remark fXX: Oscillator frequency or external clock input n = 0 to 11 m = 1, 16 to 30 39 m PD784020, 784021 8.8.2 Synchronous Serial Interface (CSI) With this interface, the master device makes the serial clock active to start transmission, then transfers 1-byte data in phase with the clock. Fig. 8-12 Block Diagram of Synchronous Serial Interface Internal bus Direction control circuit SI0 SO0/SB0 Selector Set N-ch open-drain output enabled (when SB0 or SBI mode is used) SCK0 Clear SIO Shift register Output latch Busy/ acknowledge detection circuit Bus release/ command/ acknowledge detection circuit Serial clock counter Interrupt signal generation circuit INTCSI Remark fCLK: Internal system clock frequency (system clock frequency/2) 40 Selector TM 3 output/2 Serial clock control circuit fCLK/8 fCLK/32 m PD784020, 784021 (1) Three-wire serial I/O mode This mode is designed for communication with a device incorporating a conventional synchronous serial interface. Basically, three lines are used for communication: the serial clock line (SCK0) and serial data lines (SI0 and SO0). In general, a handshake line is required to check the state of communication. (2) SBI mode The SBI mode allows communication with more than one device via two lines: the serial clock (SCK0) and serial bus (SB0). The SBI mode is the standard NEC serial interface. A master device outputs an address through the SB0 pin to select a slave device with which communication is to be performed. After a target device is selected, commands and data are transmitted between the master device and slave device. 8.9 EDGE DETECTION FUNCTION The interrupt input pins (NMI, INTP0-INTP5) are used to apply not only interrupt requests but also trigger signals for the built-in circuits. As these pins are triggered by an edge (rising or falling) of an input signal, a function for edge detection is incorporated. Moreover, a noise suppression function is provided to prevent erroneous edge detection caused by noise. Pin Detectable edge Noise suppression method NMI Rising edge or falling edge Analog delay INTP0-INTP3 Rising edge or falling edge, or both edges Clock samplingNote INTP4, INTP5 Analog delay Note INTP0 is used for sampling clock selection. 41 m PD784020, 784021 8.10 WATCHDOG TIMER A watchdog timer is incorporated for CPU runaway detection. The watchdog timer, if not cleared by software within a specified interval, generates a nonmaskable interrupt. Furthermore, once watchdog timer operation is enabled, it cannot be disabled by software. The user can specify whether priority is placed on an interrupt based on the watchdog timer or on an interrupt based on the NMI pin. H Fig. 8-13 Block Diagram of Watchdog Timer fCLK Timer fCLK/221 fCLK/219 fCLK/217 Clear signal 42 Selector fCLK/220 INTWDT m PD784020, 784021 9. INTERRUPT FUNCTION Table 9-1 lists the interrupt request handling modes. These modes are selected by software. Table 9-1 Interrupt Request Handling Modes Handling mode Vectored interrupt Handled by Software Context switching Macro service 9.1 Firmware Handling PC and PSW contents Branches to a handling routine for execution (arbitrary handling). The PC and PSW contents are pushed to and popped from the stack. Automatically selects a register bank, and branches to a handling routine for execution (arbitrary handling). The PC and PSW contents are saved to and read from a fixed area in the register bank. Performs operations such as memory-to-I/Odevice data transfer (fixed handling). Maintained INTERRUPT SOURCE An interrupt can be issued from any one of the interrupt sources listed in Table 9-2: execution of a BRK instruction, an operand error, or any of the 23 other interrupt sources. Four levels of interrupt handling priority can be set. Priority levels can be set to nest control during interrupt handling or to concurrently generate interrupt requests. Nested macro services, however, are performed without suspension. When interrupt requests having the same priority level are generated, they are handled according to the default priority (fixed). (See Table 9-2.) 43 m PD784020, 784021 Table 9-2 Interrupt Sources Default Type priority Software – Internal/ Macro Trigger external service – – BRK instruction Instruction execution Operand error When the MOV STBC,#byte or MOV WDM,#byte instruction is executed, exclusive OR of the byte operand and byte does not produce FFH. NMI Detection of edge input on the pin External WDT Watchdog timer overflow Internal 0 (highest) INTP0 Detection of edge input on the pin (TM1/TM1W capture trigger) External Enabled 1 INTP1 Detection of edge input on the pin (TM2/TM2W capture trigger) 2 INTP2 Detection of edge input on the pin (TM2/TM2W event counter input) 3 INTP3 Detection of edge input on the pin (TM0 capture trigger) 4 INTC00 TM0-CR00 match signal issued Internal Enabled 5 INTC01 TM0-CR01 match signal issued 6 INTC10 TM1-CR10 match signal issued (in 8-bit operation mode) TM1W-CR10W match signal issued (in 16-bit operation mode) 7 INTC11 TM1-CR11 match signal issued (in 8-bit operation mode) TM1W-CR11W match signal issued (in 16-bit operation mode) 8 INTC20 TM2-CR20 match signal issued (in 8-bit operation mode) TM2W-CR20W match signal issued (in 16-bit operation mode) 9 INTC21 TM2-CR21 match signal issued (in 8-bit operation mode) TM2W-CR21W match signal issued (in 16-bit operation mode) 10 INTC30 TM3-CR30 match signal issued (in 8-bit operation mode) TM3W-CR30W match signal issued (in 16-bit operation mode) 11 INTP4 Detection of edge input on the pin External Enabled 12 INTP5 Detection of edge input on the pin 13 INTAD A/D converter processing completed (ADCR transfer) Internal Enabled 14 INTSER ASI0 reception error 15 INTSR ASI0 reception completed or CSI1 transfer completed Nonmaskable – H Maskable Name Source – – Enabled INTCSI1 16 INTST ASI0 transmission completed 17 INTCSI CSI0 transfer completed 18 INTSER2 ASI2 reception error 19 INTSR2 ASI2 reception completed or CSI2 transfer completed INTCSI2 20 (lowest) INTST2 ASI2 transmission completed Remark ASI: Asynchronous serial interface CSI: Synchronous serial interface 44 – Enabled m PD784020, 784021 9.2 VECTORED INTERRUPT When a branch to an interrupt handling routine occurs, the vector table address corresponding to the interrupt source is used as the branch address. Interrupt handling by the CPU consists of the following operations : • When a branch occurs : Push the CPU status (PC and PSW contents) to the stack. • When control is returned: Pop the CPU status (PC and PSW contents) from the stack. To return control from the handling routine to the main routine, use the RETI instruction. The branch destination addresses must be within the range of 0 to FFFFH. Table 9-3 Vector Table Address Interrupt source Vector table address BRK instruction 003EH Operand error 003CH NMI 0002H WDT 0004H INTP0 0006H INTP1 0008H INTP2 000AH INTP3 000CH INTC00 000EH INTC01 0010H INTC10 0012H INTC11 0014H INTC20 0016H INTC21 0018H INTC30 001AH INTP4 001CH INTP5 001EH INTAD 0020H INTSER 0022H INTSR 0024H INTCSI1 INTST 0026H INTCSI 0028H INTSER2 002AH INTSR2 002CH INTCSI2 INTST2 002EH 45 m PD784020, 784021 9.3 CONTEXT SWITCHING When an interrupt request is generated, or when the BRKCS instruction is executed, an appropriate register bank is selected by the hardware. Then, a branch to a vector address stored in that register bank occurs. At the same time, the contents of the current program counter (PC) and program status word (PSW) are stacked in the register bank. The branch address must be within the range of 0 to FFFFH. Fig. 9-1 Context Switching Caused by an Interrupt Request 0000B 7 Transfer PC19-16 Save (Bits 8 to 11 of temporary register) 2 Register bank n (n = 0-7) PC15-0 6 Exchange X B C R5 R4 R7 5 Save Temporary register 1 A Save Register bank (0-7) R6 V VP U UP Switching between register banks (RBS0-RBS2 ← n) RSS ← 0 4 IE ← 0 3 T D E W H L PSW 9.4 MACRO SERVICE The macro service function enables data transfer between memory and special function registers (SFRs) without requiring the intervention of the CPU. The macro service controller accesses both memory and SFRs within the same transfer cycle to directly transfer data without having to perform data fetch. Since the CPU status is neither saved nor restored, nor is data fetch performed, high-speed data transfer is possible. Fig. 9-2 Macro Service Read CPU Memory Write Internal bus 46 Macro service controller Write SFR Read m PD784020, 784021 9.5 EXAMPLES OF MACRO SERVICE APPLICATIONS (1) Serial interface transmission Transmission data storage buffer (memory) Data n Data n-1 Data 2 Data 1 Internal bus TxD Transmission shift register Transmission control TXS (SFR) INTST Each time a macro service request (INTST) is generated, the next transmission data is transferred from memory to TXS. When data n (last byte) has been transferred to TXS (that is, once the transmission data storage buffer becomes empty), a vectored interrupt request (INTST) is generated. (2) Serial interface reception Reception data storage buffer (memory) Data n Data n-1 Data 2 Data 1 Internal bus Reception buffer RxD RXB (SFR) Reception shift register Reception control INTSR Each time a macro service request (INTSR) is generated, reception data is transferred from RXB to memory. When data n (last byte) has been transferred to memory (that is, once the reception data storage buffer becomes full), a vectored interrupt request (INTSR) is generated. 47 m PD784020, 784021 (3) Real-time output port INTC10 and INTC11 function as the output triggers for the real-time output ports. For these triggers, the macro service can simultaneously set the next output pattern and interval. Therefore, INTC10 and INTC11 can be used to independently control two stepping motors. They can also be applied to PWM and DC motor control. Output pattern profile (memory) Output timing profile (memory) Pn Tn Pn–1 Tn–1 P2 T2 P1 T1 Internal bus Internal bus Match (SFR) P0L CR10 (SFR) INTC10 Output latch TM1 P00-P03 Each time a macro service request (INTC10) is generated, a pattern and timing data are transferred to the buffer register (P0L) and compare register (CR10), respectively. When the contents of timer register 1 (TM1) and CR10 match, another INTC10 is generated, and the P0L contents are transferred to the output latch. When Tn (last byte) is transferred to CR10, a vectored interrupt request (INTC10) is generated. For INTC11, the same operation as that performed for INTC10 is performed. 48 m PD784020, 784021 10. LOCAL BUS INTERFACE The local bus interface enables the connection of external memory and I/O devices (memory-mapped I/O). It supports a 1M-byte memory space. (See Fig. 10-1.) Fig. 10-1 Example of Local Bus Interface A16-A19 Decoder µ PD784021 RD WR REFRQ Pseudo SRAM Kanji character generator µPD24C1000 Data bus bus Data AD0-AD7 ASTB PROM µ PD27C1001A Latch Address bus A8-A15 Gate array for I/O expansion including Centronics interface circuit, etc. 10.1 MEMORY EXPANSION By adding external memory, program memory or data memory can be expanded, 64K bytes at a time, to approximately 1M byte (three steps). 49 m PD784020, 784021 10.2 MEMORY SPACE The 1M-byte memory space is divided into eight spaces, each having a logical address. Each of these spaces can be controlled using the programmable wait and pseudo-static RAM refresh functions. Fig. 10-2 Memory Space FFFFFH 512K bytes 80000H 7FFFFH 256K bytes 40000H 3FFFFH 128K bytes 20000H 1FFFFH 64K bytes 10000H 0FFFFH 16K bytes 0C000H 0BFFFH 16K bytes 08000H 07FFFH 16K bytes 04000H 03FFFH 16K bytes 00000H 50 m PD784020, 784021 10.3 PROGRAMMABLE WAIT When the memory space is divided into eight spaces, a wait state can be separately inserted for each memory space while the RD or WR signal is active. This prevents the overall system efficiency from being degraded even when memory devices having different access times are connected. In addition, an address wait function that extends the ASTB signal active period is provided to produce a longer address decode time. (This function is set for the entire space.) 10.4 PSEUDO-STATIC RAM REFRESH FUNCTION Refresh is performed as follows: • Pulse refresh : A bus cycle is inserted where a refresh pulse is output on the REFRQ pin at regular intervals. When the memory space is divided into eight, and a specified area is being accessed, refresh pulses can also be output on the REFRQ pin as the memory is being accessed. This can prevent the refresh cycle from suspending normal memory access. • Power-down self-refresh : In standby mode, a low-level signal is output on the REFRQ pin to maintain the contents of pseudo-static RAM. 10.5 BUS HOLD FUNCTION A bus hold function is provided to facilitate connection to devices such as a DMA controller. Suppose that a bus hold request signal (HLDRQ) is received from an external bus master. In this case, upon the completion of the bus cycle being performed, the address bus, address/data bus, ASTB, RD, and WR pins are placed in the high-impedance state, and the bus hold acknowledge signal (HLDAK) is made active to release the bus for the external bus master. While the bus hold function is being used, the external wait and pseudo-static RAM refresh functions are disabled. 51 m PD784020, 784021 11. STANDBY FUNCTION The standby function allows the power consumption of the chip to be reduced. The following standby modes are supported: • HALT mode : The CPU operation clock is stopped. By occassionally inserting the HALT mode during normal operation, the overall average power consumption can be reduced. • IDLE mode : The entire system is stopped, with the exception of the oscillator circuit. This mode consumes only very little more power than STOP mode, but normal program operation can be restored in almost as little time as that required to restore normal program operation from HALT mode. • STOP mode : The oscillator is stopped. All operations in the chip stop, such that only leakage current flows. These modes can be selected by software. A macro service can be initiated in HALT mode. Fig. 11-1 Standby Mode Status Transition Macro service request Macro service qu es t ion re at er ice op rv e on se ro of d ac En te ut No S R et IN ESE IDL TP T E 4, in IN pu TP t 5 inp NM I, M 1 1 e ot ut N inp 5 TP IN 4, TP IN e2 ot I, tN es qu t re u pt inp ru T LT SE HA RE Set NM er STOP (standby) OP t ST inpu t Se ET S RE End of one operation End of macro service Program operation Int Wait for oscillation settling ttling tion se Oscilla ses p time ela IDLE (standby) Request for masked interrupt HALT (standby) Notes 1. INTP4 and INTP5 are applied when not masked. 2. Only when the interrupt request is not masked Remark NMI is enabled only by external input. The watchdog timer cannot be used to release one of the standby modes (STOP or IDLE mode). 52 m PD784020, 784021 12. RESET FUNCTION Applying a low-level signal to the RESET pin initializes the internal hardware (reset status). When the RESET input makes a low-to-high transition, the following data is loaded into the program counter (PC): • Eight low-order bits of the PC : Contents of location at address 0000H • Intermediate eight bits of the PC : Contents of location at address 0001H • Four high-order bits of the PC : 0 The PC contents are used as a branch destination address. Program execution starts from that address. Therefore, a reset start can be performed from an arbitrary address. The contents of each register can be set by software, as required. The RESET input circuit contains a noise eliminator to prevent malfunctions caused by noise. This noise eliminator is an analog delay sampling circuit. Fig. 12-1 Accepting a Reset Delay Delay Delay Initialize PC Execute instruction at reset start address RESET (input) Internal reset signal Start reset End reset For power-on reset, the RESET signal must be held active until the oscillation settling time (approximately 40 ms) has elapsed. Fig. 12-2 Power-On Reset Oscillation settling time Delay Initialize PC Execute instruction at reset start address VDD RESET (input) Internal reset signal End reset 53 m PD784020, 784021 13. INSTRUCTION SET (1) 8-bit instructions (The instructions enclosed in parentheses are implemented by a combination of operands, where A is described as r.) MOV, XCH, ADD, ADDC, SUB, SUBC, AND, OR, XOR, CMP, MULU, DIVUW, INC, DEC, ROR, ROL, RORC, ROLC, SHR, SHL, ROR4, ROL4, DBNZ, PUSH, POP, MOVM, XCHM, CMPME, CMPMNE, CMPMNC, CMPMC, MOVBK, XCHBK, CMPBKE, CMPBKNE, CMPBKNC, CMPBKC, CHKL, CHKLA Table 13-1 Instructions Implemented by 8-Bit Addressing 2nd operand #byte A r saddr r' saddr' sfr !addr16 !!addr24 1st operand A mem r3 [WHL+] [saddrp] PSWL [WHL–] [%saddrg] PSWH (MOV) (MOV) MOV (MOV)Note 6 MOV (MOV) MOV ADD Note 1 (XCH) XCH (XCH)Note 6 (XCH) (XCH) XCH MOV (ADD)Note 1 (ADD) Note 1 (ADD)Notes 1, 6 (ADD) Note 1 ADD Note 1 ADD Note 1 r MOV (MOV) MOV ADD Note 1 (XCH) XCH (ADD)Note 1 ADD Note 1 MOV MOV MOV XCH XCH XCH ADD Note 1 ADD Note 1 n NoneNote 2 (MOV) (XCH) (ADD)Note 1 ROR Note 3 MULU DIVUW INC DEC saddr MOV (MOV)Note 6 MOV ADD Note 1 (ADD)Note 1 ADD Note 1 sfr MOV MOV MOV INC XCH DEC ADD Note 1 DBNZ MOV PUSH ADDNote 1 (ADD)Note 1 ADD Note 1 POP CHKL CHKLA !addr16 MOV (MOV) !!addr24 ADD Note 1 mem MOV [saddrp] ADD Note 1 MOV [%saddrg] mem3 ROR4 ROL4 r3 MOV MOV PSWL PSWH B, C DBNZ STBC, WDM MOV [TDE+] (MOV) [TDE–] (ADD)Note 1 MOVBKNote 5 MOVMNote 4 Notes 1. ADDC, SUB, SUBC, AND, OR, XOR, and CMP are the same as ADD. 2. There is no second operand, or the second operand is not an operand address. 3. ROL, RORC, ROLC, SHR, and SHL are the same as ROR. 4. XCHM, CMPME, CMPMNE, CMPMNC, and CMPMC are the same as MOVM. 5. XCHBK, CMPBKE, CMPBKNE, CMPBKNC, and CMPBKC are the same as MOVBK. 6. When saddr is saddr2 with this combination, an instruction with a short code exists. 54 m PD784020, 784021 (2) 16-bit instructions (The instructions enclosed in parentheses are implemented by a combination of operands, where AX is described as rp.) MOVW, XCHW, ADDW, SUBW, CMPW, MULUW, MULW, DIVUX, INCW, DECW, SHRW, SHLW, PUSH, POP, ADDWG, SUBWG, PUSHU, POPU, MOVTBLW, MACW, MACSW, SACW Table 13-2 Instructions Implemented by 16-Bit Addressing 2nd operand #word AX rp saddrp rp' saddrp' strp !addr16 mem !!addr24 [saddrp] 1st operand AX [WHL+] byte n NoneNote 2 [%saddrg] (MOVW) (MOVW) (MOVW)Note 3 ADDW Note 1 (XCHW) (XCHW) (XCHW) Note 3 (XCHW) (MOVW) MOVW (MOVW) MOVW (MOVW) XCHW XCHW (XCHW) (ADD)Note 1 (ADDW) Note 1 (ADDW)Notes 1,3 (ADDW) Note 1 rp MOVW (MOVW) MOVW MOVW MOVW ADDW Note 1 (XCHW) XCHW XCHW XCHW MOVW SHRW SHLW (ADDW)Note 1 ADDW Note 1 ADDWNote 1 ADDW Note 1 saddrp MOVW (MOVW)Note 3 MOVW MULWNote 4 INCW DECW MOVW INCW ADDW Note 1 (ADDW)Note 1 ADDW Note 1 XCHW DECW ADDWNote 1 sfrp MOVW MOVW MOVW PUSH ADDW Note 1 (ADDW)Note 1 ADDW Note 1 !addr16 MOVW (MOVW) POP MOVW MOVTBLW !!addr24 mem MOVW [saddrp] [%saddrg] PSW PUSH POP SP ADDWG SUBWG post PUSH POP PUSHU POPU [TDE+] (MOVW) SACW byte MACW MACSW Notes 1. SUBW and CMPW are the same as ADDW. 2. There is no second operand, or the second operand is not an operand address. 3. When saddrp is saddrp2 with this combination, an instruction with a short code exists. 4. MULUW and DIVUX are the same as MULW. 55 m PD784020, 784021 (3) 24-bit instructions (The instructions enclosed in parentheses are implemented by a combination of operands, where WHL is described as rg.) MOVG, ADDG, SUBG, INCG, DECG, PUSH, POP Table 13-3 Instructions Implemented by 24-Bit Addressing 2nd operand #imm24 WHL 1st operand WHL rg rg saddrg !!addr24 (MOVG) mem1 [%saddrg] SP NoneNote rg' (MOVG) (MOVG) (MOVG) (MOVG) (ADDG) (ADDG) (ADDG) ADDG MOVG MOVG MOVG (SUBG) (SUBG) (SUBG) SUBG MOVG (MOVG) MOVG MOVG ADDG (ADDG) ADDG DECG SUBG (SUBG) SUBG PUSH MOVG INCG POP saddrg (MOVG) MOVG !!addr24 (MOVG) MOVG mem1 MOVG [%saddrg] MOVG SP MOVG MOVG INCG DECG Note There is no second operand, or the second operand is not an operand address. 56 m PD784020, 784021 (4) Bit manipulation instructions MOV1, AND1, OR1, XOR1, SET1, CLR1, NOT1, BT, BF, BTCLR, BFSET Table 13-4 Bit Manipulation Instructions Implemented by Addressing 2nd operand CY saddr.bit sfr.bit /saddr.bit /sfr.bit A.bit X.bit /A.bit /X.bit PSWL.bit PSWH.bit /PSWL.bit /PSWH.bit NoneNote mem2.bit /mem2.bit 1st operand !addr16.bit !!addr24.bit /!addr16.bit /!!addr24.bit CY MOV1 AND1 NOT1 AND1 OR1 SET1 OR1 CLR1 XOR1 saddr.bit MOV1 NOT1 sfr.bit SET1 A.bit CLR1 X.bit BF PSWL.bit BT PSWH.bit BTCLR mem2.bit BFSET !addr16.bit !!addr24.bit Note There is no second operand, or the second operand is not an operand address. 57 m PD784020, 784021 (5) Call/return instructions and branch instructions CALL, CALLF, CALLT, BRK, RET, RETI, RETB, RETCS, RETCSB, BRKCS, BR, BNZ, BNE, BZ, BE, BNC, BNL, BC, BL, BNV, BPO, BV, BPE, BP, BN, BLT, BGE, BLE, BGT, BNH, BH, BF, BT, BTCLR, BFSET, DBNZ Table 13-5 Call/Return and Branch Instructions Implemented by Addressing Instruction $addr20 $!addr20 !addr16 !!addr20 rp rg [rp] [rg] !addr11 [addr5] CALLF CALLF RBn None address operand Basic BCNote CALL CALL CALL CALL CALL CALL CALL instruction BR BR BR BR BR BR BR BR Composite BF instruction BT BRKCS BRK RET RETCS RETI RETCSB RETB BTCLR BFSET DBNZ Note BNZ, BNE, BZ, BE, BNC, BNL, BL, BNV, BPO, BV, BPE, BP, BN, BLT, BGE, BLE, BGT, BNH, and BH are the same as BC. (6) Other instructions ADJBA, ADJBS, CVTBW, LOCATION, SEL, NOT EI, DI, SWRS 58 m PD784020, 784021 14. H ELECTRICAL CHARACTERISTICS The electrical characteristics described in this chapter apply to the products which are improved versions of the mPD784020 and mPD784021 (other than K-rank products). For K-rank products yet to be improved (K-rank products), please consult with our sales offices. ABSOLUTE MAXIMUM RATINGS (TA = 25 °C) Parameter Rating Unit VDD –0.5 to +7.0 V AVDD AVSS to VDD + 0.5 V AVSS –0.5 to +0.5 V Input voltage VI –0.5 to VDD + 0.5 V Output voltage VO –0.5 to VDD + 0.5 V Low-level output current IOL Each pin 15 mA Total of all output pins 150 mA Each pin –10 mA Total of all output pins –100 mA Supply voltage High-level output current Symbol IOH Conditions A/D converter reference input voltage AVREF1 –0.5 to VDD + 0.3 V D/A converter reference input voltage AVREF2 –0.5 to VDD + 0.3 V AVREF3 –0.5 to VDD + 0.3 V Operating ambient temperature TA –40 to +85 °C Storage temperature Tstg –65 to +150 °C Caution Absolute maximum ratings are rated values beyond which some physical damages may be caused to the product; if any of the parameters in the table above exceeds its rated value even for a moment, the quality of the product may deteriorate. Be sure to use the product within the rated values. 59 m PD784020, 784021 OPERATING CONDITIONS • Operating ambient temperature (T A): –40 to +85 °C • Rising and falling time (tr, tf) (for pins not especially specified): 0 to 200 ms • Power supply voltage and clock cycle time: See Fig. 14-1. Fig. 14-1 Relationship between Power Supply Voltage and Clock Cycle Time 10000 Clock cycle time tCYK [ns] 4000 1000 Operation guarantee range 125 100 80 10 0 1 2 3 4 5 6 7 Power supply voltage [V] CAPACITANCE (T A = 25 °C, VDD = VSS = 0 V) Parameter Conditions Max. Unit CI f = 1 MHz 10 pF Output capacitance CO 0 V on pins other than measured pins 10 pF I/O capacitance CIO 10 pF Input capacitance 60 Symbol Min. Typ. m PD784020, 784021 OSCILLATOR CHARACTERISTICS (TA = –40 to +85 °C, VDD = 4.5 to 5.5 V, VSS = 0 V) Resonator Min. Max. Unit Oscillator frequency (f XX ) 4 25 MHz X1 input frequency (fX) 4 25 MHz X1 input rising and falling times (t XR, t XF) 0 10 ns X1 input high-level and lowlevel widths (t WXH, tWXL) 10 125 ns Recommended circuit Ceramic resonator or crystal VSS X1 C1 X2 C2 External clock X1 Parameter X2 HCMOS Inverter Caution When using the system clock generator, run wires in the portion surrounded by dotted lines according to the following rules to avoid effects such as stray capacitance: • • • • Minimize the wiring. Never cause the wires to cross other signal lines. Never cause the wires to run near a line carrying a large varying current. Cause the grounding point of the capacitor of the oscillator circuit to have the same potential as VSS. Never connect the capacitor to a ground pattern carrying a large current. • Never extract a signal from the oscillator. 61 m PD784020, 784021 OSCILLATOR CHARACTERISTICS (TA = –40 to +85 °C, VDD = 2.7 to 5.5 V, VSS = 0 V) Resonator Min. Max. Unit Oscillator frequency (fXX ) 4 16 MHz X1 input frequency (fX) 4 16 MHz X1 input rising and falling times (tXR, t XF) 0 10 ns X1 input high-level and lowlevel widths (tWXH, tWXL) 10 125 ns Recommended circuit Ceramic resonator or crystal VSS X1 C1 X2 C2 External clock X1 Parameter X2 HCMOS Inverter Caution When using the system clock generator, run wires in the portion surrounded by dotted lines according to the following rules to avoid effects such as stray capacitance: • • • • Minimize the wiring. Never cause the wires to cross other signal lines. Never cause the wires to run near a line carrying a large varying current. Cause the grounding point of the capacitor of the oscillator circuit to have the same potential as VSS. Never connect the capacitor to a ground pattern carrying a large current. • Never extract a signal from the oscillator. 62 m PD784020, 784021 DC CHARACTERISTICS (TA = –40 to +85 °C, VDD = AVDD = 2.7 to 5.5 V, VSS = AVSS = 0 V) (1/2) Parameter Low-level input voltage Symbol Conditions Min. Typ. Max. Unit VIL1 Pins other than those described in Notes 1, 2, 3, and 4 –0.3 0.3VDD V VIL2 Pins described in Notes 1, 2, 3, and 4 –0.3 0.2VDD V VIL3 VDD = +5.0 V ±10 % –0.3 +0.8 V Pins described in Notes 2, 3, and 4 High-level input voltage VIH1 Pins other than those described in Note 1 0.7VDD VDD + 0.3 V VIH2 Pins described in Note 1 0.8VDD VDD + 0.3 V VIH3 VDD = +5.0 V ±10 % 2.2 VDD + 0.3 V Pins described in Notes 2, 3, and 4 Low-level output voltage VOL1 IOL = 2 mA 0.4 V VOL2 VDD = +5.0 V ±10 % 1.0 V IOL = 8 mA Pins described in Notes 2 and 5 High-level output voltage VOH1 IOH = –2 mA VOH2 VDD = +5.0 V ±10 % VDD – 1.0 V 2.0 V IOH = –5 mA Pins described in Note 4 X1 low-level input current IIL 0 V £ V I £ VIL2 –30 mA X1 high-level input current IIH VIH2 £ VI £ VDD +30 mA Notes 1. X1, X2, RESET, P12/ASCK2/SCK2, P13/RxD2/SI2, P20/NMI, P21/INTP0, P22/INTP1, P23/INTP2/CI, P24/INTP3, P25/INTP4/ASCK/SCK1, P26/INTP5, P27/SI0, P30/RxD/SI1, P32/SCK0, P33/SO0/SB0, and TEST 2. AD0 to AD7 and A8 to A15 3. P60/A16 to P63/A19, RD, WR, P66/WAIT/HLDRQ, and P67/REFRQ/HLDAK 4. P00 to P07 5. P10 to P17 63 m PD784020, 784021 DC CHARACTERISTICS (TA = –40 to +85 °C, VDD = AVDD = 2.7 to 5.5 V, VSS = AVSS = 0 V) (2/2) Parameter Input leakage current Symbol ILI Conditions Min. Typ. 0 V £ V I £ VDD Max. Unit ±10 mA ±3 mA ±10 mA Except for the X1 pin when EXTC = 0 0 V £ VI £ VDD Analog input pins Output leakage current ILO 0 V £ VO £ VDD VDD supply current IDD1 Operating mode fXX = 25 MHz 40 60 mA fXX = 16 MHz 12 25 mA fXX = 25 MHz 22 30 mA fXX = 16 MHz 8 12 mA VDD = 2.7 to 5.5 V IDD2 HALT mode VDD = 2.7 to 5.5 V IDD3 IDLE mode fXX = 25 MHz 12 mA (EXTC = 0) fXX = 16 MHz 8 mA 15 100 kW 15 160 kW VDD = 2.7 to 5.5 V Pull-up resistance RL VI = 0 V VDD = +5.0 V ±10 % VI = 0 V VDD = 2.7 to 4.5 V 64 m PD784020, 784021 AC CHARACTERISTICS (TA = –40 to +85 °C, VDD = AVDD = 2.7 to 5.5 V, VSS = AVSS = 0 V) (1) Read/write operation (1/2) Parameter Address setup time ASTB high-level width Address hold time Symbol tSAST tWSTH tHSTLA Conditions VDD = +5.0 V ±10 % VDD = +5.0 V ±10 % VDD = +5.0 V ±10 % (referred to ASTBØ) Address hold time tHRA Min. Max. Unit (0.5 + a) T – 11 ns (0.5 + a) T – 15 ns (0.5 + a) T – 17 ns (0.5 + a) T – 40 ns 0.5T – 24 ns 0.5T – 34 ns 0.5T – 14 ns (1 + a) T – 5 ns (1 + a) T – 10 ns (referred to RD•) Address Æ RDØ delay time Address float time tDAR VDD = +5.0 V ±10 % tFRA 0 ns (2.5 + a + n) T – 37 ns (2.5 + a + n) T – 52 ns (2 + n) T – 40 ns (2 + n) T – 60 ns (1.5 + n) T – 50 ns (1.5 + n) T – 70 ns (referred to RDØ) Address Æ data input time ASTBØ Æ data input time RDØ Æ data input time tDAID tDSTID tDRID VDD = +5.0 V ±10 % VDD = +5.0 V ±10 % VDD = +5.0 V ±10 % ASTBØ Æ RDØ delay time tDSTR 0.5T – 9 ns Data hold time tHRID 0 ns 0.5T – 2 ns 0.5T – 12 ns 1.5T – 2 ns 1.5T – 12 ns 0.5T – 9 ns (1.5 + n) T – 30 ns (1.5 + n) T – 40 ns 0.5T – 14 ns (1 + a) T – 5 ns (1 + a) T – 10 ns (referred to RD•) RD• Æ address active time tDRA Upon program VDD = +5.0 V ±10 % read Upon data read RD• Æ ASTB• delay time tDRST RD low-level width tWRL Address hold time VDD = +5.0 V ±10 % VDD = +5.0 V ±10 % tHWA (referred to WR•) Address Æ WRØ delay time ASTBØ Æ data output delay time tDAW tDSTOD ASTBØ Æ data output time tDWOD ASTBØ Æ WRØ output delay time tDSTW VDD = +5.0 V ±10 % VDD = +5.0 V ±10 % 0.5T – 9 0.5T + 15 ns 0.5T + 20 ns 0.5T – 11 ns ns Remark T: TCYK (system clock cycle time) a: 1 when address wait is applied, 0 in other cases n: number of wait cycles (n • 0) 65 m PD784020, 784021 (1) Read/write operation (2/2) Parameter Data setup time Symbol tSODW Conditions VDD = +5.0 V ±10 % (referred to WR•) Data hold time tHWOD VDD = +5.0 V ±10 % (referred to WR•)Note WR• Æ ASTB• delay time tDWST WR low-level width tWWL VDD = +5.0 V ±10 % Min. Max. Unit (1.5 + n) T – 30 ns (1.5 + n) T – 40 ns 0.5T – 5 ns 0.5T – 14 ns 0.5T – 9 ns (1.5 + n) T – 30 ns (1.5 + n) T – 40 ns Note The hold time includes the time for holding VOH1 and VOL1 on the load conditions of CL = 50 pF and RL = 4.7 kW. Remark T: TCYK (system clock cycle time) n: number of wait cycles (n • 0) (2) Bus hold timing Parameter Symbol Conditions Min. Max. Unit HLDRQ• Æ float delay time tFHQC (6 + a + n) T + 50 ns HLDRQ• Æ HLDAK• delay time tDHQHHAH VDD = +5.0 V ±10 % (7 + a + n) T + 30 ns (7 + a + n) T + 40 ns Float Æ HLDAK• delay time tDCFHA 1T + 30 ns HLDRQØ Æ HLDAKØ delay time tDHQLHAL VDD = +5.0 V ±10 % 2T + 40 ns 2T + 60 ns HLDAKØ Æ active delay time tDHAC VDD = +5.0 V ±10 % Remark T: TCYK (system clock cycle time) a: 1 when address wait is applied, 0 in other cases n: number of wait cycles (n • 0) 66 1T – 20 ns 1T – 30 ns m PD784020, 784021 (3) External wait timing Parameter Symbol Address Æ WAITØ input time tDAWT ASTBØ Æ WAITØ input time ASTBØ Æ WAIT hold time ASTBØ Æ WAIT• delay time RDØ Æ WAITØ input time RDØ Æ WAITØ hold time RDØ Æ WAIT• delay time WAIT• Æ data input time tDSTWT Conditions Min. VDD = +5.0 V ±10 % VDD = +5.0 V ±10 % tHSTWTH VDD = +5.0 V ±10 % tHRWT tDRWTH tDWTID (2 + a) T – 40 ns (2 + a) T – 60 ns 1.5T – 40 ns 1.5T – 60 ns ns (0.5 + n) T + 10 ns VDD = +5.0 V ±10 % VDD = +5.0 V ±10 % Unit (0.5 + n) T + 5 tDSTWTH VDD = +5.0 V ±10 % tDRWTL Max. (1.5 + n) T – 40 ns (1.5 + n) T – 60 ns T – 50 ns T – 70 ns nT + 5 ns nT + 10 ns VDD = +5.0 V ±10 % VDD = +5.0 V ±10 % (1 + n) T – 40 ns (1 + n) T – 60 ns 0.5T – 5 ns 0.5T – 10 ns WAIT• Æ WR• delay time tDWTW 0.5T ns WAIT• Æ RD• delay time tDWTR 0.5T ns WRØ Æ WAITØ input time tDWWTL WRØ Æ WAIT hold time WRØ Æ WAIT• delay time tHWWT tDWWTH VDD = +5.0 V ±10 % VDD = +5.0 V ±10 % T – 50 ns T – 75 ns nT + 5 ns nT + 10 ns VDD = +5.0 V ±10 % (1 + n) T – 40 ns (1 + n) T – 60 ns Max. Unit Remark T: TCYK (system clock cycle time) a: 1 when address wait is applied, 0 in other cases n: number of wait cycles (n • 0) (4) Refresh timing Parameter Symbol Random read/write cycle time tRC REFRQ low-level pulse width tWRFQL Conditions VDD = +5.0 V ±10 % Min. 3T ns 1.5T – 25 ns 1.5T – 30 ns ASTBØ Æ REFRQ delay time tDSTRFQ 0.5T – 9 ns RD• Æ REFRQ delay time tDRRFQ 1.5T – 9 ns WR• Æ REFRQ delay time tDWRFQ 1.5T – 9 ns REFRQ• Æ ASTB delay time tDRFQST 0.5T – 9 ns REFRQ high-level pulse width tWRFQH 1.5T – 25 ns 1.5T – 30 ns VDD = +5.0 V ±10 % Remark T: TCYK (system clock cycle time) 67 m PD784020, 784021 SERIAL OPERATION (CSI) Parameter Serial clock cycle time Symbol tCYSK0 Input Conditions Min. VDD = +5.0 V ±10 % 500 ns 1000 ns T ns 210 ns (SCK0) Output Serial clock low-level width tWSKL0 Input VDD = +5.0 V ±10 % (SCK0) 460 ns ns 210 ns 460 ns 0.5T – 40 ns tSSSK0 80 ns tHSSK0 80 ns tWSKH0 Input VDD = +5.0 V ±10 % (SCK0) Output SI0, SB0 setup time Unit 0.5T – 40 Output Serial clock high-level width Max. (referred to SCK0•) SI0, SB0 hold time (referred to SCK0•) SO0, SB0 output delay time tDSBSK1 (referred to SCK0Ø) CMOS push-pull output 0 150 ns 0 400 ns (three-wire serial I/O mode) tDSBSK2 Open-drain output (SBI mode), R L = 1 kW SO0, SB0 output hold time tHSBSK1 During data transfer tHSBSK2 SBI mode 0.5TCYSK0 – 40 ns 4 tCYX tSSBSK 4 tCYX SB0 low-level width tWSBL 4 tCYX SB0 high-level width tWSBH 4 tCYX (referred to SCK0•) SB0 high hold time (referred to SCK0•) SB0 low setup time (referred to SCK0Ø) Remarks 1. The values listed in the above table are obtained when fXX = 25 MHz and CL = 100 pF. 2. tCYX = 1/fXX 3. T: Serial clock frequency specified using software. The minimum value is 16/fXX. 68 m PD784020, 784021 SERIAL OPERATION (IOE1, IOE2) Parameter Serial clock cycle time Symbol tCYSK1 Input Conditions Min. VDD = +5.0 V ±10 % 250 ns 500 ns T ns (SCK1, SCK2) Serial clock low-level width tWSKL1 Output Internal clock divided by 16 Input VDD = +5.0 V ±10 % 85 ns ns 0.5T – 40 ns 85 ns 210 ns 0.5T – 40 ns tSSSK1 40 ns tHSSK1 40 ns tDSOSK 0 tWSKH1 Output Internal clock divided by 16 Input VDD = +5.0 V ±10 % (SCK1, SCK2) Output SI1, SI2 setup time Unit 210 (SCK1, SCK2) Serial clock high-level width Max. Internal clock divided by 16 (referred to SCK1, SCK2•) SI1, SI2 hold time (referred to SCK1, SCK2•) SO1, SO2 output delay time 50 ns (referred to SCK1, SCK2Ø) SO1, SO2 output hold time tHSOSK During data transfer 0.5TCYSK1 – 40 ns (referred to SCK1, SCK2•) Remarks 1. The values listed in the above table are obtained when CL = 100 pF. 2. T: Serial clock frequency specified using software. The minimum value is 16/fXX. SERIAL OPERATION (UART, UART2) Parameter ASCK clock input cycle time ASCK clock low-level width ASCK clock high-level width Symbol tCYASK tWASKL tWASKH Conditions VDD = +5.0 V ±10 % VDD = +5.0 V ±10 % VDD = +5.0 V ±10 % Min. Max. Unit 125 ns 250 ns 52.5 ns 85 ns 52.5 ns 85 ns 69 m PD784020, 784021 OTHER OPERATIONS Parameter Symbol Conditions Min. Max. Unit NMI low-level width tWNIL 10 ms NMI high-level width tWNIH 10 ms INTP0 low-level width tWIT0L 3tCYSMP + 10 ns INTP0 high-level width tWIT0H 3tCYSMP + 10 ns INTP1-INTP3 and CI lowlevel width tWIT1L 3t CYCPU + 10 ns INTP1-INTP3 and CI highlevel width tWIT1H 3tCYCPU + 10 ns INTP4 and INTP5 low-level width tWIT2L 10 ms INTP4 and INTP5 high-level width tWIT2H 10 ms RESET low-level width tWRSL 10 ms RESET high-level width tWRSH 10 ms Remark tCYSMP: sampling clock specified using software tCYCPU: CPU operating clock specified using CPU software A/D CONVERTER CHARACTERISTICS (TA = –40 to +85 °C, VDD = AVDD = 3.4 to 5.5 V, +3.4 V £ AVREF1 £ AVDD, VSS = AVSS = 0 V) Parameter Symbol Conditions Resolution Min. Typ. Max. 8 Unit bit Total errorNote 1.2 % 1.0 % 1.0 % Linearity calibrationNote 0.6 % Quantization error ±1/2 LSB VDD = AV DD = +5.0 V ±10 % +3.4 V £ AV REF1 £ AVDD +2.7 V £ VDD = AVDD £ +3.3 V +2.5 V £ AV REF1 £ AVDD Conversion time Sampling time tCONV tSAMP tCYK £ 500 ns, FR = 1 120 tCYK tCYK £ 500 ns, FR = 0 180 tCYK tCYK £ 500 ns, FR = 1 24 tCYK tCYK £ 500 ns, FR = 0 36 tCYK Analog input voltage VIAN –0.3 Analog input impedance RAN AVREF1 current AIREF1 AVDD supply current AIDD1 fXX = 25 MHz AIDD2 STOP mode, CS = 0 AVREF1 + 0.3 V MW 1000 0.5 1.5 mA 2.0 5.0 mA 20 mA Note Quantization error is excluded. The error is represented in percent with respect to a full-scale value. Remark tCYK: system clock cycle time 70 m PD784020, 784021 D/A CONVERTER CHARACTERISTICS (TA = –40 to +85 °C, AVREF2 = VDD = AVDD = 2.7 to 5.5 V, AVREF3 = VSS = AVSS = 0 V) Parameter Symbol Conditions Resolution Total Min. Typ. Max. 8 errorNote Load condition: Unit bit VDD = 4.5 to 5.5 V 4 MW, 30 pF VDD = 4.5 to 5.5 V 0.4 % 0.6 % 0.6 % 0.8 % 0.6 % 0.8 % 0.8 % 1.0 % 10 ms AV REF2 = 0.75VDD AV REF3 = 0.25VDD AV REF2 = 0.75VDD AV REF3 = 0.25VDD Load condition: VDD = 4.5 to 5.5 V 2 MW, 30 pF VDD = 4.5 to 5.5 V AV REF2 = 0.75VDD AV REF3 = 0.25VDD AV REF2 = 0.75VDD AV REF3 = 0.25VDD Settling time Load condition: 2 MW, 30 pF Note Output resistance RO Analog reference voltage AVREF2 0.75VDD VDD AVREF3 0 0.25VDD V AIREF2 0 5 mA AIREF3 –5 0 mA Reference supply input current 20 kW V Note DACS0, DACS1 = 7FH 71 m PD784020, 784021 DATA RETENTION CHARACTERISTICS (TA = –40 to +85 °C) Parameter Symbol Conditions Min. Typ. 2.5 Max. Unit 5.5 V Data retention voltage VDDDR STOP mode Data retention current IDDDR VDDDR = 2.5 to 5.5 VNote 1 10 50 mA VDDDR = 2.5 V Note 1 2 10 mA VDD rising time tRVD 200 ms VDD falling time tFVD 200 ms VDD retention time tHVD 0 ms STOP release signal input time tDREL 0 ms Oscillation settling time tWAIT Crystal 30 ms Ceramic resonator 5 ms Specified pinsNote 2 0 0.1V DDDR V 0.9VDDDR VDDDR V (referred to STOP mode setting) Low-level input voltage VIL High-level input voltage VIH Notes 1. When the input voltage for the pins described in Note 2 satisfies the VIL and VIH conditions in the above table 2. Pins RESET, P20/NMI, P21/INTP0, P22/INTP1, P23/INTP2/CI, P24/INTP3, P25/INTP4/ASCK/SCK1, P26/INTP5, P27/SI0, P32/SCK0, and P33/SO0/SB0 AC Timing Test Points VDD – 1 V 0.8VDD or 2.2 V 0.8VDD or 2.2 V Test points 0.45 V 72 0.8 V 0.8 V m PD784020, 784021 Timing Waveform (1) Read operation tWSTH ASTB tSAST tDRST tDSTID tHSTLA A8-A19 tDAID tHRA AD0-AD7 tDSTR tDAR tHRID tFRA tDRID tDRA RD tWRL (2) Write operation tWSTH ASTB tSAST tDWST tDSTOD tHSTLA A8-A19 tHWA AD0-AD7 tHWOD tDSTW tDAW tDWOD tDSODW WR tWWL 73 m PD784020, 784021 Hold Timing ASTB, A8-A19, AD0-AD7, RD, WR tFHQC tDCFHA tDHAC HLDRQ tDHQLHAL tDHQHHAH HLDAK External WAIT Signal Input Timing (1) Read operation ASTB tDSTWTH tHSTWTH tDSTWT A8-A19 AD0-AD7 tDAWT tDWTID RD tDWTR tDRWTL WAIT tHRWT tDRWTH (2) Write operation ASTB tDSTWTH tHSTWTH tDSTWT A8-A19 AD0-AD7 tDAWT WR tDWTW tDWWTL WAIT tHWWT tDWWTH 74 m PD784020, 784021 Timing Waveform for Refresh (1) Random read/write cycle tRC ASTB WR tRC tRC tRC tRC RD (2) When a refresh is performed simultaneously with a memory access ASTB RD, WR tDSTRFQ tDRFQST tWRFQH REFRQ tWRFQL (3) Refresh after reading ASTB tDRFQST RD tDRRFQ REFRQ tWRFQL (4) Refresh after writing ASTB tDRFQST WR tDWRFQ REFRQ tWRFQL 75 m PD784020, 784021 Serial Operation (CSI) (1) Three-wire serial I/O mode tWSKL0 tWSKH0 SCK tSSSK0 tCYSK0 SI tHSSK0 Input data tDSBSK1 tHSBSK1 Output data SO (2) SBI mode Ý Bus release signal transfer SCK tHSBSK2 tWSBL tWSBH tSSBSK SB0 Ý Command signal transfer tWSKL0 tWSKH0 SCK tHSBSK2 tSSBSK tCYSK0 tDSBSK2 SB0 76 tSSSK0 tHSSK0 tHSBSK1 Input/Output data m PD784020, 784021 Serial Operation (IOE1, IOE2) tWSKH1 tWSKL1 SCK tSSSK1 tCYSK1 tHSSK1 Input data SI tDSOSK SO tHSOSK Output data Serial Operation (UART, UART2) tWASKH ASCK, ASCK2 tWASKL 0.8VDD 0.8 V tCYASK 77 m PD784020, 784021 Interrupt Input Timing tWNIH tWNIL 0.8VDD NMI 0.8 V tWIT0H tWIT0L 0.8VDD INTP0 0.8 V tWIT1H tWIT1L 0.8VDD CI, INTP1-INTP3 0.8 V tWIT2H tWIT2L 0.8VDD INTP4, INTP5 0.8 V Reset Input Timing tWRSH tWRSL 0.8VDD RESET 78 0.8 V m PD784020, 784021 External Clock Timing tWXH 0.8VDD X1 0.8 V tXF tXR tWXL tCYX Data Retention Timing Set STOP mode. VDD VDDDR tHVD RESET tFVD tRVD tDREL tWAIT 0.8VDD 0.8 V NMI (Released by a falling edge) 0.8VDD 0.8 V 0.8VDD NMI (Released by a rising edge) 0.8 V 79 m PD784020, 784021 15. PACKAGE DRAWINGS 80 PIN PLASTIC QFP (14×14) A B 60 61 41 40 detail of lead end C D S R Q 21 20 80 1 F J G I H M K P M N L NOTE Each lead centerline is located within 0.13 mm (0.005 inch) of its true position (T.P.) at maximum material condition. ITEM MILLIMETERS INCHES A 17.2±0.4 0.677±0.016 B 14.0±0.2 0.551 +0.009 –0.008 C 14.0±0.2 0.551 +0.009 –0.008 D 17.2±0.4 0.677±0.016 F 0.825 0.032 G 0.825 0.032 H 0.30±0.10 0.012 +0.004 –0.005 I 0.13 0.005 J 0.65 (T.P.) 0.026 (T.P.) K 1.6±0.2 L 0.8±0.2 0.063±0.008 0.031 +0.009 –0.008 M 0.15 +0.10 –0.05 0.006 +0.004 –0.003 N 0.10 0.004 P 2.7 0.106 Q 0.1±0.1 0.004±0.004 R 5°±5° 5°±5° S 3.0 MAX. 0.119 MAX. S80GC-65-3B9-4 Remark The shape and material of the ES version are the same as those of the corresponding mass-produced products. 80 m PD784020, 784021 80 PIN PLASTIC TQFP (FINE PITCH) ( 12) H A B 60 41 61 40 21 F 80 1 20 H I M J K M P G R Q S D C detail of lead end N L NOTE Each lead centerline is located within 0.10 mm (0.004 inch) of its true position (T.P.) at maximum material condition. ITEM MILLIMETERS A 14.0±0.2 INCHES 0.551 +0.009 –0.008 B 12.0±0.2 0.472 +0.009 –0.008 C 12.0±0.2 0.472 +0.009 –0.008 D 14.0±0.2 0.551 +0.009 –0.008 F 1.25 0.049 G 1.25 0.049 H 0.22 +0.05 –0.04 0.009±0.002 I 0.10 0.004 J 0.5 (T.P.) 0.020 (T.P.) K 1.0±0.2 0.039 +0.009 –0.008 L 0.5±0.2 0.020 +0.008 –0.009 M 0.145 +0.055 –0.045 0.006±0.002 N 0.10 0.004 P 1.05 0.041 Q 0.05±0.05 0.002±0.002 R 5°±5° 5°±5° S 1.27 MAX. 0.050 MAX. P80GK-50-BE9-4 Remark The shape and material of the ES version are the same as those of the corresponding mass-produced products. 81 m PD784020, 784021 H 16. RECOMMENDED SOLDERING CONDITIONS The conditions listed below shall be met when soldering the mPD784021. For details of the recommended soldering conditions, refer to our document SMD Surface Mount Technology Manual (C10535E). Please consult with our sales offices in case any other soldering process is used, or in case soldering is done under different conditions. Table 16-1 Soldering Conditions for Surface-Mount Devices (1) mPD784020GC-3B9 : 80-pin plastic QFP (14 ¥ 14 mm) mPD784021GC-3B9 : 80-pin plastic QFP (14 ¥ 14 mm) Soldering process Soldering conditions Symbol Infrared ray reflow Peak package’s surface temperature: 235 ½C Reflow time: 30 seconds or less (at 210 ½C or more) Maximum allowable number of reflow processes: 3 IR35-00-3 VPS Peak package’s surface temperature: 215 ½C Reflow time: 40 seconds or less (at 210 ½C or more) Maximum allowable number of reflow processes: 3 VP15-00-3 Wave soldering Solder temperature: 260 ½C or less Flow time: 10 seconds or less Number of flow process: 1 Preheating temperature: 120 ½C max. (measured on the package surface) WS60-00-1 Partial heating method Terminal temperature: 300 ½C or less Flow time: 3 seconds or less (for each side of device) – (2) mPD784021GK-BE9: 80-pin plastic TQFP (fine pitch) (12 ¥ 12 mm) Soldering process Infrared ray reflow Soldering conditions Peak package’s surface temperature: 235 ½C Reflow time: 30 seconds or less (at 210 ½C or more) Symbol IR35-107-2 Maximum allowable number of reflow processes: 2 Exposure limitNote: 7 days (10 hours of pre-baking is required at 125 ½C afterward.) <Cautions> Non-heat resistant trays, such as magazine and taping trays, cannot be baked before unpacking. VPS Peak package’s surface temperature: 215 ½C Reflow time: 40 seconds or less (at 200 ½C or more) Maximum allowable number of reflow processes: 2 Exposure limitNote: 7 days (10 hours of pre-baking is required at 125 ½C afterward.) <Cautions> Non-heat resistant trays, such as magazine and taping trays, cannot be baked before unpacking. Partial heating method Terminal temperature: 300 ½C or less Flow time: 3 seconds or less (for each side of device) VP15-107-2 – Note Exposure limit before soldering after dry-pack package is opened. Storage conditions: Temperature of 25 ½C and maximum relative humidity at 65 % or less Caution Do not apply more than a single process at once, except for “Partial heating method.” 82 m PD784020, 784021 APPENDIX A DEVELOPMENT TOOLS The following development tools are available for system development using the mPD784021. Language Processing Software RA78K4Note 1 Assembler package for all 78K/IV series models CC78K4Note 1 C compiler package for all 78K/IV series models CC78K4-LNote 1 C compiler library source file for all 78K/IV series models PROM Write Tools PG-1500 PROM programmer PA-78P4026GC PA-78P4038GK PA-78P4026KK Programmer adaptor, connects to PG-1500 PG-1500 controllerNote 2 Control program for PG-1500 Debugging Tools IE-784000-R In-circuit emulator for all mPD784026 sub-series models IE-784000-R-BK Break board for all 78K/IV series models IE-784026-R-EM1 IE-784000-R-EM Emulation board for evaluating mPD784026 sub-series models IE-70000-98-IF-B Interface adapter when the PC-9800 series computer (other than a notebook) is used as the host machine IE-70000-98N-IF Interface adapter and cable when a PC-9800 series notebook is used as the host machine IE-70000-PC-IF-B Interface adapter when the IBM PC/ATTM is used as the host machine IE-78000-R-SV3 Interface adapter and cable when the EWS is used as the host machine EP-78230GC-R Emulation probe for 80-pin plastic QFP (14 ¥ 14 mm) for all mPD784026 sub-series EP-78054GK-R Emulation probe for 80-pin plastic TQFP (fine pitch) (12 ¥ 12 mm) for all mPD784021 EV-9200GC-80 Socket for mounting on target system board made for 80-pin plastic QFP (14 ¥ 14 mm) EV-9500GK-80 Adapter for mounting on target system board made for 80-pin plastic TQFP (fine pitch) (12 ¥ 12 mm) EV-9900 Tool used to remove the mPD78P4026KK-T from the EV-9200GC-80 SM78K4Note 3 System simulator for all 78K/IV series models ID78K4Note 3 Integrated debugger for IE-784000-R DF784026Note 4 Device file for all mPD784026 sub-series models Real-time OS RX78K/IVNote 4 Real-time OS for 78K/IV series models MX78K4Note 2 OS for all 78K/IV series models Remark The RA78K4, CC78K4, SM78K4, and ID78K4 are used with the DF784026. 83 m PD784020, 784021 • Based on PC-9800 series (MS-DOSTM) • Based on IBM PC/AT and compatibles (PC DOSTM, WindowsTM, MS-DOS, and IBM DOSTM) • Based on HP9000 series 700TM (HP-UXTM) • Based on SPARCstationTM (SunOSTM) • Based on NEWSTM (NEWS-OSTM) 2. • Based on PC-9800 series (MS-DOS) • Based on IBM PC/AT and compatibles (PC DOS, Windows, MS-DOS, and IBM DOS) 3. • Based on PC-9800 series (MS-DOS + Windows) • Based on IBM PC/AT and compatibles (PC DOS, Windows, MS-DOS, and IBM DOS) • Based on HP9000 series 700 (HP-UX) • Based on SPARCstation (SunOS) 4. • Based on PC-9800 series (MS-DOS) • Based on IBM PC/AT and compatibles (PC DOS, Windows, MS-DOS, and IBM DOS) • Based on HP9000 series 700 (HP-UX) • Based on SPARCstation (SunOS) Notes 1. 84 m PD784020, 784021 APPENDIX B RELATED DOCUMENTS Documents Related to Devices Document No. Document name Japanese English mPD784020, 784021 Data Sheet U11514J This manual mPD784025, 784026 Data Sheet To be released soon IP-3230 mPD78P4026 Data Sheet To be released soon IP3231 mPD784026 Sub-Series User's Manual, Hardware U10898J U10898E mPD784026 Sub-Series Special Function Registers U10593J — mPD784026 Sub-Series Application Note, Hardware Basic U10573J — 78K/IV Series User's Manual, Instruction U10905J IEU-1386 78K/IV Series Instruction Summary Sheet U10594J — 78K/IV Series Instruction Set U10595J — 78K/IV Series Application Note, Software Basic U10095J — Documents Related to Development Tools (User’s Manual) Document No. Document name Japanese English Operation EEU-809 EEU-1399 Language EEU-815 EEU-1404 EEU-817 EEU-1402 Operation EEU-656 EEU-1280 Language EEU-655 EEU-1284 CC78K Series Library Source File EEU-777 — PG-1500 PROM Programmer EEU-651 EEU-1335 PG-1500 Controller PC-9800 Series (MS-DOS) Base EEU-704 EEU-1291 PG-1500 Controller IBM PC Series (PC DOS) Base EEU-5008 U10540E IE-784000-R EEU-5004 EEU-1534 IE-784026-R-EM1 EEU-5017 EEU-1528 EP-78230 EEU-985 EEU-1515 EP-78054GK-R EEU-932 EEU-1468 RA78K Series Assembler Package RA78K Series Structured Assembler Preprocessor CC78K Series C Compiler SM78K4 System Simulator Windows Base Reference U10093J U10093E SM78K Series System Simulator External Parts User Open Interface Specifications U10092J U10092E ID78K4 Integrated Debugger Reference U10440J U10440E Caution The above documents may be revised without notice. Use the latest versions when you design application systems. 85 m PD784020, 784021 Documents Related to Software to Be Incorporated into the Product (User’s Manual) Document No. Document name 78K/IV Series Real-Time OS Japanese English Basic U10603J — Installation U10604J — Debugger U10364J — To be created — OS for 78K/IV Series MX78K4 Other Documents Document No. Document name Japanese IC PACKAGE MANUAL SMD Surface Mount Technology Manual English C10943X C10535J C10535E IEI-620 IEI-1209 NEC Semiconductor Device Reliability/Quality Control System C10983J C10983E Electrostatic Discharge (ESD) Test MEM-539 — Guide to Quality Assurance for Semiconductor Device MEI-603 MEI-1202 Guide for Products Related to Micro-Computer: Other Companies MEI-604 — Quality Grades on NEC Semiconductor Device Caution The above documents may be revised without notice. Use the latest versions when you design application systems. 86 m PD784020, 784021 [MEMO] 87 m PD784020, 784021 Cautions on CMOS Devices Countermeasures against static electricity for all MOSs Caution When handling MOS devices, take care so that they are not electrostatically charged. Strong static electricity may cause dielectric breakdown in gates. When transporting or storing MOS devices, use conductive trays, magazine cases, shock absorbers, or metal cases that NEC uses for packaging and shipping. Be sure to ground MOS devices during assembling. Do not allow MOS devices to stand on plastic plates or do not touch pins. Also handle boards on which MOS devices are mounted in the same way. CMOS-specific handling of unused input pins Caution Hold CMOS devices at a fixed input level. Unlike bipolar or NMOS devices, if a CMOS device is operated with no input, an intermediatelevel input may be caused by noise. This allows current to flow in the CMOS device, resulting in a malfunction. Use a pull-up or pull-down resistor to hold a fixed input level. Since unused pins may function as output pins at unexpected times, each unused pin should be separately connected to the VDD or GND pin through a resistor. If handling of unused pins is documented, follow the instructions in the document. Statuses of all MOS devices at initialization Caution The initial status of a MOS device is unpredictable when power is turned on. Since characteristics of a MOS device are determined by the amount of ions implanted in molecules, the initial status cannot be determined in the manufacture process. NEC has no responsibility for the output statuses of pins, input and output settings, and the contents of registers at power on. However, NEC assures operation after reset and items for mode setting if they are defined. When you turn on a device having a reset function, be sure to reset the device first. MS-DOS and Windows are trademarks of Microsoft Corporation. IBM DOS, PC/AT, and PC DOS are trademarks of IBM Corporation. HP9000 series 700 and HP-UX are trademarks of Hewlett-Packard Company. SPARCstation is a trademark of SPARC International, Inc. SunOS is a trademark of Sun Microsystems, Inc. NEWS and NEWS-OS are trademarks of SONY Corporation. 88 m PD784020, 784021 Regional Information Some information contained in this document may vary from country to country. Before using any NEC product in your application, please contact the NEC office in your country to obtain a list of authorized representatives and distributors. They will verify: • Device availability • Ordering information • Product release schedule • Availability of related technical literature • Development environment specifications (for example, specifications for third-party tools and components, host computers, power plugs, AC supply voltages, and so forth) • Network requirements In addition, trademarks, registered trademarks, export restrictions, and other legal issues may also vary from country to country. NEC Electronics Inc. (U.S.) NEC Electronics (Germany) GmbH NEC Electronics Hong Kong Ltd. Mountain View, California Tel: 800-366-9782 Fax: 800-729-9288 Benelux Office Eindhoven, The Netherlands Tel: 040-2445845 Fax: 040-2444580 Hong Kong Tel: 2886-9318 Fax: 2886-9022/9044 NEC Electronics (Germany) GmbH Duesseldorf, Germany Tel: 0211-65 03 02 Fax: 0211-65 03 490 NEC Electronics Hong Kong Ltd. France Tel: 01-30-67 58 00 Fax: 01-30-67 58 99 Seoul Branch Seoul, Korea Tel: 02-528-0303 Fax: 02-528-4411 NEC Electronics (France) S.A. NEC Electronics Singapore Pte. Ltd. Spain Office Madrid, Spain Tel: 01-504-2787 Fax: 01-504-2860 United Square, Singapore 1130 Tel: 253-8311 Fax: 250-3583 NEC Electronics (France) S.A. NEC Electronics (UK) Ltd. Milton Keynes, UK Tel: 01908-691-133 Fax: 01908-670-290 NEC Electronics Italiana s.r.1. Milano, Italy Tel: 02-66 75 41 Fax: 02-66 75 42 99 NEC Electronics Taiwan Ltd. NEC Electronics (Germany) GmbH Scandinavia Office Taeby Sweden Tel: 8-63 80 820 Fax: 8-63 80 388 Taipei, Taiwan Tel: 02-719-2377 Fax: 02-719-5951 NEC do Brasil S.A. Sao Paulo-SP, Brasil Tel: 011-889-1680 Fax: 011-889-1689 J96. 3 89 m PD784020, 784021 Some related documents may be preliminary versions. Note that, however, what documents are preliminary is not indicated in this document. No part of this document may be copied or reproduced in any form or by any means without the prior written consent of NEC Corporation. NEC Corporation assumes no responsibility for any errors which may appear in this document. NEC Corporation does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from use of a device described herein or any other liability arising from use of such device. No license, either express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of NEC Corporation or others. While NEC Corporation has been making continuous effort to enhance the reliability of its semiconductor devices, the possibility of defects cannot be eliminated entirely. To minimize risks of damage or injury to persons or property arising from a defect in an NEC semiconductor device, customer must incorporate sufficient safety measures in its design, such as redundancy, fire-containment, and anti-failure features. NEC devices are classified into the following three quality grades: "Standard", "Special", and "Specific". The Specific quality grade applies only to devices developed based on a customer designated "quality assurance program" for a specific application. The recommended applications of a device depend on its quality grade, as indicated below. Customers must check the quality grade of each device before using it in a particular application. Standard: Computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots Special: Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support) Specific: Aircrafts, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems or medical equipment for life support, etc. The quality grade of NEC devices in "Standard" unless otherwise specified in NEC's Data Sheets or Data Books. If customers intend to use NEC devices for applications other than those specified for Standard quality grade, they should contact NEC Sales Representative in advance. Anti-radioactive design is not implemented in this product. M4 94. 11 90